M471B2874DZ1-CG8_技术文档

Unbuffered SoDIMM

DDR3 SDRAM

DDR3 SDRAM Specification

204pin Unbuffered SODIMM based on 1Gb D-die

64-bit Non-ECC

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications

where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any gov-

ernmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

Table Contents

1.0 DDR3 Unbuffered SoDIMM Ordering Information ......................................................................4

2.0 Key Features .................................................................................................................................4

3.0 Address Configuration .................................................................................................................4

4.0 x64 DIMM Pin Configurations (Front side/Back side) ...............................................................5

5.0 Pin Description .............................................................................................................................6

6.0 ON DIMM Thermal Sensor ............................................................................................................6

7.0 Input/Output Functional Description ..........................................................................................7

8.0 Functional Block Diagram: .......................................................................................................... 8

8.1 512MB, 64Mx64 Module(Populated as 1 rank of x16 DDR3 SDRAMs) ..................................................8

8.2 1GB, 128Mx64 Module(Populated as 2 rank of x16 DDR3 SDRAMs).................................................... 9

8.3 2GB, 256Mx64 Module(Populated as 2 rank of x8 DDR3 SDRAMs) ....................................................10

9.0 Absolute Maximum Ratings .......................................................................................................11

9.1 Absolute Maximum DC Ratings ...................................................................................................11

9.2 DRAM Component Operating Temperature Range .........................................................................11

10.0 AC & DC Operating Conditions ...............................................................................................11

10.1 Recommended DC Operating Conditions (SSTL - 15) ..................................................................11

11.0 AC & DC Input Measurement Levels .......................................................................................12

11.1 AC and DC Logic input levels for single-ended signals ...............................................................12

11.2 Differential swing requirement for differntial signals ..................................................................13

11.2.1 Single-ended requirements for differential signals ..............................................................14

11.3 AC and DC logic input levels for Differential Signals ...................................................................15

11.4 Differential Input Cross Point Voltage .......................................................................................15

11.5 Slew rate definition for Single Ended Input Signals .....................................................................16

11.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) ...................................16

11.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) ......................................16

11.6 Slew rate definition for Differential Input Signals ........................................................................16

12.0 AC and DC Output Measurement Levels ................................................................................17

12.1 Single Ended AC and DC Output Levels ....................................................................................17

12.2 Differential AC and DC Output Levels .......................................................................................17

12.3.Single Ended Output Slew Rate ................................................................................................18

12.4 Differential Output Slew Rate ...................................................................................................18

13.0 IDD specification........................................................................................................................19

13.1 IDD specification ....................................................................................................................20

14.0 Input/Output Capacitance ........................................................................................................21

14.1. 1Rx16 512MB SoDIMM ............................................................................................................21

14.2. 2Rx16 1GB SoDIMM ...............................................................................................................21

14.3. 2Rx8 2GB SoDIMM .................................................................................................................21

15.0 Electrical Characteristics and AC timing ...............................................................................22

15.1 Refresh Parameters by Device Density ......................................................................................22

15.2 DDR3 SDRAM tRCD, tRP and tRC .............................................................................................22

15.3 Timing parameters for DDR3-800, DDR3-1066 and DDR3-1333 ......................................................24

16.0 Physical Dimensions : .............................................................................................................29

16.1 64Mbx16 based 64Mx64 Module(1 Rank) ...................................................................................29

16.2 64Mbx16 based 128Mx64 Module(2 Ranks) ...............................................................................30

16.3 128Mbx8 based 256Mx64 Module(2 Ranks) ...............................................................................31

2 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

Revision History

Revision

Month

Year

History

0.5

November

2007

- First release

3 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

1.0 DDR3 Unbuffered SoDIMM Ordering Information

Number of

Height

Part Number

Density

Organization

Component Composition

Rank

M471B6474DZ1-CF7/F8/G8/H9

M471B2874DZ1-CF7/F8/G8/H9

M471B5673DZ1-CF7/F8/G8/H9

* ## : F7 / F8 / G8 / H9

512MB

1GB

2GB

64Mx64

128Mx64

256Mx64

64Mx16(K4B1G1646D-HC##)*4

64Mx16(K4B1G1646D-HC##)*8

128Mx8(K4B1G0846D-HC##)*16

1

2

30mm

2.0 Key Features

DDR3-800

DDR3-1066

DDR3-1333

Speed

Unit

6-6-6

2.5

6

7-7-7

8-8-8

9-9-9

1.5

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

1.875

ns

tCK

ns

7

8

9

15

13.125

37.5

15

13.5

36

15

ns

tRAS(min)

tRC(min)

37.5

52.5

37.5

52.5

ns

50.625

49.5

ns

•

JEDEC standard 1.5V ± 0.075V Power Supply

VDDQ = 1.5V ± 0.075V

400 MHz f_CKfor 800Mb/sec/pin, 533MHz f_CKfor 1066Mb/sec/pin, 667MHz f_CKfor 1333Mb/sec/pin

8 independent internal bank

Programmable CAS Latency: 6,7,8,9

Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333)

8-bit pre-fetch

Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

•

Bi-directional Differential Data Strobe

Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower then T_CASE85°C, 3.9us at 85°C < T_CASE≤ 95°C

•

Asynchronous Reset

3.0 Address Configuration

Organization

Row Address

A0-A12

Column Address

A0-A9

Bank Address

BA0-BA2

Auto Precharge

A10/AP

64x16(1Gb) based Module

128x8(1Gb) based Module

A0-A13

A0-A9

BA0-BA2

A10/AP

4 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

4.0 x64 DIMM Pin Configurations (Front side/Back side)

Front

Back

Front

Back

139

141

143

145

147

149

Front

140

142

144

146

148

Back

DQ38

DQ39

V

1

2

71

72

REFDQ

SS

V

3

4

DQ4

DQ5

KEY

DQ34

DQ35

SS

V

5

DQ0

DQ1

6

73

75

77

CKE0

74

76

78

CKE1

SS

V

7

8

DQ44

DQ45

SS

DD

SS

3

V

9

10

DQS0

NC

DQ40

DQ41

A15

SS

3

V

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

50

53

55

57

59

61

63

65

67

69

DM0

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

79

81

BA2

80

82

150

152

154

156

158

160

162

164

166

168

170

172

174

176

178

180

182

184

186

188

190

192

194

196

198

200

202

204

A14

SS

V

151

153

155

157

159

161

163

165

167

169

171

173

175

177

179

181

183

185

187

189

191

193

195

197

199

201

203

DQS5

SS

DD

SS

DQ2

DQ3

DQ6

DQ7

83

A12/BC

A9

84

A11

A7

DM5

V

85

86

SS

V

87

88

DQ42

DQ43

DQ46

DQ47

SS

DD

DQ8

DQ9

DQ12

DQ13

89

A8

A5

90

A6

A4

V

91

92

SS

V

93

94

DQ48

DQ49

DQ52

DQ53

SS

DD

DQS1

DM1

95

A3

A1

96

A2

A0

V

RESET

97

98

SS

V

DQS6

DM6

99

100

102

104

106

108

110

112

114

116

118

120

122

124

126

128

130

132

134

136

138

SS

DD

V

DQ10

DQ11

DQ14

DQ15

101

103

105

107

109

111

113

115

117

119

CK0

CK1

SS

V

DQ54

DQ55

SS

V

DQ50

DQ51

SS

DD

V

DQ16

DQ17

DQ20

DQ21

A10/AP

BA0

BA1

RAS

SS

V

DQ60

DQ61

SS

V

DQ56

DQ57

SS

DD

V

DQS2

DM2

WE

S0

SS

V

CAS

ODT0

DQS7

SS

V

DQ22

DQ23

DM7

SS

DD

3

V

DQ18

DQ19

ODT1

NC

A13

SS

V

121

123

125

127

129

131

133

135

137

S1

DQ58

DQ59

DQ62

DQ63

SS

V

DQ28

DQ29

SS

DD

V

CA

V

DQ24

DQ25

TEST

REF

V

SS

V

SA0

EVENT

SDA

SS

V

DQS3

DQ32

DQ33

DQ36

DQ37

SS

DDSPD

SA1

DM3

SCL

V

tt

V

tt

SS

DQ26

DQ27

DQ30

DQ31

DQS4

DM4

V

SS

Note :

1. NC = No Connect, NU = Not Useable, RFU = Reserved Future Use

2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.

3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

5 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

5.0 Pin Description

Pin Name

Description

Number Pin Name

Description

Number

CK0, CK1

Clock Inputs, positive line

2

DQ0-DQ63

Data Input/Output

64

Data Masks/ Data strobes,

Termination data strobes

CK0, CK1

Clock Inputs, negative line

2

DM0-DM7

8

CKE0, CKE1 Clock Enables

2

1

DQS0-DQS7 Data strobes

8

1

RAS

CAS

Row Address Strobe

DQS0-DQS7 Data strobes complement

Column Address Strobe

RESET

TEST

EVENT

V_DD

Reset Pin

Logic Analyzer specific test pin (No connect

on SODIMM)

WE

Write Enable

1

2

1

S0, S1

Chip Selects

Temperature event pin

Core and I/O Power

Ground

A0-A9, A11,

A13-A15

Address Inputs

14

1

18

52

V_SS

A10/AP

A12/BC

BA0-BA2

Address Input/Autoprecharge

V_REFDQ

V_REFCA

V_DDSPD

Address Input/Burst chop

1

Input/Output Reference

2

SDRAM Bank Addresses

3

SPD and Temp sensor Power

1

V_TT

ODT0, ODT1 On-die termination control

2

1

2

Termination Voltage

Reserved for future use

Total

2

SCL

SDA

Serial Presence Detect (SPD) Clock Input

NC

SPD Data Input/Output

SPD Address

204

SA0-SA1

*The VDD and VDDQ pins are tied common to a single power-plane on these desigus.

6.0 ON DIMM Thermal Sensor

EVENT

V_DDSPD

SCL

SDA

V_DDSPD

EVENT

SCL

SA0

SA1

SA2

VSS

SA0

SA1

SPD with

Integrated

TS

SDA

VSS

Temperature Sensor Characteristics

Temperature Sensor Accuracy

Grade

Range

Units

Notes

Min.

Typ.

+/- 1.0

+/- 2.0

+/- 3.0

0.25

Max.

75 < Ta < 95

40 < Ta < 125

-20 < Ta < 125

+/- 2.0

+/- 3.0

+/- 4.0

C

°C

Resolution

°C /LSB

6 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

7.0 Input/Output Functional Description

Symbol

Type

Function

The system clock inputs. All address and command lines are sampled on the cross point of the

rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the

clock inputs and output timing for read operations is synchronized to the input clock.

CK0-CK1

Input

Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,

CKE low initiates the Power Down mode or the Self Refresh mode.

CKE0-CKE1

S0-S1

Input

Enables the associated DDR3 SDRAM command decoder when low and disables the command

decoder when high. When the command decoder is disabled, new commands are ignored but previous operations

continue. Rank 0 is selected by S0; Rank 1 is selected by S1.

When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define

the operation to be executed by the SDRAM.

RAS, CAS, WE

BA0-BA2

Input

Selects which DDR3 SDRAM internal bank of eight is activated.

Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3

SDRAM mode register.

ODT0-ODT1

During a Bank Activate command cycle, defines the row address when sampled at the cross

point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle,

defines the column address when sampled at the cross point of the rising edge of CK and falling

edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and

BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a

Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to

precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn

inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

A0-A9,

A10/AP,

A11

A12/BC

A13-A15

Input

A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly)

will be performed (HIGH, no burst chop; LOW, burst chopped)

DQ0-DQ63

DM0-DM7

I/O

Data Input/Output pins.

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write operation if it is high. In

Read mode, DM lines have no effect.

Input

The data strobes, associated with one data byte, sourced with data transfers. In Write mode,

the data strobe is sourced by the controller and is centered in the data window. In Read mode,

the data strobe is sourced by the DDR3 SDRAMs and is sent at the leading edge of the data

window. DQS signals are complements, and timing is relative to the crosspoint of respective

DQS and DQS.

DQS0-DQS7

I/O

V_DD,V_DDSPD,

V_SS

Supply

Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.

Reference voltage for SSTL15 inputs.

V_REFDQ,

V_REFCA

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be

connected from the SDA bus line to VDDSPD on the system planar to

act as a pull up.

SDA

I/O

SCL

SA0-SA1

TEST

Input

I/O

This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.

Address pins used to select the Serial Presence Detect and Temp sensor base address.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules

The EVENT pin is reserved for use to flag critical module temperature. A resistor may be connected from EVENT bus

line to V_DDSPDon the system planar to act as a pullup.

Wire-OR

Out

EVENT

RESET

Input

RESET In Active Low This signal resets the DDR3 SDRAM

7 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

8.0 Functional Block Diagram:

8.1 512MB, 64Mx64 Module(Populated as 1 rank of x16 DDR3 SDRAMs)

SCL

SA0

SA1

SCL

A0

240Ω

DQS0

DM0

LDQS

LDM

± 1%

Temp Sensor

(with SPD)

EVENT

SDA

ZQ

A1

The SPD may be

DQ[0:7]

DQS1

DM1

DQ[0:7]

UDQS

UDM

A2

integrated with the Temp

Sensor or may be

D0

EVENT

a separate component.

DQ[8:15]

V

tt

V

SPD

SPD/TS

DD

240Ω

DQS2

LDQS

LDM

± 1%

V

CA

D0 - D3

REF

ZQ

DM2

DQ

D0 - D3

REF

DQ[16:23]

DQS3

DQ[0:7]

UDQS

UDM

D1

V

D0 - D3

DD

DQS3

V

D0 - D3, SPD, Temp sensor

D0 - D3

DM3

SS

DQ[8:15]

DQ[24:31]

CK0

CK1

ODT1

S1

D0 - D3

Terminated near

card edge

NC

240Ω

DQS4

LDQS

LDM

± 1%

ZQ

DM4

NC

DQ[32:39]

DQS5

DQ[0:7]

UDQS

UDM

Temp sensor

D0 - D3

EVENT

RESET

D2

DQS5

DM5

DQ[8:15]

DQ[40:47]

D0

D1

D2

D3

240Ω

DQS6

LDQS

LDM

± 1%

ZQ

DM6

DQ[48:55]

DQS7

DQ[0:7]

UDQS

UDM

D3

Address and Controllines

DQS7

DM7

DQ[8:15]

DQ[56:63]

Note :

1. DQ wiring may differ from that shown

however ,DQ, DM, DQS and DQS

relationships are maintained as shown

Vtt

Rank0

V

DD

8 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

8.2 1GB, 128Mx64 Module(Populated as 2 rank of x16 DDR3 SDRAMs)

SCL

SA0

SA1

SCL

A0

240Ω

DQS0

DM0

LDQS

LDM

LDQS

LDM

± 1%

Temp Sensor

(with SPD)

EVENT

SDA

ZQ

A1

The SPD may be

DQ[0:7]

DQS1

DM1

DQ[0:7]

UDQS

UDM

DQ[0:7]

UDQS

UDM

A2

integrated with the Temp

Sensor or may be

D0

D4

EVENT

a separate component.

DQ[8:15]

240Ω

DQS2

LDQS

LDM

LDQS

LDM

± 1%

ZQ

DM2

DQ[16:23]

DQS3

DQ[0:7]

UDQS

UDM

UDQS

UDM

D1

D5

V

tt

DQS3

tt

DM3

V

SPD

CA

SPD/TS

D0 - D7

DD

DQ[8:15]

DQ[24:31]

V

REF

DQ

REF

V

DD

V

D0 - D7, SPD, Temp sensor

D0 - D3

SS

240Ω

DQS4

LDQS

LDM

LDQS

LDM

CK0

CK1

CK0

CK1

± 1%

ZQ

DM4

D4 - D7

DQ[32:39]

DQS5

DQ[0:7]

UDQS

UDM

D0 - D3

UDQS

UDM

D2

D6

DQS5

D4 - D7

DM5

DQ[8:15]

Temp Sensor

D0 - D7

DQ[40:47]

EVENT

RESET

240Ω

DQS6

LDQS

LDM

LDQS

LDM

± 1%

ZQ

DM6

DQ[48:55]

DQS7

DQ[0:7]

UDQS

UDM

UDQS

UDM

D3

D7

DQS7

D4

D0

D5

D6

D2

D7

V4

DM7

V1

V2

V3

DQ[8:15]

DQ[56:63]

Rank0

Rank1

V3

V4

D3

D1

Vtt

V

DD

Address and Controllines

Note :

1. DQ wiring may differ from that shown

however ,DQ, DM, DQS and DQS

relationships are maintained as shown

9 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

8.3 2GB, 256Mx64 Module(Populated as 2 rank of x8 DDR3 SDRAMs)

V

DD

Vtt

240Ω

DQS3

DQS4

DQS

DM

DQS

DM

DQS

DM

DQS

DM

± 1%

DQS4

ZQ

DM3

DM4

DQ[0:7]

DQ[24:31]

DQ[32:39]

D11

D3

D11

D3

240Ω

DQS1

DQS6

DQS

DM

DQS

DM

DQS

DM

DQS

DM

± 1%

DQS6

ZQ

DM1

DM6

DQ[0:7]

DQ[8:15]

DQ[48:55]

D1

D9

D1

D9

240Ω

DQS0

DM0

DQS7

DQS

DM

DQS

DM

DQS

DM

DQS

DM

± 1%

DQS7

ZQ

Rank0

Rank1

ZQ

DM7

DQ[0:7]

DQ[56:63]

D0

D8

D0

D8

240Ω

DQS2

DQS5

DQS

DM

DQS

DM

DQS

DM

DQS

DM

± 1%

DQS5

ZQ

D10

DM2

DM5

DQ[0:7]

DQ[16:23]

DQ[40:47]

D2

D10

D2

V2

V1

V8

D9

V3

D3

D12

D5

D6

V7

V9

V5

V

tt

V

SPD

CA

SPD/TS

D0 - D15

D8

D10

D7

DD

V4

V6

V

REF

DQ

REF

SCL

SA0

SA1

SCL

Temp Sensor

A0

A1

A2

SDA

V

D0

D2

D13

D4

D15

DD

(with SPD)

EVENT

V5

tt

The SPD may be

V

D0 - D15, SPD, Temp sensor

D0 - D7

SS

V3

D1

V7

D14

V

V1

integrated with the Temp

Sensor or may be

CK0

CK1

CK0

CK1

D11

EVENT

a separate component.

V2

V9

V8

D8 - D15

D0 - D7

D8 - D15

Address and Controllines

Temp Sensor

D0 - D7

EVENT

RESET

Note :

1. DQ wiring may differ from that shown

however ,DQ, DM, DQS and DQS

relationships are maintained as shown

10 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

9.0 Absolute Maximum Ratings

9.1 Absolute Maximum DC Ratings

Symbol

VDD

Parameter

Rating

Units

Notes

1,3

1

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on any pin relative to Vss

-0.4 V ~ 1.975 V

V

VDDQ

V_IN,V_OUT

T_STG

Storage Temperature

-55 to +100

°C

1, 2

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6XVDDQ, When VDD and VDDQ are less than

500mV; VREF may be equal to or less than 300mV.

9.2 DRAM Component Operating Temperature Range

Symbol

Parameter

Normal Operating Temperature Range

rating

0 to 85

85 to 95

Unit

°C

Notes

1,2

TOPER

Extended Temperature Range (Optional)

°C

1,3

Note :

1. Operating Temperature T_OPERis the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the

JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case tem-

perature must be maintained between 0-85°C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaran-

teed in this range, but the following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9us. It is also possible to specify a component

with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with

Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 =

0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and

tREFI requirements in the Extended Temperature Range.

10.0 AC & DC Operating Conditions

10.1 Recommended DC Operating Conditions (SSTL - 15)

Rating

Typ.

1.5

Symbol

Parameter

Units

Notes

Min.

1.425

Max.

1.575

VDD

Supply Voltage

Supply Voltage for Output

V

1,2

VDDQ

1.5

Note :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

11 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

11.0 AC & DC Input Measurement Levels

11.1 AC and DC Logic input levels for single-ended signals

DDR3-800/1066/1333

Symbol

Parameter

Unit

Notes

Min.

VREF + 100

Max.

VDD

V_IH(DC)

V_IL(DC)

dc input logic high

mV

1

dc input logic low

ac input logic high

VSS

VREF - 100

-

V

_IH(AC)

VREF + 175

1,2

V_IL(AC)

ac input logic low

-

VREF - 175

0.51*VDDQ

mV

V

1,2

3,4

VREFDQ(DC)

VREFCA(DC)

I/O Reference Voltage(DQ)

I/O Reference Voltage(CMD/ADD)

0.49*VDDQ

V

Single Ended AC and DC input levels

Note :

1. For DQ and DM, V_REF= V_REFDQ. For input only pins except RESET, or V_REF= V_REFCA

2. See "Overshoot and Undershoot specifications" on component datasheet

3. The ac peak noise on V_REFmay not allow V_REFto deviate from V_REF(DC)by more than ± 1% VDD (for reference : approx. ± 15mV)

4. For reference : approx. VDD/2 ± 15mV

5. Single ended swing requirement for DQS - DQS is 350 mV(peak to peak). Differential swing requirement for DQS - DQS is 700 mV(peak to peak).

The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage

VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).

VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in above

table. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.

voltage

VDD

V

(t)

Ref

V

ac-noise

Ref

V

(DC)max

Ref

V

(DC)

Ref

VDD/2

V

(DC)min

Ref

VSS

time

Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef.

"VRef" shall be understood as VRef(DC), as defined in above Figure.

This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing

and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

12 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

11.2 Differential swing requirement for differntial signals

Definition of differntial ac-swing and "time above ac level tDVAC

tDVAC

VIHdiff(ac) min

VIHdiff min

VIHdiff(dc) min

0.0

CK - CK

DQS - DQS

VILdiff(dc) max

VILdiff max

VILdiff(ac) max

differential

voltage

time

half cycle

tDVAC

time

Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

DDR3-800 / 1066 / 1333

Symbol

Parameter

unit

Note

min

+0.2

max

VIHdiff

VILdiff

differential input high

differential input low

note 3

V

1

2

note 3

-0.2

VIHdiff(ac)

VILdiff(ac)

differential input high ac

differential input low ac

2 x (VIH(ac)-Vref)

note 3

2 x (Vref - VIL(ac))

Notes:

1. used to define a differential signal slew-rate.

2. for CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(ac) of DQs and VREFDQ; if a

reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. these values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.

Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.

tDVAC [ps] @ |VIH/Ldiff(ac)| = 350mV

tDVAC [ps] @ |VIH/Ldiff(ac)| = 300mV

Slew Rate [V/ns]

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

> 4.0

4.0

-

3.0

2.0

1.8

1.6

1.4

1.2

1.0

< 1.0

0

13 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

11.2.1 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain

requirements for single-ended signals.

CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(ac) / VIL(ac) ) for ADD/CMD

signals) in every half-cycle.

DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(ac) / VIL(ac) ) for DQ signals)

in every half-cycle preceeding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(ac)/VIL150(ac) is used for

ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK

VDD or VDDQ

VSEH min

VSEH

VDD/2 or VDDQ/2

CK or DQS

VSEL max

VSEL

VSS or VSSQ

time

Single-ended requirement for differential signals.

Note that while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have

a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to

measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing

on timing, but adds a restriction on the common mode charateristics of these signals.

Each single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU

DDR3-800/1066/1333

Symbol

VSEH

VSEL

Parameter

Unit

Notes

Min

VIH(ac)-VREFDQ+VDDQ/2

VIH(ac)-VREFCA+VDDQ/2

Note3

Max

Note3

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes

Single-ended low-level for CK, CK

V

1, 2

VIL(ac)+VREFDQ-VDDQ/2

VIL(ac)+VREFCA-VDDQ/2

Note3

Notes:

1. for CK, CK use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(ac) of DQs.

2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a

signal group, then the reduced level applies also here

3. these values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective

limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot.

14 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

11.3 AC and DC logic input levels for Differential Signals

Differential DC and AC input levels

DDR3-800/1066/1333

Symbol

Parameter

Unit

Notes

Min

+ 200

-

Max

-

- 200

VIHdiff

VILdiff

Differential input logic high

Differential input logic low

mV

1

Note :

1. Refer to "Overshoot and Undershoot specifications" on component datasheet

11.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input

signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual

cross point of true and complement signal to the midlevel between of VDD and VSS.

VDD

CK, DQS

V_IX

VDD/2

V_IX

CK, DQS

VSS

Vix Definition

Cross point voltage for differential input signals (CK, DQS)

DDR3-800/1066/1333

Symbol

Parameter

Unit

Notes

Min

Max

150

175

150

-150

-175

-150

mV

VIX

Differential input Cross point voltage relative to VDD/2 for CK/CK

Differential input Cross point voltage relative to VDD/2 for DQS/DQS

1

Note 1: Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing

VSEL/VSEH of at least VDD/2 +/-250 mV and if the differential slew rate of CK-CK is larger than 3 V/ns.

15 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

11.5 Slew rate definition for Single Ended Input Signals

11.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)

Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of

VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing

of VIL(AC)max.

11.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)

Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VRef. Hold (tIH &

tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VRef

Measured

From

Description

Defined by

Applicable for

To

Vih(AC)min-Vref

Delta TRS

Vref-Vil(AC)max

Delta TFS

Vref-Vil(DC)max

Delta TFH

Vih(DC)min-Vref

Delta TRH

Input slew rate for rising edge

Input slew rate for falling edge

Input slew rate for rising edge

Input slew rate for falling edge

Vref

Vih(AC)min

Setup

(tIS,tDS)

Vil(AC)max

Vref

Vil(DC)max

Vih(DC)min

Hold

(tIH,tDH)

Vref

Single Ended Input Slew Rate definition

Notes: This nominal slew rate applies for linear signal waveforms.

V

DDQ

IH(ac)

IH(dc)

REF

DDQ

IH(ac)

IH(dc)

REF

V

min

V

SWING(MAX)

max

IL(dc)

IL(ac)

SSQ

IL(dc)

IL(ac)

SSQ

delta TRS

delta TFS

delta TFH

delta TRH

< Figure : Input slew rate for setup>

< Figure : Input slew rate for Hold>

Input Nominal Slew Rate definition for Singel ended Signals

11.6 Slew rate definition for Differential Input Signals

Measured

From

Description

Defined by

To

VIHdiffmin - VILdiffmax

Delta TRdiff

VIHdiffmin - VILdiffmax

Delta TFdiff

Differential input slew rate for rising edge (CK-

VILdiffmax

VIHdiffmin

CK and DQS-DQS)

Differential input slew rate for falling edge (CK-

CK and DQS-DQS)

VILdiffmax

Differential input slew rate definition

Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds

VIHdiffmin

V

REF

VILdiffmax

delta TFdiff

delta TRdiff

Differential Input Slew Rate definition for DQS, DQS and CK, CK

16 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

12.0 AC and DC Output Measurement Levels

12.1 Single Ended AC and DC Output Levels

Single Ended AC and DC output levels

Symbol Parameter

DDR3-800/1066/1333

Units

Notes

V_OH(DC)DC output high measurement level (for IV curve linearity)

0.8 x VDDQ

V

V_OM(DC)DC output mid measurement level (for IV curve linearity)

V_OL(DC)DC output low measurement level (for IV curve linearity)

V_OH(AC)AC output high measurement level (for output SR)

V_OL(AC)AC output low measurement level (for output SR)

0.5 x VDDQ

0.2 x VDDQ

V

VTT + 0.1 x VDDQ

VTT - 0.1 x VDDQ

1

Note :

1. The swing of +/-0.1xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 34ohms and

an effective test load of 25ohms to VTT=VDDQ/2.

12.2 Differential AC and DC Output Levels

Differential AC and DC output levels

Symbol Parameter

V_OHdiff(AC)AC differential output high measurement level (for output SR)

V_OLdiff(DC)AC differential output low measurement level (for output SR)

DDR3-800/1066/1333

+0.2 x VDDQ

Units

V

Notes

1

-0.2 x VDDQ

Note :

1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 34ohms and

an effective test load of 25ohms to VTT=VDDQ/2 at each of the differential outputs

17 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

12.3.Single Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)

for single ended signals as shown in below Table and figure.

Single Ended Output slew rate definition

Measured

Description

Defined by

From

To

VOH(AC)-VOL(AC)

Delta TRse

Single ended output slew rate for rising edge

VOL(AC)

VOH(AC)

VOH(AC)-VOL(AC)

Delta TFse

Single ended output slew rate for falling edge

VOH(AC)

VOL(AC)

Single Ended Output slew rate

DDR3-800

DDR3-1066

DDR3-1333

Parameter

Symbol

SRQse

Units

Min

2.5

Max

Min

2.5

Max

Min

Max

Single ended output slew rate

5

2.5

5

V/ns

Note : Output slew rate is verified by design and characterization, and may not be subject to production test.

For Ron=RZQ/7 setting

V

DDQ

OH(AC)

V

REF

V

OL(AC)

SSQ

delta TFS

delta TRS

Single Ended Output Slew Rate definition

12.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and

VOHdiff(AC) for differential signals as shown in below Table and figure.

Differential Output slew rate definition

Measured

Description

Defined by

From

To

VOHdiff(AC)-VOLdiff(AC)

Delta TRdiff

Differential output slew rate for rising edge

Differential output slew rate for falling edge

Differential Output slew rate

VOLdiff(AC)

VOHdiff(AC)

VOHdiff(AC)-VOLdiff(AC)

Delta TFdiff

VOHdiff(AC)

VOLdiff(AC)

DDR3-800

Max

10

DDR3-1066

DDR3-1333

Parameter

Symbol

SRQse

Units

Min

5

Min

Max

Min

Max

10

Single ended output slew rate

5

10

5

V/ns

Note : Output slew rate is verified by design and characterization, and may not be subject to production test.

For Ron=RZQ/7 setting

V

DDQ

OHdiff(AC)

V

REF

V

OLdiff(AC)

SSQ

delta TFdiff

delta TRdiff

Differential Output Slew Rate definition

18 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

13.0 IDD specification

(IDD values are for full operating range of Voltage and Temperature)

Symbol

Conditions

Operating one bank active-precharge current;

CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Max

Units

Notes

t

IDD0

TBD

mA

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD),

t

IDD1

TBD

mA

t

RCD = RCD(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data pattern is same as IDD4W

Precharge power-down current;

t

IDD2P

IDD2Q

IDD2N

IDD3P

t

TBD

mA

All banks idle; CK = CK(IDD); CKE is LOW;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge quiet standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH;

Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS is HIGH;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Active power-down current;

t

All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

Active standby current;

All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD);

CKE is HIGH, CS is HIGH between valid commands;

t

IDD3N

IDD4W

IDD4R

TBD

mA

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current;

All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-

t

max(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs

are SWITCHING;Data bus inputs are SWITCHING

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; CK = CK(IDD),

t

RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address

bus inputs are SWITCHING; Data pattern is same as IDD4W

Burst refresh current;

CK = CK(IDD); Refresh command at every RFC(IDD) interval;

t

IDD5B

IDD6

TBD

mA

CKE is HIGH, CS is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

CK and CK at 0V; CKE ≤ 0.2V;

Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING

Extended Temperature Range Self-Refresh Current;

CK and CK at 0V; CKE ≤ 0.2V;

Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled,

Applicable for MR2 setting A6=0 and A7=1

IDD6ET

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK =

t

IDD7

t

TBD

mA

CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD);

CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;

19 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

13.1 IDD specification

M471B6474DZ1 : 512MB (64Mx64) Module

F7

F8

G8

H9

Symbol

Units

Notes

(DDR3 - 800 @ CL = 6)

(DDR3 - 1066 @ CL = 7)

(DDR3 - 1066 @ CL = 8)

(DDR3 - 1333 @ CL = 9)

IDD0

TBD

mA

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD6ET

IDD6TC

IDD7

M471B2874DZ1 : 1GB (128Mx64) Module

F7

F8

G8

H9

Symbol

Units

Notes

(DDR3 - 800 @ CL = 6)

(DDR3 - 1066 @ CL = 7)

(DDR3 - 1066 @ CL = 8)

(DDR3 - 1333 @ CL = 9)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD6ET

IDD6TC

IDD7

M471B5673DZ1 : 2GB (256Mx64) Module

F7

F8

G8

H9

Symbol

Units

Notes

(DDR3 - 800 @ CL = 6)

(DDR3 - 1066 @ CL = 7)

(DDR3 - 1066 @ CL = 8)

(DDR3 - 1333 @ CL = 9)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD6ET

IDD6TC

IDD7

20 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

14.0 Input/Output Capacitance

14.1. 1Rx16 512MB SoDIMM

M471B6474DZ1

DDR3-1066

DDR3-800

Min

Parameter

Symbol

Units

Notes

Max

Min

Max

Input/output capacitance

(DQ, DM, DQS, DQS, TDQS, TDQS)

CIO

-

TBD

-

TBD

pF

Input capacitance

(CK and CK)

CCK

TBD

Input capacitance

(All other input-only pins)

CI

-

TBD

-

TBD

pF

Input/output capacitance of ZQ pin

CZQ

14.2. 2Rx16 1GB SoDIMM

M471B2874DZ1

DDR3-1066

DDR3-800

Min

Parameter

Symbol

Units

Max

Min

Max

Input/output capacitance

(DQ, DM, DQS, DQS, TDQS, TDQS)

CIO

-

TBD

-

TBD

pF

Input capacitance

(CK and CK)

CCK

-

TBD

-

TBD

Input capacitance

(All other input-only pins)

CI

-

TBD

-

TBD

pF

Input/output capacitance of ZQ pin

CZQ

14.3. 2Rx8 2GB SoDIMM

M471B5673DZ1

DDR3-1066

DDR3-800

Min

Parameter

Symbol

Units

Max

Min

Max

Input/output capacitance

CIO

-

TBD

-

TBD

pF

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance

(CK and CK)

CCK

-

TBD

-

TBD

Input capacitance

CI

-

TBD

-

TBD

pF

(All other input-only pins)

Input/output capacitance of ZQ pin

CZQ

21 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

15.0 Electrical Characteristics and AC timing

(0 °C<T_CASE≤95 °C, V_DDQ= 1.5V ± 0.075V; V_DD= 1.5V ± 0.075V)

15.1 Refresh Parameters by Device Density

Parameter

All Bank Refresh to active/refresh cmd time

Symbol

tRFC

512Mb

90

1Gb

110

7.8

2Gb

160

7.8

4Gb

300

7.8

8Gb

350

7.8

Units

ns

0 °C ≤ T_CASE≤ 85°C

7.8

µs

Average periodic refresh interval

tREFI

85 °C < T_CASE≤ 95°C

3.9

µs

15.2 DDR3 SDRAM tRCD, tRP and tRC

Speed

Bin (CL - tRCD - tRP)

Parameter

CL

DDR3-800

DDR3-1066

DDR3-1333

Units

Note

6-6-6

min

6

7-7-7

min

7

8-8-8

min

8

9-9-9

min

9

tCK

ns

tRCD

15

13.13

37.5

50.63

7.5

15

13.5

36

tRP

15

tRAS

37.5

52.5

10

37.5

52.5

7.5

10

tRC

49.5

6

tRRD [1KB]

tRRD [2KB]

tFAW [1KB]

tFAW [2KB]

10

7.5

30

40

37.5

50

37.5

50

45

DDR3-800 Speed Bins

Speed

DDR3-800

6 - 6 - 6

CL-nRCD-nRP

Units

Note

Parameter

Symbol

t_AA

t_RCD

t_RP

t_RC

t_RAS

t_CK(AVG)

min

15

52.5

37.5

max

20

-

Intermal read command to first data

ACT to internal read or write delay time

PRE command period

ACT to ACT or REF command period

ACT to PRE command period

CL = 5 / CWL = 5

ns

-

9*tREFI

Reserved

9)

ns

1)2)3)4)

1)2)3)

CL = 6 / CWL = 5

2.5

3.3

Supported CL Settings

Supported CWL Settings

6

5

n_CK

22 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

DDR3-1066 Speed Bins

Speed

CL-nRCD-nRP

DDR3-1066

7 - 7 - 7

DDR3-1066

8 - 8 - 8

Units

Note

Parameter

Symbol

t_AA

t_RCD

t_RP

t_RC

min

max

20

-

min

15

52.5

37.5

2.5

max

20

-

Intermal read command to first data

ACT to internal read or write delay time

PRE command period

ACT to ACT or REF command period

ACT to PRE command period

13.125

50.625

37.5

ns

t_RAS

9*tREFI

3.3

9*tREFI

3.3

8

CWL = 5

CWL = 6

CWL = 5

CWL = 6

CWL = 5

CWL = 6

t_CK(AVG)

2.5

1,2,3,6

1,2,3,4

4

1,2,3,4

4

CL = 6

Reserved

CL = 7

1.875

<2.5

Reserved

ns

CL = 8

1.875

<2.5

1,2,3

Supported CL Settings

Supported CWL Settings

6,7,8

5,6

6,8

5,6

n_CK

DDR3-1333 Speed Bins

Speed

DDR3-1333

9 -9 - 9

CL-nRCD-nRP

Units

Note

Parameter

Intermal read command to first data

ACT to internal read or write delay time

PRE command period

ACT to ACT or REF command period

ACT to PRE command period

Symbol

t_AA

t_RCD

t_RP

t_RC

min

13.5

49.5

36

max

20

-

ns

n_CK

-

t_RAS

9*tREFI

3.3

8

1,2,3,7

1,2,3,4,7

4

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5,6

CWL = 7

CWL = 5,6

t_CK(AVG)

2.5

CL = 6

CL = 7

Reserved

4

1,2,3,4,7

1,2,3,4,

4

1,2,3,7

1,2,3,4,

4

1,2,3,4

4

1,2,3

5

CL = 8

CL = 9

CL = 10

1.875

<2.5

Reserved

1.5

<1.875

Reserved

CWL = 7

t_CK(AVG)

(Optional)

6,8,9

5,6,7

Supported CL Settings

Supported CWL Settings

NOTES:

Absolute Specification (TOPER;VDDQ=VDD=1.5V +/- 0.075V);

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful-

filed: Requirements from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen-

cies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat-

ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ’Supported CL’.

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the next valid speed bin limit (i.e.

3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSELECTED.

4. ’Reserved’ settings are not allowed. User must program a different value.

5. ’Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature.

6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but

verified by Design/Characterization.

7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but

verified by Design/Characterization.

8. tREFI depends on TOPER

23 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

15.3 Timing parameters for DDR3-800, DDR3-1066 and DDR3-1333

Timing Parameters by Speed Bin

Speed

DDR3-800

DDR3-1066

DDR3-1333

Units

Note

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period

t

8

-

8

-

8

-

ns

ps

6

f

CK(DLL_OFF)

t

See Speed Bins Table

CK(avg)

CK(abs)

CH(avg)

tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +

Clock Period

ps

tJIT(per)min

0.47

tJIT(per)max

tJIT(per)min

0.47

tJIT(per)max

tJIT(per)min

0.47

tJIT(per)max

Average high pulse width

t

0.53

100

90

0.53

90

0.53

80

t

f

CK(avg)

Average low pulse width

t

0.47

CL(avg)

CK(avg)

ps

Clock Period Jitter

tJIT

-100

-90

-80

(per)

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

tJIT

-90

-80

80

-70

70

ps

PS

(per, lck)

tJIT

200

180

160

140

(cc)

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tJIT

(cc, lck)

t

- 147

- 175

- 194

- 209

- 222

- 232

- 241

- 249

- 257

- 263

- 269

147

175

194

209

222

232

241

249

257

263

269

- 132

- 157

- 175

- 188

- 200

- 209

- 217

- 224

- 231

- 237

- 242

132

157

175

188

200

209

217

224

231

237

242

- 118

- 140

- 155

- 168

- 177

- 186

- 193

- 200

- 205

- 210

- 215

118

140

155

168

177

186

193

200

205

210

215

ERR(2per)

ERR(3per)

ERR(4per)

ERR(5per)

ERR(6per)

ERR(7per)

ERR(8per)

ERR(9per)

t

ERR(10per)

ERR(11per)

ERR(12per)

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

Cumulative error across n = 13, 14 ... 49, 50 cycles

t

PS

24

ERR(nper)

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

t

0.43

t

25

26

CH(abs)

CK(avg)

t

0.43

CL(abs)

DQS,DQS to DQ skew, per group, per access

DQ output hold time from DQS, DQS

DQ low-impedance time from CK, CK

DQ high-impedance time from CK, CK

t

-

200

-

150

-

125

-

100

-

DQSQ

t

0.38

-800

-

0.38

-600

-

0.38

-500

-

0.38

-450

-

QH

t

400

300

250

225

LZ(DQ)

t

HZ(DQ)

Data setup time to DQS, DQS referenced to Vih(ac)Vil(ac)

levels

t

75

25

TBD

-

TBD

-

DS(base)

Data hold time to DQS, DQS referenced to Vih(ac)Vil(ac)

levels

t

150

600

100

490

TBD

400

-

DH(base)

DQ and DM Input pulse width for each input

Data Strobe Timing

t

-

DIPW

DQS, DQS READ Preamble

DQS, DQS differential READ Postamble

DQS, DQS output high time

t

0.9

0.3

-

0.9

0.3

-

0.9

0.3

0.4

0.9

0.3

-

t

13, 19, g

11, 13, b

13, g

RPRE

CK

t

NOTE1

RPST

t

0.38

0.9

-

0.38

0.9

-

t

QSH

CK(avg)

DQS, DQS output low time

t

13, g

QSL

DQS, DQS WRITE Preamble

DQS, DQS WRITE Postamble

t

WPRE

CK

t

0.3

WPST

DQS, DQS rising edge output access time from rising CK,

CK

t

-400

-800

-

400

-300

-600

-

300

-255

-500

-

255

250

ps

13,f

DQSCK

LZ(DQS)

HZ(DQS)

DQS, DQS low-impedance time (Referenced from RL-1)

t

13,14,f

12,13,14

DQS, DQS high-impedance time (Referenced from RL+BL/

2)

t

DQS, DQS differential input low pulse width

t

0.4

0.6

0.25

-

0.4

0.6

0.25

-

0.4

0.6

0.25

-

t

DQSL

CK

DQS, DQS differential input high pulse width

DQS, DQS rising edge to CK, CK rising edge

DQS,DQS faling edge setup time to CK, CK rising edge

DQS,DQS faling edge hold time to CK, CK rising edge

t

DQSH

t

-0.25

0.2

-0.25

0.2

-0.25

0.2

t

c

DQSS

CK(avg)

t

DSS

DSH

t

0.2

-

0.2

-

0.2

-

24 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

Timing Parameters by Speed Bin (Cont.)

Speed

DDR3-800

DDR3-1066

DDR3-1333

Units

Note

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

Command and Address Timing

DLL locking time

t

512

-

512

-

512

-

nCK

DLLK

max

internal READ Command to PRECHARGE Command delay

t

e

RTP

(4t ,7.5ns)

CK

(4t ,7.5ns)

CK

(4t ,7.5ns)

CK

Delay from start of internal write transaction to internal read

command

max

t

-

e,18

e

WTR

(4t ,7.5ns)

CK

(4t ,7.5ns)

CK

(4t ,7.5ns)

CK

WRITE recovery time

t

15

4

-

15

4

-

15

4

-

ns

WR

Mode Register Set command cycle time

t

CK(avg)

MRD

max

Mode Register Set command update delay

t

-

MOD

(12t ,15ns)

CK

(12t ,15ns)

CK

(12t ,15ns)

CK

CAS# to CAS# command delay

t

4

nCK

ns

CCD

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

t

WR + roundup (t / t

)

DAL(min)

RP CK(AVG)

t

1

-

1

-

1

-

MPRR

t

37.5

max

70,000

37.5

max

70,000

36

70,000

e

RAS

max

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

t

-

RRD

(4t ,10ns)

CK

(4t ,7.5ns)

CK

(4t ,6ns)

CK

max

e

RRD

(4t ,10ns)

CK

(4t ,10ns)

CK

(4t ,7.5ns)

CK

Four activate window for 1KB page size

Four activate window for 2KB page size

t

40

50

-

37.5

50

-

30

45

-

ns

e

FAW

Command and Address setup time to CK, CK referenced to

Vih(ac) / Vil(ac) levels

t

200

275

-

125

200

-

65

140

-

ps

b,16

-

IS(base)

Command and Address hold time from CK, CK referenced to

Vih(ac) / Vil(ac) levels

t

IH(base)

Command and Address setup time to CK, CK referenced to

Vih(ac) / Vil(ac) levels

t

IS(base)

65+125

ps

ns

b,16,27

AC150

Refresh Timing

1Gb REFRESH to REFRESH OR REFRESH to ACTIVE

command interval

t

110

-

110

-

110

-

RFC

Average periodic refresh interval (0°C ≤ TCASE ≤ 85 °C)

Average periodic refresh interval (85°C ≤ TCASE ≤ 95 °C)

Calibration Timing

t

7.8

3.9

7.8

3.9

7.8

3.9

us

REFI

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation short calibration time

Reset Timing

t

512

256

64

-

512

256

64

-

512

256

64

-

t

ZQinitI

CK

t

ZQoper

t

23

ZQCS

max(5t , t

CK RFC

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

t

-

XPR

+ 10ns)

max(5t ,t

CK RFC

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

t

-

XS

+ 10ns)

(min)

+ 10ns)

(min)

+ 10ns)

(min)

t

XSDLL

DLLK

CK

t

(min) +

CK

t

(min) +

CK

t

(min) +

CKE

t

CKESR

1t

CK

Valid Clock Requirement after Self Refresh Entry (SRE)

Valid Clock Requirement before Self Refresh Exit (SRX)

t

max(5t ,10ns)

-

max(5t ,10ns)

-

max(5t ,10ns)

-

CKSRE

CKSRX

CK

max(5t ,10ns)

CK

max(5t ,10ns)

CK

25 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

Timing Parameters by Speed Bin (Cont.)

Speed

DDR3-800

DDR3-1066

DDR3-1333

Units

Note

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit

Percharge Power Down with DLL

max

t

-

XP

(3t ,7.5ns)

CK

(3t ,7.5ns)

CK

(3t ,6ns)

CK

frozen to commands not requiring a locked DLL

Exit Precharge Power Down with DLL frozen to commands

requiring a locked DLL

max

t

2

XPDLL

(10t ,24ns)

CK

(10t ,24ns)

CK

(10t ,24ns)

CK

max

CKE minimum pulse width

t

-

CKE

(3t ,7.5ns)

CK

(3t ,5.625ns)

CK

(3t ,5.625ns)

CK

Command pass disable delay

t

1

nCK

CPDED

Power Down Entry to Exit Timing

t

(min)

9*t

t

(min)

9*t

t

(min)

9*t

t

CK

15

20

PD

ACTPDEN

CKE

REFI

CKE

REFI

-

CKE

REFI

-

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

t

1

-

1

nCK

t

-

PRPDEN

RDPDEN

t

RL + 4 +1

WL + 4 +(t

RL + 4 +1

WL + 4 +(t

RL + 4 +1

WL + 4 +(t /

WR

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BL4OTF)

/

WR

t

-

nCK

9

10

9

WRPDEN

t

)

t

)

t

)

CK

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BL4OTF)

t

WL + 4 +WR +1

WL + 2 +(t

WL + 4 +WR +1

WL + 2 +(t

WL + 4 +WR +1

WL + 2 +(t

WRAPDEN

Timing of WR command to Power Down entry

(BL4MRS)

/

WR

t

WRPDEN

t

)

t

)

t

)

CK

Timing of WRA command to Power Down entry

(BL4MRS)

t

WL +2 +WR +1

1

WL +2 +WR +1

1

WL +2 +WR +1

1

10

WRAPDEN

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

ODT Timing

t

-

20,21

REFPDEN

t

CK

MRSPDEN

MOD(min)

ODT high time without write command or with wirte com-

mand and BC4

ODTH4

ODTH8

4

6

1

-

4

6

1

-

4

6

1

-

nCK

ns

ODT high time with Write command and BL8

Asynchronous RTT tum-on delay (Power-Down with DLL

frozen)

t

9

AONPD

Asynchronous RTT tum-off delay (Power-Down with DLL

frozen)

t

1

9

1

9

1

9

ns

ps

AOFPD

ODT turn-on

t

-400

0.3

400

-300

0.3

30

0.7

-250

0.3

250

7,f

8,f

f

AON

RTT_NOM and RTT_WR turn-off time from ODTLoff refer-

ence

t

0.7

t

AOF

CK(avg)

RTT dynamic change skew

t

ADC

Write Leveling Timing

First DQS pulse rising edge after tDQSS margining mode is

programmed

t

40

-

40

-

40

-

t

3

WLMRD

CK

DQS/DQS delay after tDQS margining mode is programmed

Setup time for tDQSS latch

t

25

325

0

-

25

245

0

-

25

195

0

-

WLDQSEN

CK

t

ps

ns

WLS

WLH

WLO

Hold time of tDQSS latch

t

-

Write leveling output delay

t

9

2

9

2

9

2

Write leveling output error

t

0

WLOE

26 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

Jitter Notes

Specific Note a

Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the

actual clock edges. ex) tMRD =4 [nCK] means; if one Mode Register Set command is registered at Tm, anothe Mode Register Set commdn may be reg-

istered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) +tERR(4per) min.

Specific Note b

These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective

clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold

are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.

Specific Note c

These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec val-

ues are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing.

That is, these parameters should be met whether clock jitter is present or not.

Specific Note d

These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U),

DQS(L/U)) crossing.

Specific Note e

For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all

input clock jitter specifications are satisfied.

For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For

DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e.

Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <=

12. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then

tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max -

tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and

tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)

Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured

value of tERR(nper) where 2 <= n <= 12

Specific Note g

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are

relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then

tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(der-

ated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)

27 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation"

8. For definition of RTT turn-off time tAOF see "Device Operation".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum postamble is bound by tHZDQS(max)

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter <8, 9> for definition and measurement method.

15. tREFI depends on TOPER

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

VREF(DC) = VrefDQ(DC). FOr input only pins except RESET, VRef(DC)=VRefCA(DC).

See "Address/ Command Setup, Hold and Derating" on page 52.

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,

VREF(DC)= VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC).

See "Data Setup, Hold and Slew Rate Derating" on page 58.

18. Start of internal write transaction is definited as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL

For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum preamble is bound by tLZDQS(max)

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The appropri-

ate interval between ZQCS commands can be determined from these tables and other application specific parameters. One method for calculating the interval

between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The

interval could be defined by the following formula:

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec

and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calculated as:

0.5

~

= 0.133

128ms

(1.5 x 1) + (0.15 x 15)

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-

nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

28 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

16.0 Physical Dimensions :

16.1 64Mbx16 based 64Mx64 Module(1 Rank)

Units : Millimeters

67.60

Max 3.8

1.00 ± 0.10

3.00

2X 1.80

0.10 M C A B

(OPTIONAL HOLES)

2X 4.00 ± 0.10

0.10 M C A B

0.60

0.45 ± 0.03

4.00 ± 0.10

2.55

0.25 MAX

1.00 ± 0.10

Detail A

Detail B

The used device is 64M x16 DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B1G1646D - HC**

29 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

16.2 64Mbx16 based 128Mx64 Module(2 Ranks)

Units : Millimeters

67.60

Max 3.8

1.00 ± 0.10

3.00

2X 1.80

0.10 M C A B

(OPTIONAL HOLES)

2X 4.00 ± 0.10

0.10 M C A B

0.60

0.45 ± 0.03

4.00 ± 0.10

2.55

0.25 MAX

1.00 ± 0.10

Detail A

Detail B

The used device is 64M x16 DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B1G1646D - HC**

30 of 31

Rev. 0.5 November 2007

Unbuffered SoDIMM

DDR3 SDRAM

16.3 128Mbx8 based 256Mx64 Module(2 Ranks)

Units : Millimeters

67.60

Max 3.8

1.00 ± 0.10

3.00

2X 1.80

0.10 M C A B

(OPTIONAL HOLES)

2X 4.00 ± 0.10

0.10 M C A B

0.60

0.45 ± 0.03

4.00 ± 0.10

2.55

0.25 MAX

1.00 ± 0.10

Detail A

Detail B

The used device is 128M x8 DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B1G0846D - HC**

31 of 31

Rev. 0.5 November 2007


型号：	M471B2874DZ1-CG8
厂家：	SAMSUNG
描述：	DDR DRAM Module, 128MX64, CMOS, ROHS COMPLIANT, SO-DIMM-204 动态存储器双倍数据速率内存集成电路
文件：	总31页 (文件大小：523K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M471B2874DZ1-CG8 [SAMSUNG]

相关型号：

M471B2874DZ1-CH9

M471B2874EH1

M471B2874EH1-CF8

M471B2874EH1-CH9

M471B5173QH0-YK0

M471B5273BH1

M471B5273CH0

M471B5273CH0-CK0

M471B5273DH0-CF8

M471B5273DH0-CH9

M471B5273DH0-CK0

M471B5273DH0-CMA