M485L2829CU0-CB0 [SAMSUNG]
DDR DRAM Module, 128MX72, 0.75ns, CMOS, SODIMM-200;型号: | M485L2829CU0-CB0 |
厂家: | SAMSUNG |
描述: | DDR DRAM Module, 128MX72, 0.75ns, CMOS, SODIMM-200 时钟 动态存储器 双倍数据速率 内存集成电路 |
文件: | 总25页 (文件大小:402K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM Unbuffered SODIMM
200pin Unbuffered SODIMM based on 512Mb C-die
with 64/72-bit ECC/Non ECC
66 TSOP-II with Pb-Free
(RoHS compliant)
Revision 0.2
October. 2004
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
512Mb C-die Revision History
Revision 0.0 (April, 2004)
- First version for internal review
Revision 0.1 (September, 2004)
- Preliminary spec release.
Revision 0.2 (October, 2004)
- Changed IDD current.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
200Pin Unbuffered SODIMM based on 512Mb C-die (x8, x16)
Ordering Information
Part Number
Density
256MB
512MB
256MB
512MB
1GB
Organization
32M x 64
Component Composition
Height
1,250mil
1,250mil
1,250mil
1,400mil
1,400mil
M470L3324CU0-C(L)CC/B3/A2/B0
M470L6524CU0-C(L)CC/B3/A2/B0
M485L3324CU0-C(L)CC/B3/A2/B0
M485L6523CU0-C(L)CC/B3/A2/B0
M485L2829CU0-C(L)A2/B0
32Mx16 (K4H511638C) * 4EA
32Mx16 (K4H511638C) * 8EA
32Mx16 (K4H511638C) * 5EA
64Mx8 (K4H510838C) * 9EA
st.128Mx8 (K4H1G0738C) * 9EA
64M x 64
32M x 72
64M x 72
128M x 72
Operating Frequencies
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
133MHz
166MHz
-
133MHz
133MHz
-
100MHz
133MHz
-
166MHz
200MHz
3-3-3
2.5-3-3
2-3-3
2.5-3-3
Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height - 256MB(non ECC/ECC SS, 1250mil), 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil)
• SSTL_2 Interface
• 66pin TSOP II Pb-Free package
• RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Pin Configurations (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
3
5
7
VREF
VSS
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
/CK2
VDD
CKE1
DU
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
2
4
6
8
VREF
VSS
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
136
138
140
142
144
146
148
150
152
DQ38
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
*DU/(RESET) 154
VSS
VSS
VDD
VDD
CKE0
*DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/CS1
DU
VSS
DQ36
DQ37
VDD
DM4
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
VDD
VSS
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
A12
A9
VSS
A7
A5
VSS
KEY
KEY
41
43
45
47
49
51
53
55
57
59
61
63
65
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
A3
A1
42
44
46
48
50
52
54
56
58
60
62
64
66
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VDD
A10/AP
BA0
/WE
/CS0
*DU(A13) 191
VSS
DQ32
DQ33
VDD
193
195
197
199
VDDSPD
VDDID
VSS
DQ30
DU
DQ26
DQS4
Note 1. * : These pins are not used in this module.
2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64(M470~ ) module, & used on x72(M485 ~ ) module.
3. Pins 95,122 are NC for 1Row module & used for 2Row moule(M470L6524CU0,M485L2829CU0).
Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed) DM0 ~ 7, 8(for ECC) Data - in mask
Power supply
BA0 ~ BA1
Bank Select Address
VDD
(2.5V for DDR266/333, 2.6V for DDR400)
Power Supply for DQS
(2.5V for DDR266/333, 2.6V for DDR400)
DQ0 ~ DQ63
Data input/output
VDDQ
DQS0 ~ DQS8
Data Strobe input/output
Clock input
VSS
Ground
CK0,CK0 ~ CK2, CK2
VREF
VDDSPD
SDA
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
CKE0, CKE1(for double banks) Clock enable input
CS0, CS1(for double banks)
Chip select input
RAS
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
CAS
SA0 ~ 2
NC
Address in EEPROM
No connection
WE
CB0 ~ CB7 (for x72 module)
Check bit(Data-in/data-out)
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
256MB, 32M x 64 Non ECC Module (M470L3324CU0) (Populated as 1 bank of x16 DDR SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS0
DQS0
DM0
LDQS
LDM
DQS4
DM4
LDQS
LDM
CS
CS
DQ 0
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
DQ 32
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
D0
D2
DQS1
DM1
DQ 8
UDQS
UDM
DQS5
DM5
DQ 40
UDQS
UDM
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
DQ 9
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQS2
DM2
DQ 16
LDQS
LDM
DQS6
DM6
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
LDQS
LDM
CS
CS
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
D1
D3
DQS3
DM3
DQ 24
UDQS
UDM
DQS7
DM7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
UDQS
UDM
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
BA0 - BA1
A0 - A12
BA0-BA1: DDR SDRAMs D0 - D3
A0-A12: DDR SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
D0/D2/Cap
RAS
Cap/Cap/Cap
CAS
CAS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
R=120
Ω
Clock Wiring
±
5%
Clock
Input
CKE0
SDRAMs
CK0/1/2
CK0/1/2
CK0/CK0
CK1/CK1
CK2/CK2
2 SDRAMs
2 SDRAMs
NC
WE
WE: SDRAMs D0 - D3
Card
Edge
D1/D3/Cap
Cap/Cap/Cap
V
DDSPD
SPD
V
/V
DD DDQ
Notes:
D0 - D3
D0 - D3
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
Serial PD
VREF
D0 - D3
SCL
D0 - D3
V
SS
SDA
WP
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
A0
A1
A2
SA0 SA1 SA2
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
512MB, 64M x 64 Non ECC Module (M470L6524CU0) (Populated as 2 bank of x16 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS0
DM0
LDQS
LDM
LDQS
LDM
DQS4
DM4
LDQS
LDM
LDQS
LDM
CS
CS
CS
CS
DQ 0
I/0 15
I/0 14
I/0 13
I/0 12
I/0 11
I/0 10
I/0 9
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQ 32
I/0 15
I/0 14
I/0 13
I/0 12
I/0 11
I/0 10
I/0 9
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
D0
D4
D2
D6
I/0 8
I/0 8
DQS1
DM1
DQ 8
UDQS
UDM
UDQS
UDM
DQS5
DM5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
UDQS
UDM
UDQS
UDM
I/0 7
I/0 6
I/0 5
I/0 4
I/0 3
I/0 2
I/0 1
I/0 0
I/0 8
I/0 9
I/0 7
I/0 6
I/0 5
I/0 4
I/0 3
I/0 2
I/0 1
I/0 0
I/0 8
I/0 9
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS2
DM2
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
LDQS
LDM
LDQS
LDM
DQS6
DM6
DQ48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
LDQS
LDM
LDQS
LDM
CS
CS
CS
CS
I/0 15
I/0 14
I/0 13
I/0 12
I/0 11
I/0 10
I/0 9
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
I/0 15
I/0 14
I/0 13
I/0 12
I/0 11
I/0 10
I/0 9
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
D1
D5
D3
D7
I/0 8
I/0 8
DQS3
DM3
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
UDQS
UDM
UDQS
UDM
DQS7
DM7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
UDQS
UDM
UDQS
UDM
I/0 7
I/0 6
I/0 5
I/0 4
I/0 3
I/0 2
I/0 1
I/0 0
I/0 8
I/0 9
I/0 7
I/0 6
I/0 5
I/0 4
I/0 3
I/0 2
I/0 1
I/0 0
I/0 8
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
*Clock Net Wiring
D0/D2/Cap
D1/D3/Cap
BA0 - BA1
A0 - A12
RAS
BA0-BA1: DDR SDRAMs D0 - D7
A0-A12: DDR SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
Clock Wiring
Clock
Input
R=120Ω
SDRAMs
CK0/1/2
CK0/1/2
CAS
CAS: SDRAMs D0 - D7
CK0/CK0
CK1/CK1
CK2/CK2
4 SDRAMs
4 SDRAMs
NC
Card
Edge
CKE0
CKE1
CKE: SDRAMs D0 - D3
CKE: SDRAMs D4 - D7
D4/D6/Cap
D5/D7/Cap
WE
WE: SDRAMs D0 - D7
V
DDSPD
SPD
Serial PD
V
/V
DD DDQ
D0 - D7
SCL
WP
Notes:
SDA
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
A0
A1
A2
VREF
D0 - D7
D0 - D7
V
SS
SA0 SA1
SA2
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
256MB, 32M x 72 ECC Module (M485L3324CU0) (Populated as 1 bank of x16 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
LDQS
LDM
DQS4
DM4
LDQS
LDM
DQS4
DM4
DQS
DM
CS
CS
CS
DQ 0
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
DQ 32
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
CB 0
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7
D0
D2
D4
DQS1
DM1
DQ 8
UDQS
UDM
DQS5
DM5
DQ 40
UDQS
UDM
UDQS
UDM
VDDQ
47K
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
I/0 7
I/0 6
I/0 5
I/0 4
I/0 3
I/0 2
I/0 1
I/0 0
DQ 9
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQS2
DM2
DQ 16
LDQS
LDM
DQS6
DM6
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
LDQS
LDM
CS
CS
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
I/0 15
I/0 14
I/0 13
I/0 12
I/0 8
I/0 9
I/0 10
I/0 11
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
D1
D3
D0/D2/D4
Cap/Cap/Cap
R=120
Ω
±
5%
DQS3
DM3
DQ 24
UDQS
UDM
DQS7
DM7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
UDQS
UDM
CK0/1/2
CK0/1/2
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
I/0 3
I/0 2
I/0 1
I/0 0
I/0 4
I/0 5
I/0 6
I/0 7
Card
Edge
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
D1/D3/Cap
Cap/Cap/Cap
Clock Wiring
SDRAMs
Clock
Input
CK0/CK0
CK1/CK1
CK2/CK2
2 SDRAMs
2 SDRAMs
1 SDRAMs
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D4
A0-A12: DDR SDRAMs D0 - D4
A0 - A12
RAS
RAS: SDRAMs D0 - D4
Serial PD
Notes:
SCL
WP
CAS
CAS: SDRAMs D0 - D4
CKE: SDRAMs D0 - D4
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
SDA
CKE0
A0
A1
A2
WE
WE: SDRAMs D0 - D4
SA0 SA1 SA2
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
V
DDSPD
SPD
V
/V
DD DDQ
D0 - D4
D0 - D4
VREF
D0 - D4
D0 - D4
V
SS
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
512MB, 64M x 72 ECC Module (M485L6523CU0) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DQS4
DM4
DM
I/O 3
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
CS
DQS
DQS
CS
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
D4
D0
DQS5
DQS1
DM1
DM5
DQS
DM
I/O 3
I/O 1
I/O 4
I/O 6
CS
DQS
CS
DM
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
D5
D1
I/O 2
I/O 0
I/O 5
I/O 7
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
DM
I/O 3
CS DQS
DM
I/O 7
I/O 5
I/O 0
I/O 2
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
D6
D2
I/O 6
I/O 4
I/O 1
I/O 3
DQS7
DM7
DQS3
DM3
* Clock Wiring
DDR SDRAMs
CS
DM
DQS
CS DQS
DM
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Clock
Input
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
D7
D3
CK0/CK0
CK1/CK1
5 DDR SDRAMs
4 DDR SDRAMs
*Clock Net Wiring
DQS8
DM8
D0/D4/Cap
CS
DM
DQS
I/O 0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D1/D5/Cap
D2/D6/Cap
I/O 1
I/O 2
I/O 3
I/O 7
I/O 6
I/O 5
I/O 4
D8
Serial PD
R=120Ω
SCL
WP
CK0/1/2
CK0/1/2
SDA
Card
Edge
D3/D7/Cap
A0
A1
A2
D8/Cap/Cap
SA0 SA1 SA2
Cap/Cap/Cap
BA0 - BA1
A0 - A12
BA0-BA1: DDR SDRAMs D0 - D8
A0-A12: DDR SDRAMs D0 - D8
V
DDSPD
Notes:
SPD
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms
+ 5%.
V
/V
DD DDQ
D0 - D8
D0 - D8
RAS
RAS: DDR SDRAMs D0 - D8
VREF
CAS
CAS: DDR SDRAMs D0 - D8
CKE: DDR SDRAMs D0 - D8
D0 - D8
D0 - D8
CKE0
V
SS
WE
WE: DDR SDRAMs D0 - D8
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
1GB, 128M x 72 ECC Module (M485L2829CU0) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS0
DM0
DQS4
DM4
DM
I/O 3
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
DM CS DQS
I/O 3
CS
DQS
DQS
DQS
CS
CS
DM
I/O 7
I/O 5
I/O 0
I/O 2
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
D4
D13
D9
D0
I/O 6
I/O 4
I/O 1
I/O 3
DQS5
DQS1
DM1
DM5
DQS
DM
I/O 3
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
DQS
CS
DM
I/O 3
I/O 1
I/O 4
I/O 6
CS
DQS
DQS
CS
CS
DM
I/O 7
DM
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ8
DQ9
DQ10
DQ11
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
D5
D14
D10
D1
I/O 2
I/O 0
I/O 5
I/O 7
DQ12
DQ13
DQ14
DQ15
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
CS DQS
DM
I/O 3
CS
DQS
DM
I/O 3
CS DQS
CS DQS
DM
I/O 7
I/O 5
I/O 0
I/O 2
DM
I/O 7
I/O 5
I/O 0
I/O 2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
D6
D15
D2
D11
I/O 6
I/O 4
I/O 1
I/O 3
I/O 6
I/O 4
I/O 1
I/O 3
DQS7
DM7
DQS3
DM3
CS
DM
I/O 3
CS DQS
DM
DQS
CS DQS
DM
CS DQS
DM
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
I/O 1
I/O 4
I/O 6
I/O 2
I/O 0
I/O 5
I/O 7
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
I/O 5
I/O 0
I/O 2
I/O 6
I/O 4
I/O 1
I/O 3
D7
D16
D12
D3
* Clock Wiring
DDR SDRAMs
Clock
Input
DQS8
DM8
CK0/CK0
CK1/CK1
10 DDR SDRAMs
8 DDR SDRAMs
Serial PD
CS DQS
DM
CS DQS
DM
SCL
WP
I/O 0
I/O 0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CB8
*Clock Net Wiring
SDA
I/O 1
I/O 2
I/O 3
I/O 7
I/O 6
I/O 5
I/O 4
I/O 1
I/O 2
I/O 3
I/O 7
I/O 6
I/O 5
I/O 4
CB9
D8
D17
A0
A1
A2
CB10
CB11
CB12
CB13
CB14
CB15
D0(D9) / D4(D13)/Cap
SA0 SA1 SA2
D1(D10) / D5(D14)/Cap
D2(D11) / D6(D15)/Cap
R=120Ω
CK0/1/2
CK0/1/2
Card
Edge
D3(D12) / D7(D16)/Cap
D8(D17) / Cap/Cap
BA0 - BA1
A0 - A12
BA0-BA1: DDR SDRAMs D0 - D8
A0-A12: DDR SDRAMs D0 - D8
Cap/Cap/Cap
V
DDSPD
SPD
Notes:
RAS
RAS: DDR SDRAMs D0 - D8
V
/V
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
DD DDQ
D0 - D8
D0 - D8
CAS
CAS: DDR SDRAMs D0 - D8
CKE: DDR SDRAMs D0 - D8
CKE0/1
VREF
D0 - D8
D0 - D8
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
V
WE
WE: DDR SDRAMs D0 - D8
SS
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
Unit
V
-1.0 ~ 3.6
V
VDDQ
TSTG
-1.0 ~ 3.6
V
-55 ~ +150
1.5 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD
2.3
2.7
V
VDD
2.5
2.7
2.7
V
V
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
I/O Reference voltage
VDDQ
VDDQ
VREF
2.3
2.5
2.7
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
V
V
1
2
I/O Termination voltage(system)
V
TT
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
-0.3
V
0.36
0.71
-2
V
3
4
-
2
uA
uA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;V
= V + 0.84V
IOH
-16.8
OUT
TT
Output High Current(Normal strengh driver) ;V
= V - 0.84V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
OUT
TT
Output High Current(Half strengh driver) ;V
= V + 0.45V
OUT
TT
Output High Current(Half strengh driver) ;V
= V - 0.45V
9
OUT
TT
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to
peak noise on VREF may not exceed +/-2% of the dc value.
2. V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-
ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum
difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to mini-
mum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM IDD spec table
M470L3324CU0 (32M x 64, 256MB Module)
(VDD=2.7V, T = 10°C)
Symbol
CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
IDD1
480
640
20
420
560
20
380
520
20
380
520
20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
120
100
180
240
760
860
880
20
120
100
120
180
680
740
820
20
120
100
120
180
620
640
780
20
120
100
120
180
620
640
780
20
IDD6
Normal
Low power
IDD7A
12
12
12
12
Optional
1,600
1,520
1,380
1,380
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M470L6524CU0 (64M x 64, 512MB Module)
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
720
880
40
600
740
40
560
700
40
560
700
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
240
200
360
480
1,000
1,100
1,120
40
240
200
240
360
860
920
1,000
40
240
200
240
360
800
820
960
40
240
200
240
360
800
820
960
40
IDD6
Normal
Low power
IDD7A
24
24
24
24
Optional
1,840
1,700
1,560
1,560
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM IDD spec table
M485L3324CU0 (32M x 72, 1GB Module)
(VDD=2.7V, T = 10°C)
Symbol
CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
IDD0
IDD1
600
800
30
530
700
30
480
650
30
480
650
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
150
130
230
300
950
1,080
1,100
25
150
130
150
230
850
930
1,030
25
150
130
150
230
780
800
980
25
150
130
150
230
780
800
980
25
IDD6
Normal
Low power
IDD7A
15
15
15
15
Optional
2,000
1,900
1,730
1,730
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M485L6523CU0 (64M x 72, 512MB Module)
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit
Notes
1,080
1,350
50
950
1,220
50
860
1,130
50
860
1,130
50
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
270
270
270
270
230
230
230
230
410
270
270
270
540
410
410
410
1,400
1,580
1,980
45
1,260
1,350
1,850
45
1,130
1,170
1,760
45
1,130
1,170
1,760
45
IDD6
Normal
Low power
IDD7A
27
27
27
27
Optional
3,470
3,240
2,930
2,930
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM IDD spec table
M485L2829CU0 (st.128M x 72, 1GB Module)
(VDD=2.7V, T = 10°C)
Symbol
IDD0
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,260
1,530
90
1,260
1,530
90
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
540
540
450
450
540
540
810
810
1,530
1,580
2,160
90
1,530
1,580
2,160
90
IDD6
Normal
Low power
IDD7A
54
54
Optional
3,330
3,330
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.7
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2 0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(TA= 25°C, f=100MHz)
M470L3324CU0
M470L6524CU0
Unit
Parameter
Symbol
Min
Max
45
38
38
30
7
Min
49
42
42
25
6
Max
57
50
50
30
7
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0, CKE1)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
41
34
34
25
6
pF
pF
pF
pF
pF
pF
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7)
Data & DQS input/output capacitance(DQ0~DQ63)
6
7
6
7
Input/Output Capacitance
(TA= 25°C, f=100MHz)
M485L6523CU0
Min Max
M4852829CU0
Unit
M485L3324CU0
Parameter
Symbol
Min
43
36
36
25
6
Max
48
41
41
30
7
Min
69
44
44
28
10
10
10
Max
87
53
53
34
12
12
12
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1
51
44
44
25
6
60
53
53
30
7
pF
pF
pF
pF
pF
pF
pF
Input capacitance(CKE0, CKE1)
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
6
7
6
7
6
7
6
7
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
AC Timming Parameters & Specifications
CC
B3
A2
B0
(DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5)
Parameter
Symbol
Unit Note
Min
55
Max
Min
60
Max
Min
65
Max
Min
65
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
Refresh row cycle time
Row active time
70
72
75
75
40
70K
42
70K
45
120K
45
120K
RAS to CAS delay
15
18
20
20
Row precharge time
15
18
20
20
Row active to Row active delay
Write recovery time
tRRD
tWR
10
12
15
15
15
15
15
15
Last data in to Read command
tWTR
2
1
1
1
CL=2.0
CL=2.5
CL=3.0
-
-
7.5
6
12
12
7.5
7.5
-
12
12
10
12
12
Clock cycle time
tCK
6
12
7.5
-
5
10
-
-
-
-
Clock high level width
tCH
tCL
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
0.5
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
0.5
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
ns
tCK
tCK
tCK
ns
22
13
0.9
0.4
0.72
0
1.1
0.9
0.4
0.75
0
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
Read Postamble
0.6
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.25
0.2
0.2
0.35
0.35
0.9
0.9
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
tDQSL
tIS
DQS-in low level width
15, 17~19
15, 17~19
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup
tIH
ns
tIS
0.7
0.8
1.0
1.0
ns
16~19
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
tIH
tHZ
0.7
-
0.8
-
1.0
-
1.0
-
ns
ns
ns
ns
ns
ns
16~19
11
+0.65
+0.65
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
tLZ
-0.65
10
-0.7
12
-0.75
15
-0.75
15
11
tMRD
tDS
DQ & DM setup time to DQS
0.4
0.45
0.5
0.5
j, k
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
0.5
Control & Address input pulse width
DQ & DM input pulse width
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
ns
ns
18
18
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
ns
200
200
200
200
tCK
us
7.8
7.8
7.8
7.8
-
14
21
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
-
20, 21
Data hold skew factor
tQHS
0.5
0.6
0.55
0.6
0.75
0.6
0.75
0.6
ns
21
12
DQS write postamble time
tWPST
0.4
15
0.4
18
0.4
20
0.4
20
tCK
Active to Read with Auto precharge
command
tRAP
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
23
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper system
performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR333
DDR266
PARAMETER
SYMBOL
DCSLEW
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Units
V/ns
Notes
a, m
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tIS
0
tIH
0
Units
ps
Notes
i
i
i
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tDS
0
tDH
0
Units
ps
Notes
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
tDS
0
tDH
0
Units
ps
Notes
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR333
DDR266
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Notes
e,m
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Component Notes
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be
either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics).
VDDQ
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under nor-
mal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc
input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is
recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level
for signals other than CK/CK, is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Component Notes
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
22. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Test point
Output
50Ω
VSSQ
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ
50Ω
Output
Test point
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Command Truth Table
A0 ~ A9,
A11, A12
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
L
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4
Column
Address
L
H
L
H
H
L
Write &
Column Address
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Physical Dimensions : 32M x64 (M470L3324CU0)
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
Full R 2.0
0.16 ± 0.039
(4.00 ± 0.10)
1
39 41
199
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.8+0.1/-0.0)
0.17
(4.20)
0.096
(2.40+/-0.1)
0.07
(1.8+/-0.1)
Z
Y
0.098
2.45
2
40 42
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.2+/-0.15)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4H511638C-U***
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Physical Dimensions : 64M x64 (M470L6524CU0)
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
Full R 2.0
0.16 ± 0.039
(4.00 ± 0.10)
1
39 41
199
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.8+0.1/-0.0)
0.17
(4.20)
0.096
(2.40+/-0.1)
0.07
(1.8+/-0.1)
Z
Y
0.098
2.45
2
40 42
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.2+/-0.15)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4H511638C-U***
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Physical Dimensions : 32M x72 (M485L3324CU0)
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
Full R 2.0
0.16 ± 0.039
(4.00 ± 0.10)
1
39 41
199
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.8+0.1/-0.0)
0.17
(4.20)
0.096
(2.40+/-0.1)
0.07
(1.8+/-0.1)
Z
Y
0.098
2.45
2
40 42
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.2+/-0.15)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx16 DDR SDRAM, TSOPII
DDR SDRAM Part No. : K4H511638C-U***
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Physical Dimensions : 64M x72 (M485L6523CU0)
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
Full R 2.0
0.16 ± 0.039
(4.00 ± 0.10)
1
199
39 41
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.8+0.1/-0.0)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
Z
Y
0.098
2.45
2
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
(0.45 ± 0.05)
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.2+/-0.15)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 64Mx8 DDR SDRAM, TSOPII
DDR SDRAM Part No. : K4H510838C-U***
Rev. 0.2 October. 2004
Preliminary
DDR SDRAM
256MB, 512MB, 1GB Unbuffered SODIMM
Physical Dimensions : st.128M x72 (M485L2829CU0)
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
Full R 2.0
0.16 ± 0.039
(4.00 ± 0.10)
1
199
39 41
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.8+0.1/-0.0)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
Z
Y
0.098
2.45
2
200
0.268 Max
(6.81 Max)
0.018 ± 0.001
(0.45 ± 0.05)
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.2+/-0.15)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is stacked 128Mx8 DDR SDRAM, TSOPII
DDR SDRAM Part No. : K4H1G0738C-U***
Rev. 0.2 October. 2004
相关型号:
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