M53620800CB0-C60 [SAMSUNG]
Fast Page DRAM Module, 8MX36, 60ns, CMOS, SIMM-72;
| 型号： | M53620800CB0-C60 |
| 厂家： | 
SAMSUNG |
| 描述： | Fast Page DRAM Module, 8MX36, 60ns, CMOS, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总15页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
M53620800CW0/CB0 & M53620810CW0/CB0 with Fast Page Mode
8M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
• Part Identification
The Samsung M5362080(1)0C is a 8Mx36bits Dynamic RAM
high density memory module. The Samsung M5362080(1)0C
consists of sixteen CMOS 4Mx4bits DRAMs in 24-pin SOJ
package and two CMOS 4Mx4 bit Quad CAS DRAM in 28-pin
SOJ package mounted on a 72-pin glass-epoxy substrate. A
0.1 or 0.22uF decoupling capacitor is mounted on the printed
circuit board for each DRAM. The M5362080(1)0C is a Single
In-line Memory Module with edge connections and is intended
for mounting into 72 pin edge connector sockets.
- M53620800CW0-C(4096 cycles/64ms Ref, SOJ, Solder)
- M53620800CB0-C(4096 cycles/64ms Ref, SOJ, Gold)
- M53620810CW0-C(2048 cycles/32ms Ref, SOJ, Solder)
- M53620810CB0-C(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
PERFORMANCE RANGE
• JEDEC standard PDPin & pinout
Speed
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
• PCB : Height(1000mil), double sided component
-50
90ns
110ns
-60
PIN CONFIGURATIONS
PIN NAMES
Pin
Symbol
Pin
Symbol
Pin Name
A0 - A11
A0 - A10
DQ0 - DQ35
W
Function
Address Inputs(4K Ref)
Address Inputs(2K Ref)
Data In/Out
1
2
3
4
5
6
7
8
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
RAS0, RAS1
CAS0 - CAS3
PD1 -PD4
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
Vss
Ground
A3
A4
A5
A6
NC
No Connection
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
RAS1
RAS0
DQ26
DQ8
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
NC
Vss
Vss
Vss
NC
Vss
NC
NC
* Pin connection changing available
PD1
PD2
PD3
PD4
NC
Vss
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
* NOTE : A11 is used for only M53620800CW0/CB0 (4K ref.)
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
DQ0-DQ3
DQ4-DQ7
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
CAS
RAS
OE
CAS0
RAS0
CAS0
RAS1
CAS
RAS
OE
U0
A0-
U9
A0-
A11(A10)
DQ3
W
W
W
W
W
W
W
W
A11(A10)
W
W
W
W
W
W
W
W
DQ0
DQ1
DQ2
DQ3
DQ0
CAS
RAS
OE
CAS
RAS
OE
U1
U10
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
DQ9-DQ12
DQ13-DQ16
DQ18-DQ21
DQ22-DQ25
DQ27-DQ30
DQ31-DQ34
DQ0
DQ1
DQ2
DQ3
DQ0
CAS1
CAS2
CAS3
CAS1
CAS2
CAS3
CAS
CAS
RAS
OE
U2
U11
DQ1
DQ2
DQ3
RAS
OE
A0-
A11(A10)
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
DQ0
CAS
RAS
OE
CAS
RAS
OE
U3
U12
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
DQ0
CAS
RAS
OE
CAS
RAS
OE
U4
U13
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
DQ0
CAS
RAS
OE
CAS
RAS
OE
U5
U14
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
DQ0
CAS
RAS
OE
CAS
RAS
OE
U6
U15
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
DQ0
CAS
RAS
OE
CAS
RAS
OE
U7
U16
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
CAS0
CAS1
CAS2
CAS3
RAS
CAS0
CAS1
CAS2
CAS3
RAS
DQ8
DQ17
DQ26
DQ35
DQ0
DQ1
DQ2
DQ3
DQ0
U8
U17
DQ1
DQ2
DQ3
A0-
A11(A10)
A0-
A11(A10)
OE
OE
W
W
W
A0-A11(A10)
Vcc
Vss
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +150
18
V
V
°C
W
Tstg
Pd
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
4.5
0
2.4
5.5
0
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
5.0
0
-
V
V
V
V
*1
VCC+1
0.8
*2
-
-1.0
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC.
*2 : -2.0V/20ns, Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
M53620800CW0/CB0
M53620810CW0/CB0
Symbol
Speed
Unit
Min
Max
Min
Max
ICC1
-50
-60
828
738
1008
918
mA
mA
-
-
-
-
ICC2
ICC3
Don¢t care
-
36
-
36
mA
-50
-60
-
-
828
738
-
-
1008
918
mA
mA
ICC4
-50
-60
-
-
738
648
-
-
828
738
mA
mA
ICC5
ICC6
Don¢t care
-
18
-
18
mA
-50
-60
-
-
828
738
-
-
1008
918
mA
mA
II(L)
IO(L)
-90
-10
90
10
-90
-10
90
10
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
2.4
-
-
V
V
0.4
0.4
ICC1
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3
ICC4
ICC5
ICC6
II(L)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Fast Page Mode Current * (RAS=VIL, CAS Address cycling : tPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£Vcc+0.5V, all other pins not under test=0 V)
IO(L) : Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)
VOH : Output High Voltage Level (IOH = -5mA)
: Output Low Voltage Level (IOL = 4.2mA)
VOL
* NOTE :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one page mode cycle, tPC.
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11(A10)]
Input capacitance[W]
CIN1
CIN2
CIN3
CIN4
CDQ
110
130
80
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[RAS0, RAS1]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
40
25
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, Output loading CL=100pF
-50
-60
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
Access time from RAS
90
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
tRC
50
13
25
60
15
30
3,4
3,4,5
3,10
3
tRAC
tCAC
tAA
Access time from CAS
Access time from column address
CAS to output in Low-Z
0
0
0
0
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
13
50
15
50
6
3
3
2
30
50
13
50
13
20
15
5
40
60
15
60
15
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
10
25
0
10
30
0
0
0
8
8
0
0
10
10
13
13
0
10
10
15
15
0
tRWL
tCWL
tDS
9
9
Data-in hold time
10
15
tDH
Refresh period (4K Ref)
64
32
64
32
tREF
tREF
tWCS
tCSR
tCHR
tRPC
Refresh period (2K Ref)
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
0
5
0
5
7
10
5
10
5
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, Output loading CL=100pF
-50
-60
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Access time from CAS precharge
Fast page mode cycle time
30
35
ns
ns
ns
ns
ns
ns
ns
ns
3
tCPA
tPC
35
10
50
10
10
20
5
40
10
60
10
10
20
5
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
CAS precharge(C-B-R counter test)
Hold time CAS low to CAS high
tCP
200K
200K
tRASP
tWRP
tWRH
tCPT
tCLCH
11
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS³ tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
2. VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between VIH(min) and VIL(max) and are assumed to be 5ns
for all inputs.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
4.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
10.
11.
5.
6.
Assumes that tRCD³ tRCD(max).
In order to hold the address latched by the first CAS going
low, the parameter tCLCH must be met.
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tASR
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tRAH
tASC
tRCS
tCAH
VIH -
COLUMN
ADDRESS
ROW
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tAA
tCAC
tCLZ
tOFF
tRAC
VOH -
DQ
OPEN
DATA-OUT
VOL -
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCS
tWCH
tWP
VIH -
VIL -
W
tDS
tDH
DATA-IN
VIH -
VIL -
DQ
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
¡ó
VIH -
tRHCP
RAS
VIL -
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
¡ó
VIH -
CAS
tCAS
VIL -
tRAD
tASC
tCSH
tASR
ROW
tASC
tCAH
tASC
tCAH
tRAH
tCAH
¡ó
¡ó
VIH -
VIL -
COLUMN
COLUMN
ADDRESS
COLUMN
A
ADDRESS
ADDR
ADDRESS
tRCS
tRRH
tRCS
tRCH
tCAC
tRCS
tRCH
¡ó
VIH -
VIL -
W
tCAC
tCAC
tAA
tOFF
tAA
tAA
tOFF
tOFF
tRAC
tCLZ
tCLZ
tCLZ
VOH -
VOL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
DQ
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
¡ó
VIH -
tRHCP
RAS
VIL -
tPC
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
¡ó
VIH -
VIL -
tCAS
CAS
tRAD
tASC
tRAH
ROW
tCStHCAH
tASC
tCAH
tASC
tCAH
tASR
¡ó
¡ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDR
tWCS
tWCS
tWCH
tWP
tWCS
tWCH
¡ó
tWCH
tWP
VIH -
VIL -
tWP
W
tCWL
tRWL
tDH
tCWL
tCWL
tDH
tDS
tDH
tDS
tDS
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don't care
DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don't care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
VIL -
tCSR
tWRP
CAS
W
tCHR
tWRH
VIH -
VIL -
tOFF
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tWRH
tWRP
tRRH
VIH -
VIL -
W
tAA
tCAC
tCLZ
tOFF
tRAC
VOH -
VOL -
DQ
OPEN
DATA-OUT
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWRH
tWRP
tWCS
tDS
tWCH
VIH -
VIL -
W
tWP
tDH
VIH -
VIL -
DQ
DATA-IN
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
READ CYCLE
tRCS
tCAC
VIH -
W
VIL -
tOFF
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
OPEN
VIL -
Don¢t care
Undefined
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
tRPC
VIH -
RAS
tRPC
tCP
VIL -
tCHS
VIH -
VIL -
tCSR
CAS
DQ
tOFF
VOH -
VOL -
OPEN
tWRP
tWRH
VIH -
VIL -
W
TEST MODE IN CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCP
tRPC
VIH -
tCSR
tWTS
tCHR
CAS
VIL -
tWTH
VIH -
W
VIL -
tOFF
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
M53620800CW0/CB0
M53620810CW0/CB0
DRAM MODULE
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
R.062(1.57)
.125 DIA±.002(3.18±.051)
.400(10.16)
1.00(25.40)
.250(6.35)
.080(2.03)
.250(6.35)
R.062±.004(R1.57±.10)
.250(6.35)
3.750(95.25)
( Front view )
.125(3.17)
MIN
( Back view )
Gold & Solder Plating Lead
.350(8.89)
MAX
.100(2.54)
.010(.25)MAX
MIN
.225(5.71)
MIN
.054(1.37)
.050(1.27)
.041±.004(1.04±.10)
.047(1.19)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device are 4Mx4 FP DRAM (SOJ & 300mil) & 4Mx4 Quad CAS with FP DRAM (SOJ & 300mil)
DRAM Part No. : M53620800CW0/CB0 -- K4F170411C-B(300mil) & K4P170411C-B(300mil)
M53620810CW0/CB0 -- K4F160411C-B(300mil) & K4P160411C-B(300mil)
Revision History
Rev 0.0 : Oct. 1999
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