M965G0225MQ0-C50 [SAMSUNG]
Synchronous Graphics RAM Module, 2MX64, 4.5ns, CMOS, SODIMM-144;
| 型号： | M965G0225MQ0-C50 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous Graphics RAM Module, 2MX64, 4.5ns, CMOS, SODIMM-144 时钟 动态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
M965G0225MP(Q)0 / M966G0225MP(Q)0 SGRAM SODIMM
2Mx64 SGRAM SODIMM based on 1Mx32, 2K Refresh, 3.3V Synchronous Graphic RAMs
FEATURE
GENERAL DESCRIPTION
• Performance range
Part NO.
The Samsung M965(6)G0225MP(Q)0 is a 2M bit x 64 Syn-
chronous Graphic RAM high density memory module. The
Samsung M965(6)G0225MP(Q)0 consists of four CMOS 1M x
32 bit Synchronous Graphic RAMs in 100pin QFP packages
mounted on a 144pin glass-epoxy substrate. Five 0.1uF
decoupling capacitors are mounted on the printed circuit board
for each Synchronous GRAM. The M965(6)G0225MP(Q)0 is a
Small Outline Dual In-line Memory Module and is intended for
mounting into 144-pin edge connector sockets.
Max. Freq. (tCC)
M965(6)G0225MP(Q)0-C50
M965(6)G0225MP(Q)0-C60
M965(6)G0225MP(Q)0-C70
M965(6)G0225MP(Q)0-C80
* M965(6)G0225MP0 : based on PQFP Component
M965(6)G0225MQ0 : based on TQFP Component
• Burst Mode Operation
• BLOCK-WRITE and Write-per-bit capability
• Independent byte operation via DQM0 ~ 7
• Auto & Self Refresh Capability (2048 cycles / 32ms)
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
• MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• Optional Serial PD with EEPROM (M966G0225)
• Resistor Strapping Options for speed and CAS Latency
• PCB : Height(1250mil), double sided components
200MHz (5ns) @CL=3
166MHz (6ns) @CL=3
143MHz (7ns) @CL=3
125MHz (8ns) @CL=3
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
PIN CONFIGURATIONS (Front Side / Back Side)
PIN NAMES
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
Pin Name
A0 ~ A10
BA
Function
1
3
5
7
9
VSS
2
4
6
8
VSS
95 DQ31 96 DQ30
97 DQ29 98 DQ28
99 DQ27 100 DQ26
101 DQ25 102 DQ24
Address Input(multiplexed)
Bank Select Address
Data Input / Output
Voltage Key
DQ63
DQ61
DQ59
DQ62
DQ60
DQ58
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
RSVD
RSVD
VSS
52 RSVD
54 RSVD
DQ0 ~ 63
CLK0, CLK1 Clock Input
DQ57 10 DQ56
12
103
VSS
104
VSS
56
VSS
CKE
Clock Enable Input
11
VDD
VDD
105 DQ23 106 DQ22
107 DQ21 108 DQ20
109 DQ19 110 DQ18
111 DQ17 112 DQ16
DSF
RFU
RFU
VDD
58 RFU
60 RFU
62 **SBA
13 DQ55 14 DQ54
15 DQ53 16 DQ52
17 DQ51 18 DQ50
19 DQ49 20 DQ48
CS0, CS1
RAS
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
64
VDD
CAS
113
VDD
114
VDD
CS1
RAS
WE
66 CS0
68 CAS
70 CKE
WE
21
VSS
22
VSS
115 DQM3 116 DQM2
117 DQM1 118 DQM0
23 DQM7 24 DQM6
25 DQM5 26 DQM4
27
29 DQ47 30 DQ46
31 DQ45 32 DQ44
33 DQ43 34 DQ42
35 DQ41 36 DQ40
DSF
Define Special Function
DQM
119
VSS
120
VSS
VSS
CLK1
VDD
RSVD
A10
72
74 CLK0
76
78 RSVD
80 A9
VSS
DQM0 ~ 7
VDD
VDD
28
VDD
121 DQ15 122 DQ14
123 DQ13 124 DQ12
125 DQ11 126 DQ10
127 DQ9 128 DQ8
Power Supply (3.3V)
Ground
VDD
VSS
**SDA
**SBA
**SCL
RSVD
RFU
Serial Address Data I/O
EEPROM Device Address
Serial Clock
129
VDD
130
VDD
37
VSS
38
VSS
131 DQ7 132 DQ6
133 DQ5 134 DQ4
135 DQ3 136 DQ2
137 DQ1 138 DQ0
81
83
85
87
89
91
93
BA
A7
VSS
A5
A3
A1
82 A8/AP
39 DQ39 40 DQ38
41 DQ37 42 DQ36
43 DQ35 44 DQ34
45 DQ33 46 DQ32
84
86
88
90
92
94
A6
VSS
A4
A2
A0
Reserved
Reserved for future use
No Connection
139
141 **SDA 142 **SCL
143 144
VSS
140
VSS
NC
47
VDD
48
VDD
** These pins should be NC in the system
49 RSVD 50 RSVD
VDD
VDD
VDD
VDD
which does not support SPD.
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
PIN CONFIGURATION DESCRIPTION
Pin
Name
System Clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tSS prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
A0 ~ A10
BA
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
RAS
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data Input/Output Mask
DQ0 ~ 63
DSF
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power and ground for the input buffers and the core logic.
Define Special Function
Power Supply/Ground
VDD/VSS
RESISTOR STRAPPING OPTIONS
Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information
for each clock frequency is indicated in the section titled AC CHARATERISTICS.
Clock Frequency and Memory Timing
Cycle Time
8 ns
DQ30
DQ29
1
1
0
0
0
1
0
1
7 ns
6 ns
5 ns
CAS Latency
CAS Latency
DQ31
3
0
1
2 and 3
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
FUNCTIONAL BLOCK DIAGRAM
CS1
·
CS0
·
DQM0
DQM0
DQM0
DQM4
DQM0
DQM0
DQ0
DQ0
DQ0
DQ0
DQ32
DQ0
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
U3
U2
·
U0
U1
·
·
·
·
·
DQ7
DQ7
DQ7
DQ7
DQ39
DQ7
DQM1
DQM1
DQM1
DQM5
DQM1
DQM1
DQ8
DQ8
DQ8
DQ8
DQ40
DQ8
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
DQ15
DQ15
DQ15
DQ15
DQ47
DQ15
DQM2
DQM2
DQM2
DQM6
DQM2
DQM2
DQ16
DQ16
DQ16
DQ16
DQ48
DQ16
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
DQ23
DQ23
DQ23
DQ23
DQ55
DQ23
DQM3
DQM3
DQM3
DQM3
DQM7
DQM3
DQ24
DQ24
DQ24
DQ24
DQ56
DQ24
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
DQ31
DQ31
DQ31
DQ31
DQ63
DQ31
10W
0W
CKE
RAS
CAS
WE
U0 to U3
U0 to U3
U0 to U3
U0 to U3
U0 to U3
U0 to U3
U0 to U3
CLK0
CLK1
U0, U1
U2, U3
DSF
A(10:0)
BA
Serial PD
SCL
SDA
A0 A1 A2
VDD
Vss
·
·
·
·
·
·
Five 0.1uF Capacitors
per SGRAM device
To all SGRAMs
SBA
VSS
·
* Serial PD is optional
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS)
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
4
Unit
V
V
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
3.6
Unit
V
Note
3.3
Note 4
Input high voltage
3.0
VDD+0.3
0.8
V
Input low voltage
VIL
0
-
V
Note 1
IOH = -2mA
IOL = 2mA
Note 2
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Output loading conditon
VOH
VOL
ILI
-
V
-
0.4
V
-40
-20
-
40
uA
uA
ILO
-
20
Note 3
See Figure 1
Note :
1. VIL(min.) = -1.5V AC (pulse width £ 5ns)
2. Any input 0V £ VIN £ VDD + 0.3V, all other pins are not under test = 0V.
3. Dout is disabled, 0V £ VOUT £ VDD
4. The VDD condition of M965(6)G0225MP(Q)0-C50/60 is 3.135V~3.6V.
CAPACITANCE (VCC = 3.3V, TA = 25°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A10, BA)
CIN1
CIN2
CIN3
CIN4
CIN5
COUT
-
-
-
-
-
-
26
26
18
18
18
20
pF
pF
pF
pF
pF
pF
Input capacitance (RAS, CAS, WE, CKE, DSF)
Input capacitance (CLK0,CLK1)
Input capacitance (CS0,CS1)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)
Speed
CAS
Latency
Parameter
Symbol
Test Condition
Unit Note
-50 -60 -70 -80
460 420 380 360
3
2
Operating Current
(One Bank Active)
Burst Length =1
tRC ³ tRC(min), tCC ³ tCC(min), Io = 0 mA
ICC1
mA
mA
2
-
-
-
360
ICC2P
CKE £ VIL(max), tCC = 15ns
8
8
Precharge Standby Current in
power-down mode
ICC2PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
ICC2N
120
60
Input signals are changed one time during 30ns
Precharge Standby Current
in non power-down mode
mA
mA
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
CKE £ VIL(max), tCC = 15ns
CKE & £ VIL(max), tCC = ¥
12
12
Active Standby Current
in power-down mode
ICC3PS
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3N
200
120
Active Standby Current
in non power-down mode
(One Bank Active)
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC3NS
3
2
3
2
640 580 520 460
380
800 720 640 600
600
Operating Current
(Burst Mode)
Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)
ICC4
ICC5
2
3
-
-
-
Refresh Current
tRC ³ tRC(min)
mA
mA
-
-
-
Self Refresh Current
ICC6
ICC7
CKE £ 0.2V
8
Operating Current
(One Bank Block Write)
tCC ³ tCC(min), Io=0mA, tBWC(min)
520 460 400 360 mA
Note :
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open. Address are changed only one time during tcc(min).
3. Refresh period is 32ms. Address are changed only one time during tcc(min).
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Value
Vih/Vil = 2.4V / 0.4V
1.4V
AC input levels
Input timing measurement reference level
Input rise and fall time(See note 3)
Output timing measurement reference level
Output load condition
tR/tF=1ns/ 1ns
1.4V
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
·
·
·
·
Output
Output
Z0=50W
VOL (DC) = 0.4V, IOL = 2mA
30pF
30pF
870W
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
Note : The VDD condition of M965(6)G0225MP(Q)0-C50/60 is 3.135V~3.6V.
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-50
Max
-60
Max
-70
-80
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
Min
Min Max Min Max
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
5
-
6
7
8
10
-
CLK cycle time
1000
1000
1000
1000
-
-
-
-
4.5
5.5
-
5.5
6
6
-
CLK to valid
output delay
tSAC
ns
1, 2
-
-
-
-
-
-
-
-
-
Output data hold time
CLK high pulse width
tOH
tCH
2
2
-
-
2.5
2.5
-
2.5
2.5
ns
ns
2
3
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
-
3
-
-
-
-
-
-
3
3
-
-
-
-
-
2
-
-
2.5
-
3
CLK low
pulse width
ns
ns
3
3
tCL
tSS
-
-
1.5
-
-
1.5
-
1.75
2
2.5
1
Input setup time
-
-
1
1
-
Input hold time
tSH
1
1
-
-
-
1
-
-
-
-
-
-
ns
ns
3
2
CLK to output in Low-Z
tSLZ
1
1
CAS latency=3
CAS latency=2
4.5
-
-
5.5
-
5.5
-
-
6
6
CLK to output
in Hi-Z
tSHZ
ns
-
-
-
-
-
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-50
5
-60
6
-70
7
-80
8
CLK cycle time
tCC(min)
ns
ns
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
10
18
18
40
12
18
18
42
14
18
18
49
16
18
18
48
1
1
1
1
ns
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
tBPL(min)
tBWC(min)
tMRS(min)
ns
Row active time
100
us
Row cycle time
65
66
67
68
ns
1
2, 5
2
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
2
1
1
1
2
1
1
2
1
CLK
CLK
CLK
CLK
CLK
CLK
CLK
2
Col. address to col. address delay
Block Write data-in to PRE command
Block write cycle time
1, 3
4
Mode Register Set cycle time
CAS Latency=3
CAS Latency=2
Number of valid output data
ea
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following clock unit based AC conversion table
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -60/70/80, tRDL =1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV"
Version
Symbol
Unit
-50
-60
-70
-80
CL
3
5
-
-
3
6
-
-
3
7
-
-
3
8
2
CLK
ns
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
10
2
CLK
CLK
CLK
CLK
us
4
4
8
-
-
-
3
3
7
-
-
-
3
3
7
-
-
-
3
3
6
2
2
5
100
13
-
11
-
10
-
9
7
CLK
SGRAM MODULE
SIMPLIFIED TRUTH TABLE
COMMAND
M965G0225MP(Q)0 / M966G0225MP(Q)0
CKEn-1 CKEn CS RAS CAS WE DSF DQM BA A8 A10,A9,A7~A0
Note
1, 2
1,2,7
3
Register
Mode Register Set
Special Mode Register Set
Auto Refresh
L
H
H
L
X
L
L
L
L
L
L
L
X
X
X
X
OP CODE
H
Refresh
H
L
H
L
X
Entry
3
Self
L
H
X
H
X
H
X
3
Refresh
Exit
H
X
X
X
H
3
Bank Active Write Per Bit Disable
L
4, 5
4,5,9
4
H
L
L
L
H
L
H
H
V
V
Row Address
& Row Addr.
Write Per Bit Enable
H
Read &
Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
Column
Address
(A0~A7)
H
H
H
X
X
X
H
L
L
X
X
X
H
L
4, 6
4, 5
Write &
Column
Address
Column
Address
(A0~A7)
L
L
H
H
L
L
L
L
V
V
H
L
4,5,6,9
4, 5
Block Write Auto Precharge Disable
&
Auto Precharge Enable
Column
Column
Address
(A0~A7)
H
4,5,6,9
7
H
Burst Stop
H
H
X
X
L
L
H
L
H
H
L
L
L
L
X
X
X
Bank Selection
Precharge
V
X
L
X
Both Banks
H
L
H
X
L
H
X
X
H
X
V
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
X
X
Clock Suspend or
Active Power Down
X
X
Exit
L
H
L
X
X
X
X
Entry
H
H
L
Precharge Power Down
Mode
V
X
Exit
L
H
X
X
H
DQM
H
H
X
V
X
X
X
8
L
H
X
H
X
H
X
No Operation Command
X
H
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code
A0 ~ A10, BA : Program keys. (@MRS)
A5, A6 : LMR or LCR select. (@SMRS)
Color register exists only one per DQi which both banks share.
So dose Mask Register.
Color or mask is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ¢s are idle.
A new command can be issued at the next clock of MRS/SMRS.
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
SIMPLIFIED TRUTH TABLE
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both precharge state.
4. BA : Bank select address.
If "Low" at read, (block) write, Row active and precharge, bank A is selected.
If "High" at read, (block) write, Row active and precharge, bank B is selected.
If A8 is "High" at Row precharge, BA is ignored and both banks are selected.
5. It is determined at Row active cycle.
whether Normal/Block write operates in write per bit mode or not.
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit =I/O mask
(Block) Write with write per bit mode=Masked(Block) Write
6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.
Another bank read/(block) write command can be issued at tRP after the end of burst.
7. Burst stop command is valid only at full page burst length.
8. DQM sampled at positive going edge of a CLK.
masks the data-in at the very CLK(Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
9. Graphic features added to SDRAM¢s original features.
If DSF is tied to low, graphic functions are disabled and chip operates as a 32M SDRAM with 32 DQ¢s.
SGRAM vs SDRAM
Function
MRS
Bank Active
Write
DSF
L
H
L
H
L
H
Bank Active
with
Write per bit
Disable
Bank Active
with
Write per bit
Enable
SGRAM
Function
Normal
Write
Block
Write
MRS
SMRS
If DSF is low, SGRAM functionality is identical to SDRAM functionality.
SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
TM
CAS Latency
BT
Burst Length
(Note 1)
Test Mode
CAS Latency
Burst Type
Type
Burst Length
A8
A7
0
Type
A6
A5
0
A4
0
Latency
Reserved
-
A3
A2
A1
A0
0
BT=0
BT=1
Reserved
Reserved
4
0
0
1
1
Mode Register Set
0
0
0
0
1
1
1
1
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
2
1
Vendor
Use
Only
0
1
1
0
1
0
2
0
4
1
1
1
3
1
8
8
0
0
Reserved
Reserved
Reserved
Reserved
0
Reserved
Reserved
Reserved
256(Full)
Reserved
Reserved
Reserved
Reserved
0
1
1
1
0
0
1
1
1
(Note 3)
Special Mode Register Programmed with SMRS
Address
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
X
LC
LM
X
Load Color
Load Mask
A6
0
Function
Disable
Enable
A5
0
Function
Disable
Enable
1
1
POWER UP SEQUENCE
SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. The full column burst(256bit) is available only at Sequential mode of burst type.
3. If LC and LM both high(1), data of mask and color register will be unknown.
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
BURST SEQUENCE (BURST LENGTH = 4)
Initial address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
BURST SEQUENCE (BURST LENGTH = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
0
1
6
7
0
1
2
3
4
0
3
2
5
4
7
6
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PIXEL to DQ MAPPING(at BLOCK WRITE)
Column address
7 Byte
6 Byte
5 Byte
4 Byte
3 Byte
2 Byte
1 Byte
0 Byte
I/O7 - I/O0
DQ0
A2
0
A1
0
A0
0
I/O63 - I/O56 I/O55 - I/O48 I/O47 - I/O40 I/O39 - I/O32 I/O31 - I/O24 I/O23 - I/O16 I/O15 - I/O8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
0
0
1
DQ1
0
1
0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
0
1
1
DQ3
1
0
0
DQ4
1
0
1
DQ5
1
1
0
DQ6
1
1
1
DQ7
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
PACKAGE DIMENSIONS - Proposal (Based on JEDEC STD.)
Units : Inches (millimeters)
2.66
(67.60)
2.50
2-R 0.078 Min
(2.00 Min)
(63.60)
0.16 ± 0.039
(4.00 ± 0.10)
0.75
(19.20)
1.44
(36.80)
0.13
(3.30)
2- f 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
1.15
(3.70)
0.2953 Max
(7.5 Max) * Note 1
0.024 ± 0.001
(0.60 ± 0.05)
0.16 ± 0.0039
(4.00 ± 0.10)
0.01 Max
(0.25 Max)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
(0.80 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances :±.0059(.15) unless otherwise specified
* Note 1 : This thickness is when using PQFP package. When using TQFP package, this value is 3.9mmMax.
The used device is 1Mx32, 32M SGRAM, 100pin (T)QFP
SGRAM Component Part No. : K4G323222M-P : PQFP (Height = 3.0mmMax)
K4G323222M-Q : TQFP (Height = 1.2mmMax)
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
SERIAL PRESENCE DETECT INFORMATION
• Serial PD Interface Protocol : I2C
• Current sink capability of SDA driver £ 3mA
• Maximum clock frequency : 80KHz
Contents ;
Function Supported
-60 -70
128bytes
Hex value
Byte #
Function Described
Note
-50
-80
-50
-60
-70
-80
0
1
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
80h
08h
06h
0Bh
08h
02h
40h
00h
01h
256bytes (2K bit)
2
SGRAM
11
TBD
3
# of row address on this assembly
1
1
4
# of column address on this assembly
# of module banks on this assembly
Data width of this assembly
8
5
2 bank
64 bits
-
6
7
...... Data width of this assembly
8
Voltage interface standard of this assembly
SGRAM cycle time from clock @CAS latency of 3
SGRAM access time from clock @CAS latency of 3
DIMM configuraion type
LVTTL
9
5ns
6ns
7ns
6ns
8ns
6ns
50h
45h
60h
55h
70h
60h
80h
60h
2
2
10
11
12
13
14
15
16
17
18
19
20
4.5ns
5.5ns
Non parity
00h
80h
20h
00h
01h
8Fh
02h
06h
01h
01h
Refresh rate & type
15.625us, support self refresh
Primary SGRAM width
x32
None
Error checking SGRAM width
Minimum clock delay for back-to-back random column
SGRAM device attributes : Burst lengths supported
SGRAM device attributes : # of banks on SGRAM device
SGRAM device attributes : CAS latency
SGRAM device attributes : CS latency
SGRAM device attributes : Write latency
tCCD = 1CLK
1, 2, 4, 8 & full page
2 banks
2 & 3
0 CLK
0 CLK
Non-buffered, non-registered
& redundant addressing
21
SGRAM module attributes
00h
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
22
SGRAM device attributes : General
4Eh
23
24
25
26
27
28
29
30
31
32
33
34
SGRAM cycle time @CAS latency of 2
SGRAM access time @CAS latency of 2
SGRAM cycle time @CAS latency of 1
SGRAM access time @CAS latency of 1
Minimum row precharge time (=tRP)
-
-
-
-
-
-
10ns
6ns
-
00h
00h
00h
00h
12h
0Ah
12h
28h
00h
00h
00h
00h
12h
0Ch
12h
2Ah
00h
00h
00h
00h
12h
0Eh
12h
31h
A0h
60h
00h
00h
12h
10h
12h
30h
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
18ns
10ns
18ns
40ns
18ns
12ns
18ns
42ns
18ns
14ns
18ns
49ns
18ns
16ns
18ns
48ns
Minimum row active to row active delay (tRRD)
Minimum RAS to CAS delay (=tRCD)
Minimum activate to precharge time (=tRAS)
Module bank density
1 bank of 8MB
02h
Address and Command signal Input setup time (=tSS)
Address and Command signal Input hold time (=tSH)
Data signal Input setup time (=tSS)
1.5ns
1ns
1.5ns
1ns
1.8ns
1ns
2.0ns
1ns
15h
10h
15h
15h
10h
15h
18h
10h
18h
20h
10h
20h
2
2
2
1.5ns
1.5ns
1.8ns
2.0ns
SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
Function Supported
Hex value
Byte #
Function Described
Note
-50
-60
-70
-80
-50
-60
-70
-80
35
36
Data signal Input hold time (=tSH)
Block Write Size
1ns
1ns
1ns
1ns
10h
10h
10h
10h
2
8 Columns
03h
00h
00h
37~61 Superset information (maybe used in future)
-
62
63
64
SPD data revision code
Initial Release
TBD
Checksum for bytes 0 ~ 62
Manufacturer JEDEC ID code
-
A6h
CAh
F4h
15h
Samsung
CEh
00h
01h
4Dh
39h
20h
36h
36h
47h
30h
32h
32h
35h
4Dh
65~71 ...... Manufacturer JEDEC ID code
Samsung
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Manufacturing location
Onyang Korea
Manufacturer part # (Memory module)
Manufacturer part # (Memory type & edge connector)
Manufacturer part # (Data bits)
M
9
Blank
...... Manufacturer part # (Data bits)
...... Manufacturer part # (Data bits)
Manufacturer part # (Mode & operating voltage)
Manufacturer part # (Module depth)
...... Manufacturer part # (Module depth)
Manufacturer part # ( Module banks)
Manufacturer part # (Composition component)
Manufacturer part # (Component revision)
Manufacturer part # (Package type)
Manufacturer part # (PCB revision)
Manufacturer part # (Hyphen)
6
6
G
0
2
2
5
M(M-die)
P(PQFP) / Q(TQFP)
50h / 51h
30h
0
"-"
C
2Dh
Manufacturer part # (Power)
43h
Manufacturer part # (Minimum cycle time)
Manufacturer part # (Minimum cycle time)
Manufacturer part # (TBD)
5
0
6
0
7
0
8
0
35h
30h
36h
30h
37h
30h
38h
30h
Blank
20h
30h
4Dh
-
Manufacturer revision code (For PCB)
...... Manufacturer revision code (For component)
Manufacturing date (Week)
0
M(M-die)
-
-
-
-
-
-
3
3
4
Manufacturing date (Year)
-
95~98 Assembly serial #
-
99~12 Manufacturer specific data (may be used in future)
FFh
FFh
FFh
FFh
126
127
Reserved
Reserved
128+ Unused storage locations
Note :
1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung¢s own Assembly Serial # system. All modules may have different unique serial #.
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