MC4GE04GQAPR-MWA [SAMSUNG]
Flash Memory Drive, CMOS, FBGA;
| 型号： | MC4GE04GQAPR-MWA |
| 厂家： | 
SAMSUNG |
| 描述： | Flash Memory Drive, CMOS, FBGA |
| 文件： | 总65页 (文件大小：799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NAND Flash-based Solid State Disk
N S S D
(NAND Flash-based Solid State Disk)
Module Type
Product Data sheet
Version 1.1
Sep 2006
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or sim-
ilar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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NAND Flash-based Solid State Disk
Document Title
SAMSUNG NAND Flash-based Solid State Disk
Revision History
Revision No
History
Draft Date
Remark
Preliminary
Final
0.5
1.0
Initial issue
May.09.2006
Aug.18.2006
Physical dimension was added(Slim 4/8/16GB)
GND PAD was added on Slim 32GB
Supporting SECURITY FEATURE Set
Supporting SMART FEATURE Set
Supporting HOST PROTECTED AREA FEATURE Set
Identify Device Data was updated
Software/Hardware Reset State Diagram was added
1.1
Misprint was modified(page 56)
( In graph, R/B -> BSY)
Sep.27.2006
Final
Product line-up was added(page 65)
(A-die based Small 8/16GB)
(Shared PCB based Slim 4/8/16/32GB)
The attached data sheets are prepared and approved by SAMSUNG Electronics. And SAMSUNG Electronics has the right to
change all the specifications in data sheets. SAMSUNG Electronics will evaluate and reply to any dear customer‘s requests and
questions on the parameters of this device. If dear customer has any questions, please call or fax to Memory Product Planning
Team, or contact the SAMSUNG branch office near your office
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NAND Flash-based Solid State Disk
TABLE OF CONTENTS
6
1. General Description
7
7
9
2. Physical Specifications
2.1 Small Type Physical Dimensions(16GB)
2.2 Slim Type Physical Dimensions(4/8/16GB)
2.3 Slim Type Physical Dimensions(32GB)
11
13
13
13
13
13
13
3. Product Specifications
3.1 System Interface and Configuration
3.2 System Performance
3.3 System Power Consumption
3.4 System Reliability
3.5 Environmental Specifications
14
14
14
15
16
16
16
16
17
17
19
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
4. Electrical Specifications
4.1 ZIF Connector Dimensions
4.2 Pin Assignment
4.3 Signal Descriptions
4.4 DC Characteristics
4.4.1 Absolute Maximum Ratings
4.4.2 Recommended Operating Conditions
4.4.3 Electrical Characteristics
4.5 AC Characteristics
4.5.1 Register Transfers
4.5.2 PIO Data Transfers
4.5.3 Multiword DMA Data Transfer
4.5.3.1 Initiating a Multiword DMA data burst
4.5.3.2 Sustaining a Multiword DMA data burst
4.5.3.3 Device terminating a Multiword DMA data burst
4.5.3.4 Host terminating a Multiword DMA data burst
4.5.4 Ultra DMA Data Transfer
4.5.4.1 Initiating an Ultra DMA data-in burst
4.5.4.2 Sustained Ultra DMA data-in burst
4.5.4.3 Host pausing an Ultra DMA data-in burst
4.5.4.4 Device terminating an Ultra DMA data-in burst
4.5.4.5 Host terminating an Ultra DMA data-in burst
4.5.4.6 Initiating an Ultra DMA data-out burst
4.5.4.7 Sustained Ultra DMA data-out burst
4.5.4.8 Device pausing an Ultra DMA data-out burst
4.5.4.9 Host terminating an Ultra DMA data-out burst
4.5.4.10 Device terminating an Ultra DMA data-out burst
37
37
37
37
37
37
37
37
38
38
38
38
38
38
38
39
39
39
39
39
5. ATA Registers
5.1 I/O Register Descriptions
5.2 Alternate Status Register
5.2.1 Address
5.2.2 Direction
5.2.3 Access Restrictions
5.2.4. Effect
5.2.5 Functional Description
5.3 Command Register
5.3.1 Address
5.3.2 Direction
5.3.3 Access Restrictions
5.3.4 Effect
5.3.5 Functional description
5.3.6 Field/bit description
5.4 Cylinder High Register
5.4.1 Address
5.4.2 Direction
5.4.3 Access Restrictions
5.4.4 Effect
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TABLE OF CONTENTS
39
40
40
40
40
40
40
40
40
40
41
41
41
41
42
42
42
42
42
42
42
43
43
43
43
43
43
43
44
44
44
44
44
44
44
45
45
45
45
45
45
45
46
46
46
46
46
46
47
47
47
47
47
47
48
48
48
48
48
48
49
5.4.5 Functional description
5.5 Cylinder Low Register
5.5.1 Address
5.5.2 Direction
5.5.3 Access Restrictions
5.5.4 Effect
5.5.5 Functional description
5.6 Data Port
5.6.1 Address
5.6.2 Direction
5.6.3 Access Restrictions
5.6.4 Effect
5.6.5 Functional description
5.6.6 Field/bit description
5.7 Data Register
5.7.1 Address
5.7.2 Direction
5.7.3 Access Restrictions
5.7.4 Effect
5.7.5 Functional description
5.7.6 Field/bit description
5.8 Device Control Register
5.8.1 Address
5.8.2 Direction
5.8.3 Access Restrictions
5.8.4 Effect
5.8.5 Functional description
5.8.6 Field/bit description
5.9 Device/Head Register
5.9.1 Address
5.9.2 Direction
5.9.3 Access Restrictions
5.9.4 Effect
5.9.5 Functional description
5.9.6 Field/bit description
5.10 Error Register
5.10.1 Address
5.10.2 Direction
5.10.3 Access Restrictions
5.10.4 Effect
5.10.5 Functional description
5.10.6 Field/bit description
5.11 Features Register
5.11.1 Address
5.11.2 Direction
5.11.3 Access Restrictions
5.11.4 Effect
5.11.5 Functional description
5.12 Sector Count Register
5.12.1 Address
5.12.2 Direction
5.12.3 Access Restrictions
5.12.4 Effect
5.12.5 Functional description
5.13 Sector Number Register
5.13.1 Address
5.13.2 Direction
5.13.3 Access Restrictions
5.13.4 Effect
5.13.5 Functional description
5.14 Status Register
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TABLE OF CONTENTS
49
49
49
49
49
49
50
51
51
51
51
52
5.14.1 Address
5.14.2 Direction
5.14.3 Access Restrictions
5.14.4 Effect
5.14.5 Functional description
5.14.6 Field/bit description
5.14.6.1 BSY(Busy)
5.14.6.2 DRDY(Device ready)
5.14.6.3 Command dependent
5.14.6.4 DRQ(Data request)
5.14.6.5 Obsolete bits
5.14.6.6 ERR(Error)
53
53
54
54
54
54
54
55
55
55
56
56
57
57
58
58
59
61
62
6. Command Descriptions
6.1 Supporting ATA Command Set
6.2 Security Feature Set
6.2.1 Securtity mode default setting
6.2.2 Initial setting of the user password
6.2.3 Security mode operation from power-on
6.2.4 Password lost
6.3 SMART Feature Set
6.3.1 Sub Command Set
6.3.2 SMART Data Structure(READ DATA(Doh))
6.3.3 Threshold Sector Size
6.4 R/B Status in SLEEP command
6.5 SET FEATURES
6.5.1 SET FEATURES Register Value
6.6 SET MAX
6.6.1 SET MAX FEATURES Register Value
6.7 Identify Device Data
6.8 Hardware Reset State Diagram
6.9 Software Reset State Diagram
64
65
7. Ordering Information
8. Product Line-up
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NAND Flash-based Solid State Disk
1. General Description
The NSSD(Nand Flash-based Solid State Disk) of Samsung Electronics is fully consist of semiconductor device and using NAND
Flash Memory which has a high reliability and a high technology for a storage media.
As the NSSD doesn't have a moving parts such as platter(disk) and head media, it gives a good solution in a sub. note PC and Tablet
PC for a storage device with a high performance and a power consumption and a small form factor.
Also it gives rugged features in industrial PC with an extreme environment and an increased MTBF.
For an easy adoption, the NSSD has a same host interface with HDD and has a same physical dimension.
•Density
•Power consumption
− Active : Typical 200mA
− Idle : Typical 20mA
− Standby : Typical 20mA
− 8GB,16GB,32GB NSSD are available
•Form Factor
− Small Type (56 x 48 x 3.8mm) : 8/16GB
− Slim Type (53.60 x 70.60 x 3.00mm) :32GB
(53.60 x 70.60 x 2.50mm) : 4/8/16GB
•Temperature
− Operating : -25'C ~ 85'C
•Shock
•Host interface
− PIO Mode 0 to 4.
− Operating : 1500G, duration 0.5ms, Half Sine Wave
− Vibration : 20G Peak, 10~2000Hz,(12Cycle/Axis)x3 Axis
− Multiword DMA
− Up to ATA5 UDMA Mode4 (66MHz)
•MTBF
− 1,000,000 Hours
•Performance
− Host Interface : Max 66MB/s
− Sustained Data Read : Max 56MB/s
− Sustained Data Write : Max 32MB/s
•NSSD Functional Block Diagram
ARM7
Voltage Detector
& Power on Reset
Initial
FSM
Flash
Conf_Reg
ARM I/F
Host
Conf_Reg
x8
x8
ECC
Flash Memory
Flash
Memory
Controller
x16
x16
x16
•
x16
x16
x8
HOST
P-ATA
UDMA
x32
x8
FIFO &
Control
x8
x8
Flash Memory
Flash Memory
Flash Memory
x32
Control &
Data path
SRAM
Controller
ECC
x8
Flash
Memory
Controller
x32
FIFO &
Control
x8
x32
SRAM
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NAND Flash-based Solid State Disk
2. Physical Specifications
2.1 Small Type Physical Dimensions (8/16GB)
56
2.0
0.61
2.5
5.5
1.05
P
1 7 6 L Q F
e r r t o l l C o n
0.61
5.5
R 0.5
Figure 1. Small Type(8/16GB) Top
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NAND Flash-based Solid State Disk
22.00
18.35
15.65
Connector
Contact No.
1
NAND
NAND
NAND
NAND
NAND
NAND
9.99
3.01
R 0.5
Figure 2. Small Type(8/16GB) Bottom
NAND
Connector
PCB
NAND
Capacitor
Figure 3. Small Type(8/16GB) Side
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NAND Flash-based Solid State Disk
2.2 Slim Type Physical Dimensions (4/8/16GB)
53.60
R 0.5
14.45
17.15
22.00
Connector
1.05
0.5
Contact No.
1
0.5
1 8 0 F B G A
l l e o r n t r C o
NAND
NAND
NAND
NAND
NAND
5.20
NAND
2.5
2.5
4.01
2.0
6.4
Figure 4. Slim Type(4/8/16GB) Top
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Sep. 27. 2006
NAND Flash-based Solid State Disk
R 0.5
2.0
53.60
5.5
1.05
5.5
5.5
Figure 5. Slim Type(4/8/16) Bottom
NAND
NAND
IC Chip
PCB
Figure 6. Slim Type(4/8/16GB) Side
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NAND Flash-based Solid State Disk
2.3 Slim Type Physical Dimensions (32GB)
53.60
R 0.5
14.45
17.15
22.00
Connector
1.05
0.5
Contact No.
1
0.5
1 8 0 F B G A
l l e o r n t r C o
NAND
NAND
NAND
NAND
NAND
5.20
NAND
2.5
2.5
4.01
2.0
6.4
Figure 7. Slim Type(32GB) Top
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Sep. 27. 2006
NAND Flash-based Solid State Disk
R 0.5
2.0
53.60
5.5
1.05
5.5
5.5
Figure 8. Slim Type(32GB) Bottom
NAND
NAND
Connector
PCB
Figure 9. Slim Type(32GB) Side
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Sep. 27. 2006
NAND Flash-based Solid State Disk
3. Product Specifications
3.1 System Interface and Configuration
• PIO 0~4 mode,
• Up to ATA5 and UDMA mode4(Ultra DMA66)
• Fully compatible with ATA5 Specification
3.2 System Performance
(Sandra 2005, 32GB)
Read / Write
Performance(MB/s)
Max 56
Random Read Sector
Random Write Sector
Sequential Read Sector
Sequential Write Sector
Max 13
Max 56
Max 32
3.3 System Power Consumption
(32GB)
Current
Active
Idle
Typical(mA)
200
20
Standby
20
3.4 System Reliability
MTBF
1,000,000 Hours
3.5 Environmental Specifications
Features
Temperature
Humidity
Vibration
Shock
Operating
Non-Operating
-40’C ~ 85’C
-25’C ~ 85’C
0’C to 55’C / 90~98% RH, 10cycles
20G Peak, 10 ~ 2000Hz, (12cycle / Axis) x3 Axis
1500G, duration 0.5ms, Half Sine Wave
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NAND Flash-based Solid State Disk
4. Electrical Specification
4.1 ZIF Connector Dimensions
4.93
4.00
22.00
19.50
0.5±0.10
Contact No. 1
Figure 7. Connector Top
Figure 8. Connector Side
*ZIF: Zero Insertion Force
4.2 Pin Assignment
Pin No
1
Signals
Reserved
Reserved
RESET
GROUND
DD7
Pin No
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signals
GROUND
DMARQ
GROUND
DIOW
2
3
4
5
DIOR
6
DD8
GROUND
IORDY
GROUND
DMACK
INTRQ
DA1
7
DD6
8
DD9
9
DD5
10
11
12
13
14
15
16
17
18
19
20
DD10
DD4
DD11
DD3
PDIAG
DA0
DD12
DD2
DA2
CS0
DD13
DD1
CS1
DASP
DD14
DD0
3.3V
3.3V
DD15
Reserved
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NAND Flash-based Solid State Disk
4.3 Signal Descriptions
"I" of I/O type represents an input signal from the device and "O" represents an output signal from the device.
Signal name
Pin NO
Type
Description
This is a reset signal output from the host system and to be used for inter-
face logic circuit.
RESET
3
I
This is a 16bit bi-directional data bus. The lover 8 bits are used for register
acess other that data register.
DD0 - DD15
DIOW
5-20
24
I/O
I
This rising edge of this Write Strobe signal clocks data from the host data
bus into a register on the device.
Assertion of this signal by the host during an Ultra DMA burst signals the
termination of the Ultra DMA burst.
STOP*
Activating this Read Strobe signal enables data from a register on the
device to be clocked onto the host data bus. The rising edge of this signal
latches data at the host.
DIOR
This signal is a flow control signal for Ultra DMA Read. Host asserts this
signal, and indicates that the host is ready to receive Ultra DMA read data.
HDMARDY*
HSTROBE*
IORDY
25
I
This signal is Write data strobe signal from the host for an Ultra DMA Write.
Both the rising and falling edge latch the data from DD(15:0) into the
device.
This signal is used to temporarily stop the host register access(read or
write) when the device is not ready to respond to a data transfer request.
This signal is flow control signal for Ultra DMA Write. Device asserts this
signal, and indicates that the device is ready to receive Ultra DMA Write
data.
DDMARDY*
27
30
O
O
This signal is the data in strobe signal from the device for an Ultra DMA
Read. Both the rising and falling edge latch the data from DD(15:0) into the
host.
DSTROBE*
INTRQ
This is an interrupt signal for the host system. This signal is asserted by a
selected device when the nIEN bit in the Device Control Register is "0". In
other cases, this signal should be a high impedance state.
DA0-2
31,33,34
32
I
This is a register address signal from the host system.
The host shall wait until the power on or hardware reset sequence is com-
plete for all devices on the cable;
PDIAG:CBLID*
I/O
This device chip selection signal is used to select the Control Block Regis-
ters from the host system.
CS0
CS1
35
36
I
I
This device chip selection signal is used to select the Command Block
Registers from the host system.
This signal indicates that a device is active when the power is turned on.
Upon receipt of a command from the host, the device asserts this signal. At
command completion, the device de-asserts this signal.
DASP
37
I/O
The device shall assert this signal, used for DMA data transfers between
host and device, when it is ready to transfer data.
DMARQ
DMACK
22
29
O
I
The host in response to DMARQ to either acknowledge that data has been
accepted, or that data is available shall use this signal.
The device is configured as either Device 0(Master) or Device 1(Slave)
depending upon the signal level of 40 pin DEVADR signal.
- When used as Device 1(Master), DEVADR is open
DEVADR
40
I
- When used as Device 1(Slave), the host shall have pull-up resistor. Rec-
ommended pull-up register is 10K ohm based on +3.3Vcc.
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NAND Flash-based Solid State Disk
4.4 DC Characteristics
4.4.1 Absolute Maximum Ratings
Characteristics
DC Supply Voltage
Symbol
Rating
-0.3 to 4.6
3.8
Unit
V
VDD
V
IN/VOUT
IIN
Input/Output Voltage
DC Input Current
V
+/- 200
-40 to 85
mA
°C
TSTG
Storage Temperature
4.4.2 Recommended Operating Conditions
Characteristics
DC Supply Voltage
Symbol
Rating
3.0 to 3.6
3.0 to 3.6
-25 to 85
Unit
V
VDD
V
IN/VOUT
TOPR
Input/Output Voltage
V
Operating Temperature
°C
4.4.3 Electrical Characteristics - Normal I/O
Vdd = 3.0 to 3.6(V), Ta = 25(°C), Vext = 5V ± 0.25V
Characteristics
Symbol
Test Condition
Min
Typ
Max
Unit
VIN = VDD
Normal
Down
-10
10
-
-
10
60
uA
uA
IIH
Input High Current
Pull - Down
VIN = VSS
Pull - Up
Normal
Up
-10
-60
-
-
10
-10
uA
uA
IIL
Input Low Current
VIH
VIL
Input High Voltage
CMOS
CMOS
2.0
-
-
-
-
-
-
-
V
V
Input Low Voltage
0.8
-
VOH
VOL
IOZ
6mA Buffer, IOH = -6mA
6mA Buffer, IOL = 6mA
VOUT = VDD or VSS
Output High Voltage
Output Low Voltage
2.4
-
V
0.4
10
V
Tri-state Output Leakage Current
-10
uA
NOTE:
* Schmitt Trigger test condition : V = 3.0 to 3.6(V), Ta = 25(°C)
DD
Characteristic:
These DC parameters guarantee the I/O cell characteristic at the static state only, not at the dynamic state.
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NAND Flash-based Solid State Disk
4.5 AC Characteristics
4.5.1 Register Transfers
Figure 1 defines the relationships between the interface signals for register transfers. Peripherals reporting support for PIO mode 3 or
4 shall power-up in a PIO mode 0,1, or 2.
For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 1
defines the minimum value that shall be placed in word 68.
Both hosts and devices shall support IORDY when PIO mode 3 or 4 are the currently selected mode of operation.
t0
ADDR valid
(See note 1)
t1
t2
t9
t2i
DIOR-/DIOW-
WRITE DD(7:0)
(See note 2)
t3
t4
READ DD(7:0)
(See note 2)
t5
t6
t6Z
IORDY
(See note 3,3-1)
tA
IORDY
(See note 3,3-2)
tC
tRD
IORDY
(See note 3,3-3)
tB
tC
Figure 1. Register transfer to/from device.
NOTE:
1. Device address consists of signals CS0-, CS1- and DA(2:0)
2. Data consists of DD(7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made
by the host after t from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases:
A
3-1. Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2. Device negates IORDY before t , but causes IORDY to be asserted before t .
A
A
IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.
3-3. Device negates IORDY before t . IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated.
A
The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on
DD(7:0) for t before asserting IORDY.
RD
4. DMACK- shall remain negated during a register transfer.
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NAND Flash-based Solid State Disk
Table 1 - Register transfer to/from device
Register transfer timing parameters
Cycle time
Mode 0ns Mode 1ns Mode 2ns Mode 3ns Mode 4ns
Note
t0
t1
min
min
min
min
min
min
min
min
max
min
600
70
290
-
383
50
290
-
330
30
290
-
180
30
80
70
30
10
20
5
120
25
70
25
20
10
20
5
1,4,5
Address validto DIOR-/DIOW-setup
DIOR-/DIOW- pulse width 8bit
DIOR-/DIOW- recovery time
DIOW- data setup
t2
1
1
t2i
t3
60
30
50
5
45
20
35
5
30
15
20
5
t4
DIOW- data hold
t5
DIOR- data setup
t6
DIOR- data hold
t6Z
t9
DIOR- data tristate
30
20
30
15
30
10
30
10
30
10
2
3
DIOR-/DIOW- to address valid hold
Read Data Valid to IORDY active
(if IORDY initially low after tA)
tRD
min
0
0
0
0
0
tA
tB
tC
IORDY setup time
35
1250
5
35
1250
5
35
1250
5
35
1250
5
35
1250
5
IORDY pulse width
max
max
IORDY assertion to release
NOTE:
1. t is the minimum total cycle time, t is the minimum DIOR-/DIOW- assertion time, and A host implementation shall lengthen t and/or t to ensure
0
2
2
2i
that t is equal to or greater than the value reported in the devices INDENTIFY DEVICE data. A device implementation shall support any legal host
0
implementation.
2. This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device.
3. The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY
negated at the t after the activation of DIOR- or DIOW-, then t shall be met and t is not applicable. If the device is driving IORDY negated at the
A
5
RD
time t after the activation of DIOR- or DIOW-, then t shall be met and t is not applicable.
A
RD
5
4. ATA/ATAPI standards prior to ATA/ATAPI-5 inadvertently specified an incorrect value for mode2 time t0 by utilizing the 16-bit PIO value.
5. Mode shall be selected no faster than the highest mode supported by the slowest device.
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NAND Flash-based Solid State Disk
4.5.2 PIO Data Transfers
Figure 2 defines the relationships between the interface signals for PIO data transfers. Peripherals reporting support for PIO mode 3
or 4 shall power-up in a PIO mode 0,1, or 2.
For PIO modes 3 and above, the minimum value of t0 is specified by word 68 in the IDENTIFY DEVICE parameter list. Table 2
defines the minimum value that shall be placed in word 68.
IORDY shall be supported when PIO mode 3 or 4 are the current mode of operation.
t0
ADDR valid
(See note 1)
t1
t2
t9
t2i
DIOR-/DIOW-
WRITE DD(15:0)
DD(7:0)
(See note 2)
t3
t4
READ DD(15:0)
DD(7:0)
(See note 2)
t5
t6
t6Z
IORDY
(See note 3,3-1)
tA
IORDY
(See note 3,3-2)
tC
tRD
IORDY
(See note 3,3-3)
tB
tC
Figure 2. PIO data transfer to/from device.
NOTE:
1. Device address consists of signals CS0-, CS1- and DA(2:0)
2. Data consists of DD(15:0) for all devices except devices implementing the CFA feature set when 8-bit transfers is enabled. In that case, data consists
of DD(7:0)
3. The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made
by the host after t from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases:
A
3-1. Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2. Device negates IORDY before t , but causes IORDY to be asserted before t .
A
A
IORDY is released prior to negation and may be asserted for no more than 5ns before release: no wait generated.
3-3. Device negates IORDY before t . IORDY is released prior to negation and may be asserted for no more than 5ns before release: wait generated.
A
The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on
DD(7:0) for t before asserting IORDY.
RD
4. DMACK- shall be negated during a PIO data transfer.
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NAND Flash-based Solid State Disk
Table 2 - PIO data transfer to/from device
PIO timing parameters
Cycle time
Mode 0ns Mode 1ns Mode 2ns Mode 3ns Mode 4ns
Note
t0
t1
min
min
min
min
min
min
min
min
max
min
600
70
165
-
383
50
125
-
240
30
100
-
180
30
80
70
30
10
20
5
120
25
70
25
20
10
20
5
1,4
Address valid to DIOR-/DIOW- setup
DIOR-/DIOW-
t2
1
1
t2i
t3
DIOR-/DIOW- recovery time
DIOW- data setup
60
30
50
5
45
20
35
5
30
15
20
5
t4
DIOW- data hold
t5
DIOR- data setup
t6
DIOR- data hold
t6Z
t9
DIOR- data tristate
30
20
30
15
30
10
30
10
30
10
2
3
DIOR-/DIOW- to address valid hold
Read Data Valid to IORDY active
(if IORDY initially low after tA )
tRD
min
0
0
0
0
0
tA
tB
tC
IORDY setup time
35
1250
5
35
1250
5
35
1250
5
35
1250
5
35
1250
5
IORDY pulse width
max
max
IORDY assertion to release
NOTE:
1. t is the minimum total cycle time, t is the minimum DIOR-/DIOW- assertion time, and t is the minimum DIOR-/DIOW- negation time. A host imple-
0
2
21
mentation shall lengthen t and/or t to ensure that t is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device
2
2i
0
implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device.
3. The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is
active before the PIO cycle is completed. If the device is not driving IORDY negated at the t after the activation of DIOR- or DIOW-, then t shall be met
A
5
and t is not applicable. If the device is driving IORDY negated at the time t after the activation of DIOR- or DIOW-, then t shall be met and t is not
RD
A
RD
5
applicable.
4. Mode may be selected at the highest mode for the device if CS(1:0) and AD(2:0) do not change between read or write cycles or selected at the high-
est mode supported by the slowest device if CS(1:0) or AD(2:0) do change between read or write cycles.
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NAND Flash-based Solid State Disk
4.5.3 Multiword DMA Data Transfers
Figure 3 through Figure 6 define the timing associated with Multiword DMA transfers.
For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the IDENTIFY DEVICE parameter list.
Table 3 defines the minimum value that shall be placed in word 65.
Devices shall power-up with mode 0 as the default Multiword DMA mode.
Table 3 - Multiword DMA data transfer
Multiword DMA timing parameters
Cycle time
Mode 0ns
480
215
150
5
Mode 1ns
Mode 2ns
Note
t0
tD
min
min
max
min
min
min
min
min
min
min
max
max
min
min
max
150
80
60
5
120
70
50
5
see note
see note
DIOR-/DIOW- asserted pulse width
DIOR- data access
tE
tF
DIOR- data hold
tG
tH
DIOR-/DIOW-data setup
DIOW- data hold
100
20
30
15
0
20
10
0
tI
DMACK to DIOR-/DIOW- data setup
DIOR-/DIOW- to DMACK hold
DIOR- negated pulse width
DIOW- negated pulse width
DIOR- to DMARQ delay
DIOW- to DMARQ delay
CS(1:0) valid to DIOR-/DIOW-
CS(1:0) hold
0
tJ
20
5
5
tKR
tKW
tLR
tLW
tM
tN
50
50
50
40
40
30
10
25
25
25
35
35
25
10
25
see note
see note
215
120
40
50
15
tZ
DMACK- to read data released
20
NOTE:
> t is the minimum total cycle time, t is the minimum DIOR-/DIOW- assertion time, and t (t or t , as appropriate) is the minimum DIOR-/DIOW-
0
D
K
KR
Kw
negation time. A host shall lengthen t and/or t to ensure that t is equal to the value reported in the devices IDENTIFY DEVICE data.
D
K
0
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NAND Flash-based Solid State Disk
4.5.3.1 Initiating a Multiword DMA data burst
The values for the timings for each of the Multiword DMA modes are contained in Table 50.
CS0-/CS1-
tM
See note
DMARQ
See note
DMACK-
tD
DIOR-/DIOW-
tE
READ
DD(15:0)
tG
tF
WRITE
DD(15:0)
tG
tH
Figure 3. Initiating a Multiword DMA data transfer
NOTE:
The host shall not assert DMACK- or negate both CS0 and CS1 until the assertion of DMARQ is detected. The maxium time from the assertion of
DMARQ to the assertion of DMACK- or the negation of both CS0 and CS1 is not defined.
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4.5.3.2 Sustaining a Multiword DMA data burst
The values for the timings for each of the Multiword DMA modes are contained in Table 50.
CS0-/CS1-
t0
DMARQ
DMACK-
tD
tK
DIOR-/DIOW-
tE
tE
READ
DD(15:0)
tG
tG
tF
tG
tG
tF
WRITE
DD(15:0)
tH
tH
Figure 4. Sustaining a Multiword DMA data transfer
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NAND Flash-based Solid State Disk
4.5.3.3 Device terminating a Multiword DMA data burst
The values for the timings for each of the Multiword DMA modes are contained in Table 50.
CS0-/CS1-
t0
tN
DMARQ
(See note)
tL
DMACK-
tK
tD
tJ
DIOR-/DIOW-
tE
tZ
READ
DD(15:0)
tG
tG
tF
WRITE
DD(15:0)
tH
Figure 5. Device terminating a Multiword DMA data transfer
NOTE:
To terminate the data burst, the Host shall negate DMARQ within the tL of the assertion of the current DIOR- or DIOW- pulse. The last data word for the
burst shall then be transferred by the negation of the current DIOR- or DIOW- pulse. If all data for the command has not been transferred, the Host shall
reassert DMARQ again at any later time to resume the DMA operation.
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4.5.3.4 Host terminating a Multiword DMA data burst
The values for the timings for each of the Multiword DMA modes are contained in Table 50.
CS0-/CS1-
t0
tN
DMARQ
(See note 2)
DMACK-
tK
tD
tJ
(See note 1)
DIOR-/DIOW-
tE
tZ
READ
DD(15:0)
tG
tG
tF
WRITE
DD(15:0)
tH
Figure 6. Host terminating a Multiword DMA data transfer
NOTE:
1. To terminate the transmission of a data burst, the host shall negate DMACK- within the specified time after a DIOR- or DIOW- pulse. No further
DIOR- or DIOW- pulses shall be asserted for this burst.
2. If the device is able to continue the transfer of data, the Host may leave DMARQ asserted and wait for the host to reassert DMACK- or may negate
DMARQ at any time after detecting that DMACK- has been negated.
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4.5.4 Ultra DMA data burst
Figure 7 through Figure 16 define the timings associated with all phases of Ultra DMA bursts.
Table 4 contains the values for the timings for each of the Ultra DMA modes.
Table 4 - Ultra DMA data burst timing requirements
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Comment
(See Notes 1 and 2)
Name
t2CYCTYP
tCYC
min max min max min max min max min max
240
112
160
73
120
54
90
39
60
25
Typical sustained average two cycle time
Cycle time allowing for asymmetry and clock varia-
tions (from STROBE edge to STROBE edge)
Two cycle time allowing for clock variations (from ris-
ing edge to next rising edge or from falling edge to
next falling edge of STROBE)
t2CYC
230
154
115
86
57
tDS
tDH
15
5
10
5
7
5
7
5
5
5
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender (from data valid until
STROBE edge) (See Note 4)
tDVS
tDVH
tFS
70
6
48
6
30
6
20
6
6
6
0
Data valid hold time at sender (from STROBE edge
until data may become invalid) (See Note 4)
First STROBE time (for device to first negate
DSTROBE from STOP during a data in burst)
0
230
150
0
200
150
0
170
150
0
130
100
120
tLI
tMLI
tUI
0
20
0
0
20
0
0
20
0
0
20
0
0
20
0
100 Limited interlock time (See Note 3)
Interlock time with minimum(See Note 3)
Unlimited interlock time (See Note 3)
Maximum time allowed for output drivers to release
(from asserted or negated)
tAZ
10
70
10
70
10
70
10
55
10
tZAH
tZAD
20
0
20
0
20
0
20
0
20
0
Minimum delay time required for output
Drivers to assert or negate (from released)
Envelope time (from DMACK- to STOP and
55 HDMARDY- during data in burst initiation and from
DMACK to STOP during data out burst initiation)
tENV
20
20
20
20
20
STROBE-to-DMARDY- time (if DMARDY- is negated
NA before this long after STROBE edge, the recipient
shall receive no more than one additional data word)
tSR
50
75
30
70
20
60
NA
60
Ready-to-final-STROBE time (no STROBE edges
tRFS
60
shall be sent this long after negation of DMARDY-)
tRP
160
125
100
100
100
Minimum time to assert STOP or negate DMARQ
20 Maximum time before releasing IORDY
tIORDYZ
tZIORDY
20
20
20
20
0
0
0
0
0
Minimum time before driving STROBE (See Note 5)
Setup and hold times for DMACK- (before assertion
or negation)
tACK
tSS
20
20
20
20
20
Time from STROBE edge to negation of DMARQ or
assertion of STOP (when sender terminates a burst)
50
50
50
50
50
NOTE:
1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies. For example, the sender shall stop
generating STROBE edges t
after the negation of DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the
RFS
sender.
2. All timing measurement switching points(low to high and high to low) shall be taken at 1.5V.
3. t , t , and indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the other to respond with a
UI MLI
tLI
signal before proceeding. t is an inlimited interlock that has no maximum time value. t
UI
is a limited time-out that has a defined minimum. t is a lim-
LI
MLI
ited time-out that has a defined maximum.
4. The test load for t
and t
shall be a lumped capacitor load with no cable or receivers. Timing for t
and t
shall be met for all capacitive
DVH
DVS
DVH
DVS
loads from 15 to 40 pf where all signals have the same capacitive load value.
5. t
may be greater than t
since the device has a pull up on IORDY- giving it a known state when released.
ENV
ZIORDY
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NAND Flash-based Solid State Disk
4.5.4.1 Initiating an Ultra DMA data-in burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
DMARQ
(device)
tUI
DMACK-
(host)
tACK
tACK
tENV
tENV
tFS
tFS
tZAD
tZAD
STOP
(host)
HDMARDY-
(host)
tZIORDY
DSTROBE
(device)
tAZ
tDVS
tDVH
DD(15:0)
tACK
DA0,DA1,DA2,
CS0-,CS1-
Figure 7. Initiating an Ultra DMA data-in burst
NOTE:
1. The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until DMARQ
and DMACK are asserted.
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4.5.4.2 Sustained Ultra DMA data-in burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
t2CYC
tCYC
tCYC
t2CYC
DSTROBE
at device
tDVH
tDVS
tDVH
tDVS
tDVH
DD(15:0)
at device
DSTROBE
at host
tDH
tDS tDH
tDS tDH
DD(15:0)
at host
Figure 8. Sustained Ultra DMA data-in burst
NOTE:
1. DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay
shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
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NAND Flash-based Solid State Disk
4.5.4.3 Host pausing an Ultra DMA data-in burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
DMARQ
(device)
DMACK-
(host)
tRP
STOP
(host)
tSR
HDMARDY-
(host)
tRFS
DSTROBE
(device)
DD(15:0)
(device)
Figure 9. Host pausing an Ultra DMA data-in burst
NOTE:
1. The host mat assert STOP to request termination of the ultra DMA burst no sooner than tRP after HDMARDY- is negated.
2. If the t timing is not satisfied, the host may receive zero, one, or two more data words from the Host.
SR
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NAND Flash-based Solid State Disk
4.5.4.4 Device terminating an Ultra DMA data-in burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
DMARQ
(device)
tMLI
DMACK-
(host)
tLI
tLI
tLI
tACK
tACK
STOP
(host)
HDMARDY-
(host)
tSS
tIORDYZ
DSTROBE
(device)
tZAH
tAZ
tDVH
CRC
DD(15:0)
tACK
DA0,DA1,DA2,
CS0-,CS1-
Figure 10. Device terminating an Ultra DMA data-in burst
NOTE:
1. The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
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NAND Flash-based Solid State Disk
4.5.4.5 Host terminating an Ultra DMA data-in burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
DMARQ
(device)
tLI
tMLI
DMACK-
(host)
tZAH
tAZ
tRP
tACK
tACK
STOP
(host)
HDMARDY-
(host)
tRFS
tLI
tMLI
tIORDYZ
DSTROBE
(device)
tDVS tDVH
CRC
DD(15:0)
tACK
DA0,DA1,DA2,
CS0-,CS1-
Figure 11. Host terminating an Ultra DMA data-in burst
NOTE:
1. The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE and IORDY:DDMARDY-:DSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
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NAND Flash-based Solid State Disk
4.5.4.6 Initiating an Ultra DMA data-out burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
DMARQ
(device)
tUI
DMACK-
(host)
tACK
tENV
STOP
(host)
tLI
tUI
tZIORDY
tACK
HDMARDY-
(host)
DSTROBE
(device)
tDVS tDVH
DD(15:0)
tACK
DA0,DA1,DA2,
CS0-,CS1-
Figure 12. Initiating an Ultra DMA data-out burst
NOTE:
1. The definitions for the DIOW-:STOP,IORDY:DDMARDY-:DSTROBE and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
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4.5.4.7 Sustained Ultra DMA data-out burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
t2CYC
tCYC
tCYC
t2CYC
HSTROBE
at host
tDVH
tDVS
tDVH
tDVS
tDVH
DD(15:0)
at host
HSTROBE
at device
tDH
tDS tDH
tDS tDH
DD(15:0)
at device
Figure 13. Sustained Ultra DMA data-out burst
NOTE:
1. DD(15:0) and HSTROBE signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay
shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.
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NAND Flash-based Solid State Disk
4.5.4.8 Device pausing an Ultra DMA data-out burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
tRP
DMARQ
(device)
DMACK-
(host)
STOP
(host)
tSR
DDMARDY-
(device)
tRFS
HSTROBE
(host)
DD(15:0)
(host)
Figure 14. Device pausing an Ultra DMA data-out burst
NOTE:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner that t after DDMARDY- is negated.
RP
2. If the t timing is not satisfied, the device may receive zero,one,or two more data words from the host.
SR
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Sep. 27. 2006
NAND Flash-based Solid State Disk
4.5.4.9 Host terminating an Ultra DMA data-out burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
tLI
DMARQ
(device)
tMLI
DMACK-
(host)
tSS
tLI
tACK
STOP
(host)
tLI
tIORDYZ
HDMARDY-
(host)
tACK
DSTROBE
(device)
tDVS tDVH
DD(15:0)
(host)
CRC
tACK
DA0,DA1,DA2,
CS0-,CS1-
Figure 15. Host terminating an Ultra DMA data-out burst
NOTE:
1. The definitions for the DIOW-:STOP,IORDY:DDMARDY-:DSTROBE and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
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NAND Flash-based Solid State Disk
4.5.4.10 Device terminating an Ultra DMA data-out burst
The values for the timings for each of the Ultra DMA modes are contained in 4.4.4
DMARQ
(device)
DMACK-
(host)
tLI
tMLI
tACK
STOP
(host)
tRP
tIORDYZ
DDMARDY-
(device)
tRFS
tLI
tMLI
tACK
HSTROBE
(host)
tDVS tDVH
DD(15:0)
(host)
CRC
tACK
DA0,DA1,DA2,
CS0-,CS1-
Figure 16. Device terminating an Ultra DMA data-out burst
NOTE:
1. The definitions for the DIOW-:STOP,IORDY:DDMARDY-:DSTROBE and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
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NAND Flash-based Solid State Disk
5. ATA Registers
5.1 I/O Register Descriptions
Communication to or from the device is through registers addressed by the signals from the host(CS0-,CS1-, DA(2:0), DIOR-, and
DIOW), CS0- and CS1- both asserted or negated is an invalid (not used) address except when both are negated during a DMA data
transfer. When CS0- and CS1- are both asserted or both negated and a DMA transfer is not in progress, the device shall hold DD
(15:0) in the released state and ignore transitions on DIOR- and DIOW-. When CS0- is negated and CS1- is asserted only DA (2:0)
with a value of 6th is valid. During invalid combinations of assertion and negation of CS0-, CS1-, DA0, DA1, and DA2, a device shall
keep DD(15:0) in the high impedance state and ignore transitions on DIOR- and DIOW-. Valid register addresses are described in
the clauses defining the registers.
Address - the CS and DA address of the register.
Direction - indicates if the register is read/write, read only, or write only from the host.
Access restrictions - indicates when the register may be accessed.
Effect - indicates the effect of accessing the register.
Functional description - describes the function of the register.
Field/bit description - describes the content of the register.
5.2 Alternate Status Register
5.2.1 Address
CS1
A
CS0
N
DA2
DA1
A
DA0
N
A
A=asserted, N=negated
5.2.2 Direction
This register is read only. If this address is written to by the host, the Device Control register is written.
5.2.3 Access Restrictions
When the BSY bit is set to one, the other bits in this register shall not be used. The entire contents of this register are not valid while
the device is in Sleep mode.
5.2.4. Effect
Reading this register shall not clear a pending interrupt.
5.2.5 Functional Description
This register contains the same information as the Status register in the command block.
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NAND Flash-based Solid State Disk
5.3 Command Register
5.3.1 Address
CS1
N
CS0
A
DA2
DA1
A
DA0
N
A
A=asserted, N=negated
5.3.2 Direction
This register is write only. If this address is read by the host, the Status register is read.
5.3.3 Access Restrictions
For all commands, this register shall only be written when BSY and DRQ are both cleared to zero and DMACK- is not asserted. If
written when BSY or DRQ is set to one, the results of writing the Command register are indeterminate.
5.3.4 Effect
Command prcessing begins when this register is writte. The content of the Command Blcok registers become parameters of the
command when this register is written. Writing this register clears any pending interrupt condition.
5.3.5 Functional description
This register contains the command code being sent to the device. Command execution begins immediately after this register is writ-
ten.
5.3.6 Field/bit description
7
6
5
4
3
2
1
0
Command Code
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Sep. 27. 2006
NAND Flash-based Solid State Disk
5.4 Cylinder High Register
5.4.1 Address
CS1
N
CS0
A
DA2
DA1
N
DA0
A
A
A=asserted, N=negated
5.4.2 Direction
This register is read/write.
5.4.3 Access Restrictions
This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is noet asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY or DRQ is set to one, the
result is indeterminate. The contents of this register are not valid while a device is in the Sleep mode.
5.4.4 Effect
The content of this register becomes a command parameter when the Comand register is written.
5.4.5 Functional description
The content of this register is command dependent
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5.5 Cylinder Low Register
5.5.1 Address
CS1
N
CS0
A
DA2
DA1
N
DA0
N
A
A=asserted, N=negated
5.5.2 Direction
This register is read/write.
5.5.3 Access Restrictions
This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY or DRQ is set to one, the
result is indeterminate. The contents of this register are not valid while a device is in the Sleep mode.
5.5.4 Effect
The content of this register becomes a command parameter when the Command register is written.
5.5.5 Functional description
The content of this register is command dependent
5.6 Data Port
5.6.1 Address
When DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16-bits wide.
CS1
N
CS0
N
DA2
DA1
X
DA0
X
X
A=asserted, N=negated, X=don’t care
5.6.2 Direction
This register is read/write.
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5.6.3 Access Restrictions
This port shall be accessed for host DMA data transfers only when DMACK- and DMARQ are asserted.
5.6.4 Effect
The content of this register becomes a command parameter when the Command register is written. DMA out data transfers are pro-
cessed by a series of reads to this port, each read transferring the data that follows the previous read. DMA in data transfers are pro-
cessed by a series of writes to this port, each write transferring the data that follows the previous write. The results of a read during a
DMA in or a write during a DMA out are indeterminate.
5.6.5 Functional description
The data port is 16-bits in width.
5.6.6 Field / bit description
15
14
13
5
12
4
11
3
10
2
9
1
8
0
Data(15:8)
Data(7:0)
7
6
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5.7 Data Register
5.7.1 Address
CS1
N
CS0
A
DA2
DA1
N
DA0
N
N
A=asserted, N=negated
5.7.2 Direction
This register is read/write.
5.7.3 Access Restrictions
This register shall be accessed for host PIO data transfer only when DRQ is set to on and DMACK- is not asserted.
The contents of this register are not valid while a device is in the Sleep mode.
5.7.4 Effect
PIO out data transfers are processed by a series of reads to this register, each read transferring the data that follows the previous
read. PIO in data transfers are processed by a series of writes to this register, each write transferring the data that follows the previ-
ous write. The results of a read during a PIO in or a write during a PIO out are indeterminate.
5.7.5 Functional description
The data port is 16-bits in width. When a CFA device is in 8-bit PIO data transfer mode this register is 8-bits wide using only DD7 to
DD0.
5.7.6 Field / bit description
15
14
13
5
12
4
11
3
10
2
9
1
8
0
Data(15:8)
Data(7:0)
7
6
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5.8 Device Control Register
5.8.1 Address
CS1
A
CS0
N
DA2
DA1
A
DA0
N
A
A=asserted, N=negated
5.8.2 Direction
This register is write only. If this address is read by the host, the Alternate Status register is read.
5.8.3 Access Restrictions
This register shall only be written when DMACK- is not asserted.
5.8.4 Effect
The content of this register shall take effect when written.
5.8.5 Functional description
This register allows a host to software reset attached devices and to enable or disable the assertion of the INTRQ signal by a
selected device. When the Device Control Register is written, both devices respond to the write regardless of which device is
selected. When the SRST bit is set to one, both devices shall perform the software reset protocol.
The device shall respond to the SRST bit when in the SLEEP mode.
5.8.6 Field / bit description
7
r
6
r
5
r
4
r
3
r
2
1
0
0
SRST
nIEN
• Bits 7 through 3 are reserved.
• SRST is the host software reset bit.
• nIEN is the enable bit for the device Assertion of INTRQ to the host. When the nIEN bit is cleared to zero, and the device is
selected, INTRQ shall be enabled through a tri-state buffer and shall be asserted or negated by the device as appropriate. When the
nIEN bit is set to one, or the device is not selected, the INTRQ signal shall be in a high impedance state.
• Bit 0 shall be cleared to zero.
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5.9 Device / Head Register
5.9.1 Address
CS1
N
CS0
A
DA2
DA1
A
DA0
N
A
A=asserted, N=negated
5.9.2 Direction
This register is read/write.
5.9.3 Access Restrictions
This register shall be written only when both BSY and DRQ are cleared to zero and DMACK- is not asserted.
The contents of this register are valid only when BSY is cleared to zero. If this register is written when BSY or DRQ is set to one, the
result is indeterminate.
5.9.4 Effect
The DEV bit becomes effective when this register is written by the host or the signature is set by the device. All other bits in this reg-
ister become a command parameter when the Command register is written.
5.9.5 Functional description
But 4, DEV, in this register selects the device. Other bits in this register are command dependent.
5.9.6 Field / bit description
The content of this register shall take effect when written.
7
6
#
5
4
3
#
2
#
1
#
0
#
Obsolete
Obsolete
DEV
NOTE:
Some hosts set these bits to one. Devices shall ignore these bits.
• Obsolete:These bits are obsolete.
• #:The content of these bits is command dependent
• DEV: Device select. Cleared to zero selects Device 0. Set to one selects Device1.
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5.10 Error Register
5.10.1 Address
CS1
N
CS0
A
DA2
DA1
N
DA0
A
N
A=asserted, N=negated
5.10.2 Direction
This register is read only. If this address is written to by the host, the Features register is written.
5.10.3 Access Restrictions
The contents of this register shall be valid when BSY and DRQ equal zero and ERR equals one.
The contents of this register shall be valid upon completion of power-on, or after a hardware or software reset, or after command
completion of an EXECUTE DEVICE DIAGNOSTICS. The contents of this register are not valid while a devcie is in the Sleep mode.
5.10.4 Effect
None.
5.10.5 Functional description
This register contains status for the current command.
Following a power-on, a hardware or software reset, or command completion of an EXECUTE DEVICE DIAGNOSTIC, this register
contains a diagnostic code. At command description of any command except EXECUTE DEVICE DIAGNOSTIC, the contents of this
register are valid when the ERR bit is set to one in the Status Register.
5.10.6 Field / bit description
7
#
6
#
5
#
4
#
3
#
2
1
#
0
#
ABRT
• Bit 2: ABRT(command aborted) is set to one to indicate the requested command has been command aborted because the com-
mand code or a command parameter is invalid or some other error has occurred.
•#: The content of this bit is command dependent
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5.11 Features Register
5.11.1 Address
CS1
N
CS0
A
DA2
DA1
N
DA0
A
N
A=asserted, N=negated
5.11.2 Direction
This register is write only. If this address is read by the host, the Error register is read.
5.11.3 Access Restrictions
This register shall be written only when BSY and DRQ equal zero and DMACK- is not asserted. If this register is written when BSY or
DRQ is set to one, the result is indeterminate.
5.11.4 Effect
The content of this register becomes a command parameter when the Command register is written.
5.11.5 Functional description
The content of this register is command dependent.
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5.12 Sector Count Register
5.12.1 Address
CS1
N
CS0
A
DA2
DA1
A
DA0
N
N
A=asserted, N=negated
5.12.2 Direction
This register is read/write.
5.12.3 Access Restrictions
This register shall be written only when BSY and DRQ equal zero and DMACK- is not asserted. The contents of this register are valid
only when both BSY and DRQ are zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. The con-
tents of the this register are not valid while a device is in the Sleep mode.
5.12.4 Effect
The content of this register becomes a command parameter when the Command register is written.
5.12.5 Functional description
The content of this register is command dependent.
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5.13 Sector Number Register
5.13.1 Address
CS1
N
CS0
A
DA2
DA1
A
DA0
A
N
A=asserted, N=negated
5.13.2 Direction
This register is read/write.
5.13.3 Access Restrictions
This register shall be written only when BSY and DRQ equal zero and DMACK- is not asserted. The contents of this register are valid
only when both BSY and DRQ are zero. If this register is written when BSY or DRQ is set to one, the result is indeterminate. The con-
tents of the this register are not valid while a device is in the Sleep mode.
5.13.4 Effect
The content of this register becomes a command parameter when the Command register is written.
5.13.5 Functional description
The content of this register is command dependent.
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5.14 Status Register
5.14.1 Address
CS1
N
CS0
A
DA2
DA1
A
DA0
A
A
A=asserted, N=negated
5.14.2 Direction
This register is read only. If this address is written to by the host, the Command register is written.
5.14.3 Access Restrictions
The contents of this register, except for BSY, shall be ignored when BSY is set to one. BSY is valid at all times. The contents of this
register are not valid while a device is in the Sleep mode.
5.14.4 Effect
Reading this register when an interrupt is pending causes the interrupt pending to be cleared. The host should not read the Status
Register when an interrupt is expected as this may clear the interrupt pending before the INTRQ can be recognized by the host.
5.14.5 Functional description
The register contains the device status. The contents of this register are updated to reflect the current state of the device and the
progress of any command being executed by the device.
5.14.6 Field / bit description
7
6
5
#
4
#
3
2
1
0
BSY
DRDY
DRQ
Obsolete
Obsolete
ERR
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5.14.6.1 BSY(Busy)
BSY is set to one to indicate that device is busy. After the host has written the Command Register the device shall have either the
BSY bit set to one, or the DRQ bit set to one, until command completion or the device has performed a bus release for an overlapped
command.
The BSY bit shall be set to one by the device :
1) after either the negation of RESET- or the setting of the SRST bit to one in the Device Control Regitster;
2) after writing the Command Register if the DRQ bit is not set to one;
3) between blocks of a data transfer during PIO data-in commands before the DRQ bit is cleared to zero;
4) After the transfer of a data block during PIO data-out commands before the DRQ bit is cleared to zero;
5) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall be set to one;
NOTE:
The BSY bit may be set to one and then cleared to zero so quickly, that host detection of the BSY bit being set to one is not certain.
When BSY is set to one, the device has control of the Command Block Registers and;
1) a write to a Command Block Register by the host shall be ignored by the device except for writing DEVICE
RESET command;
2) a read from a Command Block register by the host will most likely yield invalid contents except for the BSY bit itself.
The BSY bit shall be cleared to zero by the device:
1)after setting DRQ to one to indicate is ready to transfer data;
2) at command completion;
3) upon releasing the bus for an overlapped command;
4) when the device is ready to accept commands that do not require DRDY during a power on, hardware or software reset.
When BSY is cleared to zero, the host has control of the Command Block registers, the device shall:
1) not set DRQ to one;
2) not change ERR bit;
3) not change the content of any other Command Block Register;
4) set the SERV bit to one when ready to continue an overlapped command that has been bus released.
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5.14.6.2 DRDY(Device ready)
The DRDY bit shall be set to one by the device :
1) when the device is capable of accepting all commands for devices
When the DRDY bit is set to one :
1) the device shall accept and attempt to execute all implemented commands;
2) devices that implement the Power Management feature set shall maintain the DRDY bit set to one when they are in the Idle or
Standby modes.
5.14.6.3 Command dependent
The use of bits marked with # are command dependent. Bit 4 was formerly the DSC(Device Seek Complete) bit.
5.14.6.4 DRQ(Data request)
DRQ indicates that the device is ready to transfer a word of data between the host and the device. After the host has written the
Command Register the device shall either set the BSY bit to one or the DRQ bit to one, until command completion or the device has
performed a bus release for an overlapped command.
The DRQ bit shall be set to one by the device :
1) when BSY is set to one and data is ready for PIO transfer;
2) during the data transfer of DMA commands either the BSY bit, the DRQ bit, or both shall be set to one.
When the DRQ bit is set to one, the host may :
1) transfer data via PIO mode;
2) transfer data via DMA mode if DMARQ and DMACK- are asserted.
The DRQ bit shall be cleared to zero, the host may :
1) transfer data via DMA mode if DMARQ and DMACK- are asserted and BSY is set to one.
5.14.6.5 Obsolete bits
Some bits in this register were defined in previous ATA standards but have been declared obsolete in this spec
These bits are labeled "obsolete".
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5.14.6.6 ERR(Error)
ERR indicates that an error occurred during execution of the previous command.
The ERR bit shall be set to one by the device :
1) when BSY or DRQ is set to one and an error occurs in the executing command.
When the ERR bit is set to one :
1) the bits in the Error register shall be valid;
2) the device shall not change the contents of the following registers until a new command has been accepted, the SRST bit is set to
one or RESET- is asserted :
• Error Register
• Cylinder High/Low Register
• Sector Count Register
• Sector Number Register
• Device / Head Register
The ERR bit shall be cleared to zero by the device :
1) when a new command is written to the Command Register;
2) when the SRST bit is set to one;
3) when the RESET- signal is asserted.
When the ERR bit is cleared to zero at the end of a command:
1) the content of the Error Register shall be ignored by the host.
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6. Command Descriptions
6.1 Supporting ATA Command Set
Command Name
RECALIBRATE
Command Code
Command Name
Command Code
10h
20h
30h
40h
70h
90h
91h
B0h
C4h
C5h
C6h
C8h
CAh
E0h
E1h
E2h
IDLE
E3h
E4h
E5h
E6h
E7h
E8h
ECh
EFh
F1h
F2h
F3h
F4h
F5h
F6h
F8h
F9h
READ SECTOR(S)
READ BUFFER
CHECK POWER MODE
SLEEP
WRITE SECTOR(S)
READ VERIFY SECTOR(S)
SEEK
FLUSH CACHE
WRITE BUFFER
IDENTIFY DEVICE
EXECUTE DEVICE DIAGNOSTIC
INITIALIZE DEVICE PARAMETERS
SMART*1
SET FEATURES*2
READ MULTIPLE
WRITE MULTIPLE
SET MULTIPLE MODE
READ DMA
SECURITY SET PASSWORD
SECURITY UNLOCK
SECURITY ERASE PREPARE
SECURITY ERASE UNIT
SECURITY FREEZE LOCK
SECURITY DISABLE PASSWORD
READ NATIVE MAX ADDRESS
WRITE DMA
STANDBY IMMEDIATE
IDLE IMMEDIATE
STANBY
SET MAX*3
*1 : Refer to 6.3.1
*2 : Refer to 6.5.1
*3 : Refer to 6.6.1
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6.2 SECURITY FEATURE Set
The Security mode features allow the host to implement a securtity password system to prevent unauthorized access to the disk
drive.
6.2.1 SECURITY mode default setting
The NSSD is shipped with master password set to 20h value(ASCII blanks) and the lock function disabled.
The system manufacturer/dealer may set a new master password by using the SECURITY SET PASSWORD command, without
enableing the lock function.
6.2.2 Initial setting of the user password
When a user password is set, the drive automatically enters lock mode by the next powered-on
6.2.3 SECURITY mode operation from power-on
In locked mode, the NSSD rejects media access commands until a SECURITY UNLOCK command is successfully completed.
6.2.4 Password lost
If the user password is lost and High level security is set, the drive does not allow the user to access any data.
However, the drive can be unlocked using the master password.
If the user password is lost and Maxium security level is set, it is impossible to access data.
However, the drive can be unlocked using the ERASE UNIT command with the master password. The drive will erase all user data
and unlock the drive.
The execution time of SECURITY ERASE UNIT command is shown below.
- 32GB NSSD : 60 seconds
- 16GB NSSD : 30 seconds
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6.3 SMART FEATURE Set
6.3.1 Sub Command Set
SMART
READ DATA
D0h
D1h
D2h
D3h
D4h
READ LOG
D5h
D8h
D9h
DAh
E0h
READ ATTRIBUTE THRESHOLDS
ENABLE/DISABLE AUTOSAVE
SAVE ATTRIBUTE VALUES
EXECUTE OFF-LINE IMMIDIATE
ENABLE OPERATIONS
DISABLE OPERATIONS
RETURN STATUS
CHANGE THRESHOLD SECTOR SIZE
6.3.2 SMART Data Structure(READ DATA(D0h))
Byte
F/V
X
X
V
V
X
V
X
V
X
V
X
F
Descriptions
0~1
Revision code
2~3
Valid Information Count
4~7
Total number of sectors for replacement
Number of sectors actually replaced
Number of sectors initially mapped out
8~11
12~15
16~19
Threshold sector size [default value :19000h(50MB)]
Vendor specific
19~361
362
Off-line data collection status
Self-test execution status byte
Total time in seconds to complete off-line data collection activity
Vendor specific
363
364~365
366
367
Off-line data collection capability
SMART capability
368-369
F
Error logging capability
370
F
7-1
0
Reserved
1=Device error logging supported
371
X
F
F
R
X
V
Vendor specific
372
Short self-test routine recommended polling time(in minutes)
373
Extended self-test routine recommended polling time(in minutes)
374-385
386-510
511
Reserved
Vendor specific
Data structure checksum
Key :
F=the content of the byte is fixed and does not change.
V=the content of the byte is variable and may change depending on the state of the device or the commands executed by the
device.
X=the content of the byte is vendor specific and may be fixed or variable.
R=the content of the byte is reserved and shall be zero.
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6.3.3 Threshold Sector Size
Threshold Sector Size is an predefined value that makes the waring message if the number of reserved sector size is below this
value. The status can be read from Cylinder Register by READ DATA(D0h) command.
Deafult value of the Cylinder Register has C24Fh, but if the number of reserved sector size is below the Treshold Sector Size, the
Cylinder Register has 2CF4h.
In order to change the Threshold Sector Size, should be set the changed value in Sector Count Register with CHANGE THRESH-
OLD SECTOR SIZE (E0h) command.
※ Sector Count Register value (unit : MB, Range : 0~199)
6.4 BSY Status in SLEEP Command
In SLEEP command, NSSD takes 1ms to get into SLEEP state.
During this period, all the command operation is prohibitted.
The status Register value is D0h after getting into SLEEP state.
BSY
Wait 1 msec
SLEEP Command clear
SLEEP Command issue
NSSD is set to SLEEP state
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6.5 SET FEATURES
6.5.1 SET FEATURES Register Value
SET FEATURES
ENABLE WRITE CACHE
SET TRANSFER MODE
DISABLE WRITE CACHE
02h
03h
82h
Default settings after power on are Data transfer mode of Ultra DMA mode 4, PIO mode 4 and write cache enabled.
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6.6 SET MAX
6.6.1 SET MAX FEATURES Register Value
Each of SET MAX commands is identified by the value placed in the Feature register.
Below table shows these Features register values.
SET MAX
SET MAX ADDRESS
SET MAX SET PASSWORD
SET MAX LOCK
01h
02h
03h
04h
05h
SET MAX FREEZE LOCK
SET MAX UNLOCK
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6.7 Identify Device Data
Word
0
16GB
0x0040
0x3FFF
0x0000
0x0010
0x0000
0x003F
0x0000
0x0000
0xXXXX
0x0000
0x0000
0xXXXX
0xXXXX
0x8010
0x0000
0x2B00
0x4000
0x0000
0x0007
0x3FFF
0x0010
0x003F
0xFC10
0x00FB
0x0110
0x0000
0x01E8
0x0000
0x0007
0x0003
0x0078
0x0078
0x00F0
0x0078
0x0000
0x0000
0x0000
0x003C
0x0013
0x342B
0x4101
0x4000
0x3428
0x4101
0x4000
0x101F
32GB
0x0040
0x3FFF
0x0000
0x0010
0x0000
0x003F
0x0000
0x0000
0xXXXX
0x0000
0x0000
0xXXXX
0xXXXX
0x8010
0x0000
0x2B00
0x4000
0x0000
0x0007
0x3FFF
0x0010
0x003F
0xFC10
0x00FB
0x0110
0x0000
0x03D0
0x0000
0x0007
0x0003
0x0078
0x0078
0x00F0
0x0078
0x0000
0x0000
0x0000
0x003C
0x0013
0x342B
0x4101
0x4000
0x3428
0x4101
0x4000
0x101F
Description
General information
Number of logical cylinders
Specific configuration
Number of logical heads
Retired
1
2
3
4 - 5
6
Number of logical sectors per logical track
7 - 8
9
Reserved
Retired
10 -19
20 - 21
22
Serial number(20 ASCII characters)
Retired
Obsolete
23 - 26
27- 46
47
Firmware revision(8 ASCII characters)
Model number
Number of sectors on multiple commands
Reserved
48
49
Capabilities
50
Capabilities
51 - 52
53
Obsolete
Reserved
54
Number of current logical cylinders
Number of current logical heads
Number of current logical sectors per track
55
56
57
Current capacity in sectors
58
59
Multiple sector setting
60
Total number of user addressable sectors(LBA mode only)
61
62
Obsolete
63
Multi-word DMA transfer
64
Flow control PIO transfer modes supported
Minimum Multiword DMA transfer cycle time per word
Manufacturer’s recommended Multiword DMA transfer cycle time per word
Minimum PIO transfer cycle time without flow control
Minimum PIO transfer cycle time with IORDY flow control
Reserved
65
66
67
68
69 - 74
75
No DMA QUEUED command Supports
Reserved
76 - 79
80
ATA5 rev3
81
82
Command set supported
83
Command set supported
84
Command set/feature supported extension
Command set/feature enabled
Command set/feature enabled
Command set/feature default
Ultra DMA transfer
85
86
87
88
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Word
89 - 91
92
16GB
0x0000
0xFFFE
0x2040
0x0000
0x0000
0x0001
0x0000
0x0000
0x0000
32GB
0x0000
0XFFFE
0x2040
0x0000
0x0000
0x0001
0x0000
0x0000
0x0000
Description
Reserved
Master Password Revision Code
93
Hardware reset result
94 - 126
127
Reserved
Removable Media Status Notification feature set support
128
Security status
Vendor specific
Reserved
129 - 159
160 - 254
255
Integrity word
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6.8 Hardware Reset State Diagram
DHR0:RESET-
PDIAG-=X, DASP-=X, BSY=1
DHR1:Release_bus
PDIAG-=R, DASP-=X, BSY=1
RESET-asserted
xx:DHR0
RESET-negated(t=0)
DHR0:DHR1
Bus release & Device 1
DHR1:D1HR0
Bus release & Device 0
DHR1:D0HR1
D0HR0:DASP-_wait
PDIAG-=R, DASP-=R, BSY=1
D1HR0:Set_DASP-
PDIAG-=R, DASP-=R, BSY=1
t=1ms
D0HR0:D0HR1
DASP-asserted
D1HR0:D1HR1
D0HR1:Sample_DASP-
PDIAG-=R, DASP-=R, BSY-=1
D1HR1:Set_status
PDIAG-=R, DASP-=A, BSY=1
Sample DASP-
D0HR1:D0HR1
Status set, passed diagnostic
D1HR1:DI2
DASP-asserted
D0HR1:D0HR2
Device_idle_NS
t=500ms
BSY=0, PDIAG-=A
D0HR1:D0HR3
Clear bit 7
Status set, failed diagnostic
D1HR1:DI2
Device_idle_NS
BSY=0, PDIAG-=N
D0HR2:Sample_PDIAG-
PDIAG-=R, DASP-=R, BSY=1
D0HR3:Set_status
PDIAG-=R, DASP-=R, BSY=1
Resemble PDIAG-
D0HR2:D0HR2
Status set
PDIAG-asserted
D0HR3:DI1
D0HR2a:D0HR3
Device_idle_S
BSY=0
Clear bit 7
t=31ms
D0HR2b:D0HR3
Set bit 7
BSY
DRQ
0
REL
0
SERV
0
C/D
0
I/O
0
INTRQ
R
DMARQ
R
PDIAG-
DASP-
V
V
V
61
Sep. 27. 2006
NAND Flash-based Solid State Disk
6.9 Software Reset State Diagram
D0SR0:SRST
PDIAG-=R, BSY=1
D0SR3:Set_status
PDIAG-=R, BSY=1
Status Set
D0SR3:DI1
SRST set to one
xx:D0SR0
SRST cleared to zero & no Device 1 (t=0)
Device_idle_S
D0SR0:D0SR3
Clear bit 7
BSY=0
D0SR1:PDIAG-_wait
PDIAG-=R, BSY=1
SRST cleared to zero & no Device 1 (t=0)
D0SR0:D0SR1
t=1ms
D0SR1:D0SR2
D1HR1:Set_status
PDIAG-=R, BSY=1
PDIAG-asserted
D0SR2a:D0SR3
Clear bit 7
Resemble PDIAG-
D0SR2:D0SR2
t=31ms
D0SR2b:D0SR3
Set bit 7
BSY
V
DRQ
REL
0
SERV
C/D
0
I/O
0
INTRQ
R
DMARQ
PDIAG-
DASP-
R
0
0
R
V
Device0 : software reset state diagram
62
Sep. 27. 2006
NAND Flash-based Solid State Disk
D1SR0:SRST
PDIAG-=X, BSY=1
D1SR1:Release_PDIAG-
PDIAG-=X, BSY=1
D1SR2:Set_status
PDIAG-=R, BSY=1
SRST = 1
xx:D1SR0
SRST = 0
D1SR0:D1SR1
PDIAG-released
D1SR1:D1SR2
Status Set, passed diagnostics
D1SR2:DI2
Device_idle_NS
BSY=0, PDIAG-=A
Status Set, failed diagnostics
D1SR2:DI2
Device_idle_NS
BSY=0, PDIAG-=N
BSY
DRQ
0
REL
0
SERV
C/D
0
I/O
0
INTRQ
R
DMARQ
R
PDIAG-
DASP-
R
V
0
V
Device 1 : software reset state diagram
63
Sep. 27. 2006
NAND Flash-based Solid State Disk
7. Ordering Information
MC X X X X X X X X X X - X X X X X
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
11. Flash Package
1. Module: M
2. Card: C
P : TSOP1(LF)
12. PCB Revision AND Production Site
P : None(STS)
Q : 1st Rev.(STS)
3~4. Flash Density
4G : 4G
R : 2nd Rev.(STS)
8D: 8G DDP
AQ : 16G QDP
BO : 32G(16G QDP*2)
13. " - "
5. Feature
14. Packing Type
E : NSSD
M : Module Type
6~8. NSSD Density
04G : 4G Byte
15. Controller
08G : 8G byte
X : S4LD166X01(LQFP) W : S4LD166X01(FBGA)
16G : 16G Byte
32G : 32G Byte
16. Controller Firmware Revision
9. NSSD Type
A : None
6 : NSSD Type1(56x48) Q : NSSD Type2(54x71)
B : 1st Rev.
C : 2nd Rev.
D : 3rd Rev.
10. Component Generation
Z : None(No Cont.)
M : 1st Generation
B : 3rd Generation
D : 5th Generation
A : 2nd Generation
C : 4th Generation
17 ~ 18. Customer Grade
" Customer List Reference "
64
Sep. 27. 2006
NAND Flash-based Solid State Disk
8. Product Line-up
M-die Based
Part Number
Density
16GB
Type
Small
Slim
Remark
Remark
MCAQE16G6MPP-MXA
MCBOE32GQMPQ-MWA
32GB
A-die Based
Part Number
Density
08GB
16GB
32GB
4GB
Type
Small
Small
Slim
MC8DE08G6APP-MXA
MCAQE16G6APP-MXA
MCBOE32GQAPQ-MWA
MC4GE04GQAPR-MWA
MC8DE08GQAPR-MWA
MCAQE16GQAPR-MWA
MCBOE32GQAPR-MWA
Slim
Slim
Slim
Will be available end of 2006 year.
R code(12th) means shared PCB.
8GB
16GB
32GB
Slim
65
Sep. 27. 2006
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