MD16R1624DF0-CK8 [SAMSUNG]
Rambus DRAM Module, 32MX32, CMOS, RIMM-232;
| 型号： | MD16R1624DF0-CK8 |
| 厂家： | 
SAMSUNG |
| 描述： | Rambus DRAM Module, 32MX32, CMOS, RIMM-232 动态存储器 |
| 文件： | 总16页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Change History
Version 1.0 (July 2002)
* First copy.
* Based on version 1.1 (July 2002) 256/288Mbit A-die 32 Bit RIMM Module Datasheet
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
(16Mx16)*4(8/16)pcs 32 Bit RIMM Module based on 256Mb D-die, 32s banks,16K/32ms Ref, 2.5V
(16Mx18)*4(8/16)pcs 32 Bit RIMM Module based on 288Mb D-die, 32s banks,16K/32ms Ref, 2.5V
Overview
Key Timing Parameters
The 32 Bit RIMM® module is a general purpose high-perfor-
mance line of memory modules suitable for use in a broad
range of applications including computer memory, personal
computers, workstations, and other applications where high
bandwidth and low latency are required.
The following table lists the frequency and latency bins
available for 32 Bit RIMM modules.
Table 1: 32 Bit RIMM Module Frequency and Latency
Speed
The 32 Bit RIMM module consists of 256Mb/288Mb
RDRAM® devices. These are extremely high-speed CMOS
DRAMs organized as 16M words by 16 or 18 bits. The use
of Rambus Signaling Level (RSL) technology permits the
use of conventional system and board design technologies.
RIMM 3200 modules support 800MHz transfer rate per pin,
resulting in total module bandwidth of 3200MB/s or
3.2GB/s. RIMM 4200 modules support 1066MHz transfer
rate per pin, resulting in total module bandwidth of
4200MB/s or 4.2GB/s.
t
RAC
Organi-
zation
(Row
Access
Time)
ns
Part Number
I/O Freq.
(MHz)
32P MD16/18R1624DF0-CT9
32 MD16/18R1624DF0-CN9
35 MD16/18R1624DF0-CM9
32P MD16/18R1628DF0-CT9
32 MD16/18R1628DF0-CN9
35 MD16/18R1628DF0-CM9
32P MD16/18R162GDF0-CT9
32 MD16/18R162GDF0-CN9
35 MD16/18R162GDF0-CM9
40 MD16/18R1624DF0-CM8
45 MD16/18R1624DF0-CK8
40 MD16/18R1628DF0-CM8
45 MD16/18R1628DF0-CK8
40 MD16/18R162GDF0-CM8
45 MD16/18R162GDF0-CK8
32M x
32/36
The 32 Bit RIMM module provides two independent 16 or
18 bit memory channels to facilitate compact system design.
The "Thru" Channel enters and exits the module to support a
connection to or from a controller, memory slot, or termina-
tion. The "Term" Channel is terminated on the module and
supports a connection from a controller or another memory
slot.
64M x
32/36
RIMM 4200
1066MHz
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM device multi-bank architecture
supports up to four simultaneous transactions per device.
128M x
32/36
32M x
32/36
Features
♦ 2 Independent RDRAM channels, 1 pass through and 1
terminated on 32 Bit RIMM module
♦ High speed 800 and 1066MHz RDRAM devices
♦ 232 edge connector pads with 1mm pad spacing
♦ Module PCB size: 133.35mm x 34.93mm x 1.27mm
(5.25” x 1.375” x 0.05”)
64M x
32/36
RIMM 3200
800MHz
128M x
32/36
♦ Each RDRAM device has 32 banks, for a total of 512, 256, 128
banks on each 512/576MB, 256/288MB, 128/144MB module
respectively
Form Factor
♦ Gold plated edge connector pad contacts
♦ Serial Presence Detect (SPD) support
♦ Operates from a 2.5 volt supply (±5%)
♦ Low power and powerdown self refresh modes
♦ Separate Row and Column buses for higher efficiency
♦ WBGA package (92 balls)
The 32 Bit RIMM modules are offered in 232-pad 1mm edge
connector pad pitch suitable for 232 contact RIMM connec-
tors. Figure 1 below, shows a sixteen device 32 Bit RIMM
module.
Note: On double sided modules, RDRAM devices are also installed on bottom side of PCB.
Figure 1 : 32 Bit RIMM module with heat spreader removed
Page 1
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Table 2: Module Pad Numbers and Signal Names
Pin
A1
Pin Name
Pin
B1
Pin Name
Pin
Pin Name
Pin
B59
Pin Name
Gnd
Gnd
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
Gnd
Gnd
A2
SCK_THRU_L
Gnd
B2
CMD_THRU_L
Gnd
Vterm
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
Vterm
A3
B3
Vterm
Vterm
A4
DQA8_THRU_L
Gnd
B4
DQA7_THRU_L
Gnd
Gnd
Gnd
A5
B5
DQA3_THRU_R
Gnd
DQA4_THRU_R
Gnd
A6
DQA6_THRU_L
Gnd
B6
DQA5_THRU_L
Gnd
A7
B7
DQA5_THRU_R
Gnd
DQA6_THRU_R
Gnd
A8
DQA4_THRU_L
Gnd
B8
DQA3_THRU_L
Gnd
A9
B9
DQA7_THRU_R
Gnd
DQA8_THRU_R
Gnd
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
DQA2_THRU_L
Gnd
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
DQA1_THRU_L
Gnd
Vdd
Vdd
DQA0_THRU_L
Gnd
CTMN_THRU_L
Gnd
Gnd
Gnd
SCK_THRU_R
Gnd
CTMN_TERM_L
Gnd
CFM_THRU_L
Gnd
CTM_THRU_L
Gnd
CMD_THRU_R
Gnd
CTM_TERM_L
Gnd
CFMN_THRU_L
Gnd
ROW2_THRU_L
Gnd
Vref
Vcmos
ROW1_THRU_L
Gnd
ROW0_THRU_L
Gnd
Vdd
Vdd
SVdd
SWP
COL4_THRU_L
Gnd
COL3_THRU_L
Gnd
Vdd
Vdd
SCL
SDA
COL2_THRU_L
Gnd
COL1_THRU_L
Gnd
Vdd
Vdd
SA0
SA1
COL0_THRU_L
Gnd
DQB0_THRU_L
Gnd
Vdd
Vdd
SA2
SIN_TERM
Gnd
DQB1_THRU_L
Gnd
DQB2_THRU_L
Gnd
Gnd
DQB8_TERM
Gnd
DQB7_TERM
Gnd
DQB3_THRU_L
Gnd
DQB4_THRU_L
Gnd
DQB6_TERM
Gnd
DQB5_TERM
Gnd
DQB5_THRU_L
Gnd
DQB6_THRU_L
Gnd
DQB4_TERM
Gnd
DQB3_TERM
Gnd
DQB7_THRU_L
Gnd
DQB8_THRU_L
Gnd
DQB2_TERM
Gnd
DQB1_TERM
Gnd
SOUT_THRU
Gnd
SIN_THRU
Gnd
DQB0_TERM
Gnd
COL0_TERM
Gnd
DQB8_THRU_R
Gnd
DQB7_THRU_R
Gnd
COL1_TERM
Gnd
COL2_TERM
Gnd
DQB6_THRU_R
Gnd
DQB5_THRU_R
Gnd
COL3_TERM
Gnd
COL4_TERM
Gnd
DQB4_THRU_R
Gnd
DQB3_THRU_R
Gnd
ROW0_TERM
Gnd
ROW1_TERM
Gnd
DQB2_THRU_R
Gnd
DQB1_THRU_R
Gnd
ROW2_TERM
Gnd
CFMN_TERM
Gnd
DQB0_THRU_R
Gnd
COL0_THRU_R
Gnd
CTM_TERM_R
Gnd
CFM_TERM
Gnd
COL1_THRU_R
COL2_THRU_R
Page 2
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Table 2: Module Pad Numbers and Signal Names (Continued)
Pin
Pin Name
Pin
B47
Pin Name
Pin
Pin Name
Pin
Pin Name
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
Gnd
Gnd
A105
A106
A107
A108
A109
A110
A111
A112
A113
A114
A115
A116
CTMN_TERM_R
Gnd
B105
B106
B107
B108
B109
B110
B111
B112
B113
B114
B115
B116
DQA0_TERM
Gnd
COL3_THRU_R
Gnd
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
COL4_THRU_R
Gnd
DQA1_TERM
Gnd
DQA2_TERM
Gnd
ROW0_THRU_R
Gnd
ROW1_THRU_R
Gnd
DQA3_TERM
Gnd
DQA4_TERM
Gnd
ROW2_THRU_R
Gnd
CFMN_THRU_R
Gnd
DQA5_TERM
Gnd
DQA6_TERM
Gnd
CTM_THRU_R
Gnd
CFM_THRU_R
Gnd
DQA7_TERM
Gnd
DQA8_TERM
Gnd
CTMN_THRU_R
Gnd
DQA0_THRU_R
Gnd
CMD_TERM
Gnd
SCK_TERM
Gnd
DQA1_THRU_R
DQA2_THRU_R
Table 3: Module Connector Pad Description
Signal
Module Connector Pads
I/O
I
Type
RSL
Description
Clock From Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Positive polarity.
CFM_THRU_L
CFM_THRU_R
CFMN_THRU_L
CFMN_THRU_R
CMD_THRU_L
CMD_THRU_R
A14
Clock From Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Positive polarity.
B54
I
I
I
I
I
I
I
I
RSL
RSL
RSL
Clock From Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Negative polarity.
A16
Clock From Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for receiving RSL signals from the
controller. Negative polarity.
B52
Serial Command Input used to read from and write to the control
B2
VCMOS registers. Also used for power management. Connects to left
RDRAM device on "Thru" Channel.
Serial Command Input used to read from and write to the control
VCMOS registers. Also used for power management. Connects to right
RDRAM device on "Thru" Channel.
A73
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to left RDRAM
device on "Thru" Channel.
COL4_THRU_L..C
OL0_THRU_L
A20, B20, A22, B22, A24
B48, A48, B46, A46, B44
B14
RSL
RSL
RSL
"Thru" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Thru" Channel.
COL4_THRU_R..C
OL0_THRU_R
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
CTM_THRU_L
Page 3
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Table 3: Module Connector Pad Description (Continued)
Signal
Module Connector Pads
I/O
I
Type
RSL
Description
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
CTM_THRU_R
A54
B12
A56
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
CTMN_THRU_L
CTMN_THRU_R
I
I
RSL
RSL
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to left RDRAM device on "Thru" Channel.
DQA8_THRU_L is non-functional on modules with x16 RDRAM
devices.
DQA8_THRU_L..
DQA0_THRU_L
A4, B4, A6, B6, A8, B8,
A10, B10, A12
I/O
I/O
I/O
I/O
RSL
RSL
RSL
RSL
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to right RDRAM device on "Thru" Channel.
DQA8_THRU_R is non-functional on modules with x16 RDRAM
devices.
DQA8_THRU_R..
DQA0_THRU_R
B67, A67, B65, A65, B63,
A63, B58, A58, B56
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to left RDRAM device on "Thru" Channel.
DQB8_THRU_L is non-functional on modules with x16 RDRAM
devices.
DQB8_THRU_L..
DQB0_THRU_L
B32, A32, B30, A30, B28,
A28, B26, A26, B24
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to right RDRAM device on "Thru" Channel.
DQB8_THRU_R is non-functional on modules with x16 RDRAM
devices.
DQB8_THRU_R..
DQB0_THRU_R
A36, B36, A38, B38, A40,
B40, A42, B42, A44
ROW2_THRU_L..
ROW0_THRU_L
Row bus. 3-bit bus containing control and address information for
row accesses. Connects to left RDRAM device on "Thru" Channel.
B16, A18, B18
A52, B50, A50
I
I
RSL
RSL
Row bus. 3-bit bus containing control and address information for
row accesses. Connects to right RDRAM device on "Thru" Chan-
nel.
ROW2_THRU_R..
ROW0_THRU_R
Serial Clock input. Clock source used to read from and write to
SCK_THRU_L
SCK_THRU_R
SIN_THRU
A2
I
I
VCMOS "Thru" Channel RDRAM control registers. Connects to left
RDRAM device on "Thru" Channel.
Serial Clock input. Clock source used to read from and write to
VCMOS "Thru" Channel RDRAM control registers. Connects to right
RDRAM device on "Thru" Channel.
A71
B34
"Thru" Channel Serial I/O for reading from and writing to the con-
I/O VCMOS trol registers. Attaches to SIO0 of right RDRAM device on "Thru"
Channel.
Page 4
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Table 3: Module Connector Pad Description (Continued)
Signal
Module Connector Pads
I/O
Type
Description
"Thru" Channel Serial I/O for reading from and writing to the con-
SOUT_THRU
A34
I/O VCMOS trol registers. Attaches to SIO1 of left RDRAM device on "Thru"
Channel.
Clock from master. Connects to right RDRAM device on "Term"
CFM_TERM
CFMN_TERM
CMD_TERM
B103
I
I
I
I
I
I
I
I
RSL
RSL
Channel. Interface clock used for receiving RSL signals from the
controller. Positive polarity.
Clock from master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for receiving RSL signals from the
controller. Negative polarity.
B101
Serial Command Input used to read from and write to the control
A115
VCMOS registers. Also used for power management. Connects to right
RDRAM device on "Term" Channel.
"Term" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Term" Channel.
COL4_TERM..
COL0_TERM
B97, A97, B95, A95, B93
RSL
RSL
RSL
RSL
RSL
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
CTM_TERM_L
CTM_TERM_R
CTMN_TERM_L
CTMN_TERM_R
B73
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
A103
B71
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
A105
"Term" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Term”
Channel. Connects to right RDRAM device on "Term" Channel.
DQA8_TERM is non-functional on modules with x16 RDRAM
devices.
B113, A113, B111, A111,
B109, A109, B107, A107,
B105
DQA8_TERM..
DQA0_TERM
I/O
I/O
RSL
"Term" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Term”
Channel. Connects to right RDRAM device on "Term" Channel.
DQB8_TERM is non-functional on modules with x16 RDRAM
devices.
DQB8_TERM..
DQB0_TERM
A85, B85, A87, B87, A89,
B89, A91, B91, A93
RSL
RSL
"Term" Channel Row bus. 3-bit bus containing control and address
information for row accesses. Connects to right RDRAM device on
"Term" Channel.
ROW2_TERM..
ROW0_TERM
A101, B99, A99
B115
I
I
Serial Clock input. Clock source used to read from and write to
VCMOS "Term" Channel RDRAM control registers. Connects to right
SCK_TERM
RDRAM device on "Term" Channel.
Page 5
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Table 3: Module Connector Pad Description (Continued)
Signal
Module Connector Pads
I/O
Type
Description
"Term" Channel Serial I/O for reading from and writing to the con-
SIN_TERM
B83
I/O VCMOS trol registers. Attaches to SIO0 of left RDRAM device on "Term"
Channel.
VTERM
A60, B60, A61, B61
"Term" Channel Termination voltage.
A1, A3, A5, A7, A9, A11,
A13, A15, A17, A19, A21,
A23, A25, A27, A29, A31,
A33, A35, A37, A39, A41,
A43, A45, A47, A49, A51,
A53, A55, A57, A59, A62,
A64, A66, A68, A70, A72,
A74, A84, A86, A88, A90,
A92, A94, A96, A98, A100,
A102, A104, A106, A108,
A110, A112, A114, A116,
B1, B3, B5, B7, B9, B11,
B13, B15, B17, B19, B21,
B23, B25, B27, B29, B31,
B33, B35, B37, B39, B41,
B43, B45, B47, B49, B51,
B53, B55, B57, B59, B62,
B64, B66, B68, B70, B72,
B74, B84, B86, B88, B90,
B92, B94, B96, B98, B100,
B102, B104, B106, B108,
B110, B112, B114, B116
Gnd
Ground reference for RDRAM core and interface.
SA0
SA1
SA2
SCL
SDA
A81
B81
A83
A79
B79
I
I
SVDD Serial Presence Detect Address 0.
SVDD Serial Presence Detect Address 1.
SVDD Serial Presence Detect Address 2.
SVDD Serial Presence Detect Clock.
I
I
I/O
SVDD Serial Presence Detect Data (Open Collector I/O).
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1 and
SA2.
SVDD
A77
Serial Presence Detect Write Protect (active high). When low, the
SPD can be written as well as read.
SWP
VCMOS
Vdd
B77
B75
I
SVDD
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
Supply voltage for the RDRAM core and interface logic.
A69, B69, A76, B76, A78,
B78, A80, B80, A82, B82
Logic threshold reference voltage for both "Thru" Channel and
"Term" Channel RSL signals.
Vref
A75
Page 6
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Vdd
2 per
RDRAM device
0.22/0.1µFa
Gnd
VREF
SIO0
Left RDRAM Device of "Thru" Channel
SIO1
SCK
CMD
Vref
1 per
2 RDRAM devices
Plus one
(256/288Mb)
Near Connector
*0.22/0.1µFa
Gnd
.
.
.
VCMOS
SIO0
SIO1
SCK
CMD
Vref
1 per
Right RDRAM Device of "Thru" Channel
2 RDRAM devices
*0.22/0.1µFa
(256/288Mb)
Gnd
SVDD
*0.22/0.1µFa
Gnd
Vterm
Vterm
1 per
2 termination
resistors
Gnd
SIO0
SIO1
SCK
CMD
Vref
Left RDRAM Device of "Term" Channel
(256/288Mb)
Module
Capacity
N
.
.
.
512/576MB 16
256/288MB
128/144MB
8
4
SIO0
SIO1
SCK
CMD
Vref
Right RDRAM Device of "Term" Channel
(256/288Mb)
SVDD
Vcc
SCL
SWP
SWP
47Kohm
SCL
SDA
SDA
A1
A0
A2
SA0
SA1
SA2
U0
Serial Presence Detect
Note :
* 0.1uF : 800MHz products for 128/144MB and 256/288MB
* 0.22uF : the other products
Figure 1: 32 Bit RIMM Module Functional Diagram
Page 7
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MD18R1624(8/G)DF0
Absolute Maximum Ratings
Table 4 : Absolute Maximum Ratings
Symbol
VI,ABS
Parameter
Min
Max
Unit
Voltage applied to any RSL or CMOS signal pad with respect to Gnd
Voltage on VDD with respect to Gnd
Storage temperature
- 0.3
- 0.5
- 50
-
VDD + 0.3
VDD + 1.0
100
V
VDD,ABS
TSTORE
TPLATE
V
°C
°C
Plate temperature
92
DC Recommended Electrical Conditions
Table 5 : DC Recommended Electrical Conditions
Symbol
VDD
Parameter and Conditions Min
Max
Unit
Supply voltagea
2.50 - 0.13
2.50 + 0.13
V
VCMOS
CMOS I/O power supply at pad for 2.5V controllers
CMOS I/O power supply at pad for 1.8V controllers
VDD
1.8 - 0.1
VDD
1.8 + 0.2
V
V
VREF
Reference voltagea
1.4 - 0.2
1.4 + 0.2
3.6
V
V
V
V
SVdd
VTERM
Serial Presence Detector- positive power supply
Termination Voltage
2.2
1.8 - 0.09
-
1.8 + 0.09
0.46
V
TERMVREF
Nominal RSL signal half swing
a. see Direct RDRAMTM datasheet for more details
32 Bit RIMM Module Capacity and Number of RDRAM device
Table 6: 32 Bit RIMM Module Capacity and Number of RDRAM device
512/576MB
16
256/288MB
8
128/144MB
Unit
4
Number of 256/288Mb RDRAM Devices
pcs
channel 1
channel 2
8
8
4
4
2
2
Page 8
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
32 Bit RIMM Module Current Profile
Table 7 : 32 Bit RIMM Module Current Profile
512/576MB
Max
256/288MB
Max
128/144MB
Max
Total 32 Bit RIMM Module Capacity
32 Bit RIMM module power conditions a
IDD
Unit
RIMM 4200
1356/1456c
1116/1176
2700/2800
2180/2240
3400/3500
2740/2800
1516/1636
1206/1296
2860/2980
2270/2360
3560/3680
2830/2920
1324/1424
1084/1144
1900/2000
1540/1600
2200/2300
1780/1840
1484/1604
1174/1264
2060/2180
1630/1720
2360/2480
1870/1960
1308/1408
1068/1128
1500/1600
1220/1280
1600/1700
1300/1360
1468/1588
1158/1248
1660/1780
1310/1400
1760/1880
1390/1480
One RDRAM device per channel in Readb,
balance in NAP mode
IDD1
mA
mA
mA
mA
mA
mA
RIMM 3200
RIMM 4200
RIMM 3200
RIMM 4200
RIMM 3200
RIMM 4200
RIMM 3200
RIMM 4200
RIMM 3200
RIMM 4200
RIMM 3200
One RDRAM device per channel in Readb,
balance in Standby mode
IDD2
IDD3
IDD4
IDD5
IDD6
One RDRAM device per channel in Readb,
balance in Active mode
One RDRAM device per channel in Write,
balance in NAP mode
One RDRAM device per channel in Write,
balance in Standby mode
One RDRAM device per channel in Write,
balance in Active mode
a. Actual power will depend on memory controller and usage patterns. Power does not include Refresh Current.
b. I/O current is a function of the % of 1’s, to add I/O power for 50% 1’s for a X16 need to add 257mA or 290mA for X18 ECC module for the follow-
ing: V = 2.5V, V = 1.8V, V = 1.4V and V = V - 0.5V.
DD
TERM
REF
DIL
REF
c. Current values represent X32(Non-Ecc) / X36(Ecc)
Page 9
Version 1.0 July 2002
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MD18R1624(8/G)DF0
AC Electrical Specifications
Table 8 : AC Electrical Specifications
Parameter and Conditions:a
128MB, 256MB, 512MB Modules
Symbol
Min
Typ
Max
Unit
ZL
ZUL-CMOS
TPD
Module Impedance of RSL Signals
25.2
23.8
28.0
28.0
30.8
32.2
Ω
Ω
Module Impedance of SCK and CMD signals
Propagation Delay variation of RSL signals. Average clock delay from
finger to finger of all RSL clock nets (CTM, CTMN, CFM, and
CFMN)
See
table10b
ps
a,c
∆TPD
Propagation delay variation of RSL signals with respect to TPD
-21
21
ps
ps
∆TPD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay a
-250
250
∆TPD-SCK,CMD
Propagation delay variation of CMD signal with respect to SCK
signal
-200
200
ps
Vα/VIN
Attenuation Limit
17.0
4.0
%
%
V
XF/VIN
XB/VIN
Forward crosstalk coefficient (300ps input rise time @ 20%-80%)
Backward crosstalk coefficient (300ps input rise time @ 20%-80%)
DC Resistance Limit
V
2.0
0.8
%
RDC
-
-
Ω
a. Specifications apply per channel
b. T or Average clock delay is defined as the delay from finger to finger of RSL signal.
PD
c. If the module meets the following specification, it is compliant to the specification. If the module does not meet these specifications, the specifica-
tion can be adjusted by the “Adjusted ∆T Specification” table 9 below.
PD
Adjusted ∆TPD Specification
Table 9 : Adjusted ∆TPD Specification
Adjusted
Min/Max
Absolute
Min / Max
Symbol
∆TPD
Parameter and Conditions
Unit
Propagation delay variation of RSL signals with
respect to TPD for 4, 8 and 16 device modules
+/-
[17+(18*(N/
2) *∆Z0)]a
-30
30
ps
a. Where:
N = Number of RDRAM devices installed on the RIMM module
∆Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0)
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)
Page10
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MD18R1624(8/G)DF0
32 Bit RIMM Module TPD Specification
Table 10 : 32 Bit RIMM Module TPD Specification
32 Bit RIMM Module Capacity
512MB
Max
256MB
Max
128MB
Max
IDD
Unit
Parameter and Condition for RIMM4200,
RIMM3200
TPD
Propagation delay per channel, all RSL signals
1.36
1.02
0.89
ns
Page11
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Physical Dimensions -1 ( For PCB )
The following defines the 2 channel RDRAM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate.
The dimensions without tolerance specification use the default tolerance of ±0.127[±0.005].
133.35±0.127[5.250±0.005]
2.85[0.112]
2.85[0.112]
127.65[5.026]
4.00±0.15
[0.157±0.006]
DIA 2.44
COMPONENT AREA
(A SIDE)
R 2.00
7.468[0.294]
A-1
A-116
1.00[0.039]
5.68[0.2236]
8.60[0.339]
B-116
B-1
COMPONENT AREA
(B SIDE)
R 2.00
DIA 2.44
Note : The gray area above represents the contact surface of the heat spreader.
0.80±0.10
[0.031±0.004]
Heat spreader
1.00[0.039]
3.00±0.10
[0.118±0.004]
Min.4.88
[0.192]
0.15±0.10
[0.006±0.004]
2.99±0.05
[0.12±0.002]
3.00±0.10
[0.118±0.004]
DETAIL A
DETAIL B
Figure 3 : 32 Bit RIMM Module PCB Physical Dimensions
Page12
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
Physical Dimensions -2 ( For Heat Spreader )
The following defines the 2 channel RDRAM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate.
The dimensions without tolerance specification use the default tolerance of ±0.127[±0.005].
132.76±0.25[5.226±0.009]
127.66±0.12[5.023±0.005]
112.7±0.12[4.436±0.005]
2.9[0.114]
DIA 2.36±0.05[0.09±0.001]
Center-Point
http://www.samsungsemi.com
WARNING ! HOT SURFACE
1.00±0.07
[0.04±0.002]
12.7±0.07[0.5±0.002] 12.7±0.07[0.5±0.002]
133.35±0.127[5.250±0.005]
A
http://www.samsungsemi.com
WARNING ! HOT SURFACE
A
SECTION A-A
SECTION A-A
Max 7.80
[0.307]
Max 4.70
[0.185]
Heat Spreader
Heat Spreader
CSP
CSP
Thermal
Thermal
Conductive
Gap Filling
Material
Conductive
Gap Filling
Material
PCB
PCB
1.27±0.10
[0.050±0.004]
1.27±0.10
[0.050±0.004]
[ Single side module ]
[ Double side module ]
Figure 4: Heat Spreader Physical Dimensions
Page13
Version 1.0 July 2002
MD16R1624(8/G)DF0
MD18R1624(8/G)DF0
32 Bit RIMM Module Marking
The 32 Bit RIMM modules available from Samsung are
marked like Figure 5 below. This marking also assists users
to specify and verify if the correct 32 Bit RIMM modules are
installed in their systems. In the diagram, a label is shown
attached to the 32 Bit RIMM module’s heat spreader.
Information contained on the label is specific to the 32 Bit
RIMM module and provides RDRAM device information
without requiring removal of the 32 Bit RIMM module’s
heat spreader.
A
C
E
F
G
B
D
KOREA 0240 512MB /16 ECC
MD18R162GDF0-CN9 RIMM 4200 102
K
J
I
H
Label Field
Description
Marked Text
SAMSUNG
Unit
A
B
C
Vendor Logo
Country
32 Bit RIMM Module Vendor SAMSUNG Logo Area
Country of origin
-
-
-
KOREA
yyww
Year & Week code Manufactured Year & Week code
Module Memory
Capacity
Number of 8-bit or 9-bit MBytes of RDRAM storage in 32 Bit
RIMM module
D
E
F
128MB, 256MB, 512MB
4/8/16
-
Number of
RDRAM devices
Number of RDRAM devices contained in the 32 Bit RIMM
module
RDRAM
devices
Indicates whether the 32 Bit RIMM module supports 8 (non
ECC) or 9 (ECC) bit Bytes
blank = 8 bit Bytes
ECC = 9 bit Bytes
ECC Support
-
G
H
Notice!
Hot surface caution notice.
ISO Standard
-
-
-
Caution Logo
-
Gerber : 10 = 1.0 ver.
Gerber & SPD
Version
PCB Gerber file & SPD code version used on 32 Bit RIMM
Module
I
-
SPD
: 2 = 1.3 ver.
J
Product Name
Part No.
Product Name
RIMM 4200, RIMM 3200
See Table 1
-
-
K
SAMSUNG 32 Bit RIMM module part No.
Figure 5 : 32 Bit RIMM Module Marking Example
Page14
Version 1.0 July 2002
Table Of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Timing Parameters/Part Numbers . . . . . . . . . . . . . . . . 1
Module Pad Numbers and Signal Names . . . . . . . . . . . 2 - 3
Module Connector Pad Description . . . . . . . . . . . . . . . 3 - 6
32 Bit RIMM Module Functional Diagram . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 8
DC Recommended Electrical Conditions . . . . . . . . . . . . . . 8
32 Bit RIMM Module Supply Current Profile . . . . . . . . . . 9
AC Electrical Specifications . . . . . . . . . . . . . . . . . . . 10 - 11
Physical Dimensions -1 ( For PCB ) . . . . . . . . . . . . . . . . . 12
Physical Dimensions -2 ( For Heat Spreader). . . . . . . . . . 13
Standard 32 Bit RIMM Module Marking . . . . . . . . . . . . . 14
Copyright © July 2002, Samsung Electronics.
All rights reserved.
Direct Rambus, Direct RDRAM and SO-RIMM are trade-
marks of Rambus Inc. Rambus, RDRAM, RIMM and the
Rambus Logo are registered trademarks of Rambus Inc.
This document contains advanced information that is subject
to change by Samsung Electronics without notice
Document Version 1.0
Samsung Electronics Co. Ltd.
San #16 Banwol-ri, Taean-Eup Hwasung-City,
Gyeonggi-Do, KOREA
Telephone: 82-31-208-6369
Fax: 82-31-208-6799
http://www.intl.samsungsemi.com
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