MN18R1624EF0-CM8 [SAMSUNG]
Rambus DRAM Module, 64MX18, CMOS;
| 型号： | MN18R1624EF0-CM8 |
| 厂家： | 
SAMSUNG |
| 描述： | Rambus DRAM Module, 64MX18, CMOS 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MN18R1624(8)EF0
MP18R1624(8)EF0
Revision History
Version 0.1 (February 2004) -Preliminary
- First Copy
- Based on the 1.2 ver. (Dec. 2003) 288Mbit D-die NexMod™ Module Datasheet.
Version 1.0 (May 2004)
- Eliminate "Preliminary"
Version 1.0 May 2004
MN18R1624(8)EF0
MP18R1624(8)EF0
(16Mx18)*4(8)pcs NexMod™ Module based on 288Mb E-die, 32s banks,16K/32ms Refresh, 2.5V
- Terminations/DRCG/VRM(generates Vterm) on module
- RDRAM VREF generated on module
Overview
♦ Stacked PCB design improves signal integrity and margin
The NexMod™ module is a general purpose for high-
- Shortened channel length by stacking PCB and placing
performance memory subsystem suitable for a broad range
termination on module
of applications including networking, digital consumer,
mobile "Thin and light" PCs, and other applications systems
where high bandwidth and low latency are required.
- Optional BGA or PGA connectors to mainboard enable
mounting flexibility
- BGA interposers within module
The NexMod product family addresses the needs of
customers designing space-constrained systems. The Single-
Channel RDRAM® NexMod memory module is a cost
effective, small volumetric form factor solution that provides
virtually all the components needed for a complete Rambus®
Channel. The NexMod module simplifies system layout and
speeds time-to-market by placing the end-of-channel termi-
nation, VRM(Voltage Regulator Module) and DRCG(Direct
Rambus™ Clock Generator) all on the module.
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available for NexMod modules.
Table 1: Part Number by Freq. & Latency
Speed
The NexMod module is consisted of 288Mb RDRAM
devices. These are extremely high speed CMOS DRAMs
organized as 16M words by 18 bits. The use of Rambus
Signaling Level(RSL) technology permits up to 1066MHz
transfer rates while using conventional system and board
design technologies. RDRAM devices are capable of
sustained data transfers up to at 0.94ns per two bytes (7.5ns
per 16 bytes)
I/O
Bin Freq.
(MHz)
t
(Row
Access
Organization
Part Number
rac
Time) ns
a
b
-CT9
-CM8
-CT9
-CM8
1066
800
32P
40
MN (P )18R1624EF0-CT9
MN(P)18R1624EF0-CM8
MN(P)18R1628EF0-CT9
MN(P)18R1628EF0-CM8
64M x 18
1066
800
32P
40
128M x 18
a. BGA type connector
b. PGA type connector
The RDRAM Architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The seperate control and data buses
with independent row and column control yield high bus
efficiency. The RDRAM device’s thirty-two bank architec-
ture supports up to four simultaneous transactions per
device.
Form Factor
The NexMod modules are offered in 200-ball(or pin)
1.27mm bottom connector ball(or pin) pitch form factor
suitable for 200 contact NexMod connectors. Figure 1
below, shows a eight device NexMod module.
Features
♦ High speed up to 1066MHz RDRAM storage
♦ 200 bottom connector pads with 1.27mm pad spacing
♦ Module footprint : 1.1 inches x 2.0 inches
♦ Module PCB size : 50.80mm x 27.94mm x 1.0mm
♦ Interposer type-1 PCB size: 7.62mm x 26.67mm x 1.1mm
♦ Interposer type-2 PCB size: 7.62mm x 26.67mm x 2.1mm
♦ Each RDRAM device has 32 banks, for a total of 128/256
banks on 144MB/288MB module respectively
♦ Serial Presence Detect(SPD) support
♦ Operates from a 2.5 volt supply (± 5%)
♦ Low power and powerdown self refresh modes
♦ Sperate Row and Column buses for heigher efficiency
♦ WBGA lead-free package (92 balls)
Figure 1 : NexMode Module shown with heat spreader
removed
♦ Simplifies system layout and speeds time-to-market
Version 1.0 May 2004
Page 1
MN18R1624(8)EF0
MP18R1624(8)EF0
Figure 2 : NexMode Module Pin Location
1
1
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
1
2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
C16
1
C15
C1
C2
C3
U2
3
3
U1
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
C17
C18
C22
J1
J3
U5
80 100
80 100
J3 connector
J1 connector
The marker"
•" is directing the pin #1 of
J1 connector
.
Top View
KOREA
0415
256MB/8 BGA 1066-32P ECC
MN18R1628EF0- CT9 102
Warranty Void
If Removed
NexMod
Module
Version 1.0 May 2004
Page 2
MN18R1624(8)EF0
MP18R1624(8)EF0
Table 2: Module Ball (or Pin) Numbers and Signal Names
Table 2a : J1 Connector
Pin Pin Name
A1 Vdd
Pin
Pin Name
Vdd
Pin
Pin Name
Vcmos
Pin
Pin Name
Pin
Pin Name
Vcmos
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
Vcmos
DQA8
CMD
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A2
Vdd
Vdd
Vdd
Vdd
Vdd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Vdd
Vdd
Vdd
SA0
SA1
SA2
PCLK/M
SCK
Gnd
Gnd
A3
DQA6
DQA4
DQA2
DQA0
CFM
Gnd
Vterm*
Vterm*
Vterm*
Gnd
A4
Gnd
DQA7
DQA5
DQA3
DQA1
CTMN
CTM
A5
Gnd
A6
Gnd
A7
Gnd
Gnd
A8
CFMN
ROW1
COL4
COL2
COL0
DQB0
DQB2
DQB4
DQB6
Gnd
Gnd
CTMN-DRCG*
CTM-DRCG*
Gnd
A9
Gnd
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
Gnd
ROW2
ROW0
COL3
COL1
DQB1
DQB3
DQB5
DQB7
DQB8
Gnd
Gnd
Vref
Gnd
Vref
Gnd
Gnd
Gnd
SIN
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
REFCLK
SDA
Gnd
Vdd3.3
Vdd3.3
SWP
SYNCLK/N
Gnd
SVdd
A100 SCL
* Note : Vterm, CTMN-DRCG and CTM-DRCG pins are only used if internal VRM and DRCG options are not used on the NexMod Module.
Table 2b : J3 Connector
Pin
B1
Pin Name
Vcmos
Pin
B21
Pin Name
Vcmos
Pin
B41
Pin Name
Vcmos
Pin
B61
Pin Name
Vdd
Pin
Pin Name
Vdd
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B2
Gnd
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
Gnd
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
RESERVED*
Gnd
Vdd
Vdd
Vdd
Vdd
Vdd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Vdd
Vdd
Vdd
Vdd
Vdd
Gnd
B3
Vterm
Vterm
Vterm
Gnd
B4
B5
B6
B7
Gnd
B8
Gnd
B9
Gnd
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
Gnd
Vref
Vref
Gnd
RESERVED*
Gnd
Gnd
Gnd
Gnd
Vdd
Gnd
Vdd
Gnd
Gnd
Gnd
* Note : Reserved pins are used during module assembly at the factory. Do not connect in system layout.
Version 1.0 May 2004
Page 3
MN18R1624(8)EF0
MP18R1624(8)EF0
Table 3 : Module Connector Pad Description
Signal
Pins
I/O
Type
Description
A7, A8, A9, A10, A11, A12, A13,
A37, A40, A42, A43, A44, A45, A46,
A47, A48, A49, A50, A51, A52, A53,
A54, A55, A56, A57, A58, A79, A82,
A86, A87, A90, A93, A95, A96, A97,
B2, B6, B7, B8, B9, B10, B13, B15,
B16, B17, B18, B19, B20, B39, B40,
B42, B43, B44, B45, B46, B47, B48,
B49, B50, B51, B52, B53, B54, B55,
B56, B57, B58, B59, B60, B77, B80,
B87, B88, B89, B90, B91, B92, B93,
B94, B100
Ground reference for connenctor pads, RDRAM core, and
interface. 79 pads.
Gnd
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
CFM
A27
I
I
RSL
RSL
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
CFMN
CMD
A28
Serial command input used to read from and write to the con-
trol registers. Also used for power management.
A63
I
VCMOS
RSL
COL4..
COL0
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
A30, A72, B31, A73, A32
I
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
CTM
A69
A68
O
O
RSL
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
CTMN
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device. DQA8 is non-
functional on modules with x16 RDRAM devices
DQA8..
DQA0
A62, B64, A23, B65, A24, B66, A25,
B67, A26
I/O
I/O
RSL
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device. DQB8 is non-
functional on modules with x16 RDRAM devices.
DQB8..
DQB0
A78, A77, A36, A76, A35, A75, A34,
A74, A33
ROW2..
ROW0
Row bus. 3-bit bus containing control and address information
for row accesses.
A70, A29, A71
A22
I
I
RSL
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
SCK
VCMOS
B14, B22, A23, B24, B25, B26, B27,
B28, B29, B30, B31, B32, B33, B34,
B35, B36, B37, B38, B62, B63, B64,
B65, B66, B67, B68, B69, B70, B71,
B72, B73, B74, B75, B76
These pads are not connected. These 33 connector pads are
reserved for future use.
NC
SA0
SA1
SA2
SCL
A17
A18
A19
A100
I
I
I
I
SVdd
SVdd
SVdd
SVdd
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock
Version 1.0 May 2004
Page 4
MN18R1624(8)EF0
MP18R1624(8)EF0
Signal
SDA
Pins
I/O
I/O
Type
Description
A39
A94
SVdd
Serial Presence Detect Data(Open Collector I/O)
Serial I/O for reading from and writing to the control registers.
Attaches to SIO0 of the first RDRAM device on the module
SIN
I/O VCMOS
SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1
and SA2
SVdd
A80
Serial Presence Detect Write Protection(active high). When
low, the SPD can be written as well as read
SWP
A59
A20
A60
A38
A89
I
SVdd
PCLK/M
Vdd3.3 Phase detector input(DRCG)
Vdd3.3 Phase detector input(DRCG)
Vdd3.3 Reference clock(DRCG)
SYN-
CLK/N
REFCLK
CTM-
DRCG
Clock to master routed to last device in channel. Positive
polarity
I
I
RSL
RSL
CTMN-
DRCG
Clock to master routed to last device in channel. Negative
polarity
A88
Vdd3.3
Vcmos
A98, A99
Supply voltage for DRCG
A41, A61, A81, B1, B21, B41
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT
A1, A2, A3, A4, A5, A6, A14, A15,
A16, A21, B61, B78, B79, B81, B82,
B83, B84, B85, B86, B95, B96, B97,
B98, B99
Vdd
Vref
Supply voltage for the RDRAM core and interface logic
Logic threshold reference voltage for RSL signals.
A91, A92, B11, B12
Version 1.0 May 2004
Page 5
MN18R1624(8)EF0
MP18R1624(8)EF0
PCLK/M
CTM
SYNCLK/N
REFCLK
DRCG
CTMN
Resistor option
CTMN-DRCG CTM-DRCG
Vdd
2 per
RDRAM device
0.1µF
SIO0
SIO1
SCK
CMD
Vref
U1
RDRAM device (288Mb)
Gnd
VREF
1 per
2 RDRAM devices
Plus one
Near Connector
0.1µF
SIO0
SIO1
SCK
CMD
Vref
U2
RDRAM device (288Mb)
Gnd
VCMOS
1 per
2 RDRAM devices
0.1µF
SIO0
SIO1
SCK
CMD
Vref
U3
RDRAM device (288Mb)
Gnd
•
•
•
•
•
•
Module
N
SIO0
SIO1
SCK
CMD
Vref
Capacity
UN
144MB
288MB
4
8
RDRAM device (288Mb)
10kΩ
91Ω
39Ω
91Ω
39Ω
27Ω
VTERM
VTERM
GND
GND
GND
VDD
VRGND
VTERM
VDD
Note 1. Rambus Channel signals form a loop through
the RIMM module, with the exception of the SIO chain.
Note 2. See Serial Presence Detection Specification for
information on the SPD device and its contents.
SVDD
Serial Presence Detect
SVDD
Vcc
A1
SCL
WP
A0
SDA
A2
SCL
SWP
SDA
47KΩ
0.1µF
U0
SA0
SA1
SA2
Gnd
Figure 3: NexMod Module Functional Diagram
Version 1.0 May 2004
Page 6
MN18R1624(8)EF0
MP18R1624(8)EF0
Absolute Maximum Ratings
Table 4 : Absolute Maximum Rating
Symbol
VI,ABS
VDD,ABS
TSTORE
Parameter
Voltage applied to any RSL or CMOS signal pad with respect to Gnd
Voltage on VDD with respect to Gnd
Min
- 0.3
- 0.5
- 50
Max
VDD + 0.3
VDD + 1.0
100
Unit
V
V
Storage temperature
°C
DC Recommended Electrical Conditions
Table 5 : DC Recommended Electrical Conditions
Symbol
VDD
Parameter and Conditions
Min
Max
Unit
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
VCMOS
CMOS I/O power supply at pad for 2.5V controllers
CMOS I/O power supply at pad for 1.8V controllers
VDD
1.8 - 0.1
VDD
1.8 + 0.2
V
V
VREF
Reference voltage
1.4 - 0.2
1.8 - 0.2
2.2
1.4 + 0.2
1.8 + 0.2
3.6
V
V
V
VTERM
VSPD
Termination Voltage
Serial Presence Detector- Positive power supply
Table 6 : NexMod Module Capacity and Number of RDRAM device
NexMod Module Capacity
Number of 288Mb RDRAM devices
144MB
288MB
4
8
Version 1.0 May 2004
Page 7
MN18R1624(8)EF0
MP18R1624(8)EF0
NexMod Module Current Profile
Table 7 : NexMod Module Current Profile
144MB
4
288MB
8
NexMod Module Capacity:
Number of 288Mb RDRAM devices
NexMod module power conditions a b c
IDD
Unit
Freq.
Max
Max
-1066
-800
762
612
778
628
One RDRAM device in Readd, balance in NAP
mode
IDD1
mA
mA
mA
mA
mA
mA
-1066
-800
1065
885
1485
1265
1870
1545
768
One RDRAM device in Readd, balance in Standby
mode
IDD2
IDD3
IDD4
IDD5
IDD6
-1066
-800
1230
1005
752
One RDRAM device in Readd, balance in Active
mode
-1066
-800
One RDRAM device in Write, balance in NAP
mode
592
608
-1066
-800
1055
865
1475
1245
1860
1525
One RDRAM device in Write, balance in Standby
mode
-1066
-800
1220
985
One RDRAM device in Write, balance in Active
mode
a. Actual power will depend on memory controller and usage patterns. Power does not include Refresh Current.
b. Memory current only, Total power of module should include all active elements’ power on termination module.
c. DRCG on NexMod module always consume power regardless internal DRCG option. (example: VDD = 3.0± 0.15V, IDD= Max. 150mA)
d. I/O current is a function of the % of 1’s, to add I/O power for 50% 1’s, X18 ECC module needs to add 290mA for the following: V = 2.5V, V
DD
TERM
= 1.8V, V
= 1.4V and V
= V
- 0.5V.
REF
DIL
REF
Version 1.0 May 2004
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MN18R1624(8)EF0
MP18R1624(8)EF0
AC Electrical Specifications
Table 8 : AC Electrical Specifications
Parameter and Conditions
Module Impedance of RSL Signals
Symbol
ZL
ZUL-CMOS
TPD
Min
Typ
Max
Unit
Ω
25.2
28
30.8
Module Impedance of SCK and CMOS signals
23.8
28
32.2
Ω
Propagation Delay variation of RSL signals. Average clock delay
from pad to pad of all RSL clock nets (CTM, CTMN, CFM, and
CFMN)
See
Table10a,b
ns
∆TPD
Propagation delay variation of RSL signals with respect to TPD b,c for 4
and 8 device modules
-21
-250
-200
21
ps
ps
ps
∆TPD-CMOS
Propagation delay variation of SCK and CMD signals with respect to an
average clock delay
250
200
∆TPD-
Propagation delay variation of CMD signals with respect to SCK signal
SCK,CMD
a. Table 10 lists parameters and specifications for different storage capacity NexMod Modules that use 288Mb RDRAM devices.
b. T or Average clock delay is defined as the delay from finger to finger of RSL signal.
PD
c. If the NexMod module meets the following specification, then it is compliant to the specification. If the NexMod module does not meet these specifi-
cations, then the specification can be adjusted by the “Adjusted ∆T Specification“ table 9 below.
PD
Adjusted ∆TPD Specification
Table 9 : Adjusted ∆TPD Specification
Absolute
Symbol
Parameter and Conditions
Adjusted Min/Max
Unit
Min / Max
∆TPD
Propagation delay variation of RSL signals with respect to
+/-[17+(18*N*∆Z0)]a
-30
30
ps
TPD for 4 and 8 device modules
a. Where:
N = Number of RDRAM devices installed on the NexMod module
∆Z0 = delta Z0% = (max Z0 - min Z0)/(min Z0)
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)
Version 1.0 May 2004
Page 9
MN18R1624(8)EF0
MP18R1624(8)EF0
AC Electrical Specifications for NexMod Modules
Table 10: AC Electrical Specifications for NexMod Modules
NexMod Module Capacity
Number of 288Mb RDRAM devices
Parameter and Condition for NexMod modules
144MB
4
288MB
8
Symbol
Unit
Freq.
Max
Max
-1066
-800
1.28
1.28
16.0
12.0
4.0
1.32
1.32
16.0
16.0
4.0
TPD
Propagation Delay, all RSL signals
ns
%
%
%
Ω
-1066
-800
Vα/VIN
VXF/VIN
VXB/VIN
RDC
Attenuation Limit
-1066
-800
Forward crosstalk coefficient (300ps input rise time @ 20%-80%)
Backward crosstalk coefficient (300ps input rise time @ 20%-80%)
DC Resistance Limit
2.0
4.0
-1066
-800
2.0
2.0
1.5
2.0
-1066
-800
0.9
1.4
0.9
1.4
Version 1.0 May 2004
Page10
MN18R1624(8)EF0
MP18R1624(8)EF0
Physical Dimension -1 (Top View layout dimension)
The following defines the NexMod module dimensions. All units are in millimeters.
The dimension without tolerance specification use the default tolerance of ±0.1[±0.004].
2.5055
2.5745
40.6400
50.8000
1.8165
1.8165
J1
J3
Ball diameter
0.6500±0.07
27.9400
1.2700
1.2700
Figure 4a : Module physical dimension
Location of Resistors
DRCG
multiply
factor
Populated
Resitor
Type
1
2
R39/R54
R39/R38
R37/R54
R37/R38
4
5.333
6
3
4*
8
* Only Type 4 module is available.
Figure 4b : termination module layout
Figure 4: NexMode Module Top view layout Dimension
Version 1.0 May 2004
Page11
MN18R1624(8)EF0
MP18R1624(8)EF0
Physical Dimension -2 (Vertical dimension)
The following defines the NexMod module dimensions. All units are in millimeters with inches in brackets[ ], where approriate.
The dimension without tolerance specification use the default tolerance of ±0.4[±0.015].
Module Heat spreader
VRM, DRCG, Termination resistors
BGA interposers
PGA or BGA
cnnection to
mainboard
288Mb RDRAM devices
Figure 5a : NexMod Module vertical structure
3.30mm [0.129]
1.10mm
[0.043]
13.48mm [0.530]
2.10mm [0.083]
4.50mm [0.177]
49.53mm [1.950]
Figure 5b : 288MB NexMod Module with PGA connector vertical dimensions
3.30mm [0.129]
1.10mm
[0.043]
10.20mm [0.401]
10.43mm [0.410]
2.10mm [0.083]
1.10mm [0.043]
49.53mm [1.950]
Figure 5c : 288MB NexMod Module with BGA connector vertical dimensions
Figure 5: NexMod Module Vertical Dimension
Version 1.0 May 2004
Page12
MN18R1624(8)EF0
MP18R1624(8)EF0
3.3mm [0.129]
1.1mm [0.043]
6.86mm [0.270]
7.09mm [0.279]
1.1mm [0.043]
0.23mm [0.009]
49.53mm [1.95]
Figure 5d : 144MB NexMod Module with BGA connector vertical dimensions
3.3mm [0.129]
1.1mm [0.043]
10.14mm [0.399]
4.50mm [0.177]
49.53mm [1.95]
Figure 5e : 144MB NexMod Module with PGA connector vertical dimensions
Figure 5: NexMod Module Vertical Dimension
Version 1.0 May 2004
Page13
MN18R1624(8)EF0
MP18R1624(8)EF0
NexMod Module Marking
Information contained on the label is specific to the NexMod
module and provides RDRAM device information without
requiring removal of the NexMod module’s heat spreader.
The NexMod modules available from Samsung are marked
like Figure 5 below. This marking also assists users to
specify and verify if the correct NexMod modules are
installed in their systems. In the diagram, a label is shown
attached to the NexMod module’s heat spreader.
A
M
K
E
J
C
N
B
F
KOREA
256MB/8 BGA 1066-32P ECC
MN18R1628EF0- CT9 102
0415
D
Warranty Void
If Removed
G
H
L
I
Label Field
Description
Marked Text
Unit
A
B
C
Vendor Logo
Country
NexMod Module Vendor SAMSUNG Logo Area
Country of origin
SAMSUNG
KOREA
yyww
-
-
-
Year & Week code Manufactured Year & Week code
Module Memory
Capacity
Number of 9-bit MBytes of RDRAM storage in NexMod
Module
D
E
F
128/256MB
4/8
MBytes
Number of
RDRAM devices
Number of RDRAM devices contained in the NexMod
module
RDRAM
devices
Indicates whether the NexMod Module supports 9 (ECC)
bit Bytes
ECC Support
ECC = 9 bit Bytes
-
G
H
Notice!
Hot surface caution notice.
ISO Standard
-
-
-
Caution Logo
-
Gerber :
Gerber & SPD
Version
PCB Gerber file & SPD code version used on NexMod
Module
I
-
SPD
: 2 = 1.3 ver.
J
tRAC
Row Access Time
-32P, -40
ns
K
L
Memory Speed
Part No.
Data transfer speed for RDRAM device
SAMSUNG NexMod Module part No.
Module connector to main board
the direction of J1 connector’s pin #1
1066, 800
MHz
See Table 1
BGA/PGA
•
-
-
-
M
N
Connector type
Index pin marking
Figure 5: NexMod Module Marking Example
Version 1.0 May 2004
Page14
Table Of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Timing Parameters/Part Numbers . . . . . . . . . . . . . . . . 1
NexMod Module Pad Numbers and Signal Names . . . . 2 -3
NexMod Module Connector Pad Description. . . . . . . . 4 - 5
NexMod Module Functional Diagram . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Recommended Electrical Conditions . . . . . . . . . . . . . . 7
NexMod Module Supply Current Profile . . . . . . . . . . . . . . 8
AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 9 - 10
Physical Dimensions -1 ( Top View ) . . . . . . . . . . . . . . . . 11
Physical Dimensions -2 ( Vertical View) . . . . . . . . . . 12-13
Standard NexMod Module Marking . . . . . . . . . . . . . . . . . 14
Copyright ©May 2004, Samsung Electronics.
All rights reserved.
Direct Rambus and Direct RDRAM and SO-RIMM are
trademarks of Rambus Inc. Rambus, RDRAM, RIMM and
the Rambus Logo are registered trademarks of Rambus Inc.
This document contains advanced information that is subject
to change by Samsung Electronics without notice
Document Version 1.0
Samsung Electronics Co. Ltd.
San #16 Banwol-ri, Taean-Eup Hwasung-City,
Gyeonggi-Do, KOREA
Telephone: 82-31-208-6369
Fax: 82-31-208-6799
http://www.intl.samsungsemi.com
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