S3C72E8 [SAMSUNG]
The S3C72E8/P72E8 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers.; 该S3C72E8 / P72E8是SAM47核心为基础的4位CMOS单芯片微控制器。它有一个定时器/计数器， LCD驱动器。
| 型号： | S3C72E8 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3C72E8/P72E8 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers. |
| 文件： | 总27页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C72E8/P72E8
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72E8/P72E8 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and
LCD drivers.
The S3P72E8 is especially suited for use in data bank, telephone and LCD general purpose.
It is built around the SAM47 core CPU and contains ROM, RAM, 39 I/O lines, programmable timer/counter,
buzzer output, enough LCD dot matrix, and segment drive pins.
The S3C72E8/P72E8 can be used for dedicated control functions in a variety of applications, and is especially
designed for multi data bank, telephone and LCD game.
OTP
The S3C72E8 microcontroller is also available in OTP (One Time Programmable) version, S3P72E8. S3P72E8
microcontroller has an on-chip 8 K-byte one-time-programable EPROM instead of masked ROM. The S3P72E8
is comparable to S3C72E8, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C72E8/P72E8
FEATURES SUMMARY
Memory
LCD Display
•
•
•
12 characters dot matrix display (5 x 7)
•
•
•
8192 ´ 8 bit program memory
5120 ´ 4 bit data memory in S3C72E8
108 x 5 bit display memory
12 digit display (8 segments)
60 segments and 9 common pins
Power-Down Modes
39 I/O Pins
•
•
Idle mode (only CPU clock stops)
•
•
•
Input: 6 pins
Stop mode (Main-System clock and CPU clock
stops)
I/O: 17 pins
Output: maximum 16 pins for 1-bit level output
(sharing with segment driver outputs)
Oscillation Sources
•
•
•
•
Crystal, ceramic, or External RC for system clock
Main-system clock frequency: 0.4 MHz - 6MHz
Sub-system clock frequency: 32,768kHz
CPU clock divider circuit (by 4,8, or 64)
8-Bit Basic Timer
Four internal timer functions
•
8-Bit Timer/Counter 0
•
•
•
•
Programmable 8-bit timer
External event counter
Instruction Execution Times
•
•
•
0.67, 1.33, 10.7 µs at 6MHz
0.95, 1.91, 15.3 µs at 4.19 MHz
122 µs at 32.768 kHz
Arbitrary clock frequency output
External clock signal divider
Watch Timer
Operating Temperature
•
Time interval generation: 0,5ms, 3,9ms at
32768Hz
° °
-45 C to 85 C
•
•
4 frequency (2/4/8/16 kHz) outputs to BUZ pin
Operating Voltage Range
1.8 V to 5.5 V
Interrupts
•
•
Three external vectored interrupts: INT0, INT1,
INTP0
Package Type
100-pin QFP Package
•
•
Two internal vectored interrupts: INTB, INTT0
Two quasi-interrupts: INTW, INT2
•
Memory Mapped I/O Structure
1-2
S3C72E8/P72E8
PRODUCT OVERVIEW
BLOCK DIAGRAM
XIN
XOUT
RESET
XTIN XTOUT
INTT0, INTB, INTW
INT0, INT1, INTP0, INT2
P0.0-P0.3/
K0-K3
Input Port 0
8-Bit
Timer/
Counter 0
Interrupt
Control
Block
Instruction
Register
Clock
P1.0/INT0
P1.1/INT1
Input Port 1
I/O Port 2
P2.0/BUZ
P2.1/CLO
Program
Counter
Watch Timer
Basic Timer
Internal
Interrupts
P4.0/TCL0
P4.1/TCLO0
P4.2
I/O Port 4
I/O Port 5
Program
Status Word
Instruction Decoder
P5.0-P5.3
Arithmetic
and
Logic Unit
P6.0-P6.3/
KS0-KS3
COM0-COM8
SEG16-SEG59
SEG0-SEG15
/P8.0-P8.15
I/O Port 6
I/O Port 7
LCD
Driver/
Controller
Stack
Pointer
P7.0-P7.3/
KS4-KS7
P8.0-P8.15/
SEG0-SEG15
Output Port 8
Data and
Display
Memory
8 K Byte
Program
Memory
Figure 1-1. S3C72E8/P72E8 Specified Block Diagram
1-3
PRODUCT OVERVIEW
S3C72E8/P72E8
PIN ASSIGNMENTS
SEG59
COM4
COM5
COM6
COM7
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15/P8.15
SEG14/P8.14
SEG13/P8.13
SEG12/P8.12
SEG11/P8.11
SEG10/P8.10
SEG9/P8.9
COM8
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S3C72E8
100-QFP 1420C
V
DD
V
SS
Xout
Xin
TEST
XTin
XTout
RESET
P2.0/BUZ
P2.1/CLO
P5.0
P5.1
P5.2
P5.3
TCL0/P4.0
TCLO0/P4.1
Figure 1-2. S3C72E8 Pin Assignment Diagram
1-4
S3C72E8/P72E8
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Description
Pin Name
Pin
Circuit
Pin
Share Pin
Type
Type Number
I
K0-K3
P0.0 - P0.3
4-bit input port.
1 and 4-bit read, and test are possible.
Pull-up registers.
A-1
A-3
D
35-32
P1.0
P1.1
2-bit Input port.
1 and 4-bit read, and test are possible, 2-bit pull-up
resistors are assignable by software.
I
37
36
INT0
INT1
P2.0
P2.1
2-bit I/O port. 1 and 4-bit read/write, and test are
possible.
I/O
23
24
BUZ
CLO
Each individual pin can be specified as input or
output.
2-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
P4.0
P4.1
P4.2
P5.0 - P5.3
4-bit I/O port. 1, 4, and 8-bit read/write, and test are
possible.
4-pin unit can be specified as input or output.
4-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
I/O
I/O
E
29
30
31
TCL0
TCLO0
E-1
E-1
E-1
25-28
Individual pins are software configurable as open-
drain or push-pull output.
P6.0 - P6.3
P7.0 - P7.3
4-bit I/O port. 1, 4,and 8-bit read/write, and test are
possible.
Each individual pin can be specified as input or
output.
4-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
D-1
7-10
KS0 - KS3
KS4 - KS7
4-bit I/O port. 1, 4, and 8-bit read/write, and test are
possible.
4-pin unit can be specified as input or output.
4-bit pull-up resistors are assignable by software.
Pull-up resistors are automatically disabled for
output pins.
11-14
42-57
P8.0 - P8.15
O
4-bit controllable output.
(Dual function as segment output pins)
H-9
SEG0 -
SEG15
SEG16-SEG59
LCD segment display signal output.
H-10
58-100
,1
-
SEG0 - SEG15
COM0 - COM8
LCD segment display signal output.
LCD common signal output.
H-9
42-57
P8.0 - P8.15
-
H-11
38-41
2-6
INT0 - INT1
I
External interrupts. The triggering edge for INT0,
and INT1 is selectable
37-36
P1.0 -P1.1
KS0 - KS7
K0 - K3
I/O Quasi-interrupt input for falling edge detection.
7-14
P6.0 - P7.3
P0.0 - P0.3
I
Vector interrupt input
35-32
K0 - K3: falling edge detection
1-5
PRODUCT OVERVIEW
S3C72E8/P72E8
Table 1-1. Pin Descriptions (Continued)
Description
Pin Name
BUZ
Pin
Type
Circuit
Type
Pin
Num.
Share Pin
I/O 2,4,8 kHz or 16kHz frequency output for buzzer
signal.
-
23
P2.0
CLO
X , X
Clock output
-
-
24
P2.1
-
-
-
Crystal, ceramic or RC oscillator pins for main
system clock.
18, 17
in out
XT , XT
in
Crystal oscillator pins for sub-system clock.
-
-
20, 21
29
-
out
TCL0
I/O External clock input for Timer/Counter 0
I/O Timer/Counter 0 clock output
P4.0
TCLO0
-
30
P4.1
I
-
-
I
Reset input (active low).
Power supply.
B
-
22
-
-
-
-
RESET
V
V
15
DD
Ground.
-
16
SS
TEST
Test input: it must be connected to V
-
19
SS
1-6
S3C72E8/P72E8
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
V
DD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-channel
P-channel
IN
IN
N-channel
Schmitt Trigger
Vss
Figure 1-5. Pin Circuit Type A-3
Figure 1-3. Pin Circuit Type A
V
DD
V
DD
Pull-up
Pull-up
Register
Pull-up
Resistor
Enable
IN
P-channel
Schmitt Trigger
IN
Figure 1-6. Pin Circuit Type B
Figure 1-4. Pin Circuit Type A-1
1-7
PRODUCT OVERVIEW
S3C72E8/P72E8
V
DD
V
DD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-channel
P-channel
Data
Data
OUT
IN/OUT
Type C
Output
Disable
N-channel
Output
Disable
V
SS
Schmitt Trigger
Figure 1-9. Pin Circuit Type D-1
Figure 1-7. Pin Circuit Type C
V
DD
VDD
Pull-up
Resistor
PNE
Pull-Up
Resistor
VDD
Pull-up
Resistor
Enable
Pull-Up
Resistor
Enable
Data
P-channel
P-channel
I/O
Data
Output
Disable
Type C
In/Out
N-channel
Output
Disable
Schmitt Trigger
Figure 1-10. Pin Circuit Type E
Figure 1-8. Pin Circuit Type D
1-8
S3C72E8/P72E8
PRODUCT OVERVIEW
V
DD
Pull-up
resistor
PNE
V
DD
VLC2
Pull-up
Resistor
Enable
Data
P-channel
Segment
Data
I/O
OUT
Output
Disable
N-channel
VLC0
Figure 1-11. Pin Circuit Type E-1
Figure 1-13. Pin Circuit Type H-10
V
DD
SEG Data/P8.0-P8.15
VLC1
VLC2
VLC0
OUT
OUT
Vss
COM
Data
Key
strobe
Polarity
Vss
Vss
Figure 1-12. Pin Circuit Type H-9
Figure 1-14. Pin Circuit Type H-11
1-9
S3C72E8/P72E8
ELECTRICAL DATA
13 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72E8/P72E8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
STANDARD ELECTRICAL CHARACTERISTICS
— Absolute maximum ratings
— D.C electrical characteristics
— Main-system clock oscillator characteristics
— Sub-system clock oscillator characteristics
— I/O capacitance
— A.C electrical characteristics
— Operating voltage range
MISCELLANEOUS TIMING WAVEFORMS
— A.C timing measurement point
— Clock timing measurement at X
in
— Clock timing measurement at XT
— TCL0 timing
in
— Input timing for RESET
— Input timing for external interrupts
STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13–1
ELECTRICAL DATA
S3C72E8/P72E8
Table 13-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
V
Supply Voltage
Input Voltage
Output Voltage
High Level
–
Ports 0, 1, 2, 4, 5, 6, 7
–
– 0.3 to + 6.5
V
V
DD
V
– 0.3 to V
+ 0.3
I
DD
DD
V
– 0.3 to V
+ 0.3
V
O
I
One pin
– 15
mA
mA
mA
mA
mA
mA
OH
Output current
Low Level
All output pins
– 30
I
One pin
All pins
Peak value
30
OL
(note)
(note)
Output Current
15
100
RMS value
Peak value
60
RMS value
–
T
A
°
C
Operating
– 40 to + 85
Temperature
Storage
T
°
C
–
– 65 to + 150
STG
Temperature
NOTE : RMS value = Peak Value ´
Duty .
Table 13-2. D.C Characteristics
= 1.8 V to 5.5 V)
DD
°
°
(T = – 40 C to + 85 C, V
A
Parameter
Input High
Symbol
Conditions
Pins except below
Port0, 1, 6, 7, P4.0, RESET
X , X and XT
Min.
Typ.
Max.
Units
0.7 V
V
V
V
VIH1
–
V
DD
DD
DD
DD
0.8 V
DD
Voltage
VIH2
VIH3
VIL1
–
–
–
–
–
–
V
– 0.1
IN OUT IN
DD
0.3 V
Input Low
Voltage
All input pins except below
–
DD
DD
0.2 V
VIL2
Port0, 1, 6, 7, P4.0, RESET
X ,X
IN OUT
and XT
IN
VIL3
0.1
–
V
= 4.5 V to 5.5 V
V
– 1.0
Output High
Voltage
VOH1
DD
Port2, 4, 5, 6, 7
= – 1mA
DD
I
OH
13–2
S3C72E8/P72E8
ELECTRICAL DATA
Table 13-2. D.C Characteristics(continued)
(T = – 40 °C to + 85C, V
A DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
V
V
= 4.5 V to 5.5 V
Output Low
Voltage
–
–
2
OL1
DD
Port2, 4, 5, 6, 7
I
= 15mA
OL
V
I
= 1.8 V to 5.5 V
–
–
–
–
0.4
DD
=1.6mA
OL
I
Vin = V
DD
Input High
Leakage Current
3
mA
LIH1
All input pins except below
I
Vin = V
DD
20
LIH2
X , X
XT
IN
IN OUT,
I
V
= 0 V
Input Low
Leakage Current
–
–
–
–
– 3
LIL1
IN
All input pins except X , X
IN OUT,
XT and RESET
IN
I
V
= 0 V
– 20
LIL2
IN
X , X
XT
IN
IN OUT,
I
V
= V
Output High
Leakage Current
–
–
–
–
3
LOH1
O
DD
Port2, 4, 5, 6, 7
V = 0 V
I
Output Low
Leakage Current
– 3
100
LOL1
O
Port2, 4, 5, 6, 7
V
= 5 V, V = 0 V
Pull-up Resistor
RL1
25
50
KW
DD
IN
All pins except RESET
V
V
= 3 V
50
100
250
200
400
DD
= 5 V, V = 0 V
IN
RL2
100
DD
RESET
= 3 V
V
200
500
VM1
VM2
VM3
VM4
–
800
DD
V
Medium Output
COM0-COM8
COM0-COM8
SEG0-CSEG59
SEG0-CSEG59
VM1 – 0.2
VM2 – 0.2
VM3 – 0.2
VM4 – 0.2
–
VM1 + 0.2
VM2 + 0.2
VM3 + 0.2
VM4 + 0.2
90
V
OM1
(1)
V
Voltage
OM2
V
OM3
V
OM4
V
= V –0.5V
DD
High Output
ROH1
SEG0-SEG59
KW
kW
O
Impedance
Low Output
Resistor
ROH2
ROL1
ROL2
COM0-COM8
SEG0-SEG59
–
–
–
–
–
–
25
90
2
VO = 0.5V
SEG0-SEG15
(key strobe)
ROL3
COM0-COM8
–
–
25
13–3
ELECTRICAL DATA
S3C72E8/P72E8
Table 13-2. D.C Characteristics (continued)
(T = – 40 °C to + 85C, V
A
= 1.8 V to 5.5 V)
DD
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Supply Current (2) (3)
IDD1 Run mode :
6MHz
–
5.1
8
mA
V
= 5 V ± 10%
DD
Crystal oscillator
C1 = C2 = 22pF
4.19MHz
6MHz
3.8
2.5
6
4
V
= 3 V ± 10%
DD
4.19MHz
6MHz
1.8
1.3
3
IDD2 Idle mode :
= 5 V ± 10%
2.5
V
DD
Crystal oscillator
C1 = C2 = 22pF
4.19MHz
1.1
0.5
1.8
1.5
V
= 3 V ± 10%
6MHz
DD
4.19MHz
0.4
30
1.0
45
Run mode: V
DD
= 3 V ± 10%
IDD3
–
–
mA
32kHz crystal oscillator
IDD4 Idle mode:
= 3 V ± 10%
LCD ON (4)
LCD OFF
17
30
V
DD
32kHz crystal oscillator
= 3 V ± 10%
V
6
15
5
DD
32kHz crystal oscillator
Stop mode; V
XTIN = 0V
= 5 V ± 10%,
IDD5
–
2.4
DD
Stop mode; V
XTIN = 0V
= 3 V ± 10%,
0.6
3
DD
NOTES:
1. VM1=2.75/3.75 V , VM2=1/3.75 V , VM3=2/3.75 V , VM4=1.75/3.75 V
DD
DD
DD
DD
2. Supply current does not include current drawn through internal pull-down resistor and LCD driving resistors.
3. For D.C. electrical voltages, PCON register must be set to 0011B.
4. The mode of I
(LCD ON) is normal.
DD4
13–4
S3C72E8/P72E8
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Clock
Configuration
Oscillator
Parameter
Test Condition
Min
Typ
Max Units
Ceramic
Oscillator
Oscillation
frequency(fx)
–
0.4
–
6.0
MHz
XIN
XOUT
(1)
C1
C2
(2)
After VDD reaches
the minimum level of
its variable range
–
–
–
4
6
ms
Stabilization time
Oscillation
Crystal
–
0.4
MHz
XIN
XOUT
(1)
Oscillator
frequency(fx)
C1
C2
(2)
VDD = 4.5 V to 5.5 V
VDD = 1.8 V to 5.5 V
–
–
–
–
–
–
10
60
6
ms
Stabilization time
X input frequency(fx)
in
External
Clock
0.4
MHz
XIN
XOUT
(1)
X input high and low
in
–
83.3
–
–
2
1250
–
ns
level width (t , t
)
XH XL
RC
Frequency
VDD = 5 V
MHz
XIN
XOUT
Oscillator
R
VDD = 3 V
–
1
–
NOTES:
1. Oscillation frequency and input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a power-on or release of STOP mode.
13–5
ELECTRICAL DATA
S3C72E8/P72E8
Table 13-4. Recommended Oscillator Constants
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
13–6
S3C72E8/P72E8
ELECTRICAL DATA
Table 13-5. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
Crystal
–
32
32.768 35
kHz
XTIN XTOUT
Oscillator
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V
VDD = 1.8 V to 5.5 V
–
–
–
1.0
–
2
ms
10
XTIN XTOUT XT input frequency (1)
in
External
Clock
32
–
100
kHz
XT input high and low
in
–
5
–
15
ms
level width (t
, t )
XTH XTL
NOTES:
1. Oscillation frequency and input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on or release of STOP mode.
Table 13-6. Input/Output Capacitance
°
(T = 25 C, V
= 0 V )
DD
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
C
IN
Input
Capacitance
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
C
Output
Capacitance
–
–
–
–
15
15
pF
pF
OUT
C
I/O Capacitance
IO
13–7
ELECTRICAL DATA
S3C72E8/P72E8
Table 13-7. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
t
V
V
= 2.7 V to 5.5 V
0.67
–
64
µs
Instruction Cycle
Time
CY
DD
(NOTE)
= 1.8 V to 5.5 V
1.33
114
0
DD
122
–
1952
1.5
With sub-system clock (fxt)
f
V
DD
= 2.7 V to 5.5 V
MHz
TCL0 Input
Frequency
TI
V
V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
1
–
kHz
µs
DD
t
t
0.48
–
–
TCL0 Input High,
Low Width
TIH
DD
TIL
V
DD
= 1.8 V to 5.5 V
1.8
10
t
,
–
–
µs
µs
External Interrupt
Input
High, Low Width
INT0, INT1, KS0 - KS7
INTH
t
INTL
10
10
KS0 - KS3
–
t
–
RSL
RESET Low Level
Width
NOTE: Unless otherwise specified, the values of instruction cycle time condition assume a main-system clock (fx) source.
13–8
S3C72E8/P72E8
ELECTRICAL DATA
Main Oscillator
Frequency
CPU Clock
1.5 MHz
6 MHz
0.75 MHz
3 MHz
400 kHz
15.625 kHz
1
2
3
4
5
6
7
1.8 V
Supply Voltage(V)
CPU CLOCK = 1/nx oscillator frequency (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-8. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
–
Min
1.8
–
Typ
–
Max
5.5
10
–
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
Release signal set time
I
V
= 1.8 V
0.1
µA
µs
DDDR
DDDR
t
–
0
–
SREL
217 / fx
t
Oscillator stabilization wait
time
–
–
ms
WAIT
Released by RESET
(1)
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization time, all CPU operations are stopped to avoid unstable operation upon oscillation start.
2. The basic timer mode register (BMOD) interval timer delays execution of CPU instructions during the wait time.
13–9
ELECTRICAL DATA
S3C72E8/P72E8
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 13-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
13–10
S3C72E8/P72E8
ELECTRICAL DATA
0.8VDD
0.2VDD
0.8VDD
0.2VDD
MEASUREMENT
POINTS
Figure 13-4. A.C. Timing Measurement Points (Except for X and XT )
in in
1 / fx (1 / fXT)
tXL ( XTL)
t
tXH (tXTH)
Xin (XTin)
VDD – 0.5 V
0.4 V
Figure 13-5. Clock Timing Measurement at X and XT
in in
13–11
ELECTRICAL DATA
S3C72E8/P72E8
1 /fTI
tTIL
tTIH
V
DD
0.8
TCL0
0.2 VDD
Figure 13-6. TCL0 Timing
tRSL
RESET
0.2 V
DD
Figure 13-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1
INTP0
KS0 to KS7
0.8VDD
0.2VDD
Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts
13–12
S3C72E8/P72E8
MECHANICAL DATA
14 MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
—
—
—
Package dimensions in millimeters
Pad diagram
Pad/pin coordinate data table
23.90 ± 0.3
0-8
+0.10
-0.05
20.00 ± 0.2
0.15
0.10 MAX
100-QFP-1420C
#100
#1
0.65
0.3 ± 0.1
(0.58)
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.10 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 14-1. 100-QFP-1420 Package Dimensions
14-1
S3C72E8/P72E8
KS57P21408 OTP
15 S3P72E8 OTP
OVERVIEW
The S3P72E8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72E8
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72E8 is fully compatible with the S3C72E8, both in function and in pin configuration. Because of its
simple programming requirements, the S3P72E8 is ideal for use as an evaluation chip for the S3C72E8.
15-1
KS57P21408 OTP
S3C72E8/P72E8
SEG59
COM4
COM5
COM6
COM7
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15/P8.15
SEG14/P8.14
SEG13/P8.13
SEG12/P8.12
SEG11/P8.11
SEG10/P8.10
SEG9/P8.9
COM8
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
P7.0/KS4
P7.1/KS5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SDAT
SCLK
/P7.2/KS6
/P7.3/KS7
S3P72E8
100-QFP 1420C
V
/V
DD
SS
DD
V
V
/
SS
Xout
Xin
V
/
TEST
PP
XTin
XTout
RESET / RESET
P2.0/BUZ
P2.1/CLO
P5.0
P5.1
P5.2
P5.3
TCL0/P4.0
TCLO0/P4.1
Figure 15-1. S3P72E8 Pin Assignments (100-QFP Package)
15-2
S3C72E8/P72E8
KS57P21408 OTP
Table 15-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P3.1
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.0
SCLK
14
19
I/O
I
Serial clock pin. Input only pin.
V
(TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in writing
mode and when 5 V is applied, OTP is in reading
mode. (Option)
PP
22
I
I
Chip initialization
RESET
RESET
V
/ V
V
/ V
SS
15/16
Logic power supply pin. VDD should be tied to
+5 V during programming.
DD
SS
DD
Table 15-2. Comparison of S3P72E8 and S3C72E8 Features
S3P72E8
Characteristic
S3C72E8
Program Memory
8 Kbyte EPROM
1.8 V to 5.5 V
8 Kbyte mask ROM
1.8 V to 5.5V
Operating Voltage (V
)
DD
V
= 5 V, V (TEST)=12.5V
PP
OTP Programming Mode
DD
100 QFP
User Program 1 time
Pin Configuration
100 QFP
EPROM Programmability
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V (TEST) pin of the S3P72E8, the EPROM programming mode is entered. The
PP
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-3. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
15-3
KS57P21408 OTP
S3C72E8/P72E8
Table 15-4. D.C Characteristics
(T = –40 °C to +85C, VDD = 1.8 V to 5.5V)
A
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Supply Current (2)(3)
Run mode :
=5V±10%
6MHz
I
–
5.1
8
mA
DD1
V
DD
Crystal oscillator
C1=C2=22pF
4.19MHz
3.8
6
V
=3V±10%
6MHz
2.5
1.8
1.3
4
3
DD
4.19MHz
6MHz
Idle mode :
=5V±10%
I
2.5
DD2
V
DD
Crystal oscillator
C1=C2=22pF
4.19MHz
1.1
1.8
V
=3V±10%
6MHz
0.5
0.4
30
1.5
1.0
45
DD
4.19MHz
Run mode : V =3V±10%
DD
32kHz crystal oscillator
I
–
–
mA
DD3
Idle mode :
V
LCD ON(4)
LCD OFF
I
17
6
30
15
DD4
=3V±10%
DD
32kHz crystal oscillator
=3V±10%
V
DD
32kHz crystal oscillator
Stop mode; V =5V±10%
DD
I
–
2.4
0.6
5
3
DD5
Stop mode; V =3V±10%
DD
NOTES:
1.
2.
VM1=2.75/3.75 VDD, VM2=1/3.75 VDD, VM3=2/3.75 VDD, VM4=1.75/3.75 VDD
Supply current does not include current drawn through internal pull-down resistor and LCD driving resistors.
3.
5.
For D.C. electrical voltages, PCON register must be set to 0011B.
The mode of I
(LCD ON) is normal.
DD4
15-4
S3C72E8/P72E8
KS57P21408 OTP
Main Oscillator
Frequency
CPU Clock
1.5 MHz
6 MHz
0.75 MHz
3 MHz
400 kHz
15.625 kHz
1
2
3
4
5
6
7
1.8 V
Supply Voltage(V)
CPU CLOCK = 1/nx oscillator frequency (n = 4, 8, 64)
Figure 15-2. Standard Operating Voltage Range
15-5
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