S3C80F9BXX-LR_技术文档

S3C80F9B/C80G9B

8-BIT CMOS

MICROCONTROLLERS

USER'S MANUAL

Revision 1

Preface

The S3C80F9B/C80G9B Microcontroller User's Manual is designed for application designers and programmers

who are using S3C80F9B/C80G9B microcontroller for application development. It is organized in two main parts:

Part I Programming Model

Part II Hardware Descriptions

Part I contains software-related information to familiarize you with the microcontroller's architecture, programming

model, instruction set, and interrupt structure. It has six chapters:

Chapter 1

Chapter 2

Chapter 3

Product Overview

Address Spaces

Addressing Modes

Chapter 4

Chapter 5

Chapter 6

Control Registers

Interrupt Structure

Instruction Set

Chapter 1, "Product Overview," is a high-level introduction to S3C80F9B/C80G9B with general product

descriptions, as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register

addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined

stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the

S3C8-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register

values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,

alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3C80F9B/C80G9B interrupt structure in detail and further

prepares you for additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series

microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of

each instruction are presented in a standard format. Each instruction description includes one or more practical

examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in

Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the

first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed

information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the

S3C80F9B/C80G9B microcontroller. Also included in Part II are electrical, mechanical, OTP, and development

tools data. It has ten chapters:

Chapter 7

Chapter 8

Chapter 9

Chapter 10

Chapter 11

Clock Circuits

Chapter 12

Chapter 13

Chapter 14

Chapter 15

Chapter 16

Timer 1

Counter A

Electrical Data 1

Electrical Data 2

Mechanical Data

RESET and Power-Down 1

RESET and Power-Down 2

I/O Ports

Basic Timer and Timer 0

Two order forms are included at the back of this manual to facilitate customer order for S3C80F9B/C80G9B

microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these

forms, fill them out, and then forward them to your local Samsung Sales Representative.

S3C80F9B/C80G9B

iii

Table of Contents

Part I — Programming Model

Chapter 1

Product Overview

S3C8-Series Microcontrollers .......................................................................................................................1-1

S3C80F9B/C80G9B Microcontroller.............................................................................................................1-1

Features........................................................................................................................................................1-2

Block Diagram...............................................................................................................................................1-3

Pin Assignments ...........................................................................................................................................1-4

Pin Circuits....................................................................................................................................................1-11

Chapter 2

Address Spaces

Overview .......................................................................................................................................................2-1

Program Memory ..........................................................................................................................................2-2

Register Page Pointer (PP)..................................................................................................................2-5

Register Set 1.......................................................................................................................................2-6

Register Set 2.......................................................................................................................................2-6

Prime Register Space ..........................................................................................................................2-7

Working Registers................................................................................................................................2-8

Using the Register Pointers..................................................................................................................2-9

Register Addressing......................................................................................................................................2-11

Common Working Register Area (C0H–CFH) .....................................................................................2-13

4-Bit Working Register Addressing ......................................................................................................2-14

8-Bit Working Register Addressing ......................................................................................................2-16

System and User Stacks...............................................................................................................................2-18

Chapter 3

Addressing Modes

Overview .......................................................................................................................................................3-1

Register Addressing Mode (R).............................................................................................................3-2

Indirect Register Addressing Mode (IR)...............................................................................................3-3

Indexed Addressing Mode (X)..............................................................................................................3-7

Direct Address Mode (DA) ...................................................................................................................3-10

Indirect Address Mode (IA)...................................................................................................................3-12

Relative Address Mode (RA)................................................................................................................3-13

Immediate Mode (IM) ...........................................................................................................................3-14

Chapter 4

Control Registers

Overview .......................................................................................................................................................4-1

S3C80F9B/C80G9B

v

Table of Contents (Continued)

Chapter 5

Interrupt Structure

Overview........................................................................................................................................................5-1

Interrupt Types......................................................................................................................................5-2

Interrupt Vector Addresses...................................................................................................................5-5

Enable/Disable Interrupt Instructions (EI, DI).......................................................................................5-7

System-Level Interrupt Control Registers ............................................................................................5-7

Interrupt Processing Control Points......................................................................................................5-8

Peripheral Interrupt Control Registers..................................................................................................5-9

System Mode Register (SYM)..............................................................................................................5-10

Interrupt Mask Register (IMR) ..............................................................................................................5-11

Interrupt Priority Register (IPR) ............................................................................................................5-12

Interrupt Request Register (IRQ)..........................................................................................................5-14

Interrupt Pending Function Types ........................................................................................................5-15

Interrupt Source Polling Sequence.......................................................................................................5-16

Interrupt Service Routines....................................................................................................................5-16

Generating Interrupt Vector Addresses................................................................................................5-17

Nesting of Vectored Interrupts..............................................................................................................5-17

Instruction Pointer (IP)..........................................................................................................................5-17

Fast Interrupt Processing .....................................................................................................................5-17

Chapter 6

Instruction Set

Overview........................................................................................................................................................6-1

Flags Register (FLAGS) .......................................................................................................................6-6

Flag Descriptions..................................................................................................................................6-7

Instruction Set Notation ........................................................................................................................6-8

Condition Codes ...................................................................................................................................6-12

Instruction Descriptions ........................................................................................................................6-13

Chapter 7

Clock Circuit

Overview........................................................................................................................................................7-1

System Clock Circuit.............................................................................................................................7-1

Clock Status During Power-Down Modes ............................................................................................7-2

System Clock Control Register (CLKCON)..........................................................................................7-3

vi

S3C80F9B/C80G9B

Table of Contents (Continued)

Chapter 8

RESET and Power-Down 1 (S3C80F9B)

System Reset................................................................................................................................................8-1

Overview...............................................................................................................................................8-1

System Reset by LVD Circuit...............................................................................................................8-2

System Reset by nReset Pin.............................................................................................................8-2

Watch-Dog Timer Reset.......................................................................................................................8-2

System Reset Operation ......................................................................................................................8-3

Hardware Reset Values .......................................................................................................................8-4

Power-Down Modes......................................................................................................................................8-6

Back-up Mode ......................................................................................................................................8-6

IDLE Mode............................................................................................................................................8-9

Recommendation for Unusued Pins ....................................................................................................8-10

Summary Table of Back-up Mode, Stop Mode, and, Reset Status .....................................................8-11

Chapter 9

RESET and Power-Down 2 (S3C80G9B)

System Reset................................................................................................................................................9-1

Overview...................................................................................................................................................9-1

System Reset by LVD Circuit ...................................................................................................................9-2

System Reset by Reset Pin ...................................................................................................................9-2

Watch-Dog Timer Reset...........................................................................................................................9-2

Internal Power-on Reset...........................................................................................................................9-3

System Reset Operation...........................................................................................................................9-6

Hardware Reset Values............................................................................................................................9-7

Power-Down Modes......................................................................................................................................9-9

Back-Up Mode..........................................................................................................................................9-9

Stop Mode.................................................................................................................................................9-11

Sources to Release Stop Mode................................................................................................................9-12

Idle Mode ..................................................................................................................................................9-13

Recommendation for Unusued Pins.........................................................................................................9-14

Summary Table of Back-Up Mode, Stop Mode, and Reset Status..........................................................9-15

Chapter 10

I/O Ports

Overview .......................................................................................................................................................10-1

Port Data Registers..............................................................................................................................10-5

Pull-Up Resistor Enable Registers.......................................................................................................10-6

S3C80F9B/C80G9B

vii

Table of Contents (Continued)

Basic Timer and Timer 0

Chapter 11

Module Overview...........................................................................................................................................11-1

Basic Timer (BT)...................................................................................................................................11-1

Timer 0..................................................................................................................................................11-1

Basic Timer Control Register (BTCON) ...............................................................................................11-2

Basic Timer Function Description.........................................................................................................11-3

Timer 0 Control Register (T0CON).......................................................................................................11-3

Timer 0 Function Description................................................................................................................11-5

Chapter 12

Timer 1

Overview........................................................................................................................................................12-1

Timer 1 Overflow Interrupt....................................................................................................................12-2

Timer 1 Capture Interrupt .....................................................................................................................12-2

Timer 1 Match Interrupt ........................................................................................................................12-3

Timer 1 Control Register (T1CON).......................................................................................................12-5

Chapter 13

Counter A

Overview........................................................................................................................................................13-1

Counter A Control Register (CACON)..................................................................................................13-3

Counter A Pulse Width Calculations.....................................................................................................13-4

Chapter 14

Electrical Data 1 (S3C80F9B)

Overview........................................................................................................................................................14-1

Chapter 15

Electrical Data 2 (S3C80G9B)

Overview........................................................................................................................................................15-1

Chapter 16

Mechanical Data

Overview........................................................................................................................................................16-1

viii

S3C80F9B/C80G9B

List of Figures

Figure

Title

Page

Number

1-1

1-2

1-3

1-4

1-5

1-6

1-7

1-8

Block Diagram............................................................................................................1-3

Pin Assignment Diagram (42-Pin SDIP Package) .....................................................1-4

Pin Assignment Diagram (44-Pin QFP Package) ......................................................1-5

S3C80F9B Pin Assignment (48-pin ELP) ..................................................................1-6

Pin Assignment Diagram (32-Pin SOP Package)......................................................1-7

S3C80G9 Pin Assignment Diagram (28-Pin SOP Package).....................................1-7

Pin Circuit Type 1 (Port 0 and Port2) .........................................................................1-11

Pin Circuit Type 2 (Port 1)..........................................................................................1-12

Pin Circuit Type 3 (P3.0) ............................................................................................1-13

Pin Circuit Type 4 (P3.1) Circuit.................................................................................1-14

Pin Circuit Type 5 (P3.2, P3.3)...................................................................................1-14

Pin Circuit Type 6 (P3.4, P3.5)...................................................................................1-15

Pin Circuit Type 7 (Port 4)..........................................................................................1-15

Pin Circuit Type 8 (nRESET) .....................................................................................1-15

1-9

1-10

1-11

1-12

1-13

1-14

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

Program Memory Address Space..............................................................................2-2

Internal Register File Organization.............................................................................2-4

Register Page Pointer (PP)........................................................................................2-5

Set 1, Set 2, and Prime Area Register Map...............................................................2-7

8-Byte Working Register Areas (Slices).....................................................................2-8

Contiguous 16-Byte Working Register Block.............................................................2-9

Non-Contiguous 16-Byte Working Register Block.....................................................2-10

16-Bit Register Pair ....................................................................................................2-11

Register File Addressing............................................................................................2-12

Common Working Register Area ...............................................................................2-13

4-Bit Working Register Addressing............................................................................2-15

4-Bit Working Register Addressing Example.............................................................2-15

8-Bit Working Register Addressing............................................................................2-16

8-Bit Working Register Addressing Example.............................................................2-17

Stack Operations........................................................................................................2-18

2-9

2-10

2-11

2-12

2-13

2-14

2-15

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

Register Addressing...................................................................................................3-2

Working Register Addressing.....................................................................................3-2

Indirect Register Addressing to Register File.............................................................3-3

Indirect Register Addressing to Program Memory.....................................................3-4

Indirect Working Register Addressing to Register File ..............................................3-5

Indirect Working Register Addressing to Program or Data Memory..........................3-6

Indexed Addressing to Register File ..........................................................................3-7

Indexed Addressing to Program or Data Memory with Short Offset..........................3-8

Indexed Addressing to Program or Data Memory......................................................3-9

Direct Addressing for Load Instructions.....................................................................3-10

Direct Addressing for Call and Jump Instructions......................................................3-11

Indirect Addressing.....................................................................................................3-12

Relative Addressing ...................................................................................................3-13

Immediate Addressing................................................................................................3-14

3-9

3-10

3-11

3-12

3-13

3-14

4-1

Register Description Format ......................................................................................4-4

S3C80F9B/C80G9B

ix

List of Figures (Continued)

Figure

Title

Page

Number

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

S3C8-Series Interrupt Types......................................................................................5-2

S3C80F9B/C80G9B Interrupt Structure.....................................................................5-4

ROM Vector Address Area.........................................................................................5-5

Interrupt Function Diagram.........................................................................................5-8

System Mode Register (SYM)....................................................................................5-10

Interrupt Mask Register (IMR) ....................................................................................5-11

Interrupt Request Priority Groups...............................................................................5-12

Interrupt Priority Register (IPR) ..................................................................................5-13

Interrupt Request Register (IRQ) ...............................................................................5-14

6-1

System Flags Register (FLAGS) ................................................................................6-6

7-1

7-2

7-3

7-4

Main Oscillator Circuit (External Crystal or Ceramic Resonator) ............................7-1

External Clock Circuit .................................................................................................7-1

System Clock Circuit Diagram....................................................................................7-2

System Clock Control Register (CLKCON)................................................................7-3

8-1

8-2

8-3

Reset block diagram...................................................................................................8-1

Block diagram for Back-up mode ...............................................................................8-6

Timing diagram for Back-up mode input and release by LVD....................................8-6

9-1

9-2

9-3

9-4

9-5

9-6

Reset block diagram For the S3C80G9B...................................................................9-2

Power-on reset Circuit................................................................................................9-3

Timing Diagram for Power-on Reset Circuit...............................................................9-3

Reset Timing Diagram for the S3C80G9B in STOP mode ........................................9-5

Block diagram for Back-up mode in the S3C80G9B..................................................9-9

Timing Diagram For Back-Up Mode Input And Release by LVD...............................9-10

10-1

10-2

S3C80F9B/C80G9B I/O Port Data Register Format..................................................10-5

Pull-up Resistor Enable Registers (Ports 0 and 2 only).............................................10-6

11-1

11-2

11-3

11-4

11-5

11-6

Basic Timer Control Register (BTCON) .....................................................................11-2

Timer 0 Control Register (T0CON).............................................................................11-4

Simplified Timer 0 Function Diagram: Interval Timer Mode.......................................11-5

Simplified Timer 0 Function Diagram: PWM Mode ....................................................11-6

Simplified Timer 0 Function Diagram: Capture Mode ................................................11-7

Basic Timer and Timer 0 Block Diagram....................................................................11-8

12-1

12-2

12-3

12-4

12-5

Simplified Timer 1 Function Diagram: Capture Mode ................................................12-2

Simplified Timer 1 Function Diagram: Interval Timer Mode.......................................12-3

Timer 1 Block Diagram...............................................................................................12-4

Timer 1 Control Register (T1CON).............................................................................12-5

Timer 1 Registers .......................................................................................................12-6

x

S3C80F9B/C80G9B

List of Figures (Continued)

Figure

Title

Page

Number

13-1

13-2

13-3

13-4

Counter A Block Diagram...........................................................................................13-2

Counter A Control Register (CACON) .......................................................................13-3

Counter A Registers...................................................................................................13-4

Counter A Output Flip-Flop Waveforms in Repeat Mode ..........................................13-5

14-1

14-2

14-3

14-4

14-5

14-6

Stop Mode Release Timing When Initiated by an External Interrupt.........................14-5

Stop Mode Release Timing When Initiated by a RESET...........................................14-5

Stop Mode Release Timing When Initiated by a LVD................................................14-6

Input Timing for External Interrupts (Port 0, P2.3–P2.0)............................................14-7

Input Timing for RESET .............................................................................................14-7

Operating Voltage Range of S3C80F9B....................................................................14-9

15-1

15-2

15-3

15-4

15-6

Stop Mode Release Timing When Initiated by an External Interrupt.........................15-5

Stop Mode Release Timing When Initiated by a RESET...........................................15-5

Input Timing for External Interrupts (Port 0, P2.3–P2.0)............................................15-7

Input Timing for RESET .............................................................................................15-7

Operating Voltage Range of S3C80G9A ...................................................................15-9

16-1

16-2

16-3

16-4

16-5

28-SOP-375 Package Dimensions ............................................................................16-1

32-Pin SOP Package Dimension ...............................................................................16-2

42-Pin SDIP Package Dimension ..............................................................................16-3

44-Pin QFP Package Dimension ...............................................................................16-4

48-Pin ELP Package Dimension................................................................................16-5

S3C80F9B/C80G9B

xi

List of Tables

Table

Title

Page

Number

1-1

1-2

1-3

Pin Descriptions of 44-QFP and 42-SDIP..................................................................1-8

Pin Descriptions of 28-SOP and 32-SOP ..................................................................1-9

Pin Descriptions of 48-ELP ........................................................................................1-10

2-1

S3C80F9B/C80G9B Register Type Summary...........................................................2-3

4-1

4-2

Mapped Registers (Set 1) ..........................................................................................4-2

Each function description and pin assignment of P3CON in 42/44 pin package. .....4-27

5-1

5-2

5-3

S3C80F9B/C80G9B Interrupt Vectors.......................................................................5-6

Interrupt Control Register Overview...........................................................................5-7

Vectored Interrupt Source Control and Data Registers .............................................5-9

6-1

6-2

6-3

6-4

6-5

6-6

Instruction Group Summary .......................................................................................6-2

Flag Notation Conventions.........................................................................................6-8

Instruction Set Symbols..............................................................................................6-8

Instruction Notation Conventions ...............................................................................6-9

Opcode Quick Reference...........................................................................................6-10

Condition Codes.........................................................................................................6-12

8-1

8-2

8-3

8-4

Reset Condition..........................................................................................................8-2

Set 1 Register Values After Reset .............................................................................8-4

Guideline for Unused Pins to Reduced Power Consumption. ...................................8-10

Summary of each mode.............................................................................................8-11

9-1

9-2

9-3

9-4

9-5

Reset Condition not in STOP mode...........................................................................9-4

Reset Condition in STOP mode.................................................................................9-4

Set 1 Register Values after Reset..............................................................................9-7

Guideline for Unused Pins to Reduced Power Consumption. ...................................9-14

Summary of each mode.............................................................................................9-15

10-1

10-2

10-3

10-4

10-5

S3C80F9B/C80G9B Port Configuration Overview (44-QFP/48ELP).........................10-2

S3C80F9B/C80G9B Port Configuration Overview (42-SDIP) ...................................10-3

S3C80F9B/C80G9B Port Configuration Overview (32-SOP) ....................................10-4

S3C80G9B Port Configuration Overview (28-SOP)...................................................10-4

Port Data Register Summary .....................................................................................10-5

S3C80F9B/C80G9B

xiii

List of Tables (Continued)

Table

Title

Page

Number

14-1

14-2

14-3

14-4

14-5

14-6

14-7

14-8

Absolute Maximum Ratings........................................................................................14-2

D.C. Electrical Characteristics....................................................................................14-2

Characteristics of Low Voltage Detect circuit.............................................................14-4

Data Retention Supply Voltage in Stop Mode............................................................14-4

Input/Output Capacitance...........................................................................................14-6

A.C. Electrical Characteristics ....................................................................................14-6

Oscillation Characteristics ..........................................................................................14-8

Oscillation Stabilization Time......................................................................................14-8

15-1

15-2

15-3

15-4

15-5

15-6

15-7

15-8

Absolute Maximum Ratings........................................................................................15-2

D.C. Electrical Characteristics....................................................................................15-2

Characteristics of Low Voltage Detect circuit.............................................................15-4

Data Retention Supply Voltage in Stop Mode............................................................15-4

Input/Output Capacitance...........................................................................................15-6

A.C. Electrical Characteristics ....................................................................................15-6

Oscillation Characteristics ..........................................................................................15-8

Oscillation Stabilization Time......................................................................................15-8

xiv

S3C80F9B/C80G9B

List of Programming Tips

Description

Chapter 2:

Page

Number

Address Spaces

Setting the Register Pointers ........................................................................................................................2-9

Using the RPs to Calculate the Sum of a Series of Registers......................................................................2-10

Addressing the Common Working Register Area.........................................................................................2-14

Standard Stack Operations Using PUSH and POP......................................................................................2-19

Chapter 8:

RESET and Power-down 1

To enter STOP mode....................................................................................................................................8-7

Chapter 9:

RESET and Power-down 2

To enter STOP mode....................................................................................................................................9-11

Chapter 11:

Basic Timer and Timer 0

Configuring the Basic Timer..........................................................................................................................11-9

Programming Timer 0 ...................................................................................................................................11-10

Chapter 13:

Counter A

To generate 38 kHz, 1/3duty signal through P3.1 ........................................................................................13-6

To generate a one pulse signal through P3.1...............................................................................................13-7

S3C80F9B/C80G9B

xv

List of Register Descriptions

Register

Identifier

Full Register Name

Page

Number

BTCON

CACON

CLKCON

EMT

FLAGS

IMR

IPH

IPL

IPR

IRQ

P0CONH

P0CONL

P0INT

P0PND

P0PUR

P1CONH

P1CONL

P2CONH

P2CONL

P2INT

P2PND

P2PUR

P3CON

P4CON

PP

Basic Timer Control Register .....................................................................................4-5

Counter A Control Register........................................................................................4-6

System Clock Control Register ..................................................................................4-7

External Memory Timing Register..............................................................................4-8

System Flags Register ...............................................................................................4-9

Interrupt Mask Register..............................................................................................4-10

Instruction Pointer (High Byte) ...................................................................................4-11

Instruction Pointer (Low Byte)....................................................................................4-11

Interrupt Priority Register ...........................................................................................4-12

Interrupt Request Register.........................................................................................4-13

Port 0 Control Register (High Byte)............................................................................4-14

Port 0 Control Register (Low Byte) ............................................................................4-15

Port 0 External Interrupt Enable Register ..................................................................4-16

Port 0 External Interrupt Pending Register ................................................................4-17

Port 0 Pull-up Resistor Enable Register ....................................................................4-18

Port 1 Control Register (High Byte)............................................................................4-19

Port 1 Control Register (Low Byte) ............................................................................4-20

Port 2 Control Register (High Byte)............................................................................4-21

Port 2 Control Register (Low Byte) ............................................................................4-22

Port 2 External Interrupt Enable Register ..................................................................4-23

Port 2 External Interrupt Pending Register ................................................................4-24

Port 2 Pull-up Resistor Enable Register ....................................................................4-25

Port 3 Control Register...............................................................................................4-26

Port 4 Control Resistor Enable Register....................................................................4-28

Register Page Pointer ................................................................................................4-29

Register Pointer 0.......................................................................................................4-30

Register Pointer 1 .....................................................................................................4-30

Stack Pointer (Low Byte)............................................................................................4-31

Stop Control Register.................................................................................................4-31

System Mode Register .............................................................................................4-32

Timer 0 Control Register............................................................................................4-33

Timer 1 Control Register............................................................................................4-34

RP0

RP1

SPL

STOPCON

SYM

T0CON

T1CON

S3C80F9B/C80G9B

xvii

List of Instruction Descriptions

Instruction

Mnemonic

Full Register Name

Page

Number

ADC

ADD

AND

BAND

BCP

BITC

BITR

BITS

BOR

BTJRF

BTJRT

BXOR

CALL

CCF

CLR

COM

CP

CPIJE

CPIJNE

DA

DEC

DECW

DI

DIV

DJNZ

EI

ENTER

EXIT

IDLE

INC

INCW

IRET

JP

JR

Add with carry.............................................................................................................6-14

Add .............................................................................................................................6-15

Logical AND ...............................................................................................................6-16

Bit AND.......................................................................................................................6-17

Bit Compare ...............................................................................................................6-18

Bit Complement..........................................................................................................6-19

Bit Reset.....................................................................................................................6-20

Bit Set.........................................................................................................................6-21

Bit OR.........................................................................................................................6-22

Bit Test, Jump Relative on False ...............................................................................6-23

Bit Test, Jump Relative on True.................................................................................6-24

Bit XOR.......................................................................................................................6-25

Call Procedure............................................................................................................6-26

Complement Carry Flag .............................................................................................6-27

Clear...........................................................................................................................6-28

Complement...............................................................................................................6-29

Compare.....................................................................................................................6-30

Compare, Increment, and Jump on Equal .................................................................6-31

Compare, Increment, and Jump on Non-Equal .........................................................6-32

Decimal Adjust ...........................................................................................................6-33

Decrement..................................................................................................................6-35

Decrement Word ........................................................................................................6-36

Disable Interrupts .......................................................................................................6-37

Divide (Unsigned).......................................................................................................6-38

Decrement and Jump if Non-Zero..............................................................................6-39

Enable Interrupts........................................................................................................6-40

Enter...........................................................................................................................6-41

Exit..............................................................................................................................6-42

Idle Operation.............................................................................................................6-43

Increment ...................................................................................................................6-44

Increment Word..........................................................................................................6-45

Interrupt Return ..........................................................................................................6-46

Jump...........................................................................................................................6-47

Jump Relative.............................................................................................................6-48

Load............................................................................................................................6-49

Load Bit ......................................................................................................................6-51

Load Memory .............................................................................................................6-52

Load Memory and Decrement....................................................................................6-54

Load Memory and Increment .....................................................................................6-55

Load Memory with Pre-Decrement ............................................................................6-56

Load Memory with Pre-Increment..............................................................................6-57

Load Wore..................................................................................................................6-58

LD

LDB

LDC/LDE

LDCD/LDED

LDCI/LDEI

LDCPD/LDEPD

LDCPI/LDEPI

LDW

S3C80F9B/C80G9B

xix

List of Instruction Descriptions (Continued)

Instruction

Mnemonic

Full Register Name

Page

Number

MULT

OR

POP

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

RCF

RET

RL

RLC

RR

RRC

SB0

SB1

SBC

Multiply (Unsigned).....................................................................................................6-59

Next.............................................................................................................................6-60

No Operation ..............................................................................................................6-61

Logical OR..................................................................................................................6-62

Pop from Stack ...........................................................................................................6-63

Pop User Stack (Decrementing).................................................................................6-64

Pop User Stack (Incrementing) ..................................................................................6-65

Push to Stack..............................................................................................................6-66

Push User Stack (Decrementing)...............................................................................6-67

Push User Stack (Incrementing) ................................................................................6-68

Reset Carry Flag.........................................................................................................6-69

Return.........................................................................................................................6-70

Rotate Left ..................................................................................................................6-71

Rotate Left Through Carry..........................................................................................6-72

Rotate Right................................................................................................................6-73

Rotate Right Through Carry .......................................................................................6-74

Select Bank 0..............................................................................................................6-75

Select Bank 1..............................................................................................................6-76

Subtract with Carry .....................................................................................................6-77

Set Carry Flag.............................................................................................................6-78

Shift Right Arithmetic ..................................................................................................6-79

Set Register Pointer....................................................................................................6-80

Stop Operation............................................................................................................6-81

Subtract ......................................................................................................................6-82

Swap Nibbles..............................................................................................................6-83

Test Complement under Mask ...................................................................................6-84

Test under Mask.........................................................................................................6-85

Wait for Interrupt.........................................................................................................6-86

Logical Exclusive OR..................................................................................................6-87

SCF

SRA

SRP/SRP0/SRP1

STOP

SUB

SWAP

TCM

TM

WFI

XOR

xx

S3C80F9B/C80G9B

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range

of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupt

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more

interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to

specific interrupt levels.

S3C80F9B/C80G9B Microcontroller

The S3C80F9B/C80G9B single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process

and is based on Samsung's newest CPU architecture.

The S3C80F9B/C80G9B is the microcontroller which has 32-Kbyte mask-programmable ROM.

The S3P80F9B/P80G9B is the microcontroller which has 32-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers developed S3C80F9B/C80G9B by integrating the

following peripheral modules with the powerful SAM87 RC core:

— Internal LVD circuit and 16 bit-programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).

— One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

— One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3C80F9B/C80G9B is a versatile general-purpose microcontroller which is especially suitable for use as

remote transmitter controller. It is currently available in a 28-pin SOP (Only for S3C80G9B), 32-pin SOP, 42-pin

SDIP and 44-pin QFP, 48-ELP (Only for S3C80F9B) package.

1-1

PRODUCT OVERVIEW

S3C80F9B/C80G9B

FEATURES

CPU

Carrier Frequency Generator

•

SAM87RC CPU core

•

One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Memory

Back-up mode

•

32-Kbyte internal ROM (S3C80F9B/C80G9B)

: 0000H–7FFFH

•

When V_DDis lower than V_LVD, the chip enters

Back-up mode to block oscillation and reduce

the current consumption.

Data memory: 272-byte RAM (318 register)

In S3C80G9B, this function is disabled when

operating state is “STOP mode”.

Instruction Set

•

78 instructions

When nRESET pin is lower than Input Low

Voltage (V_IL), the chip enters Back-up mode to

IDLE and STOP instructions added for power-

down modes

block oscillation and reduce the current

consumption.

Instruction Execution Time

500 ns at 8-MHz f_OSC(minimum)

•

Low Voltage Detect Circuit

•

Low voltage detect to get into Back-up mode.

Interrupts

Low level detect voltage

− S3C80F9B: 2.20 V (Typ) ± 200mV

− S3CC80G9B: 1.90 V (Typ) ± 200mV

•

22 interrupt sources with 16 vector and 7 level.

I/O Ports

Operating Temperature Range

•

Three 8-bit I/O ports (P0–P2), one 8-bit output

port(P4) and 6-bit port (P3) for a total of 38 bit-

programmable pins.(44-QFP,48-ELP)

°

•

–25 C to + 85 C

Three 8-bit I/O ports (P0–P2), one 8-bit output

port(P4) and 4-bit port (P3) for a total of 36 bit-

programmable pins.(42-SDIP)

Operating Voltage Range

•

1.7V to 3.6V at 4 MHz f_OSC(S3C80G9B)

2.0V to 5.0V at 8 MHz f_OSC(S3C80F9B)

Three 8-bit I/O ports (P0–P2) and one 2-bit I/O

port (P3) for a total of 26-bit programmable pins.

(32-SOP)

Package Type

•

48-pin ELP-0707(Only for S3C80F9B)

Timers and Timer/Counters

44-pin QFP-1010B

42-pin SDIP

•

One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer

(software reset) function

32-pin SOP

One 8-bit timer/counter (Timer 0) with three

operating modes; Interval mode, Capture and

PWM mode.

28-pin SOP (Only for S3C80G9B)

One 16-bit timer/counter (Timer1) with two

operating modes; Interval mode and Capture.

1-2

S3C80F9B/C80G9B

PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-0.3 (INT0-INT3)

P0.4-P0.7 (INT4)

P1.0-P1.7

Port 1

TEST

LVD

Port 0

VDD

nRESET

MAIN

OSC

XIN

P2.0-2.3 (INT5-INT8)

P2.4-2.7 (INT9)

Port 2

Port 3

Port 4

XOUT

I/O Port and Interrupt

Control

8-Bit

Basic

Timer

P3.0-T0PWM/

T0CAP/(T1CAP)

P3.1-REM/(T0CK)

P3.2/(T0CK)

P3.3/(T1CAP)

P3.4-3.5

8-Bit

Timer/

Counter

SAM87RC

CPU

16-Bit

Timer/

Counter

P4.0-4.7

317-Bytes

Register

File

32K-Bytes

ROM

Carrier

Registor

(Counter A)

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW

S3C80F9B/C80G9B

PIN ASSIGNMENTS

P4.3

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

P4.2

P4.1

P4.0

1

2

3

4

5

6

7

8

P0.7/INT4

P0.6/INT4

P0.5/INT4

P0.4/INT4

P0.3/INT3

P0.2/INT2

P0.1/INT1

P0.0/INT0

P4.4

P4.5

P4.6

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P4.7

P3.3/T1CAP

P2.0/INT5

P2.1/INT6

P2.2/INT7

P2.3/INT8

P2.4/INT9

P3.0/T0PWM/T0CAP/SDAT

9

S3C80F9B/C80G9B

R3.1/REM/SCLK

VDD

10

11

12

13

14

15

16

17

18

19

20

21

(Top View)

VSS

XOUT

XIN

TEST

42-SDIP

P2.5/INT9

P2.6/INT9

nRESET

P2.7/INT9

P1.0

P3.2/T0CK

Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

1-4

S3C80F9B/C80G9B

PRODUCT OVERVIEW

P1.3

P1.2

P1.1

P4.7

P3.3/T1CAP

P3.2/T0CK

P1.0

P2.7/INT9

P3.5

22

21

20

19

18

17

16

15

14

13

12

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

P4.3

34

35

36

37

38

39

40

41

42

43

44

S3C80F9B/C80G9B

(Top View)

P4.2

P4.1

P4.0

(44-QFP)

P2.0/INT5

P2.1/INT6

P2.2/INT7

P3.4

nRESET

Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

1-5

PRODUCT OVERVIEW

S3C80F9B/C80G9B

NC

24

P0.4/INT4

37

38

39

2

3

P1.3

P1.2

P1.1

P0.5/INT4

P0.6/INT4

P0.7/INT4

22

21

20

19

18

17

16

15

S3C80F9B

0

4

P4.7

P4.3

P4.2

P4.1

41

2

4

43

44

Top View

P3.3/T1CAP

P3.2/T0CK

P1.0

P2.7/INT9

P3.5

P4.0

(48-ELP)

P2.0/INT5

P2.1/INT6

P2.2/INT7

NC

4

5

46

47

48

1

4

P3.4

n

RESET

1

3

Figure 1-4. S3C80F9B Pin Assignment (48-pin ELP)

1-6

S3C80F9B/C80G9B

PRODUCT OVERVIEW

VDD

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VSS

XIN

XOUT

TEST

1

2

3

4

5

6

7

8

P3.1/REM/T0CK/SCLK

P3.0/T0PWM/T0CAP/T1CAP/SDAT

P2.4/INT9

P2.3/INT8

P2.2/INT7

P2.1/INT6

P2.0/INT5

P0.7/INT4

P0.6/INT4

P0.5/INT4

P0.4/INT4

P0.3/INT3

P0.2/INT2

P0.1/INT1

P0.0/INT0

P2.5/INT9

P2.6/INT9

nRESET

P2.7/INT9

P1.0

S3C80F9B/C80G9B

(Top View)

9

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

10

11

12

13

14

15

16

32-SOP

Figure 1-5. Pin Assignment Diagram (32-Pin SOP Package)

VDD

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VSS

XOUT

XIN

TEST

RESET

P1.0

1

2

3

4

5

6

7

8

P3.1/REM/T0CK/SCLK

P3.0/T0PWM/T0CAP/T1CAP/SDAT

P2.3/INT8

P2.2/INT7

P2.1/INT6

P2.0/INT5

P0.7/INT4

P0.6/INT4

P0.5/INT4

P0.4/INT4

P0.3/INT3

P0.2/INT2

P0.1/INT1

S3C80G7/C80G9

(Top View)

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

28-SOP

9

10

11

12

13

14

INT0/P0.0

Figure 1-6. S3C80G9 Pin Assignment Diagram (28-Pin SOP Package)

1-7

PRODUCT OVERVIEW

S3C80F9B/C80G9B

Table 1-1. Pin Descriptions of 44-QFP and 42-SDIP

Pin Description

Circuit 42 Pin 44 Pin

Shared

Names

Type

No.

Functions

P0.0–P0.7

I/O

I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors can be assigned

by software. Pins can be assigned

individually as external interrupt inputs

with noise filters, interrupt enable/

disable, and interrupt pending control.

SED & R circuit built in P0 for STOP

releasing.

1

34–41 30–37

Ext. INT

(INT0 - 4)

P1.0–P1.7

I/O

I/O port with bit-programmable pins.

Configurable to input mode or output

mode. Pin circuits are either push-pull or

n-channel open-drain type.

2

1

20

16

–

24–30 20–26

P2.0–P2.3

P2.4–P2.7

I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors can be assigned

by software. Pins can be assigned

individually as external interrupt inputs

with noise filters, interrupt enable/

disable, and interrupt pending control.

SED & R circuit built in P2 for STOP

releasing.

4–8,

16, 17

19

42–44

1,2,

10,11,

15

Ext. INT

(INT5–9)

P3.0

P3.1

I/O

2-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull

output mode, or n-channel open-drain

output mode. Input mode with pull-up

resistors can be assigned by software.

The two port 3 pins have high current

drive capability

3

4

9–10

3–4

T0PWM/T0CAP

REM

P3.2–P3.3

P3.4–P3.5

P4.0–P4.7

I

C-MOS Input port with pull-up resistors

5

6

7

21

22

17

18

(T0CK)

(T1CAP)

O

Open drain output port for high current

drive

None

13–14

–

8- bit-programmable output pins.

Configurable to open drain output port or

push-pull output port.

1–3

42,23

31-33

41–38

27–29

19

X_IN, X_OUT

nRESET

–

I

System clock input and output pins

–

8

13,14

18

7,8

12

–

System reset signal input pin and back-

up mode input.

TEST

I

Test signal input pin (for factory use only;

must be connected to V_SS.)

–

15

9

–

V_DD

V_SS

–

Power supply input pin

Ground pin

–

11

12

5

6

–

1-8

S3C80F9B/C80G9B

PRODUCT OVERVIEW

Table 1-2. Pin Descriptions of 28-SOP and 32-SOP

Names

Type

Pin Description

Circuit

Type

28 Pin

No.

32 Pin

No.

Shared

Functions

P0.0–P0.7

I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors are assignable by

software. Pins can be assigned individually

as external interrupt inputs with noise

filters, interrupt enable/ disable, and

interrupt pending control. SED & R circuit

built in P0 for STOP releasing.

1

15-21

17–24

Ext. INT

P1.0–P1.7

I/O I/O port with bit-programmable pins.

Configurable to input mode or output mode.

Pin circuits are either push-pull or n-

channel open-drain type.

2

1

6-13

9–16

–

P2.0–P2.3

P2.4–P2.7

I/O I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors can be assigned by

software. Pins can be assigned individually

as external interrupt inputs with noise

filters, interrupt enable/disable, and

22-25

None

25–28

29,5, 6,8

Ext. INT

interrupt pending control. SED & R circuit

built in P2 for STOP releasing.

P3.0

P3.1

I/O 2-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull

output mode, or n-channel open-drain

output mode. Input mode with pull-up

resistors can be assigned by software. The

two port 3 pins have high current drive

capability.

3

4

26

27

30,31

T0PWM/

T0CAP/

T1CAP

REM/T0CK

X_IN, X_OUT

RESET

–

I

System clock input and output pins

–

8

2,3

7

2,3

7

–

System reset signal input pin and back-up

mode input.

TEST

I

Test signal input pin (for factory use only;

–

4

–

must be connected to V ).

SS

V_DD

V_SS

–

Power supply input pin

Ground pin

–

28

1

32

1

–

1-9

PRODUCT OVERVIEW

S3C80F9B/C80G9B

Table 1-3. Pin Descriptions of 48-ELP

Names

Type

Pin Description

Circuit

Type

48 Pin

No.

Shared

Functions

P0.0–P0.7

I/O

I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors can be assigned by

software. Pins can be assigned individually

as external interrupt inputs with noise filters,

interrupt enable/ disable, and interrupt

pending control. SED & R circuit built in P0

for STOP releasing.

1

32–35

37–40

Ext. INT

(INT0–4)

P1.0–P1.7

I/O

I/O port with bit-programmable pins.

Configurable to input mode or output mode.

Pin circuits are either push-pull or n-channel

open-drain type.

2

1

17

21–23

–

25–28

P2.0–P2.3

P2.4–P2.7

I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors can be assigned by

software. Pins can be assigned individually

as external interrupt inputs with noise filters,

interrupt enable/ disable, and interrupt

pending control.

45–47

1,2,

10,11,

16

Ext. INT

(INT5–9)

SED & R circuit built in P2 for STOP

releasing.

P3.0

P3.1

I/O

2-bit I/O port with bit-programmable pins.

Configurable to input mode, push-pull output

mode, or n-channel open-drain output mode.

Input mode with pull-up resistors can be

assigned by software.

3

4

3–4

T0PWM/ T0CAP

REM

The two port 3 pins have high current drive

capability

P3.2–P3.3

I

C-MOS Input port with pull-up resistors

5

18

19

(T0CK)

(T1CAP)

P3.4–P3.5

P4.0–P4.7

O

Open drain output port for high current drive

6

7

14–15

–

8- bit-programmable output pins.

Configurable to open drain output port or

push-pull output port.

44–41

31–29

20

X_IN, X_OUT

RESET

–

I

System clock input and output pins

–

8

7,8

13

–

System reset signal input pin and back-up

mode input.

TEST

I

Test signal input pin (for factory use only;

must be connected to V_SS.)

–

9

–

V_DD

V_SS

–

Power supply input pin

Ground pin

–

5

6

–

1-10

S3C80F9B/C80G9B

PRODUCT OVERVIEW

PIN CIRCUITS

VDD

Pull-up

Resistor

Pull-up

Enable

VDD

Data

Input/

Output

Disable

VSS

External

Interrupt

Noise

Filter

Stop release

Stop

Figure 1-7. Pin Circuit Type 1 (Port 0 and Port2)

1-11

PRODUCT OVERVIEW

S3C80F9B/C80G9B

PIN CIRCUITS (Continued)

VDD

Pull-up

Resistor

Pull-up

Enable

VDD

Data

Input/

Output

Open-Drain

Output Disable

VSS

Normal

Input

Noise

Filter

Figure 1-8. Pin Circuit Type 2 (Port 1)

1-12

S3C80F9B/C80G9B

PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

VDD

Pull-up

Resistor

Pull-up

Enable

P3CON.2

VDD

M

U

X

Port 3.0 Data

T0_PWM

Data

P3.0/T0PWM

T0CAP/(T1CAP)

Open-Drain

Output Disable

VSS

P3.0 Input

P3CON.2,6,7

M

U

X

T0CAP/(T1CAP)

Noise filter

Figure 1-9. Pin Circuit Type 3 (P3.0)

1-13

PRODUCT OVERVIEW

S3C80F9B/C80G9B

PIN CIRCUITS (Continued)

VDD

Pull-up

Resistor

Pull-up

Enable

P3CON.5

VDD

M

U

X

Port 3.1 Data

CAOF(CACON.0)

Carrier On/Off (P3.7)

Data

P3.1/REM/(T0CK)

Open-Drain

Output

Disable

VSS

P3.1 Input

P3CON.5,6,7

M

T0CK

U

X

Noise filter

Figure 1-10. Pin Circuit Type 4 (P3.1) Circuit

VDD

Pull-up

Resistor

Input

M

U

X

T0CK : P3.2

T1CAP: P3.3

Figure 1-11. Pin Circuit Type 5 (P3.2, P3.3)

1-14

S3C80F9B/C80G9B

PRODUCT OVERVIEW

PIN CIRCUITS (Continued)

Output

Data

VSS

Figure 1-12. Pin Circuit Type 6 (P3.4, P3.5)

VDD

Data

Output

Open-Drain

Output Disable

VSS

Figure 1-13. Pin Circuit Type 7 (Port 4)

VDD

Pull-up

Resistor

nRESET

Figure 1-14. Pin Circuit Type 8 (nRESET)

1-15

S3C80F9B/C80G9B

ADDRESS SPACES

2

ADDRESS SPACES

OVERVIEW

The S3C80F9B/C80G9B microcontroller has two types of address space:

— Internal program memory (ROM)

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and

data between the CPU and the register file.

The S3C80F9B/C80G9B has a programmable internal 32-Kbyte ROM. An external memory interface is not

implemented.

The 256-byte physical register space is expanded into an addressable area of 320 bytes by the use of addressing

modes.

There are 318 mapped registers in the internal register file. Of these, 272 are for general-purpose use. (This

number includes a 16-byte working register common area that is used as a “scratch area” for data operations, a

192-byte prime register area, and a 64-byte area (Set 2) that is also used for stack operations). Nineteen 8-bit

registers are used for CPU and system control and 28 registers are mapped peripheral control and data registers.

Three register locations are not mapped.

2-1

ADDRESS SPACES

S3C80F9B/C80G9B

PROGRAM MEMORY

Program memory (ROM and RAM) stores program code or table data. The S3C80F9B/C80G9B has 32-Kbyte of

internal programmable ROM. The program memory address range is therefore 0000H–7FFFH of ROM (see

Figure 2-1).

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this

address range can be used as normal program memory. If you do use the vector address area to store program

code, be careful to avoid overwriting vector addresses stored in these locations.

The ROM address at which program execution starts after a reset is 0100H.

(HEX)

7FFFH

(DECIMAL)

32,767

32-Kbyte

Internal

Program

Memory

(ROM)

S3C80F9B/C80G9B

255

0

0FFH

0H

Interrupt

Vector Area

Figure 2-1. Program Memory Address Space

2-2

S3C80F9B/C80G9B

ADDRESS SPACES

The S3C80F9B/C80G9B register file has 318 registers. To increase the size of the internal register file, the upper

64-byte area of the register file is expanded two 64-byte areas, set 1 and set 2. The remaining 192-byte area of

the physical register file contains freely-addressable, general-purpose registers called prime registers.

The extension of register space into separately addressable sets is supported internally by addressing mode

restrictions.

Specific register types and the area (in bytes) they occupy in the S3C80F9B/C80G9B internal register space are

summarized in Table 2-1.

Table 2-1. S3C80F9B/C80G9B Register Type Summary

Register Type

Number of Bytes

General-purpose registers (including the 16-byte common

working register area, the 192-byte prime register area, and the

64-byte set 2 area)

272

CPU and system control registers

19

27

Mapped clock, peripheral, and I/O control and data registers

318

Total Addressable Bytes

2-3

ADDRESS SPACES

S3C80F9B/C80G9B

Set 1

Set 2

FFH

E0H

FFH

System and

Peripheral

Control Register

(Register Addressing

Mode)

General Purpose

Data Register

64

Bytes DFH

System Register

(Register Addressing

Mode)

(Indirect Register or

Indexed Addressing

Modes or

D0H

CFH

256

Bytes

Stack Operations)

Working Register

(Working Register

Addressing only)

C0H

BFH

Prime

Data Register

192

Bytes

~

(All Addressing

Mode)

00H

Figure 2-2. Internal Register File Organization

2-4

S3C80F9B/C80G9B

ADDRESS SPACES

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using

an 8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by

the register page pointer (PP, DFH). In the S3C80F9B/C80G9B microcontroller, a paged register file expansion is

not implemented and the register page pointer settings therefore always point to “page 0.”

Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always

'0000', automatically selecting page 0 as the source and destination page for register addressing. These page

pointer (PP) register settings, as shown in Figure 2-3, should not be modified during normal operation.

Register Page Pointer (PP)

DFH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Destination register page seleciton bits:

0 0 0 0 Destination: page 0

Source register page selection bits:

0 0 0 0 Source: page 0

NOTE:

In this microcontroller, only page 0 is implemented. A hardware reset operation

writes the 4-bit destination and source values shown above to the register page

pointer. These values should not be modified.

Figure 2-3. Register Page Pointer (PP)

2-5

ADDRESS SPACES

S3C80F9B/C80G9B

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

In some S3C8-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into

two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to

address one bank or the other. In the S3C80F9B/C80G9B microcontroller, bank 1 is not implemented. A

hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not

necessary.

The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The

lower 32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–

C0H). You can use the common working register area as a “scratch” area for data operations being performed in

other areas of the register file.

Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte

working register area can only be accessed using working register addressing. ( For more information about

working register addressing, please refer to Section 3, “Addressing Modes,” .)

Register Set 2

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another

64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH)

are addressed as part of page 0 in the S3C80F9B/C80G9B register space.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only

Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect

addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-6

S3C80F9B/C80G9B

ADDRESS SPACES

PRIME REGISTER SPACE

The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space or,

more simply, the prime area. You can access registers in this address using any addressing mode. (In other

words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All

registers in prime area locations are addressable immediately following a reset.

Set 1

FFH

FCH

FFH

C0H

Set 2

E0H

D0H

C0H

CPU and system registers

Prime

Register

Area

General-purpose registers

Peripheral control registers

00H

Figure 2-4. Set 1, Set 2, and Prime Area Register Map

2-7

ADDRESS SPACES

S3C80F9B/C80G9B

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as

consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to

form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block

anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected

working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers; R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers; R0–R15)

All of the registers in an 8-byte working register slice have the same binary value for their five most significant

address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.

The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

Slice 32

FFH

F8H

F7H

F0H

1 1 1 1 1 X X X

Set 1

Only

RP1 (Registers R8-R15)

Each register pointer points to

one 8-byte slice of the register

space, selecting a total 16-

byte working register block.

CFH

C0H

~

0 0 0 0 0 X X X

10H

FH

8H

7H

0H

RP0 (Registers R0-R7)

Slice 1

Figure 2-5. 8-Byte Working Register Areas (Slices)

2-8

S3C80F9B/C80G9B

ADDRESS SPACES

USING THE REGISTER POINTERS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable

8-byte working register slices in the register file. After a reset, they point to the working register common area:

RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see

Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently

pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in

set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed

addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general

programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see

Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous)

areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can

define the working register area very flexibly to support program requirements.

ꢀ

PROGRAMMING TIP — Setting the Register Pointers

SRP

SRP1

SRP0

CLR

LD

#70H

#48H

#0A0H

RP0

RP1,#0F8H

;

RP0 ← 70H, RP1 ← 78H

RP0 ← no change, RP1 ← 48H,

RP0 ← A0H, RP1 ← no change

RP0 ← 00H, RP1 ← no change

RP0 ← no change, RP1 ← 0F8H

Register File

Contains 32

8-Byte Slices

0 0 0 0 1 X X X

RP1

FH (R15)

16-byte

contiguous

working

8-Byte Slice

8H

7H

0 0 0 0 0 X X X

RP0

register block

0H (R0)

Figure 2-6. Contiguous 16-Byte Working Register Block

2-9

ADDRESS SPACES

S3C80F9B/C80G9B

F7H (R7)

F0H (R0)

8-Byte Slice

Register File

Contains 32

8-Byte Slices

16-byte

contiguous

working

1 1 1 1 0 X X X

register block

RP0

7H (R15)

0H (R0)

0 0 0 0 0 X X X

RP1

8-Byte Slice

Figure 2-7. Non-Contiguous 16-Byte Working Register Block

ꢀ

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H

contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

SRP0

ADD

ADC

#80H

;

RP0 ← 80H

R0 ← R0 + R1

R0 ← R0 + R2 + C

R0 ← R0 + R3 + C

R0 ← R0 + R4 + C

R0 ← R0 + R5 + C

R0,R1

R0,R2

R0,R3

R0,R4

R0,R5

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this

example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to

calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

ADC

80H,81H

80H,82H

80H,83H

80H,84H

80H,85H

;

80H ← (80H) + (81H)

80H ← (80H) + (82H) + C

80H ← (80H) + (83H) + C

80H ← (80H) + (84H) + C

80H ← (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of

instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.

2-10

S3C80F9B/C80G9B

ADDRESS SPACES

REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register

pair, you can access all locations in the register file except for set 2. With working register addressing, you use a

register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that

space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register

pair, the address of the first 8-bit register is always an even number and the address of the next register is always

an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the

least significant byte is always stored in the next (+ 1) odd-numbered register.

Working register addressing differs from Register addressing because it uses a register pointer to identify a

specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

n = Even address

Rn+1

Figure 2-8. 16-Bit Register Pair

2-11

ADDRESS SPACES

S3C80F9B/C80G9B

General-Purpose

Registers

Special-Purpose

Registers

Set 1

FFH

D0H

Control

Registers

Set 2

System

Registers

CFH

C0H

BFH

C0H

RP1

RP0

D7H

D6H

Register

Pointers

Each register pointer (RP) can independently point

to one of the 24 8-byte "slices" of the register file

(other than set 2). After a reset, RP0 points to

locations C0H-C7H and RP1 to locations C8H-CFH

(that is, to the common working register area).

Prime

Registers

NOTE: Only page 0 is implemented. Page 0

contains all of the addressable registers in

the internal register file.

00H

Page 0

Register Addressing Only

All

Indirect

Register,

Indexed

Addressing

Modes

Addressing

Modes

Can be Pointed by Register Pointer

Figure 2-9. Register File Addressing

2-12

S3C80F9B/C80G9B

ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations

C0H–CFH, as the active 16-byte working register block:

RP0 → C0H–C7H

RP1 → C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working

registers by operations that address any location on any page in the register file. Typically, these working

registers serve as temporary buffers for data operations between different pages.

Page 0

Set 1

FFH

FCH

E0H

DFH

Set 2

CFH

C0H

BFH

Following a hareware

reset, register pointers RP0 and

RP1 point to the common working

register area, locations C0H-CFH.

Prime

Area

~

1 1 0 0

0 0 0 0

1 0 0 0

RP0 =

RP1 = 1 1 0 0

00H

Figure 2-10. Common Working Register Area

2-13

ADDRESS SPACES

S3C80F9B/C80G9B

ꢀ

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,

using working register addressing mode only.

Example 1:

LD

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

SRP

LD

#0C0H

R2,40H

;

R2 (C2H) ← the value in location 40H

Example 2:

ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

SRP

ADD

#0C0H

R3,#45H

; R3 (C3H) ← R3 + 45H

4-Bit Working Register Addressing

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in

a register pointer serves as an addressing "window" that makes it possible for instructions to access working

registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected

working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);

— The five high-order bits in the register pointer select an 8-byte slice of the register space;

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are

concatenated with the three low-order bits from the instruction address to form the complete address. As long as

the address stored in the register pointer remains unchanged, the three bits from the address will always point to

an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing: The high-order bit of the instruction

'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the

three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-14

S3C80F9B/C80G9B

ADDRESS SPACES

RP0

RP1

Selects

RP0 or RP1

Address

OPCODE

4-bit address

procides three

low-order bits

Register pointer

provides five

high-order bits

Together they create an

8-bit register address

Figure 2-11. 4-Bit Working Register Addressing

RP1

RP0

0

1

0

1

0

1

0

1

0 0 0

Selects RP0

R6

1

OPCODE

Register

address

(76H)

0

Instruction:

'INC R6'

0

1

0

1 1 1 0

Figure 2-12. 4-Bit Working Register Addressing Example

2-15

ADDRESS SPACES

S3C80F9B/C80G9B

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To

initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working

register addressing.

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit

addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the

three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing: The four high-order bits of the instruction

address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register

address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from

RP1 and the three address bits from the instruction are concatenated to form the complete register address,

0ABH (10101011B).

RP0

RP1

Selects

RP0 or RP1

Address

These address

bits indicate

8-bit working

register

8-bit logical

address

1

0

addressing

Three low-

order bits

Register pointer

provides five

high-order bits

8-bit physical address

Figure 2-13. 8-Bit Working Register Addressing

2-16

S3C80F9B/C80G9B

ADDRESS SPACES

RP1

1

RP0

0

1

0

1

0

1

0

1

0

0 0 0

Selects RP1

R11

8-bit address

from instruction

'LD R11, R2'

1

0 1 1

Specifies working

register addressing

Register address (0ABH)

1

0

1

0

1

0 1 1

Figure 2-14. 8-Bit Working Register Addressing Example

2-17

ADDRESS SPACES

S3C80F9B/C80G9B

SYSTEM AND USER STACKS

S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH

and POP instructions are used to control system stack operations. The S3C80F9B/C80G9B architecture supports

stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents

of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to

their original locations. The stack address value is always decreased by one before a push operation and

increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top

of the stack, as shown in Figure 2-15.

High Address

PCL

PCH

Top of

stack

PCH

Top of

stack

Flags

Stack contents

after a call

Stack contents

after an

instruction

interrupt

Low Address

Figure 2-15. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL)

Register location D9H contain the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset,

the SPL value is undetermined. Because only internal memory 256-byte is implemented in The

S3C80F9B/C80G9B, the SPL must be initialized to an 8-bit value in the range 00–FFH.

2-18

S3C80F9B/C80G9B

ADDRESS SPACES

ꢀ

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD

SPL,#0FFH

;

SPL ← FFH

(Normally, the SPL is set to 0FFH by the initialization

routine)

•

PUSH

•

PP

;

Stack address 0FEH ← PP

RP0

RP1

R3

; Stack address 0FDH ← RP0

; Stack address 0FCH ← RP1

;

Stack address 0FBH ← R3

•

POP

R3

;

R3 ← Stack address 0FBH

RP1 ← Stack address 0FCH

RP0 ← Stack address 0FDH

PP ← Stack address 0FEH

RP1

RP0

PP

2-19

S3C80F9B/C80G9B

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The program counter is used to fetch instructions that are stored in program memory for execution. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to

determine the location of the data operand. The operands specified in instructions may be condition codes,

immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are

available for each instruction:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

— Immediate (IM)

3-1

ADDRESSING MODES

S3C80F9B/C80G9B

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).

Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-

byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

Program Memory

Register File

OPERAND

8-bit register

file address

dst

Points to one

register in register

file

OPCODE

One-Operand

Instruction

Value used in

instruction execution

(Example)

Sample Instruction:

DEC CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

Register File

MSB Points to

RP0 ot RP1

RP0 or RP1

Selected

RP points

to start

Program Memory

of working

register

block

4-bit

Working Register

3 LSBs

dst

src

Points to the

woking register

(1 of 8)

OPCODE

OPERAND

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD R1, R2

;

Where R1 and R2 are registers in the curruntly

selected working register area.

Figure 3-2. Working Register Addressing

3-2

S3C80F9B/C80G9B

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the

operand. Depending on the instruction used, the actual address may point to a register in the register file, to

program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to

indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be

accessed using Indirect Register addressing mode.

Program Memory

Register File

ADDRESS

8-bit register

file address

dst

Points to one

register in register

file

OPCODE

One-Operand

Instruction

Address of operand

used by instruction

(Example)

OPERAND

Value used in

instruction execution

Sample Instruction:

RL

@SHIFT

;

Where SHIFT is the label of an 8-bit register address.

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

S3C80F9B/C80G9B

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Program Memory

Example

Register

Pair

dst

Instruction

References

Program

Points to

Register Pair

OPCODE

16-Bit

Memory

Address

Points to

Program

Memory

Program Memory

OPERAND

Sample Instructions:

Value used in

instruction

CALL

JP

@RR2

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

S3C80F9B/C80G9B

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP points

to start of

woking register

block

Program Memory

4-bit

~

3 LSBs

Working

Register

Address

dst

src

Point to the

Woking Register

(1 of 8)

ADDRESS

OPERAND

OPCODE

Sample Instruction:

OR R3, @R6

Value used in

instruction

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

S3C80F9B/C80G9B

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP points

to start of

working

register

block

Program Memory

4-bit Working

Register Address

dst

src

Register

Pair

Next 2-bit Point

to Working Register

Pair

OPCODE

Example Instruction

References either

Program Memory or

Data Memory

16-Bit

(1 of 4)

address

points to

program

memory

or data

Program Memory

or

Data Memory

LSB Selects

memory

Value used in

Instruction

OPERAND

Sample Instructions:

LCD

LDE

R5,@RR6

R3,@RR14

@RR4, R8

; Program memory access

External data memory access

;

NOTE: LDE command is not available, because an external interface is not implemented

for the S3C80F9B/C80G9B.

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

S3C80F9B/C80G9B

ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to

calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access

locations in the internal register file or in external memory (if implemented). You cannot, however, access

locations C0H–FFH in set 1 using Indexed addressing.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128

to +127. This applies to external memory accesses only (see Figure 3–8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained

in a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address

(see Figure 3–9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for

external data memory (if implemented).

Register File

MSB Points to

RP0 or RP1

~

Selected RP

points to

start of

working

register

block

Value used in

Instruction

OPERAND

+

Program Memory

Base Address

3 LSBs

Two-Operand

Instruction

Example

dst/src

x

INDEX

Points to one of the

Woking Registers

(1 of 8)

OPCODE

Sample Instruction:

LD R0, #BASE[R1]

;

Where BASE is an 8-bit immediate value.

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

S3C80F9B/C80G9B

INDEXED ADDRESSING MODE (Continued)

Register File

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP points

to start of

working

register

block

~

Program Memory

OFFSET

NEXT 2 BITS

4-bit Working

Register Address

dst/src

x

Register

Pair

Point to Working

Register Pair

(1 of 4)

OPCODE

16-Bit

address

added to

offset

Program Memory

or

LSB Selects

Data Memory

+

16-Bit

8-Bit

Value used in

Instruction

OPERAND

16-Bit

Sample Instructions:

LDC

LDE

R4, #04H[RR2]

R4,#04H[RR2]

;

The values in the program address (RR2 + 04H)

are loaded into register R4.

Identical operation to LDC example, except that

external data memory is accessed.

NOTE: LDE command is not available, because an external interface is not implemented

for the S3C80F9B/C80G9B.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3C80F9B/C80G9B

ADDRESSING MODES

INDEXED ADDRESSING MODE (Continued)

Register File

RP0 or RP1

MSB Points to

RP0 or RP1

Selected

RP points

to start of

working

register

block

Program Memory

OFFSET

~

OFFSET

NEXT 2 BITS

4-bit Working

Register Address

dst/src

x

Register

Pair

Point to Working

Register Pair

OPCODE

16-Bit

address

added to

offset

Program Memory

or

LSB Selects

Data Memory

+

16-Bit

Value used in

Instruction

OPERAND

16-Bit

Sample Instructions:

LDC

LDE

R4, #1000H[RR2]

R4,#1000H[RR2]

;

The values in the program address (RR2 + 1000H)

are loaded into register R4.

Identical operation to LDC example, except that

external data memory is accessed.

NOTE: LDE command is not available, because an external interface is not implemented

for the S3C80F9B/C80G9B.

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES

S3C80F9B/C80G9B

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Address

Used

Program Memory

Upper Address Byte

Lower Address Byte

LSB Selects Program

dst/src

"0" or "1"

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

OPCODE

Sample Instructions:

LDC

LDE

R5,1234H

; The values in the program address (1234H)

are loaded into register R5.

; Identical operation to LDC example, except

that external data memory is accessed.

NOTE: LDE command is not available, because an external interface is not

implemented for the S3C80F9B/C80G9B.

Figure 3-10. Direct Addressing for Load Instructions

3-10

S3C80F9B/C80G9B

ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

Program Memory

Next OPCODE

Program

Memory

Address

Used

Lower Address Byte

Upper Address Byte

OPCODE

Sample Instructions:

JP

C,JOB1

;

Where JOB1 is a 16-bit immediate address

Where DISPLAY is a 16-bit immediate address

CALL DISPLAY

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES

S3C80F9B/C80G9B

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program

memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program

memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are

assumed to be all zeros.

Program Memory

Next Instruction

LSB Must be Zero

dst

Current

OPCODE

Instruction

Lower Address Byte

Upper Address Byte

Program Memory

Locations 0-255

Sample Instruction:

CALL #40H

;

The 16-bit value in program memory addresses 40H

and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

S3C80F9B/C80G9B

ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified

in the instruction. The displacement value is then added to the current PC value. The result is the address of the

next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction

immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The

instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current

PC Value

+

Displacement

Current Instruction

OPCODE

Signed

Displacement Value

Sample Instructions:

JR

ULT,$+OFFSET

;

Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES

S3C80F9B/C80G9B

IMMEDIATE MODE (IM)

In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.

The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing

mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The operand value is in the instruction)

Sample Instruction:

LD

R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3C80F9B/C80G9B

CONTROL REGISTERS

4

CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3C80F9B/C80G9B control registers are presented in an easy-to-read

format. You can use this section as a quick-reference source when writing application programs. Figure 4-1

illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed

information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual.

Data and counter registers are not described in detail in this reference section. More information about all of the

registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this

manual.

4-1

CONTROL REGISTERS

S3C80F9B/C80G9B

Table 4-1. Mapped Registers (Set 1)

Register Name

Mnemonic

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

Decimal

208

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

R/W

R ^(note)

R/W

Timer 0 counter

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

209

210

211

212

213

214

Register pointer 1

RP1

215

Locations D8H is not mapped.

Stack pointer (low byte)

SPL

IPH

217

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

R/W

R ^(note)

R/W

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

IPL

IRQ

IMR

System mode register

SYM

Register page pointer

PP

Port 0 data register

P0

Port 1 data register

P1

Port 2 data register

P2

Port 3 data register

P3

Port 4 data register

P4

Port 2 interrupt enable register

Port 2 interrupt pending register

Port 0 pull-up resistor enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 2 pull-up enable register

Port 3 control register

P2INT

P2PND

P0PUR

P0CONH

P0CONL

P1CONH

P1CONL

P2CONH

P2CONL

P2PUR

P3CON

P4CON

Port 4 control register

4-2

S3C80F9B/C80G9B

CONTROL REGISTERS

Table 4-1. Mapped Registers (Continued)

Register Name

Mnemonic

P0INT

Decimal

241

Hex

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

R/W

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

P0PND

242

R/W

CACON

243

R/W

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)

Timer 1 control register

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

T1DATAL

T1CON

244

R/W

245

R/W

R ^(note)

R/W

246

247

248

249

R/W

250

FAH

FBH

R/W

W

STOP Control register

STOPCON

251

Locations FCH is not mapped.

R ^(note)

R/W

Basic timer counter

BTCNT

EMT

253

FDH

FEH

FFH

External memory timing register

Interrupt priority register

254

255

IPR

R/W

NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.

4-3

CONTROL REGISTERS

S3C80F9B/C80G9B

Bit number(s) that is/are appended to the

register name for bit addressing

Name of individual

bit or bit function

Register address

(hexadecimal)

Register

Full Register name

mnemonic

D5H

FLAGS - System Flags Register

.7

.6

.5

.4

.3

.2

.1

.0

Bit Identifier

RESET Value

Read/Write

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

0

R/W

0

R/W

.7

Carry Flag (C)

0

1

Operation dose not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit7

.6

Zero Flag

0

1

Operation result is a non-zero value

Operation result is zero

.5

Sign Flag

0

1

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

' - ' = Not used

Description of the

effect of specific

bit settings

RESETvalue notation:

'-' = Not used

'x' = Undetermind value

'0' = Logic zero

'1' = Logic one

Addressing mode or

modes you can use to

modify register values

Bit number:

MSB = Bit 7

LSB = Bit 0

Figure 4-1. Register Description Format

4-4

S3C80F9B/C80G9B

CONTROL REGISTERS

BTCON — Basic Timer Control Register

D3H

Set 1

Bit Identifier

Reset Value

Read/Write

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Register addressing mode only

Addressing Mode

.7 – .4

Watchdog Timer Function Disable Code (for System Reset)

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Any other value

.3 and .2

Basic Timer Input Clock Selection Bits

f

/4096

/1024

/128

0

1

0

1

0

1

OSC

Invalid setting; not used for S3C80F9B/C80G9B

(1)

.1

Basic Timer Counter Clear Bit

0

1

No effect

Clear the basic timer counter value

(2)

.0

Clock Frequency Divider Clear Bit for Basic Timer and Timer 0

0

1

No effect

Clear both block frequency dividers

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to ‘00H’. Immediately following the write

operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the

write operation, the BTCON.0 value is automatically cleared to "0".

4-5

CONTROL REGISTERS

S3C80F9B/C80G9B

CACON — Counter A Control Register

F3H

Set 1

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

Bit Identifier

Reset Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

Counter A Input Clock Selection Bits

f_OSC

0

1

0

1

0

1

f_OSC/2

f_OSC/4

f_OSC/8

.5 and .4

Counter A Interrupt Timing Selection Bits

0

1

0

1

0

1

Elapsed time for Low data value

Elapsed time for High data value

Elapsed time for combined Low and High data values

Invalid setting; not used for S3C80F9B/C80G9B

.3

.2

.1

.0

Counter A Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Counter A Start Bit

0

1

Stop counter A

Start counter A

Counter A Mode Selection Bit

0

1

One-shot mode

Repeating mode

Counter A Output Flip-Flop Control Bit

0

1

Flip-Flop Low level (T-FF = Low)

Flip-flop High level (T-FF = High)

4-6

S3C80F9B/C80G9B

CONTROL REGISTERS

CLKCON — System Clock Control Register

D4H

Set 1

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

Bit Identifier

Reset Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

Oscillator IRQ Wake-up Function Enable Bit

Not used for S3C80F9B/C80G9B

.6 and .5

.4 and .3

Main Oscillator Stop Control Bits

Not used for S3C80F9B/C80G9B

CPU Clock (System Clock) Selection Bits ⁽¹⁾

f

/16

0

1

0

1

0

1

OSC

/8

/2

(non-divided)

Subsystem Clock Selection Bits ⁽²⁾

.2 – .0

1

0

1

Invalid setting for S3C80F9B/C80G9B

Select main system clock (MCLK)

Other value

NOTES:

1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the

appropriate values to CLKCON.3 and CLKCON.4.

2. These selection bits are required only for systems that have a main clock and a subsystem clock. The

S3C80F9B/C80G9B uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.

4-7

CONTROL REGISTERS

S3C80F9B/C80G9B

(note)

EMT — External Memory Timing Register

FEH

Set 1

Bit Identifier

Reset Value

.7

0

.6

1

.5

1

.4

1

.3

1

.2

1

.1

0

.0

–

R/W

–

Read/Write

Register addressing mode only

Addressing Mode

.7

External WAIT Input Function Enable Bit

0

1

Disable WAIT input function for external device

Enable WAIT input function for external device

.6

Slow Memory Timing Enable Bit

0

1

Disable slow memory timing

Enable slow memory timing

.5 and .4

Program Memory Automatic Wait Control Bits

0

1

0

1

0

1

No wait

Wait one cycle

Wait two cycles

Wait three cycles

.3 and .2

Data Memory Automatic Wait Control Bits

0

1

0

1

0

1

No wait

Wait one cycle

Wait two cycles

Wait three cycles

.1

.0

Stack Area Selection Bit

0

1

Select internal register file area

Select external data memory area

Not used for S3C80F9B/C80G9B

NOTE: The EMT register is not used for S3C80F9B/C80G9B, because an external peripheral interface is not implemented in

the S3C80F9B/C80G9B. The program initialization routine should clear the EMT register to '00H' following a reset.

Modification of EMT values during normal operation may cause a system malfunction.

4-8

S3C80F9B/C80G9B

CONTROL REGISTERS

FLAGS — System Flags Register

D5H

Set 1

Bit Identifier

Reset Value

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

0

.0

0

R/W

R

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

.5

.4

.3

.2

.1

.0

Carry Flag (C)

0

1

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

0

1

Operation result is ≤ +127 or ≥ –128

Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0

1

Add operation completed

Subtraction operation completed

Half-Carry Flag (H)

0

1

No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

0

1

Interrupt return (IRET) in progress (when read)

Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0

1

Bank 0 is selected (normal setting for S3C80F9B/C80G9B)

Invalid selection (bank 1 is not implemented)

4-9

CONTROL REGISTERS

S3C80F9B/C80G9B

IMR — Interrupt Mask Register

DDH

Set 1

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

Bit Identifier

Reset Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

.5

.4

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.7–P2.4

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.3–P2.0

0

1

Disable (mask)

Enable (un-mask)

Not used for S3C80F9B/C80G9B

.3

.2

Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt

0

1

Disable (mask)

Enable (un-mask)

.1

.0

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow

0

1

Disable (mask)

Enable (un-mask)

4-10

S3C80F9B/C80G9B

CONTROL REGISTERS

IPH — Instruction Pointer (High Byte)

DBH

Set 1

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

Bit Identifier

Reset Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 – .1

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction

pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL

register (DBH).

IPL ^{— Instruction Pointer (Low Byte)}

DBH

Set 1

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

.0

x

Bit Identifier

Reset Value

x

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 – .0

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH

register (DAH).

4-11

CONTROL REGISTERS

S3C80F9B/C80G9B

IPR — Interrupt Priority Register

FFH

Set 1

Bit Identifier

Reset Value

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Group priority undefined

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

Group priority undefined

.6

.5

.3

.2

.0

Interrupt Subgroup C Priority Control Bit

0

1

IRQ6 > IRQ7

IRQ7 > IRQ6

Interrupt Group C Priority Control Bit

0

1

IRQ5 > (IRQ6, IRQ7)

(IRQ6, IRQ7) > IRQ5

Interrupt Subgroup B Priority Control Bit (see Note)

0

1

IRQ4

Interrupt Group B Priority Control Bit (see Note)

0

1

IRQ2 >IRQ4

IRQ4 > IRQ2

Interrupt Group A Priority Control Bit

0

1

IRQ0 > IRQ1

IRQ1 > IRQ0

NOTE: The S3C80F9B/C80G9B interrupt structure uses only seven levels: IRQ0−IRQ2, and IRQ4-IRQ7.

Because IRQ3 is not recognized, the interrupt Subgroup B setting (IPR.3) is not evaluated.

4-12

S3C80F9B/C80G9B

CONTROL REGISTERS

IRQ — Interrupt Request Register

DCH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R

Read/Write

Register addressing mode only

Addressing Mode

.6

.5

Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4

0

1

Not pending

Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0

0

1

Not pending

Pending

Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4

Not pending

Pending

0

1

.4

Level 4 (IRQ4) Request Pending Bit; External Interrupts P2.3–P2.0

0

1

Not pending

Pending

.3

.2

Not used for S3C80F9B/C80G9B

Level 2 (IRQ2) Request Pending Bit; Counter A Interrupt

0

1

Not pending

Pending

.1

.0

Level 1 (IRQ1) Request Pending Bit; Timer 1 Match/Capture or Overflow

0

1

Not pending

Pending

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow

0

1

Not pending

Pending

NOTE: Interrupt level IRQ3 is not used in the S3C80F9B/C80G9B interrupt structure.

4-13

CONTROL REGISTERS

S3C80F9B/C80G9B

P0CONH — Port 0 Control Register (High Byte)

E8H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

.5 and .4

.3 and .2

P0.7/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.6/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.5/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1 and .0

P0.4/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:

1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector

address (E8H).

2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

4-14

S3C80F9B/C80G9B

CONTROL REGISTERS

P0CONL — Port 0 Control Register (Low Byte)

E9H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

.5 and .4

.3 and .2

P0.3/INT3 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.2/INT2 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.1/INT1 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1 and .0

P0.0/INT0 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:

1. The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector

address.

2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

4-15

CONTROL REGISTERS

S3C80F9B/C80G9B

P0INT — Port 0 External Interrupt Enable Register

F1H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

.5

.4

.3

.2

.1

.0

P0.7 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.6 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.5 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.4 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.3 External Interrupt (INT3) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.2 External Interrupt (INT2) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.1 External Interrupt (INT1) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.0 External Interrupt (INT0) Enable Bit

0

1

Disable interrupt

Enable interrupt

4-16

S3C80F9B/C80G9B

CONTROL REGISTERS

P0PND — Port 0 External Interrupt Pending Register

F2H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

(see Note)

.7

P0.7 External Interrupt (INT4) Pending Flag

0

1

No P0.7 external interrupt pending (when read)

P0.7 external interrupt is pending (when read)

.6

.5

.4

.3

.2

.1

.0

P0.6 External Interrupt (INT4) Pending Flag

0

1

No P0.6 external interrupt pending (when read)

P0.6 external interrupt is pending (when read)

P0.5 External Interrupt (INT4) Pending Flag

0

1

No P0.5 external interrupt pending (when read)

P0.5 external interrupt is pending (when read)

P0.4 External Interrupt (INT4) Pending Flag

0

1

No P0.4 external interrupt pending (when read)

P0.4 external interrupt is pending (when read)

P0.3 External Interrupt (INT3) Pending Flag

0

1

No P0.3 external interrupt pending (when read)

P0.3 external interrupt is pending (when read)

P0.2 External Interrupt (INT2) Pending Flag

0

1

No P0.2 external interrupt pending (when read)

P0.2 external interrupt is pending (when read)

P0.1 External Interrupt (INT1) Pending Flag

0

1

No P0.1 external interrupt pending (when read)

P0.1 external interrupt is pending (when read)

P0.0 External Interrupt (INT0) Pending Flag

No P0.0 external interrupt pending (when read)

P0.0 external interrupt is pending (when read)

0

1

NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag. Writing a “1” to an interrupt

pending flag (P0PND.0–7) has no effect.

4-17

CONTROL REGISTERS

S3C80F9B/C80G9B

P0PUR — Port 0 Pull-up Resistor Enable Register

E7H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

.5

.4

.3

.2

.1

.0

P0.7 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.6 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.5 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.4 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.3 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.2 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.1 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.0 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

4-18

S3C80F9B/C80G9B

CONTROL REGISTERS

P1CONH — Port 1 Control Register (High Byte)

EAH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P1.7 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P1.6 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P1.5 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P1.4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

4-19

CONTROL REGISTERS

S3C80F9B/C80G9B

P1CONL — Port 1 Control Register (Low Byte)

EBH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P1.3 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P1.2 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P1.1 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P1.0 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

4-20

S3C80F9B/C80G9B

CONTROL REGISTERS

P2CONH — Port 2 Control Register (High Byte)

ECH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P2.7 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.6 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.5 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control

register, location EEH, set 1.

4-21

CONTROL REGISTERS

S3C80F9B/C80G9B

P2CONL — Port 2 Control Register (Low Byte)

EDH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P2.3 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.2 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.1 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.0 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode ; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control

register, location EEH, set 1.

4-22

S3C80F9B/C80G9B

CONTROL REGISTERS

P2INT — Port 2 External Interrupt Enable Register

E5H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

5.

.4

.3

.2

.1

.0

P2.7 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.6 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.5 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.4 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.3 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.2 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.1 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.0 External Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

4-23

CONTROL REGISTERS

S3C80F9B/C80G9B

P2PND — Port 2 External Interrupt Pending Register

DBH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

P2.7 External Interrupt (INT9) Pending Flag ^{(see note)}

.7

.6

.5

.4

.3

.2

.1

.0

0

1

No P2.7 external interrupt pending (when read)

P2.7 external interrupt is pending (when read)

P2.6 External Interrupt (INT9) Pending Flag

0

1

No P2.6 external interrupt pending (when read)

P2.6 external interrupt is pending (when read)

P2.5 External Interrupt (INT9) Pending Flag

0

1

No P2.5 external interrupt pending (when read)

P2.5 external interrupt is pending (when read)

P2.4 External Interrupt S(INT9) Pending Flag

0

1

No P2.4 external interrupt pending (when read)

P2.4 external interrupt is pending (when read)

P2.3 External Interrupt (INT8) Pending Flag

0

1

No P2.3 external interrupt pending (when read)

P2.3 external interrupt is pending (when read)

P2.2 External Interrupt (INT7) Pending Flag

0

1

No P2.2 external interrupt pending (when read)

P2.2 external interrupt is pending (when read)

P2.1 External Interrupt (INT6) Pending Flag

0

1

No P2.1 external interrupt pending (when read)

P2.1 external interrupt is pending (when read)

P2.0 External Interrupt (INT5) Pending Flag

0

1

No P2.0 external interrupt pending (when read)

P2.0 external interrupt is pending (when read)

NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag. Writing a “1” to an interrupt

rending flag (P2PND.0–7) has no effect.

4-24

S3C80F9B/C80G9B

CONTROL REGISTERS

P2PUR — Port 2 Pull-up Resistor Enable Register

EEH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

.5

.4

.3

.2

.1

.0

P2.7 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.6 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.5 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.4 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.3 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.2 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.1 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.0 Pull-up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

4-25

CONTROL REGISTERS

S3C80F9B/C80G9B

P3CON — Port 3 Control Register

EFH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 and .6

Package selection and Alternative function select.

32 pin package

P3.0: TOPWM/T0CAP/T1CAP, P3.1 : REM/T0CK

OTHER 42/44 pin package

P3.0: T0PWM/T0CAP , P3.3 : T1CAP

P3.1: REM , P3.2 : T0CK

0

.5

P3.1 function selection bits

0

1

Normal I/O selection

Alternative function enable(REM/T0CK)

.4 and .3

P3.1 mode selection bit

0

1

0

1

0

1

Schmitt trigger input mode

Open- drain output mode

Push pull output mode

Schmitt trigger input with pull up resistor.

.2

Function Selection Bits for P3.0 & P3.3

0

1

Normal I/O selection

Alternative function enable(P3.0: T0PWM/T0CAP, P3.3: T1CAP)

.1 and .0

P3.0 mode selection bit

0

1

0

1

0

1

Schmitt trigger input mode

Open- drain output mode

Push pull output mode

Schmitt trigger input with pull up resistor.

NOTES:

1. The port 3 data register, P3, at location E3H, contains seven bit values which correspond to the following port 3 pin

functions (bit 6 is not used for the S3C80F9B/C80G9B:

a. P3, bit 7: carrier signal on (“1”) or off (“0”).

b. P3, bit 1: P3.1/REM/T0CK pin status, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin level.

c. P3, bit 2,3: P3.2,P3.3 are selected only to input pin with pull up resistor automatically.

d. P3, bit 4,5: P3.4,P3.5 are selected only to open drain output pin automatically.

2. The alternative function enable/disable are enabled in accordance with Function selection bit(bit5 and bit2) .

3. In case of 42/44 pin package, the pin assign for alternative functions can be selectable relating to mode selection

bit(bit0,1,2,3,4and 5)

4. Following Table is the specific example about the alternative function and pin assignment according to the each bit

control of P3CON in 42/44 pin package.

4-26

S3C80F9B/C80G9B

CONTROL REGISTERS

Table 4-2. Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package

P3CON

Each function description and assignment to P3.0–P3.3

B5 B4 B3 B2 B1 B0

P3.0

Normal I/O

T0_CAP

T0PWM

P3.1

Normal I/O

Normal Input

REM

P3.2

Normal Input

P3.3

Normal Input

0

1

x

0

1

0

1

0

1

0

1

0

1

0

1

x

0

1

0

1

0

1

0

1

0

1

x

0

1

0

1

x

0

1

0

1

0

1

0

1

x

0

1

0

x

0

1

0

1

0

1

Normal Input

T1CAP/Normal Input

Normal Input

Normal Input/

Normal Input

T0PWM

Normal I/O

T0_CAP

T0PWM

T0CK

Normal Input

T0CK

Normal Input

REM

T0CK

Normal Input

REM

T0CK/Normal Input

T1CAP/Normal Input

T0PWM

REM

T0PWM

Normal Input

REM

T0PWM

T0_CAP

REM

4-27

CONTROL REGISTERS

S3C80F9B/C80G9B

P4CON — Port 4 Control Resistor Enable Register

F0H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7

.6

.5

.4

.3

.2

.1

.0

P4.7 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.6 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.5 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.4 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.3 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.2 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.1 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

P4.0 Mode Selection Bit

0

1

Open-drain output mode

Push-pull output mode

4-28

S3C80F9B/C80G9B

CONTROL REGISTERS

PP — Register Page Pointer

DFH

Set 1

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

Bit Identifier

Reset Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 – .4

.3 – .0

Destination Register Page Selection Bits

Destination: page 0 (see note)

0

Source Register Page Selection Bits

Source: page 0 (see note)

0

NOTE: In the S3C80F9B/C80G9B microcontroller, a paged expansion of the internal register file is not implemented. For this

reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are

automatically set to ‘0000B’ following a hardware reset. These values should not be changed during normal operation.

4-29

CONTROL REGISTERS

S3C80F9B/C80G9B

RP0 — Register Pointer 1

D6H

Set 1

.7

1

.6

1

.5

0

.4

0

.3

0

.2

–

.1

–

.0

–

Bit Identifier

Reset Value

R/W

–

Read/Write

Register addressing mode only

Addressing Mode

.7 – .3

Register Pointer 0 Address Value

Register pointer 0 can independently point to one of the 24 8-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to address C0H in register set 1, selecting the 8-byte working register

slice C0H–C7H.

Not used for S3C80F9B/C80G9B

.2 – .0

RP1 — Register Pointer 1

D7H

Set 1

.7

1

.6

1

.5

0

.4

0

.3

1

.2

–

.1

–

.0

–

Bit Identifier

Reset Value

R/W

–

Read/Write

Register addressing mode only

Addressing Mode

.7 – .3

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 24 8-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to address C8H in register set 1, selecting the 8-byte working register

slice C8H–CFH.

Not used for S3C80F9B/C80G9B

.2 – .0

4-30

S3C80F9B/C80G9B

CONTROL REGISTERS

SPL — Stack Pointer

D9H

Set 1

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

Bit Identifier

Reset Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

.7 – .0

Stack Pointer Address (Low Byte)

The SP value is undefined following a reset.

STOPCON ^{— Stop Control Register}

FBH

Set 1

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

Bit Identifier

Reset Value

W

Read/Write

Register addressing mode only

Addressing Mode

.7—.0

Stop Control Register enable bits

1

0

1

0

1

0

1

Enable STOPCON

NOTES:

1. To get into STOP mode, stop control register must be enabled just before STOP instruction.

2. When STOP mode is released, stop control register (STOPCON) value is cleared automatically.

3. It is prohibited to write another value into STOPCON.

4-31

CONTROL REGISTERS

S3C80F9B/C80G9B

SYM — System Mode Register

DEH

Set 1

.7

0

.6

–

.5

–

.4

x

.3

x

.2

x

.1

0

.0

0

Bit Identifier

Reset Value

R/W

–

R/W

Read/Write

Register addressing mode only

Addressing Mode

(1)

.7

Tri-State External Interface Control Bit

0

1

Normal operation (disable tri-state operation)

Set external interface lines to high impedance (enable tri-state operation)

(2)

.6 and .5

.4 – .2

Not used for S3C80F9B/C80G9B

(3)

Fast Interrupt Level Selection Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IRQ0

IRQ1

Not used for S3C80F9B/C80G9B

IRQ4

IRQ5

IRQ6

IRQ7

(4)

.1

Fast Interrupt Enable Bit

0

1

Disable fast interrupt processing

Enable fast interrupt processing

(5)

.0

Global Interrupt Enable Bit

0

1

Disable global interrupt processing

Enable global interrupt processing

NOTES:

1. Because an external interface is not implemented for the S3C80F9B/C80G9B, SYM.7 must always be

"0".

2. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a “1” to this bit during

normal operation, a system malfunction may occur.

3. You can select only one interrupt level at a time for fast interrupt processing.

4. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.

5. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"

to SYM.0).

4-32

S3C80F9B/C80G9B

CONTROL REGISTERS

T0CON — Timer 0 Control Register

D2H

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

R/W

Register addressing mode only

Addressing Mode

.7 and .6

Timer 0 Input Clock Selection Bits

0

1

0

1

0

1

f

/4096

/256

/8

OSC

External clock input (at the T0CK pin, P3.1)

.5 and .4

Timer 0 Operating Mode Selection Bits

0

1

0

1

0

1

Interval timer mode (counter cleared by match signal)

Capture mode (rising edges, counter running, OVF interrupt can occur)

Capture mode (falling edges, counter running, OVF interrupt can occur)

PWM mode (OVF interrupt can occur)

.3

.2

.1

.0

Timer 0 Counter Clear Bit

0

1

No effect (when write)

Clear T0 counter, T0CNT (when write)

Timer 0 Overflow Interrupt Enable Bit ^(note)

0

1

Disable T0 overflow interrupt

Enable T0 overflow interrupt

Timer 0 Match/Capture Interrupt Enable Bit

0

1

Disable T0 match/capture interrupt

Enable T0 match/capture interrupt

Timer 0 Match/Capture Interrupt Pending Flag

0

1

No T0 match/capture interrupt pending (when read)

Clear T0 match/capture interrupt pending condition (when write)

T0 match/capture interrupt is pending (when read)

No effect (when write)

NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0 match/

capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.

4-33

CONTROL REGISTERS

S3C80F9B/C80G9B

T1CON — Timer 1 Control Register

FAH

Set 1

Bit Identifier

Reset Value

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

R/W

Read/Write

R/W

Register addressing mode only

Addressing Mode

.7 and .6

Timer 1 Input Clock Selection Bits

0

1

0

1

0

1

f

/4

OSC

/8

/16

Internal clock (counter A flip-flop, T-FF)

.5 and .4

Timer 1 Operating Mode Selection Bits

0

1

0

1

0

1

Interval timer mode (counter cleared by match signal)

Capture mode (rising edges, counter running, OVF can occur)

Capture mode (falling edges, counter running, OVF can occur)

Capture mode (rising and falling edges, counter running, OVF can occur)

.3

.2

.1

.0

Timer 1 Counter Clear Bit

0

1

No effect (when write)

Clear T1 counter, T1CNT (when write)

Timer 1 Overflow Interrupt Enable Bit ^(note)

0

1

Disable T1 overflow interrupt

Enable T1 overflow interrupt

Timer 1 Match/Capture Interrupt Enable Bit

0

1

Disable T1 match/capture interrupt

Enable T1 match/capture interrupt

Timer 1 Match/Capture Interrupt Pending Flag

0

1

No T1 match/capture interrupt pending (when read)

Clear T1 match/capture interrupt pending condition (when write)

T1 match/capture interrupt is pending (when read)

No effect (when write)

NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/

capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.

4-34

S3C80F9B/C80G9B

INSTRUCTION SET

6

INSTRUCTION SET

OVERVIEW

The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8

microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the

instruction set include:

— A full complement of 8-bit arithmetic and logic operations, including multiply and divide

— No special I/O instructions (I/O control/data registers are mapped directly into the register file)

— Decimal adjustment included in binary-coded decimal (BCD) operations

— 16-bit (word) data can be incremented and decremented

— Flexible instructions for bit addressing, rotate, and shift operations

Data Types

The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can

be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least

significant (right-most) bit.

Register Addressing

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is

specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory

addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."

Addressing Modes

There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative

(RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to

Section 3, "Addressing Modes."

6-1

INSTRUCTION SET

S3C80F9B/C80G9B

Table 6-1. Instruction Group Summary

Operands Instruction

Mnemonic

Load Instructions

CLR

dst

Clear

LD

dst,src

dst

Load

LDB

Load bit

LDE

Load external data memory

Load program memory

LDC

LDED

LDCD

LDEI

Load external data memory and decrement

Load program memory and decrement

Load external data memory and increment

Load program memory and increment

LDCI

LDEPD

LDCPD

LDEPI

LDCPI

LDW

Load external data memory with pre-decrement

Load program memory with pre-decrement

Load external data memory with pre-increment

Load program memory with pre-increment

Load word

POP

Pop from stack

POPUD

POPUI

PUSH

PUSHUD

PUSHUI

dst,src

src

Pop user stack (decrementing)

Pop user stack (incrementing)

Push to stack

dst,src

Push user stack (decrementing)

Push user stack (incrementing)

6-2

S3C80F9B/C80G9B

INSTRUCTION SET

Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Mnemonic

Arithmetic Instructions

ADC

ADD

CP

dst,src

Add with carry

Add

dst,src

dst

Compare

DA

Decimal adjust

Decrement

Decrement word

Divide

DEC

DECW

DIV

dst

dst,src

dst

INC

Increment

INCW

MULT

SBC

SUB

dst

Increment word

Multiply

dst,src

Subtract with carry

Subtract

Logic Instructions

AND

COM

OR

dst,src

dst

Logical AND

Complement

dst,src

Logical OR

XOR

Logical exclusive OR

6-3

INSTRUCTION SET

Mnemonic

S3C80F9B/C80G9B

Table 6-1. Instruction Group Summary (Continued)

Operands Instruction

Program Control Instructions

BTJRF

BTJRT

CALL

CPIJE

CPIJNE

DJNZ

ENTER

EXIT

IRET

JP

dst,src

dst

Bit test and jump relative on false

Bit test and jump relative on true

Call procedure

dst,src

r,dst

Compare, increment and jump on equal

Compare, increment and jump on non-equal

Decrement register and jump on non-zero

Enter

Exit

Interrupt return

cc,dst

dst

Jump on condition code

Jump unconditional

JP

JR

cc,dst

Jump relative on condition code

RET

Return

WFI

Wait for interrupt

Bit Manipulation Instructions

BAND

BCP

BITC

BITR

BITS

BOR

BXOR

TCM

TM

dst,src

dst

Bit AND

Bit compare

Bit complement

Bit reset

dst

Bit set

dst,src

Bit OR

Bit XOR

Test complement under mask

Test under mask

6-4

S3C80F9B/C80G9B

INSTRUCTION SET

Table 6-1. Instruction Group Summary (Concluded)

Operands Instruction

Mnemonic

Rotate and Shift Instructions

RL

dst

Rotate left

RLC

RR

Rotate left through carry

Rotate right

RRC

SRA

SWAP

Rotate right through carry

Shift right arithmetic

Swap nibbles

CPU Control Instructions

CCF

DI

Complement carry flag

Disable interrupts

Enable interrupts

Enter Idle mode

No operation

EI

IDLE

NOP

RCF

SB0

SB1

SCF

Reset carry flag

Set bank 0

Set bank 1

Set carry flag

SRP

src

Set register pointers

Set register pointer 0

Set register pointer 1

Enter Stop mode

SRP0

SRP1

STOP

6-5

INSTRUCTION SET

S3C80F9B/C80G9B

FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these

bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and

FLAGS.2 are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank

address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register

can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register.

For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the

AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously,

two write will occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, Set 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Bank address

status flag (BA)

Carry flag (C)

Zero flag (Z)

Sign flag (S)

Overflow flag (V)

Fast interrupt

status flag (FIS)

Half-carry flag (H)

Decimal adjust flag (D)

Figure 6-1. System Flags Register (FLAGS)

6-6

S3C80F9B/C80G9B

INSTRUCTION SET

FLAG DESCRIPTIONS

C

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to

the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the

specified register. Program instructions can set, clear, or complement the carry flag.

Z

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For

operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is

logic zero.

S

V

D

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the

result. A logic zero indicates a positive number and a logic one indicates a negative number.

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than

– 128. It is also cleared to "0" following logic operations.

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a

subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by

programmers, and cannot be used as a test condition.

H

Half-Carry Flag (FLAGS.2)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows

out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous

addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a

program.

FIS ^{Fast Interrupt Status Flag (FLAGS.1)}

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.

When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET

instruction is executed.

BA ^{Bank Address Flag (FLAGS.0)}

The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected,

bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and

is set to "1" (select bank 1) when you execute the SB1 instruction.

6-7

INSTRUCTION SET

S3C80F9B/C80G9B

INSTRUCTION SET NOTATION

Table 6-2. Flag Notation Conventions

Flag

C

Z

Description

Carry flag

Zero flag

S

V

D

H

0

Sign flag

Overflow flag

Decimal-adjust flag

Half-carry flag

Cleared to logic zero

Set to logic one

1

*

Set or cleared according to operation

Value is unaffected

Value is undefined

–

x

Table 6-3. Instruction Set Symbols

Symbol

dst

src

@

Description

Destination operand

Source operand

Indirect register address prefix

Program counter

PC

IP

Instruction pointer

FLAGS

RP

#

Flags register (D5H)

Register pointer

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix

Opcode

H

D

B

opc

6-8

S3C80F9B/C80G9B

Notation

INSTRUCTION SET

Table 6-4. Instruction Notation Conventions

Description Actual Operand Range

cc

r

Condition code

Working register only

See list of condition codes in Table 6-6.

Rn (n = 0–15)

rb

r0

rr

Bit (b) of working register

Rn.b (n = 0–15, b = 0–7)

Rn (n = 0–15)

Bit 0 (LSB) of working register

Working register pair

RRp (p = 0, 2, 4, ..., 14)

reg or Rn (reg = 0–255, n = 0–15)

reg.b (reg = 0–255, b = 0–7)

R

Register or working register

Bit 'b' of register or working register

Register pair or working register pair

Rb

RR

reg or RRp (reg = 0–254, even number only, where

p = 0, 2, ..., 14)

IA

Ir

Indirect addressing mode

addr (addr = 0–254, even number only)

@Rn (n = 0–15)

Indirect working register only

IR

Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

IRR

Indirect register pair or indirect working

register pair

@RRp or @reg (reg = 0–254, even only, where

p = 0, 2, ..., 14)

X

Indexed addressing mode

#reg [Rn] (reg = 0–255, n = 0–15)

XS

Indexed (short offset) addressing mode

#addr [RRp] (addr = range –128 to +127, where

p = 0, 2, ..., 14)

XL

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 0–65535, where

p = 0, 2, ..., 14)

DA

RA

Direct addressing mode

Relative addressing mode

addr (addr = range 0–65535)

addr (addr = number in the range +127 to –128 that is

an offset relative to the address of the next instruction)

IM

Immediate addressing mode

#data (data = 0–255)

IML

Immediate (long) addressing mode

#data (data = range 0–65535)

6-9

INSTRUCTION SET

S3C80F9B/C80G9B

Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

–

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

DEC

R1

DEC

IR1

ADD

r1,r2

ADD

r1,Ir2

ADD

R2,R1

ADD

IR2,R1

ADD

R1,IM

BOR

r0–Rb

U

P

E

R

RLC

R1

RLC

IR1

ADC

r1,r2

ADC

r1,Ir2

ADC

R2,R1

ADC

IR2,R1

ADC

R1,IM

BCP

r1.b, R2

INC

R1

INC

IR1

SUB

r1,r2

SUB

r1,Ir2

SUB

R2,R1

SUB

IR2,R1

SUB

R1,IM

BXOR

r0–Rb

JP

IRR1

SRP/0/1

IM

SBC

r1,r2

SBC

r1,Ir2

SBC

R2,R1

SBC

IR2,R1

SBC

R1,IM

BTJR

r2.b, RA

DA

R1

DA

IR1

OR

r1,r2

OR

r1,Ir2

OR

R2,R1

OR

IR2,R1

OR

R1,IM

LDB

r0–Rb

POP

R1

POP

IR1

AND

r1,r2

AND

r1,Ir2

AND

R2,R1

AND

IR2,R1

AND

R1,IM

BITC

r1.b

COM

R1

COM

IR1

TCM

r1,r2

TCM

r1,Ir2

TCM

R2,R1

TCM

IR2,R1

TCM

R1,IM

BAND

r0–Rb

N

I

PUSH

R2

PUSH

IR2

TM

r1,r2

TM

r1,Ir2

TM

R2,R1

TM

IR2,R1

TM

R1,IM

BIT

r1.b

DECW

RR1

DECW

IR1

PUSHUD PUSHUI

IR1,R2

MULT

R2,RR1

MULT

IR2,RR1

MULT

IM,RR1

LD

r1, x, r2

B

L

E

IR1,R2

RL

R1

RL

IR1

POPUD

IR2,R1

POPUI

IR2,R1

DIV

R2,RR1

DIV

IR2,RR1

DIV

IM,RR1

LD

r2, x, r1

INCW

RR1

INCW

IR1

CP

r1,r2

CP

r1,Ir2

CP

R2,R1

CP

IR2,R1

CP

R1,IM

LDC

r1, Irr2, xL

CLR

R1

CLR

IR1

XOR

r1,r2

XOR

r1,Ir2

XOR

R2,R1

XOR

IR2,R1

XOR

R1,IM

LDC

r2, Irr2, xL

RRC

R1

RRC

IR1

CPIJE

Ir,r2,RA

LDC

r1,Irr2

LDW

LD

r1, Ir2

RR2,RR1 IR2,RR1 RR1,IML

SRA

R1

SRA

IR1

CPIJNE

Irr,r2,RA

LDC

r2,Irr1

CALL

IA1

LD

IR1,IM

LD

Ir1, r2

H

E

X

RR

R1

RR

IR1

LDCD

r1,Irr2

LDCI

r1,Irr2

LD

R2,R1

LD

R2,IR1

LD

R1,IM

LDC

r1, Irr2, xs

SWAP

R1

SWAP

IR1

LDCPD

r2,Irr1

LDCPI

r2,Irr1

CALL

IRR1

LD

IR2,R1

CALL

DA1

LDC

r2, Irr1, xs

6-10

S3C80F9B/C80G9B

INSTRUCTION SET

Table 6-5. Opcode Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

–

8

9

A

B

C

D

E

F

U

P

E

R

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

LD

r1,R2

LD

r2,R1

DJNZ

r1,RA

JR

cc,RA

LD

r1,IM

JP

cc,DA

INC

r1

EXIT

WFI

↓

SB0

SB1

IDLE

STOP

DI

N

I

B

L

E

EI

RET

IRET

RCF

SCF

CCF

NOP

H

E

X

LD

r1,R2

LD

r2,R1

DJNZ

r1,RA

JR

cc,RA

LD

r1,IM

JP

cc,DA

INC

r1

6-11

INSTRUCTION SET

S3C80F9B/C80G9B

CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under

which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"

after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump

instructions.

Table 6-6. Condition Codes

Binary

Mnemonic

Description

Always false

Flags Set

0000

1000

F

–

T

Always true

–

0111 ^(note)

1111 ^(note)

0110 ^(note)

1110 ^(note)

1101

C

Carry

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

NC

Z

No carry

Zero

NZ

PL

MI

OV

Not zero

Plus

0101

Minus

0100

Overflow

1100

NOV

EQ

No overflow

Equal

0110 ^(note)

1110 ^(note)

1001

NE

Not equal

GE

Greater than or equal

Less than

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

0001

LT

1010

GT

Greater than

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

0010

LE

1111 ^(note)

0111 ^(note)

1011

UGE

ULT

UGT

ULE

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

0011

NOTES:

1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For

example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;

after a CP instruction, however, EQ would probably be used.

2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-12

S3C80F9B/C80G9B

INSTRUCTION SET

INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM8

instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The

following information is included in each instruction description:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Shorthand notation of the instruction's operation

— Textual description of the instruction's effect

— Specific flag settings affected by the instruction

— Detailed description of the instruction's format, execution time, and addressing mode(s)

— Programming example(s) explaining how to use the instruction

6-13

INSTRUCTION SET

S3C80F9B/C80G9B

ADC — Add with carry

ADC

dst,src

dst ← dst + src + c

Operation:

The source operand, along with the setting of the carry flag, is added to the destination operand

and the sum is stored in the destination. The contents of the source are unaffected. Two's-

complement addition is performed. In multiple precision arithmetic, this instruction permits the

carry from the addition of low-order operands to be carried into the addition of high-order

operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Set if the result is "0"; cleared otherwise.

Z:

S: Set if the result is negative; cleared otherwise.

Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

V:

D:

Always cleared to "0".

H: Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

12

13

r

lr

dst

src

3

6

14

15

R

IR

dst

6

16

R

IM

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and

register 03H = 0AH:

ADC

R1,R2

→

R1 = 14H, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#11H

R1 = 1BH, R2 = 03H

Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H

Register 01H = 32H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",

and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds

03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

6-14

S3C80F9B/C80G9B

INSTRUCTION SET

ADD — Add

ADD

dst,src

Operation:

dst ← dst + src

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D: Always cleared to "0".

H: Set if a carry from the low-order nibble occurred.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

02

03

r

lr

dst

src

3

6

04

05

R

IR

dst

6

06

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD

R1,R2

→

R1 = 15H, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#25H

R1 = 1CH, R2 = 03H

Register 01H = 24H, register 02H = 03H

Register 01H = 2BH, register 02H = 03H

Register 01H = 46H

In the first example, destination working register R1 contains 12H and the source working register

R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in

register R1.

6-15

INSTRUCTION SET

S3C80F9B/C80G9B

AND — Logical AND

AND

dst, src

Operation:

dst ← dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the

destination. The AND operation results in a "1" bit being stored whenever the corresponding bits

in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the

source are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

52

53

r

lr

dst

src

3

6

54

55

R

IR

dst

6

56

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND

R1,R2

→

R1 = 02H, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#25H

R1 = 02H, R2 = 03H

Register 01H = 01H, register 02H = 03H

Register 01H = 00H, register 02H = 03H

Register 01H = 21H

In the first example, destination working register R1 contains the value 12H and the source

working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source

operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

6-16

S3C80F9B/C80G9B

INSTRUCTION SET

BAND — Bit AND

BAND

dst,src.b

BAND

dst.b,src

Operation:

dst(0) ← dst(0) AND src(b)

or

dst(b) ← dst(b) AND src(0)

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of

the destination (or source). The resultant bit is stored in the specified bit of the destination. No

other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

67

r0

Rb

dst | b | 0

src | b | 1

3

6

67

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,

the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

BAND

R1,01H.1

01H.1,R1

→

R1 = 06H, register 01H = 05H

Register 01H = 05H, R1 = 07H

In the first example, source register 01H contains the value 05H (00000101B) and destination

working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1

value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value

06H (00000110B) in register R1.

6-17

INSTRUCTION SET

S3C80F9B/C80G9B

BCP — Bit Compare

BCP

dst,src.b

Operation:

dst(0) – src(b)

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.

The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both

operands are unaffected by the comparison.

Flags:

C: Unaffected.

Z: Set if the two bits are the same; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

3

6

17

r0

Rb

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H and register 01H = 01H:

BCP

R1,01H.1

→

R1 = 07H, register 01H = 01H

If destination working register R1 contains the value 07H (00000111B) and the source register

01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of

the source register (01H) and bit zero of the destination register (R1). Because the bit values are

not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

6-18

S3C80F9B/C80G9B

INSTRUCTION SET

BITC — Bit Complement

BITC

dst.b

Operation:

dst(b) ← NOT dst(b)

This instruction complements the specified bit within the destination without affecting any other

bits in the destination.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

2

4

57

rb

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H

BITC

R1.1

→

R1 = 05H

If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"

complements bit one of the destination and leaves the value 05H (00000101B) in register R1.

Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is

cleared.

6-19

INSTRUCTION SET

S3C80F9B/C80G9B

BITR — Bit Reset

BITR

dst.b

Operation:

dst(b) ← 0

The BITR instruction clears the specified bit within the destination without affecting any other bits

in the destination.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

2

4

77

rb

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BITR

R1.1

→

R1 = 05H

If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one

of the destination register R1, leaving the value 05H (00000101B).

6-20

S3C80F9B/C80G9B

INSTRUCTION SET

BITS — Bit Set

BITS

dst.b

Operation:

dst(b) ← 1

The BITS instruction sets the specified bit within the destination without affecting any other bits in

the destination.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

2

4

77

rb

dst | b | 1

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BITS

R1.3

→

R1 = 0FH

If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit

three of the destination register R1 to "1", leaving the value 0FH (00001111B).

6-21

INSTRUCTION SET

S3C80F9B/C80G9B

BOR — Bit OR

BOR

dst,src.b

dst.b,src

Operation:

dst(0) ← dst(0) OR src(b)

or

dst(b) ← dst(b) OR src(0)

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the

destination (or the source). The resulting bit value is stored in the specified bit of the destination.

No other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

07

r0

Rb

dst | b | 0

src | b | 1

3

6

07

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,

the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:

Given: R1 = 07H and register 01H = 03H:

BOR

R1, 01H.1

01H.2, R1

→

R1 = 07H, register 01H = 03H

Register 01H = 07H, R1 = 07H

In the first example, destination working register R1 contains the value 07H (00000111B) and

source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs

bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value

(07H) in working register R1.

In the second example, destination register 01H contains the value 03H (00000011B) and the

source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically

ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H

in register 01H.

6-22

S3C80F9B/C80G9B

INSTRUCTION SET

BTJRF — Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation:

If src(b) is a "0", then PC ← PC + dst

The specified bit within the source operand is tested. If it is a "0", the relative address is added to

the program counter and control passes to the statement whose address is now in the PC;

otherwise, the instruction following the BTJRF instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

(Note 1)

dst

src

opc

dst

3

10

37

RA

rb

src | b | 0

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRF

SKIP,R1.3

→

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"

tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the

memory location pointed to by the SKIP. (Remember that the memory location must be within the

allowed range of + 127 to – 128.)

6-23

INSTRUCTION SET

S3C80F9B/C80G9B

BTJRT — Bit Test, Jump Relative on True

BTJRT

dst,src.b

Operation:

If src(b) is a "1", then PC ← PC + dst

The specified bit within the source operand is tested. If it is a "1", the relative address is added to

the program counter and control passes to the statement whose address is now in the PC;

otherwise, the instruction following the BTJRT instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

(Note 1)

dst

src

opc

dst

3

10

37

RA

rb

src | b | 1

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRT

SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"

tests bit one in the source register (R1). Because it is a "1", the relative address is added to the

PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the

memory location must be within the allowed range of + 127 to – 128.)

6-24

S3C80F9B/C80G9B

INSTRUCTION SET

BXOR — Bit XOR

BXOR

dst,src.b

BXOR

dst.b,src

Operation:

dst(0) ← dst(0) XOR src(b)

or

dst(b) ← dst(b) XOR src(0)

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)

of the destination (or source). The result bit is stored in the specified bit of the destination. No

other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Cleared to "0".

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

27

r0

Rb

dst | b | 0

src | b | 1

3

6

27

Rb

r0

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,

the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):

BXOR

R1,01H.1

01H.2,R1

→

R1 = 06H, register 01H = 03H

Register 01H = 07H, R1 = 07H

In the first example, destination working register R1 has the value 07H (00000111B) and source

register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs

bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in

bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is

unaffected.

6-25

INSTRUCTION SET

S3C80F9B/C80G9B

CALL — Call Procedure

CALL

dst

Operation:

SP

@SP

SP

@SP

PC

←

SP – 1

PCL

SP –1

PCH

dst

The current contents of the program counter are pushed onto the top of the stack. The program

counter value used is the address of the first instruction following the CALL instruction. The

specified destination address is then loaded into the program counter and points to the first

instruction of a procedure. At the end of the procedure the return instruction (RET) can be used

to return to the original program flow. RET pops the top of the stack back into the program

counter.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

3

14

F6

F4

D4

DA

IRR

IA

dst

2

12

14

Examples:

Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:

CALL

3521H

→

SP = 0000H

(Memory locations 0000H = 1AH, 0001H = 4AH, where

4AH is the address that follows the instruction.)

CALL

@RR0

#40H

→

SP = 0000H (0000H = 1AH, 0001H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the

value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the

stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the

value 3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the

statement "CALL @RR0" produces the same result except that the 49H is stored in stack

location 0001H (because the two-byte instruction format was used). The PC is then loaded with

the value 3521H, the address of the first instruction in the program sequence to be executed.

Assuming that the contents of the program counter and stack pointer are the same as in the first

example, if program address 0040H contains 35H and program address 0041H contains 21H, the

statement "CALL #40H" produces the same result as in the second example.

6-26

S3C80F9B/C80G9B

INSTRUCTION SET

CCF — Complement Carry Flag

CCF

Operation:

C ← NOT C

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic

zero; if C = "0", the value of the carry flag is changed to logic one.

Flags:

C: Complemented.

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

EF

Example:

Given: The carry flag = "0":

CCF

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H),

changing its value from logic zero to logic one.

6-27

INSTRUCTION SET

S3C80F9B/C80G9B

CLR — Clear

CLR

dst

Operation:

dst ← "0"

The destination location is cleared to "0".

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

B0

B1

R

IR

Examples:

Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

CLR

00H

→

Register 00H = 00H

@01H

Register 01H = 02H, register 02H = 00H

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H

value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)

addressing mode to clear the 02H register value to 00H.

6-28

S3C80F9B/C80G9B

INSTRUCTION SET

COM — Complement

COM

dst

Operation:

dst ← NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are

changed to "0s", and vice-versa.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

60

61

R

IR

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM

R1

→

R1 = 0F8H

R1 = 07H, register 07H = 0EH

@R1

In the first example, destination working register R1 contains the value 07H (00000111B). The

statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,

and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value

of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-29

INSTRUCTION SET

S3C80F9B/C80G9B

CP — Compare

CP

dst,src

Operation:

dst – src

The source operand is compared to (subtracted from) the destination operand, and the

appropriate flags are set accordingly. The contents of both operands are unaffected by the

comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst |

src

2

4

6

A2

r

A3

r

lr

opc

src

dst

src

3

6

A4

A5

R

IR

6

A6

R

IM

Examples:

1. Given: R1 = 02H and R2 = 03H:

CP R1,R2 →

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the value

03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value

(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are

"1".

2. Given: R1 = 05H and R2 = 0AH:

CP

JP

INC

LD

R1,R2

UGE,SKIP

R1

SKIP

R3,R1

In this example, destination working register R1 contains the value 05H which is less than the

contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"

and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"

executes, the value 06H remains in working register R3.

6-30

S3C80F9B/C80G9B

INSTRUCTION SET

CPIJE — Compare, Increment, and Jump on Equal

CPIJE

dst,src,RA

Operation:

If dst – src = "0", PC ← PC + RA

Ir ← Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is "0",

the relative address is added to the program counter and control passes to the statement whose

address is now in the program counter. Otherwise, the instruction immediately following the

CPIJE instruction is executed. In either case, the source pointer is incremented by one before the

next instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src dst

RA

3

12

C2

r

Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 02H:

CPIJE

R1,@R2,SKIP

→

R2 = 04H, PC jumps to SKIP location

In this example, working register R1 contains the value 02H, working register R2 the value 03H,

and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value

02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the

relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that

the memory location must be within the allowed range of + 127 to – 128.)

6-31

INSTRUCTION SET

S3C80F9B/C80G9B

CPIJNE — Compare, Increment, and Jump on Non-Equal

CPIJNE

dst,src,RA

Operation:

If dst – src _ "0", PC ← PC + RA

Ir ← Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is not

"0", the relative address is added to the program counter and control passes to the statement

whose address is now in the program counter; otherwise the instruction following the CPIJNE

instruction is executed. In either case the source pointer is incremented by one before the next

instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src dst

RA

3

12

D2

r

Ir

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 04H:

CPIJNE R1,@R2,SKIP

→

R2 = 04H, PC jumps to SKIP location

Working register R1 contains the value 02H, working register R2 (the source pointer) the value

03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts

04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the

relative address is added to the PC and the PC then jumps to the memory location pointed to by

SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.

(Remember that the memory location must be within the allowed range of + 127 to – 128.)

6-32

S3C80F9B/C80G9B

INSTRUCTION SET

DA — Decimal Adjust

DA

dst

Operation:

dst ← DA dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or

subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table

indicates the operation performed. (The operation is undefined if the destination operand was not

the result of a valid addition or subtraction of BCD digits):

Instruction

Carry

Before DA

Bits 4–7

Value (Hex)

H Flag

Before DA

Bits 0–3

Value (Hex)

Number Added

to Byte

Carry

After DA

0

1

0

1

0–9

0–8

0–9

A–F

9–F

A–F

0–2

0–3

0–9

0–8

7–F

6–F

0

1

0

1

0

1

0

1

0

1

0–9

A–F

0–3

0–9

A–F

0–3

0–9

A–F

0–3

0–9

6–F

0–9

6–F

00

0

1

0

1

06

ADD

ADC

60

66

60

66

00 = – 00

FA = – 06

A0 = – 60

9A = – 66

SUB

SBC

Flags:

C: Set if there was a carry from the most significant bit; cleared otherwise (see table).

Z: Set if result is "0"; cleared otherwise.

S: Set if result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

40

41

R

IR

6-33

INSTRUCTION SET

S3C80F9B/C80G9B

DA — Decimal Adjust

DA

(Continued)

Example:

Given: Working register R0 contains the value 15 (BCD), working register R1 contains

27 (BCD), and address 27H contains 46 (BCD):

ADD

DA

R1,R0

R1

;

C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH

R1 ← 3CH + 06

If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is

incorrect, however, when the binary representations are added in the destination location using

standard binary arithmetic:

0 0 0 1 0 1 0 1

15

27

+ 0 0 1 0 0 1 1 1

0 0 1 1 1 1 0 0

=

3CH

The DA instruction adjusts this result so that the correct BCD representation is obtained:

0 0 1 1 1 1 0 0

+ 0 0 0 0 0 1 1 0

0 1 0 0 0 0 1 0

=

42

Assuming the same values given above, the statements

SUB

DA

27H,R0

@R1

;

C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = 1

@R1 ← 31–0

leave the value 31 (BCD) in address 27H (@R1).

6-34

S3C80F9B/C80G9B

INSTRUCTION SET

DEC — Decrement

DEC

dst

Operation:

dst ← dst – 1

The contents of the destination operand are decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

00

01

R

IR

Examples:

Given: R1 = 03H and register 03H = 10H:

DEC

R1

→

R1 = 02H

Register 03H = 0FH

@R1

In the first example, if working register R1 contains the value 03H, the statement "DEC R1"

decrements the hexadecimal value by one, leaving the value 02H. In the second example, the

statement "DEC @R1" decrements the value 10H contained in the destination register 03H by

one, leaving the value 0FH.

6-35

INSTRUCTION SET

S3C80F9B/C80G9B

DECW — Decrement Word

DECW

dst

Operation:

dst ← dst – 1

The contents of the destination location (which must be an even address) and the operand

following that location are treated as a single 16-bit value that is decremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

8

80

81

RR

IR

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

DECW

RR0

→

R0 = 12H, R1 = 33H

@R2

Register 30H = 0FH, register 31H = 20H

In the first example, destination register R0 contains the value 12H and register R1 the value

34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word

and decrements the value of R1 by one, leaving the value 33H.

NOTE:

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW

instruction. To avoid this problem, we recommend that you use DECW as shown in the following

example:

LOOP:

DECW

LD

OR

RR0

R2,R1

R2,R0

NZ,LOOP

JR

6-36

S3C80F9B/C80G9B

INSTRUCTION SET

DI — Disable Interrupts

DI

Operation:

SYM (0) ← 0

Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all

interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,

but the CPU will not service them while interrupt processing is disabled.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

8F

Example:

Given: SYM = 01H:

DI

If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the

register and clears SYM.0 to "0", disabling interrupt processing.

Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

6-37

INSTRUCTION SET

S3C80F9B/C80G9B

DIV— Divide (Unsigned)

DIV

dst,src

Operation:

dst ÷ src

dst (UPPER) ← REMAINDER

dst (LOWER) ← QUOTIENT

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)

is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of

8

the destination. When the quotient is ≥ 2 , the numbers stored in the upper and lower halves of

the destination for quotient and remainder are incorrect. Both operands are treated as unsigned

integers.

8

9

Flags:

C: Set if the V flag is set and quotient is between 2 and 2 –1; cleared otherwise.

Z: Set if divisor or quotient = "0"; cleared otherwise.

S: Set if MSB of quotient = "1"; cleared otherwise.

8

V: Set if quotient is ≥ 2 or if divisor = "0"; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

RR

src

opc

src

dst

3

26/10

94

95

96

R

IR

IM

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.

Examples:

Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:

DIV

RR0,R2

→

R0 = 03H, R1 = 40H

R0 = 03H, R1 = 20H

R0 = 03H, R1 = 80H

RR0,@R2

RR0,#20H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H

(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit

RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the

value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination

register RR0 (R0) and the quotient in the lower half (R1).

6-38

S3C80F9B/C80G9B

INSTRUCTION SET

DJNZ — Decrement and Jump if Non-Zero

DJNZ

r,dst

Operation:

r ← r – 1

If r ≠ 0, PC ← PC + dst

The working register being used as a counter is decremented. If the contents of the register are

not logic zero after decrementing, the relative address is added to the program counter and

control passes to the statement whose address is now in the PC. The range of the relative

address is +127 to –128, and the original value of the PC is taken to be the address of the

instruction byte following the DJNZ statement.

NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at

the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

r | opc

dst

2

8 (jump taken)

8 (no jump)

rA

RA

r = 0 to F

Example:

Given: R1 = 02H and LOOP is the label of a relative address:

SRP

#0C0H

DJNZ

R1,LOOP

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the

destination operand instead of a numeric relative address value. In the example, working register

R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.

Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative

address specified by the LOOP label.

6-39

INSTRUCTION SET

S3C80F9B/C80G9B

EI — Enable Interrupts

EI

Operation:

SYM (0) ← 1

An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to

be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was

set while interrupt processing was disabled (by executing a DI instruction), it will be serviced

when you execute the EI instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

9F

Example:

Given: SYM = 00H:

EI

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the

statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for

global interrupt processing.)

6-40

S3C80F9B/C80G9B

INSTRUCTION SET

ENTER — Enter

ENTER

Operation:

SP

@SP

IP

←

SP – 2

IP

PC

IP

@IP

IP + 2

This instruction is useful when implementing threaded-code languages. The contents of the

instruction pointer are pushed to the stack. The program counter (PC) value is then written to the

instruction pointer. The program memory word that is pointed to by the instruction pointer is

loaded into the PC, and the instruction pointer is incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

14

1F

Example:

The diagram below shows one example of how to use an ENTER statement.

Before

After

Data

Address

IP

Data

Address

IP

0050

0040

0022

0043

0110

0020

Address

Data

1F

Address

40 Enter

Data

1F

PC

SP

40 Enter

PC

SP

41 Address H 01

42 Address L 10

43 Address H

41 Address H 01

42 Address L 10

43 Address H

20

21

22

00

50

IPH

IPL

Data

110 Routine

Memory

22 Data

Stack

6-41

INSTRUCTION SET

S3C80F9B/C80G9B

EXIT — Exit

EXIT

Operation:

IP

←

@SP

SP

PC

IP

SP + 2

@IP

IP + 2

This instruction is useful when implementing threaded-code languages. The stack value is

popped and loaded into the instruction pointer. The program memory word that is pointed to by

the instruction pointer is then loaded into the program counter, and the instruction pointer is

incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

1

14 (internal stack)

16 (internal stack)

2F

Example:

The diagram below shows one example of how to use an EXIT statement.

Before

After

Data

Address

IP

Data

Address

IP

0050

0040

0022

0052

0060

0022

Address

Data

Address

Data

PC

SP

PC

SP

50 PCL old

51 PCH

60

00

60

Main

140 Exit

2F

20

21

22

00

50

IPH

IPL

Data

Memory

Data

22

Stack

6-42

S3C80F9B/C80G9B

INSTRUCTION SET

IDLE — Idle Operation

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle

mode can be released by an interrupt request (IRQ) or an external reset operation.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

1

4

6F

–

Example:

The instruction

IDLE

stops the CPU clock but not the system clock.

6-43

INSTRUCTION SET

S3C80F9B/C80G9B

INC — Increment

INC

dst

Operation:

dst ← dst + 1

The contents of the destination operand are incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

dst | opc

opc

1

4

rE

r

r = 0 to F

dst

2

4

20

21

R

IR

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC

R0

→

R0 = 1CH

00H

@R0

Register 00H = 0DH

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement "INC

R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it

contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the

value of register 1BH from 0FH to 10H.

6-44

S3C80F9B/C80G9B

INSTRUCTION SET

INCW — Increment Word

INCW

dst

Operation:

dst ← dst + 1

The contents of the destination (which must be an even address) and the byte following that

location are treated as a single 16-bit value that is incremented by one.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

8

A0

A1

RR

IR

Examples:

Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:

INCW

RR0

→

R0 = 1AH, R1 = 03H

@R1

Register 02H = 10H, register 03H = 00H

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H

in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the

value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect

Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to

00H and register 02H from 0FH to 10H.

NOTE:

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an

INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the

following example:

LOOP:

INCW

LD

OR

RR0

R2,R1

R2,R0

NZ,LOOP

JR

6-45

INSTRUCTION SET

S3C80F9B/C80G9B

IRET — Interrupt Return

IRET

IRET (Normal)

IRET (Fast)

Operation:

FLAGS ← @SP

SP ← SP + 1

PC ← @SP

PC ↔ IP

FLAGS ← FLAGS'

FIS ← 0

SP ← SP + 2

SYM(0) ← 1

This instruction is used at the end of an interrupt service routine. It restores the flag register and

the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the

fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast

interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

IRET

(Normal)

Bytes

Cycles

Opcode

(Hex)

opc

1

10 (internal stack)

12 (internal stack)

BF

IRET

(Fast)

Bytes

Cycles

Opcode

(Hex)

opc

1

6

BF

Example:

In the figure below, the instruction pointer is initially loaded with 100H in the main program before

interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are

swapped. This causes the PC to jump to address 100H and the IP to keep the return address.

The last instruction in the service routine normally is a jump to IRET at address FFH. This causes

the instruction pointer to be loaded with 100H "again" and the program counter to jump back to

the main program. Now, the next interrupt can occur and the IP is still correct at 100H.

0H

IRET

FFH

Interrupt

Service

Routine

100H

JP to FFH

FFFFH

NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order

of the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with

a reset of the IPR register).

6-46

S3C80F9B/C80G9B

INSTRUCTION SET

JP — Jump

JP

cc,dst

(Conditional)

JP

dst

(Unconditional)

Operation:

If cc is true, PC ← dst

The conditional JUMP instruction transfers program control to the destination address if the

condition specified by the condition code (cc) is true; otherwise, the instruction following the JP

instruction is executed. The unconditional JP simply replaces the contents of the PC with the

contents of the specified register pair. Control then passes to the statement addressed by the

PC.

Flags:

No flags are affected.

Format: ⁽¹⁾

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(2)

cc | opc

dst

3

8

ccD

DA

cc = 0 to F

opc

dst

2

8

30

IRR

NOTES:

1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the

opcode are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

JP

C,LABEL_W

@00H

→

LABEL_W = 1000H, PC = 1000H

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to

that location. Had the carry flag not been set, control would then have passed to the statement

immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents

of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-47

INSTRUCTION SET

S3C80F9B/C80G9B

JR — Jump Relative

JR

cc,dst

Operation:

If cc is true, PC ← PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the

program counter and control passes to the statement whose address is now in the program

counter; otherwise, the instruction following the JR instruction is executed. (See list of condition

codes).

The range of the relative address is +127, –128, and the original value of the program counter is

taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

(1)

cc | opc

dst

2

6

ccB

RA

cc = 0 to F

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each

four bits.

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

JR

C,LABEL_X

→

PC = 1FF7H

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will

pass control to the statement whose address is now in the PC. Otherwise, the program

instruction following the JR would be executed.

6-48

S3C80F9B/C80G9B

INSTRUCTION SET

LD — Load

LD

dst, src

Operation:

dst ← src

The contents of the source are loaded into the destination. The source's contents are unaffected.

No flags are affected.

Flags:

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

IM

R

dst | opc

src | opc

opc

src

dst

2

4

rC

r8

r

2

3

4

r9

R

r

r = 0 to F

dst | src

4

C7

D7

r

lr

r

Ir

opc

src

dst

src

6

E4

E5

R

IR

opc

dst

6

E6

D6

R

IM

IR

opc

src

dst

x

3

6

F5

87

97

IR

r

R

x [r]

r

dst | src

src | dst

x

x [r]

6-49

INSTRUCTION SET

S3C80F9B/C80G9B

LD — Load

LD

(Continued)

Examples:

Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,

register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

LD

R0,#10H

→

R0 = 10H

R0,01H

R0 = 20H, register 01H = 20H

Register 01H = 01H, R0 = 01H

R1 = 20H, R0 = 01H

01H,R0

R1,@R0

@R0,R1

R0 = 01H, R1 = 0AH, register 01H = 0AH

Register 00H = 20H, register 01H = 20H

Register 02H = 20H, register 00H = 01H

Register 00H = 0AH

00H,01H

02H,@00H

00H,#0AH

@00H,#10H

@00H,02H

R0,#LOOP[R1]

#LOOP[R0],R1

Register 00H = 01H, register 01H = 10H

Register 00H = 01H, register 01H = 02, register 02H = 02H

R0 = 0FFH, R1 = 0AH

Register 31H = 0AH, R0 = 01H, R1 = 0AH

6-50

S3C80F9B/C80G9B

INSTRUCTION SET

LDB — Load Bit

LDB

dst,src.b

LDB

dst.b,src

Operation:

dst(0) ← src(b)

or

dst(b) ← src(0)

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the

source is loaded into the specified bit of the destination. No other bits of the destination are

affected. The source is unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

6

47

r0

Rb

dst | b | 0

src | b | 1

3

6

47

Rb

r0

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit

address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0 = 06H and general register 00H = 05H:

LDB

R0,00H.2

00H.0,R0

→

R0 = 07H, register 00H = 05H

R0 = 06H, register 00H = 04H

In the first example, destination working register R0 contains the value 06H and the source

general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the

00H register into bit zero of the R0 register, leaving the value 07H in register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit

zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general

register 00H.

6-51

INSTRUCTION SET

S3C80F9B/C80G9B

LDC/LDE — Load Memory

LDC/LDE

dst,src

Operation:

dst ← src

This instruction loads a byte from program or data memory into a working register or vice-versa.

The source values are unaffected. LDC refers to program memory and LDE to data memory. The

assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number

for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

1.

2.

3.

4.

5.

6.

7.

8.

9.

opc

dst | src

src | dst

dst | src

src | dst

dst | src

src | dst

dst | 0000

src | 0000

dst | 0001

src | 0001

2

10

C3

D3

E7

F7

A7

B7

A7

B7

A7

B7

r

Irr

2

3

4

10

12

14

Irr

r

XS

XL

r

XS [rr]

r

XL

r

XL [rr]

r

XL [rr]

L

H

XL

r

DA

r

L

DA

L

H

DA

r

DA

r

10.

DA

NOTES:

1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.

2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte.

3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes.

4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of

values, used in formats 9 and 10, are used to address data memory.

6-52

S3C80F9B/C80G9B

INSTRUCTION SET

LDC/LDE — Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations

0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory

locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

LDC

R0,@RR2

;

R0 ← contents of program memory location 0104H

R0 = 1AH, R2 = 01H, R3 = 04H

LDE

R0,@RR2

;

R0 ← contents of external data memory location 0104H

R0 = 2AH, R2 = 01H, R3 = 04H

LDC ^(note)@RR2,R0

;

11H (contents of R0) is loaded into program memory

location 0104H (RR2),

working registers R0, R2, R3 → no change

LDE

LDC

LDE

@RR2,R0

;

11H (contents of R0) is loaded into external data memory

location 0104H (RR2),

working registers R0, R2, R3 → no change

R0,#01H[RR2]

;

R0 ← contents of program memory location 0105H

(01H + RR2),

R0 = 6DH, R2 = 01H, R3 = 04H

;

R0 ← contents of external data memory location 0105H

(01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H

LDC ^(note)#01H[RR2],R0

;

11H (contents of R0) is loaded into program memory location

0105H (01H + 0104H)

LDE

LDC

LDE

#01H[RR2],R0

;

11H (contents of R0) is loaded into external data memory

location 0105H (01H + 0104H)

R0,#1000H[RR2] ; R0 ← contents of program memory location 1104H

(1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

;

R0,#1000H[RR2] ; R0 ← contents of external data memory location 1104H

;

(1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

LDC

LDE

R0,1104H

;

R0 ← contents of program memory location 1104H, R0 = 88H

;

R0 ← contents of external data memory location 1104H,

R0 = 98H

LDC ^(note)1105H,R0

;

11H (contents of R0) is loaded into program memory location

1105H, (1105H) ← 11H

LDE

1105H,R0

;

11H (contents of R0) is loaded into external data memory

location 1105H, (1105H) ← 11H

NOTE: These instructions are not supported by masked ROM type devices.

6-53

INSTRUCTION SET

S3C80F9B/C80G9B

LDCD/LDED — Load Memory and Decrement

LDCD/LDED dst,src

Operation:

dst ← src

rr ← rr – 1

These instructions are used for user stacks or block transfers of data from program or data

memory to the register file. The address of the memory location is specified by a working register

pair. The contents of the source location are loaded into the destination location. The memory

address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

2

10

E2

r

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and

external data memory location 1033H = 0DDH:

LDCD

R8,@RR6

;

0CDH (contents of program memory location 1033H) is loaded

into R8 and RR6 is decremented by one

R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ← RR6 – 1)

LDED

R8,@RR6

;

0DDH (contents of data memory location 1033H) is loaded

into R8 and RR6 is decremented by one (RR6 ← RR6 – 1)

R8 = 0DDH, R6 = 10H, R7 = 32H

6-54

S3C80F9B/C80G9B

INSTRUCTION SET

LDCI/LDEI — Load Memory and Increment

LDCI/LDEI

dst,src

Operation:

dst ← src

rr ← rr + 1

These instructions are used for user stacks or block transfers of data from program or data

memory to the register file. The address of the memory location is specified by a working register

pair. The contents of the source location are loaded into the destination location. The memory

address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes

'Irr' even for program memory and odd for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

2

10

E3

r

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and

1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI

R8,@RR6

;

0CDH (contents of program memory location 1033H) is loaded

into R8 and RR6 is incremented by one (RR6 ← RR6 + 1)

R8 = 0CDH, R6 = 10H, R7 = 34H

LDEI

R8,@RR6

;

0DDH (contents of data memory location 1033H) is loaded

into R8 and RR6 is incremented by one (RR6 ← RR6 + 1)

R8 = 0DDH, R6 = 10H, R7 = 34H

6-55

INSTRUCTION SET

S3C80F9B/C80G9B

LDCPD/LDEPD — Load Memory with Pre-Decrement

LDCPD/

LDEPD

dst,src

Operation:

rr ← rr – 1

dst ← src

These instructions are used for block transfers of data from program or data memory from the

register file. The address of the memory location is specified by a working register pair and is first

decremented. The contents of the source location are then loaded into the destination location.

The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for external data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src | dst

2

14

F2

Irr

r

Examples:

Given: R0 = 77H, R6 = 30H, and R7 = 00H:

LDCPD @RR6,R0

;

(RR6 ← RR6 – 1)

77H (contents of R0) is loaded into program memory location

2FFFH (3000H – 1H)

R0 = 77H, R6 = 2FH, R7 = 0FFH

LDEPD @RR6,R0

;

(RR6 ← RR6 – 1)

77H (contents of R0) is loaded into external data memory

location 2FFFH (3000H – 1H)

R0 = 77H, R6 = 2FH, R7 = 0FFH

6-56

S3C80F9B/C80G9B

INSTRUCTION SET

LDCPI/LDEPI — Load Memory with Pre-Increment

LDCPI/

LDEPI

dst,src

Operation:

rr ← rr + 1

dst ← src

These instructions are used for block transfers of data from program or data memory from the

register file. The address of the memory location is specified by a working register pair and is first

incremented. The contents of the source location are loaded into the destination location. The

contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler

makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src | dst

2

14

F3

Irr

r

Examples:

Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:

LDCPI

@RR6,R0

;

(RR6 ← RR6 + 1)

7FH (contents of R0) is loaded into program memory

location 2200H (21FFH + 1H)

R0 = 7FH, R6 = 22H, R7 = 00H

LDEPI

@RR6,R0

;

(RR6 ← RR6 + 1)

7FH (contents of R0) is loaded into external data memory

location 2200H (21FFH + 1H)

R0 = 7FH, R6 = 22H, R7 = 00H

6-57

INSTRUCTION SET

S3C80F9B/C80G9B

LDW — Load Word

LDW

dst,src

Operation:

dst ← src

The contents of the source (a word) are loaded into the destination. The contents of the source

are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

RR

src

RR

IR

opc

src

dst

3

8

C4

C5

src

4

8

C6

RR

IML

Examples:

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,

register 01H = 02H, register 02H = 03H, and register 03H = 0FH:

LDW

RR6,RR4

00H,02H

→

R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH

Register 00H = 03H, register 01H = 0FH,

register 02H = 03H, register 03H = 0FH

LDW

RR2,@R7

→

R2 = 03H, R3 = 0FH,

04H,@01H

RR6,#1234H

02H,#0FEDH

Register 04H = 03H, register 05H = 0FH

R6 = 12H, R7 = 34H

Register 02H = 0FH, register 03H = 0EDH

In the second example, please note that the statement "LDW 00H,02H" loads the contents of the

source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general

register 00H and the value 0FH in register 01H.

The other examples show how to use the LDW instruction with various addressing modes and

formats.

6-58

S3C80F9B/C80G9B

INSTRUCTION SET

MULT — Multiply (Unsigned)

MULT

dst,src

Operation:

dst ← dst ∞ src

The 8-bit destination operand (even register of the register pair) is multiplied by the source

operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination

address. Both operands are treated as unsigned integers.

Flags:

C: Set if result is > 255; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if MSB of the result is a "1"; cleared otherwise.

V: Cleared.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

RR

src

opc

src

dst

3

22

84

85

86

R

IR

IM

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

MULT

00H, 02H

→

Register 00H = 01H, register 01H = 20H, register 02H = 09H

Register 00H = 00H, register 01H = 0C0H

00H, @01H

00H, #30H

Register 00H = 06H, register 01H = 00H

In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in

the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The

16-bit product, 0120H, is stored in the register pair 00H, 01H.

6-59

INSTRUCTION SET

S3C80F9B/C80G9B

NEXT — Next

PC ← @ IP

IP ← IP + 2

The NEXT instruction is useful when implementing threaded-code languages. The program

memory word that is pointed to by the instruction pointer is loaded into the program counter. The

instruction pointer is then incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

10

0F

Example:

The following diagram shows one example of how to use the NEXT instruction.

Before

After

Data

Address

IP

Data

Address

IP

0043

0120

0045

0130

Address

Data

Address

43 Address H

Data

PC

43 Address H 01

PC

44 Address L 10

45 Address H

44 Address L

45 Address H

120 Next

Memory

130 Routine

Memory

6-60

S3C80F9B/C80G9B

INSTRUCTION SET

NOP — No Operation

NOP

Operation:

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are

executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

FF

Example:

When the instruction

NOP

is encountered in a program, no operation occurs. Instead, there is a delay in instruction

execution time.

6-61

INSTRUCTION SET

S3C80F9B/C80G9B

OR — Logical OR

OR

dst,src

Operation:

dst ← dst OR src

The source operand is logically ORed with the destination operand and the result is stored in the

destination. The contents of the source are unaffected. The OR operation results in a "1" being

stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is

stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

42

43

r

lr

dst

src

3

6

44

45

R

IR

dst

6

46

R

IM

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and

register 08H = 8AH:

OR

R0,R1

→

R0 = 3FH, R1 = 2AH

R0,@R2

00H,01H

01H,@00H

00H,#02H

R0 = 37H, R2 = 01H, register 01H = 37H

Register 00H = 3FH, register 01H = 37H

Register 00H = 08H, register 01H = 0BFH

Register 00H = 0AH

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,

the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result

(3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing

modes and formats.

6-62

S3C80F9B/C80G9B

INSTRUCTION SET

POP — Pop From Stack

POP

dst

Operation:

dst ← @SP

SP ← SP + 1

The contents of the location addressed by the stack pointer are loaded into the destination. The

stack pointer is then incremented by one.

Flags:

No flags affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

8

50

51

R

IR

Examples:

Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,

and stack register 0FBH = 55H:

POP

00H

→

Register 00H = 55H, SP = 00FCH

@00H

Register 00H = 01H, register 01H = 55H, SP = 00FCH

In the first example, general register 00H contains the value 01H. The statement "POP 00H"

loads the contents of location 00FBH (55H) into destination register 00H and then increments the

stack pointer by one. Register 00H then contains the value 55H and the SP points to location

00FCH.

6-63

INSTRUCTION SET

S3C80F9B/C80G9B

POPUD — Pop User Stack (Decrementing)

POPUD

dst,src

Operation:

dst ← src

IR ← IR – 1

This instruction is used for user-defined stacks in the register file. The contents of the register file

location addressed by the user stack pointer are loaded into the destination. The user stack

pointer is then decremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

8

92

R

IR

Example:

Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and

register 02H = 70H:

POPUD 02H,@00H

→

Register 00H = 41H, register 02H = 6FH, register 42H = 6FH

If general register 00H contains the value 42H and register 42H the value 6FH, the statement

"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The

user stack pointer is then decremented by one, leaving the value 41H.

6-64

S3C80F9B/C80G9B

INSTRUCTION SET

POPUI — Pop User Stack (Incrementing)

POPUI

dst,src

Operation:

dst ← src

IR ← IR + 1

The POPUI instruction is used for user-defined stacks in the register file. The contents of the

register file location addressed by the user stack pointer are loaded into the destination. The user

stack pointer is then incremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

src

dst

3

8

93

R

IR

Example:

Given: Register 00H = 01H and register 01H = 70H:

POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H

→

If general register 00H contains the value 01H and register 01H the value 70H, the statement

"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user

stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

6-65

INSTRUCTION SET

S3C80F9B/C80G9B

PUSH — Push To Stack

PUSH

src

Operation:

SP ← SP – 1

@SP ← src

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)

into the location addressed by the decremented stack pointer. The operation then adds the new

value to the top of the stack.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

src

2

8 (internal clock)

8 (external clock)

70

R

8 (internal clock)

8 (external clock)

71

IR

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:

PUSH

40H

→

Register 40H = 4FH, stack register 0FFH = 4FH,

SPH = 0FFH, SPL = 0FFH

PUSH

@40H

Register 40H = 4FH, register 4FH = 0AAH, stack register

0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH

In the first example, if the stack pointer contains the value 0000H, and general register 40H the

value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It

then loads the contents of register 40H into location 0FFFFH and adds this new value to the top

of the stack.

6-66

S3C80F9B/C80G9B

INSTRUCTION SET

PUSHUD — Push User Stack (Decrementing)

PUSHUD

dst,src

Operation:

IR ← IR – 1

dst ← src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements

the user stack pointer and loads the contents of the source into the register addressed by the

decremented stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst

src

3

8

82

IR

R

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:

PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H

→

If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The

01H register value, 05H, is then loaded into the register addressed by the decremented user

stack pointer.

6-67

INSTRUCTION SET

S3C80F9B/C80G9B

PUSHUI — Push User Stack (Incrementing)

PUSHUI

dst,src

Operation:

IR ← IR + 1

dst ← src

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user

stack pointer and then loads the contents of the source into the register location addressed by

the incremented user stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst

src

3

8

83

IR

R

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:

PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H

→

If the user stack pointer (register 00H, for example) contains the value 03H, the statement

"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H

register value, 05H, is then loaded into the location addressed by the incremented user stack

pointer.

6-68

S3C80F9B/C80G9B

INSTRUCTION SET

RCF — Reset Carry Flag

RCF

Operation:

C ← 0

The carry flag is cleared to logic zero, regardless of its previous value.

Flags:

C:

Cleared to "0".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

CF

Example:

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

6-69

INSTRUCTION SET

S3C80F9B/C80G9B

RET — Return

RET

Operation:

PC ← @SP

SP ← SP + 2

The RET instruction is normally used to return to the previously executing procedure at the end of

a procedure entered by a CALL instruction. The contents of the location addressed by the stack

pointer are popped into the program counter. The next statement that is executed is the one that

is addressed by the new program counter value.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

1

8 (internal stack)

10 (internal stack)

AF

Example:

Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:

RET PC = 101AH, SP = 00FEH

→

The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte

of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the

PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to

memory location 00FEH.

6-70

S3C80F9B/C80G9B

INSTRUCTION SET

RL — Rotate Left

RL

dst

Operation:

C ← dst (7)

dst (0) ← dst (7)

dst (n + 1) ← dst (n), n = 0–6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is

moved to the bit zero (LSB) position and also replaces the carry flag.

7

0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

90

91

R

IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

RL

00H

→

Register 00H = 55H, C = "1"

Register 01H = 02H, register 02H = 2EH, C = "0"

@01H

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)

and setting the carry and overflow flags.

6-71

INSTRUCTION SET

S3C80F9B/C80G9B

RLC — Rotate Left Through Carry

RLC

dst

Operation:

dst (0) ← C

C ← dst (7)

dst (n + 1) ← dst (n), n = 0–6

The contents of the destination operand with the carry flag are rotated left one bit position. The

initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

7

0

C

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

10

11

R

IR

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

00H

→

Register 00H = 54H, C = "1"

@01H

Register 01H = 02H, register 02H = 2EH, C = "0"

In the first example, if general register 00H has the value 0AAH (10101010B), the statement

"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag

and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H

(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

6-72

S3C80F9B/C80G9B

INSTRUCTION SET

RR — Rotate Right

RR

dst

Operation:

C ← dst (0)

dst (7) ← dst (0)

dst (n) ← dst (n + 1), n = 0–6

The contents of the destination operand are rotated right one bit position. The initial value of bit

zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7

0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

E0

E1

R

IR

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

RR

00H

→

Register 00H = 98H, C = "1"

Register 01H = 02H, register 02H = 8BH, C = "1"

@01H

In the first example, if general register 00H contains the value 31H (00110001B), the statement

"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to

bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also

resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

6-73

INSTRUCTION SET

S3C80F9B/C80G9B

RRC — Rotate Right Through Carry

RRC

dst

Operation:

dst (7) ← C

C ← dst (0)

dst (n) ← dst (n + 1), n = 0–6

The contents of the destination operand and the carry flag are rotated right one bit position. The

initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit

7 (MSB).

7

0

C

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".

Z: Set if the result is "0" cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

C0

C1

R

IR

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC

00H

→

Register 00H = 2AH, C = "1"

@01H

Register 01H = 02H, register 02H = 0BH, C = "1"

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")

replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new

value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both

cleared to "0".

6-74

S3C80F9B/C80G9B

INSTRUCTION SET

SB0 — Select Bank 0

SB0

Operation:

BANK ← 0

The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,

selecting bank 0 register addressing in the set 1 area of the register file.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

4F

Example:

The statement

SB0

clears FLAGS.0 to "0", selecting bank 0 register addressing.

6-75

INSTRUCTION SET

S3C80F9B/C80G9B

SB1 — Select Bank 1

SB1

Operation:

BANK ← 1

The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,

selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not

implemented in some KS88-series microcontrollers.)

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

5F

Example:

The statement

SB1

sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.

6-76

S3C80F9B/C80G9B

INSTRUCTION SET

SBC — Subtract With Carry

SBC

dst,src

Operation:

dst ← dst – src – c

The source operand, along with the current value of the carry flag, is subtracted from the

destination operand and the result is stored in the destination. The contents of the source are

unaffected. Subtraction is performed by adding the two's-complement of the source operand to

the destination operand. In multiple precision arithmetic, this instruction permits the carry

("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of

high-order operands.

Flags:

C: Set if a borrow occurred (src > dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign

of the result is the same as the sign of the source; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

32

33

r

lr

dst

src

3

6

34

35

R

IR

dst

6

36

R

IM

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register

03H = 0AH:

SBC

R1,R2

→

R1 = 0CH, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#8AH

R1 = 05H, R2 = 03H, register 03H = 0AH

Register 01H = 1CH, register 02H = 03H

Register 01H = 15H,register 02H = 03H, register 03H = 0AH

Register 01H = 95H; C, S, and V = "1"

In the first example, if working register R1 contains the value 10H and register R2 the value 03H,

the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the

destination (10H) and then stores the result (0CH) in register R1.

6-77

INSTRUCTION SET

S3C80F9B/C80G9B

SCF — Set Carry Flag

SCF

Operation:

Flags:

C ← 1

The carry flag (C) is set to logic one, regardless of its previous value.

C: Set to "1".

No other flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4

DF

Example:

The statement

SCF

sets the carry flag to logic one.

6-78

S3C80F9B/C80G9B

INSTRUCTION SET

SRA — Shift Right Arithmetic

SRA

dst

Operation:

dst (7) ← dst (7)

C ← dst (0)

dst (n) ← dst (n + 1), n = 0–6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit

position 6.

7

6

0

C

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

D0

D1

R

IR

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

00H

→

Register 00H = 0CD, C = "0"

@02H

Register 02H = 03H, register 03H = 0DEH, C = "0"

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C

flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the

value 0CDH (11001101B) in destination register 00H.

6-79

INSTRUCTION SET

S3C80F9B/C80G9B

SRP/SRP0/SRP1 — Set Register Pointer

SRP

src

SRP0

SRP1

Operation:

If src (1) = 1 and src (0) = 0 then: RP0 (3–7)

←

src (3–7)

src (4–7),

0

If src (1) = 0 and src (0) = 1 then: RP1 (3–7)

If src (1) = 0 and src (0) = 0 then: RP0 (4–7)

RP0 (3)

RP1 (4–7)

RP1 (3)

src (4–7),

1

The source data bits one and zero (LSB) determine whether to write one or both of the register

pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register

pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

src

opc

src

2

4

31

IM

Examples:

The statement

SRP #40H

sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location

0D7H to 48H.

The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to

68H.

6-80

S3C80F9B/C80G9B

INSTRUCTION SET

STOP — Stop Operation

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the

microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,

peripheral registers, and I/O port control and data registers are retained. Stop mode can be

released by an external reset operation or by external interrupts. For the reset operation, the

RESET pin must be held to Low level until the required oscillation stabilization interval has

elapsed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

1

4

7F

–

Example:

The statement

STOP

halts all microcontroller operations.

6-81

INSTRUCTION SET

S3C80F9B/C80G9B

SUB — Subtract

SUB

dst,src

Operation:

dst ← dst – src

The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. Subtraction is performed by adding the

two's complement of the source operand to the destination operand.

Flags:

C: Set if a "borrow" occurred; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result is negative; cleared otherwise.

V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the

sign of the result is of the same as the sign of the source operand; cleared otherwise.

D: Always set to "1".

H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst |

src

2

4

6

22

r

23

r

lr

opc

src

dst

src

3

6

24

25

R

IR

6

26

R

IM

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

SUB

R1,R2

→

R1 = 0FH, R2 = 03H

R1,@R2

01H,02H

01H,@02H

01H,#90H

01H,#65H

R1 = 08H, R2 = 03H

Register 01H = 1EH, register 02H = 03H

Register 01H = 17H, register 02H = 03H

Register 01H = 91H; C, S, and V = "1"

Register 01H = 0BCH; C and S = "1", V = "0"

In the first example, if working register R1 contains the value 12H and if register R2 contains the

value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination

value (12H) and stores the result (0FH) in destination register R1.

6-82

S3C80F9B/C80G9B

INSTRUCTION SET

SWAP — Swap Nibbles

SWAP

dst

Operation:

dst (0 – 3) ↔ dst (4 – 7)

The contents of the lower four bits and upper four bits of the destination operand are swapped.

7

4 3

0

Flags:

C: Undefined.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Undefined.

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

2

4

F0

F1

R

IR

Examples:

Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:

SWAP

00H

→

Register 00H = 0E3H

@02H

Register 02H = 03H, register 03H = 4AH

In the first example, if general register 00H contains the value 3EH (00111110B), the statement

"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value

0E3H (11100011B).

6-83

INSTRUCTION SET

S3C80F9B/C80G9B

TCM — Test Complement Under Mask

TCM

dst,src

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask). The TCM statement complements the destination operand, which is then ANDed with the

source mask. The zero (Z) flag can then be checked to determine the result. The destination and

source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always cleared to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

62

63

r

lr

dst

src

3

6

64

65

R

IR

dst

6

66

R

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and

register 02H = 23H:

TCM

R0,R1

→

R0 = 0C7H, R1 = 02H, Z = "1"

R0,@R1

00H,01H

00H,@01H

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "1"

Register 00H = 2BH, register 01H = 02H,

register 02H = 23H, Z = "1"

TCM

00H,#34

→

Register 00H = 2BH, Z = "0"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register

for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one

and can be tested to determine the result of the TCM operation.

6-84

S3C80F9B/C80G9B

INSTRUCTION SET

TM — Test Under Mask

TM

dst,src

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand

(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to

determine the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

72

73

r

lr

dst

src

3

6

74

75

R

IR

dst

6

76

R

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and

register 02H = 23H:

TM

R0,R1

→

R0 = 0C7H, R1 = 02H, Z = "0"

R0,@R1

00H,01H

00H,@01H

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

Register 00H = 2BH, register 01H = 02H, Z = "0"

Register 00H = 2BH, register 01H = 02H,

register 02H = 23H, Z = "0"

TM

00H,#54H

→

Register 00H = 2BH, Z = "1"

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1

the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register

for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic

zero and can be tested to determine the result of the TM operation.

6-85

INSTRUCTION SET

S3C80F9B/C80G9B

WFI — Wait For Interrupt

WFI

Operation:

The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take

place during this wait state. The WFI status can be released by an internal interrupt, including a

fast interrupt .

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

1

4n

3F

( n = 1, 2, 3, ......)

Example:

The following sample program structure shows the sequence of operations that follow a "WFI"

statement:

Main program

.

EI

WFI

(Enable global interrupt)

(Wait for interrupt)

(Next instruction)

.

Interrupt occurs

Interrupt service routine

.

Clear interrupt flag

IRET

Service routine completed

6-86

S3C80F9B/C80G9B

INSTRUCTION SET

XOR — Logical Exclusive OR

XOR

dst,src

Operation:

dst ← dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is

stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever

the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C: Unaffected.

Z: Set if the result is "0"; cleared otherwise.

S: Set if the result bit 7 is set; cleared otherwise.

V: Always reset to "0".

D: Unaffected.

H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

src

opc

dst | src

src

2

4

6

B2

B3

r

lr

dst

src

3

6

B4

B5

R

IR

dst

6

B6

R

IM

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and

register 02H = 23H:

XOR

R0,R1

→

R0 = 0C5H, R1 = 02H

R0,@R1

00H,01H

00H,@01H

00H,#54H

R0 = 0E4H, R1 = 02H, register 02H = 23H

Register 00H = 29H, register 01H = 02H

Register 00H = 08H, register 01H = 02H, register 02H = 23H

Register 00H = 7FH

In the first example, if working register R0 contains the value 0C7H and if register R1 contains

the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0

value and stores the result (0C5H) in the destination register R0.

6-87

S3C80F9B/C80G9B

CLOCK CIRCUITS

7

CLOCK CIRCUITS

OVERVIEW

The clock frequency for the S3C80F9B/C80G9B can be generated by an external crystal, or supplied by an

external clock source. The clock frequency for the S3C80F9B can range from 1MHz to 8 MHz and for the

S3C80G9B can range from 1 MHz to 4 MHz. The maximum CPU clock frequency, as determined by CLKCON

register, is 8 MHz (for the S3C80F9B) and 4 MHz (for the S3C80G9B). The X_INand X_OUTpins connect the

external oscillator or clock source to the on-chip clock circuit.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal or ceramic resonator oscillation source (or an external clock)

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (f

divided by 1, 2, 8, or 16)

OSC

— Clock circuit control register, CLKCON

X

IN

C1

C2

XIN

External

Clock

Open Pin

XOUT

Figure 7-2. External Clock Circuit

Figure 7-1. Main Oscillator Circuit

(External Crystal or Ceramic Resonator)

7-1

CLOCK CIRCUITS

S3C80F9B/C80G9B

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator starts, by a Reset

operation or by an external interrupt. To enter the Stop mode, STOPCON (STOP Control register) has to be

loaded with value, #0A5H before STOP instruction execution. After recovering from the Stop mode by a reset

or an external interrupt, STOPCON register is automatically cleared.

— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the

interrupt structure, timer 0, timer 1, and counter A. Idle mode is released by a reset or by an interrupt

(external or internally generated).

STOP

Instruction

STOPCON

CLKCON.3, .4

Oscillator

Stop

1/2

1/8

M

U

X

Main

OSC

CPU

Clock

Oscillator

Wake-up

1/16

Noise

Filter

(1)

INT Pin

NOTES

1.

An external interrupt with an RC-delay noise filter (for the S3C80F9B/C80G9B

INT0-9) is fiexed to release Stop mode and "wake up" the main oscillator.

Because the S3C80F9B/C80G9B has no subsystem clock,

2.

the 3-bit CLKCON signature code (CLKCON.2-CLKCON.0) is no meaning.

Figure 7-3. System Clock Circuit Diagram

7-2

S3C80F9B/C80G9B

CLOCK CIRCUITS

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and

has the following functions:

— Oscillator frequency divide-by value

CLKCON register setting control whether or not an external interrupt can be used to trigger a Stop mode release.

(This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7.

In S3C80F9B/C80G9B, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in

S3C80F9B/C80G9B.

After a reset, the main oscillator is activated, and the f_OSC/16(the slowest clock speed) is selected as the CPU

clock. If necessary, you can then increase the CPU clock speed to f_OSC, f_OSC/2, or f_OSC/8

.

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

Divide-by selection bits

for CPU clock frequency

00 = fosc/16

Not used

01 = fosc/8

10 = fosc/2

11 = fosc (non-divided)

Figure 7-4. System Clock Control Register (CLKCON)

7-3

S3C80F9B/C80G9B

RESET AND POWER-DOWN 1 (S3C80F9B)

8

RESET and Power-Down 1 (S3C80F9B)

SYSTEM RESET

OVERVIEW

The interlocking work of nReset pin and LVD circuit supplies two operating modes: back-up mode input, and

system reset input. Back-up mode input automatically creates a chip stop state when the nReset pin is set to low

level or the voltage at V_DDis lower than V_LVD. When the nReset pin is at a high state and the LVD circuit detects

rising edge of V_DDon the point V_LVD, the Reset pulse generator makes a Reset pulse, and system Reset occurs.

System Reset pulse occurs by three sources - nReset pin, LVD circuit, and Basic Timer - as below.

1. The rising edge detection of LVD circuit while the rising slope of V_DDpass the voltage of V_LVD(Low level

Detect Voltage).

2. The Reset pulse generation by transiting of nReset pin to High level from Low level on the condition that V_DD

is higher level state than V_LVD(Low level Detect Voltage).

3. BT overflow for watch-dog timer. See the chapter 11. Basic Timer and Timer 0 for more understanding.

VDD

LVD

nRESET/

Back-up

mode

Back-up mode

System Reset

Noise

Filter

Rising Edge

Detector

Reset Pulse

Generator

fosc

BT (WDT)

Figure 8-1. Reset block diagram

8-1

RESET AND POWER-DOWN 1 (S3C80F9B

SYSTEM RESET BY LVD CIRCUIT

S3C80F9B/C80G9B

The Low Voltage detect circuit is built on the S3C80F9B product for system Reset and back-up mode. It detects a

falling/rising slope of V_DDby comparing the voltage at V_DDwith V_LVD(Low level Detect Voltage). The system

Reset pulse is generated by the rising slope of V_DD. While the voltage at V_DDis rising up and passing V_LVD, the

Reset pulse is occurred at the moment "V_DD≥ V_LVD". The other way, while the voltage at V_DDis falling down and

passing V_LVD, the chip go into back-up mode at the moment "V_DD= V_LVD".

SYSTEM RESET BY nRESET PIN

When the nReset pin transiting to V_IH(high input level of reset pin) from V_IL(low input level of reset pin), the

Reset pulse is generated on the condition of "V_DD≥ V_LVD"

WATCH-DOG TIMER RESET

The S3C80F9B build a watch-dog timer that can recover to normal operation from abnormal function. Watch-dog

timer generates a system Reset signal if not clearing a BT-Basic Counter within a specific time by program.

System Reset can return to the proper operation of chip. For more understanding of watch-dog timer function,

please see the chapter 11, Basic Timer and Timer0.

NOTE

The system Reset operation depends on the interlocking work of the nReset pin and LVD circuit. So if the

both Reset source is not the exact Reset condition at the same time, the system Reset is not occurred.

Refer to following table for more information.

Table 8-1. Reset Condition

Condition

Reset

System Reset

Slope of V_DD

V_DD

The voltage level of reset pin

(Vreset)

Source

Rising up from

V_DD< V_LVD

Vreset > V_IH

Vreset < V_IH

LVD circuit

System reset occurs

No system reset

V_DD≥ V_LVD

V_DD> V_LVD

–

V_DD< V_LVD

Transition from

“Vreset < V_IL” to “V_IH< Vreset”

V_DD> V_LVD

Standstill

Transition from

Reset pin

System reset occurs

(V_DD> V_LVD

)

“Vreset < V_IL” to “V_IH< Vreset”

8-2

S3C80F9B/C80G9B

RESET AND POWER-DOWN 1 (S3C80F9B)

SYSTEM RESET OPERATION

System Reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal

CPU and peripheral modules. This procedure brings the S3C80F9B into a known operating status. To allow time

for internal CPU clock oscillation to stabilize, the Reset pulse generator must be held to active level for a minimum

time interval after the power supply comes within tolerance. The minimum required Reset operation for a

oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are then Reset to

their default hardware values (see Tables 8-2).

In summary, the following sequence of events occurs during a Reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0, 1, 2 and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.

— Peripheral control and data register settings are disabled and reset to their default hardware values (see

Table 8-2).

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM

location 0100H (and 0101H) is fetched and executed.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the

basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic

timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can

disable it by writing '1010B' to the upper nibble of BTCON. But we recommend you should use it to

prevent the chip malfunction.

8-3

RESET AND POWER-DOWN 1 (S3C80F9B

HARDWARE RESET VALUES

S3C80F9B/C80G9B

Tables 8-2 list the reset values for CPU and system registers, peripheral control registers, and peripheral data

registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An 'x' means that the bit value is undefined after a reset.

— A dash ('–') means that the bit is either not used or not mapped (but a 0 is read from the bit position)

Table 8-2. Set 1 Register Values After Reset

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

7

0

1

0

x

6

0

1

0

x

5

0

1

0

x

4

0

1

0

x

3

0

1

0

x

2

0

1

0

x

−

1

0

1

0

−

0

1

0

−

Timer 0 counter (read-only)

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

208

209

210

211

212

213

214

215

1

0

1

Register pointer 1

RP1

Location D8H (SPH) is not mapped.

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register (read-only)

Interrupt mask register

SPL

IPH

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

x

0

x

0

x

0

x

–

0

–

0

x

0

x

–

0

x

0

x

0

x

0

x

0

1

0

x

0

x

0

1

0

x

0

x

0

x

0

x

0

IPL

IRQ

IMR

System mode register

SYM

PP

Register page pointer

Port 0 data register

P0

Port 1 data register

P1

Port 2 data register

P2

Port 3 data register

P3

Port 4 data register

P4

Port 2 interrupt enable register

Port 2 interrupt pending register

Port 0 pull-up enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

P2INT

P2PND

P0PUR

P0CONH

P0CONL

8-4

S3C80F9B/C80G9B

RESET AND POWER-DOWN 1 (S3C80F9B)

Table 8-2. Set 1 Register Values After Reset (Continued)

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

7

0

1

0

1

0

6

0

1

0

1

0

5

0

1

0

1

0

4

0

1

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 2 pull-up enable register

Port 3 control register

P1CONH

P1CONL

P2CONH

P2CONL

P2PUR

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

P3CON

Port 4 control register

P4CON

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

P0INT

P0PND

CACON

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

T1DATAL

T1CON

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)

Timer 1 control register

Stop control register

STOPCON 251

Locations FCH is not mapped.

Basic timer counter

BTCNT

EMT

253

254

255

FDH

FEH

FFH

x

0

x

1

x

1

x

1

x

1

x

1

x

0

x

-

External memory timing register

Interrupt priority register

IPR

x

NOTES:

1. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a 1 to this bit during

normal operation, a system malfunction may occur.

2. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are

read/write addressable.

3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.

4. Interrupt pending flags are noted by shaded table cells.

8-5

RESET AND POWER-DOWN 1 (S3C80F9B

S3C80F9B/C80G9B

POWER-DOWN MODES

BACK-UP MODE

For reducing current consumption, S3C80F9B goes into Back-up mode in related to nReset pin or LVD circuit.

While external nReset pin is low state or a falling slope of V_DDis detected by LVD circuit on the point of V_LVD, chip

changes to the back-up mode, where CPU and peripheral operation were stopped due to oscillation stop and the

supply current is reduced to less than 25 µA at 5.0 V. In back-up mode, chip can not release stop state by any

interrupt. The only way to release back-up mode is system Reset operation by interactive work of nReset pin and

LVD circuit. The system Reset of watch dog timer is not occurred in back up mode.

VDD

LVD

Back-up mode

System Reset

nRESET/

Back-up mode

NF

Figure 8-2. Block Diagram for Back-up Mode

Voltage [V]

Slope of RESET &

VDD pin

VDD

Rising edge detected

(VDD >= VLVD)

VLVD

Low level

Reset Pulse generated,

oscillation starts

detect voltage

Falling edge detected,

oscillation stop.

(VDD < VLVD)

Normal Operation

Back up Mode

Normal Operation

NOTES:

1, When the rising edge is detected by LVD circuit, Back-up mode is relesase (VLVD =< VDD)

2. When the falling edge is detected by LVD circuit, Back-up mode is activated (VLVD > VDD)

Figure 8-3. Timing Diagram for Back-up Mode Input and Release by LVD

8-6

S3C80F9B/C80G9B

Stop Mode

RESET AND POWER-DOWN 1 (S3C80F9B)

Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the

operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current

is reduced to less than 25 µA at 5.0 V. All system functions stop when the clock "freezes," but data stored in the

internal register file is retained. Stop mode can be released in one of two ways: by a system reset or by an

external interrupt.

After releasing from STOP mode, the value of stop control register (STOPCON) is cleared automatically.

)

PROGRAMMING TIP - To enter STOP mode.

This example shows how to enter the stop mode.

ORG

0000H

; Reset address

•

JP

T,START

ENTER_STOP:

LD

STOPCON,#0A5H

STOP

NOP

RET

ORG

JP

0100H-3

T,START

ORG

0100H

; Reset address

START

MAIN

LD

•

BTCON,#03

; clear basic timer counter.

NOP

•

CALL

ENTER_STOP

; Enter the STOP mode

•

LD

JP

BTCON,#02H

T,MAIN

; clear basic timer counter.

•

8-7

RESET AND POWER-DOWN 1 (S3C80F9B

S3C80F9B/C80G9B

Using system Reset to Release Stop Mode

Stop mode is released when the Reset signal goes active by LVD circuit or nReset pin: all system and peripheral

control registers are Reset to their default hardware values and the contents of all data registers are retained.

When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization

routine by fetching the program instruction stored in ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. For the S3C80F9B

microcontroller, we recommend using the INT0-9 interrupt at P0 and P2.

Please note the following conditions for Stop mode release:

— If you release Stop mode using an external interrupt, the current values in system and peripheral control

registers are unchanged.

— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation

stabilization interval. To do this, you must make the appropriate control and clock settings before entering

Stop mode.

— If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains

unchanged and the currently selected clock value is used.

The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service

routine, the instruction immediately following the one that initiated Stop mode is executed.

Using a SED & R (Stop Error Detect and Recovery )to Release Stop Mode

The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that

can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2. One is

releasing from stop status by switching the level of input port (P0 or P2) and the other is keeping the chip from the

stop mode when the chip is in abnormal status.

•

Releasing from stop mode

When the level of a pin on Port0 and Port2 is switching, the chip is released from stop mode even though external

interrupt is disabled.

•

Keeping the chip from entering abnormal - stop mode

This circuit detects the abnormal status by checking the port (P0 and P2) status. If the chip is in abnormal status it

keeps from entering stop mode.

NOTE

Do not use stop mode if you are using an external clock source because X_ininput must be cleared

internally to V_SSto reduce current leakage.

8-8

S3C80F9B/C80G9B

IDLE MODE

RESET AND POWER-DOWN 1 (S3C80F9B)

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some

peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but

the following peripherals, which remain active:

— Interrupt logic

— Timer 0

— Timer 1

— Counter A

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

1. Execute a Reset. All system and peripheral control registers are reset to their default values and the contents

of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the

hardware reset value for the CLKCON register. If all interrupts are masked in the IMR register, a reset is the

only way you can release Idle mode.

2. Activate any enabled interrupt; internal or external. When you use an interrupt to release Idle mode, the 2-bit

CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The

interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately

following the one which initiated Idle mode is executed.

NOTE

Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode. To

release Idle mode, you can use either an external interrupt or an internally-generated interrupt.

8-9

RESET AND POWER-DOWN 1 (S3C80F9B

S3C80F9B/C80G9B

RECOMMENDATION FOR UNUSUED PINS

To reduce overall power consumption, please configure unused pins according to the guideline description Table

8-3.

Table 8-3. Guideline for Unused Pins to Reduced Power Consumption.

Pin Name

Recommend

• Set Input mode

• Enable Pull-up Resister

• No Connection for Pins

Example

Port 0

• P0CONH ← # 00H or 0FFH

• P0CONL ← # 00H or 0FFH

• P0PUR ← # 0FFH

Port 1

• Set Open-Drain Output mode

• Set P1 Data Register to #00H.

• Disable Pull-up Resister

• P1CONH ← # 55H

• P1CONL ← # 55H

• P1

← # 00H

• No Connection for Pins

Port 2

• Set Push-pull Output mode

• Set P2 Data Register to #00H.

• Disable Pull-up resister

• P2CONH ← # 0AAH

• P2CONL ← # 0AAH

• P2

← # 00H

• No Connection for Pins

• P2PUR ← # 00H

P3.0–3.1

• Set Push-pull Output mode

• Set P3 Data Register to #00H.

• No Connection for Pins

• P3CON ← # 11010010B

• P3

← # 00H

P3.2– P3.3

P3.4–P3.5

–

• No connection

• Set P3 Data Register to #00H.

• P3

← # 00H

Port 4

TEST

• Set Push-pull Output mode

• Set P4 Data Register to #00H.

• P4CON ← # 0FFH

• P4

← # 00H

• Connect to Vss.

–

8-10

S3C80F9B/C80G9B

RESET AND POWER-DOWN 1 (S3C80F9B)

SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND, RESET STATUS

For more understanding, please see the below description Table 8-4.

Table 8-4. Summary of Each Mode.

Item/Mode

Back-up

Reset status

Stop

Approach

Condition

• External nReset pin is low

level state or V^DDis lower

than V_LVD

• External nReset pin is on rising

edge.

• The rising edge at V_DDis

• STOPCON ← # A5H

STOP

( LD STOPCON,#0A5H

STOP)

detected by LVD circuit.

(When V_DD≥ V_LVD

)

• WDT overflow signal is

activated.

PORT

status

• All I/O port is floating status

except P3.2 and P3.3

• All I/O port is floating status

except P3.2 and P3.3

• All port is keep the previous

status.

• All port becomes input mode • Disable all pull-up resister

• Input port data is not

changed.

but is blocked.

except P3.2 and P3.3

• Disable all pull-up resister

except P3.2 and P3.3

Control

Register

• All control register and

system register are

initialized as list of Table 8-2

• All control register and system

register are initialized as list of

Table 8-2.

–

Releasing

Condition

• External nReset pin is high

(Rising edge)

• After passing an oscillation

warm-up time

• External interrupt, or Reset

• SED & R Circuit.

• The rising edge of LVD

circuit is generated.

Others

• There is no current

• There can be input leakage

• It depend on control

consumption in chip.

current in chip.

program

8-11

S3C80F9B/C80G9B

RESET and POWER-DOWN 2

9

RESET and Power-Down 2 (S3C80G9B)

SYSTEM RESET

OVERVIEW

The interlocking work of nReset pin and LVD circuit supplies two operating modes: back-up mode input, and

system Reset input. Back-up mode input automatically creates a chip stop state when the nReset pin is set to low

level or the voltage at V_DDis lower than V_LVD. When the nReset pin is at a high state and the LVD circuit detects

rising edge of V_DDon the point V_LVD, the Reset pulse generator makes a reset pulse, and system Reset occurs.

When the operating mode is in “STOP mode”, the LVD circuit is disabled to reduce the current consumption under

6uA instead of 25uA (at V_DD= 5.0 V). Therefor, although the voltage at V_DDis lower than V_LVD, the chip doesn’t

go into back-up mode when the operating state is in stop mode and nReset pin is High level (Vreset > V_IH).

The S3C80G9B has four different system reset sources as following:

1. Not in stop mode, the rising edge detection of LVD circuit while the rising slope of V_DDpass the voltage of

V_LVD(Low level Detect Voltage).

2. The Reset pulse generation by transiting of nReset pin to High level from Low level on the condition that V_DD

is higher level state than V_LVD(Low level Detect Voltage).

3. Internal Power-on Reset

4. BT overflow for watchdog timer. See the chapter 11. Basic Timer and Timer 0 for more understanding.

9-1

RESET and POWER-DOWN 2

S3C80F9B/C80G9B

Enable/Disable

VDD

LVD

STOP

STOPCON

nRESET/

Back-up

Mode

Back-up mode

System Reset

Noise

Filter

Rising Edge

Detector

Reset Pulse

Generator

Internal POR

fosc

BT (WDT)

Figure 9-1 Reset block diagram For the S3C80G9B

SYSTEM RESET BY LVD CIRCUIT

The Low Voltage detect circuit is built on the S3C80G9B product to generate a system Reset when the operating

state is not in stop mode. When the operating status is not stop mode it detects a slope of V_DDby comparing the

voltage at V_DDwith V_LVD(Low level Detect Voltage). The system Reset pulse is generated by the rising slope of

V_DD. While the voltage at V_DDis rising up and passing V_LVD, the Reset pulse is occurred at the moment “V_DD≥

V_LVD“. The other way, while the voltage at V_DDis falling down and passing V_LVD, the chip go into back-up mode

at the moment “V_DD= V_LVD”. This function is disabled when the operating state is “STOP mode” to reduce the

current consumption under 6uA instead of 25uA (at V_DD= 5.0V).

SYSTEM RESET BY nRESET PIN

When the nReset pin transiting to V_IH(high input level of nReset pin) from VIL (low input level of reset pin), the

reset pulse is generated on the condition of “V_DD≥ V_LVD“.

WATCH-DOG TIMER RESET

The S3C80G9B build a watchdog timer that can recover to normal operation from abnormal function. Watchdog

timer generates a system reset signal if not clearing a BT-Basic Counter within a specific time by program.

System reset can return to the proper operation of chip. For more understanding of watchdog timer function,

please see the chapter 11, Basic Timer and Timer0.

9-2

S3C80F9B/C80G9B

RESET and POWER-DOWN 2

INTERNAL POWER-ON RESET

The power-on reset circuit is built on the S3C80G9B product. During a power-on Reset, the voltage at V_DDgoes to

High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High level. The power-on

Reset circuit makes a Reset signal whenever the power supply voltage is powering-up and the Schmitt trigger

input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal capacitor, and a

Schmitt trigger input transistor.

VDD

R: On-Chip Resistor

C: On-Chip Capacitor

System Reset

C

Schmitt Trigger Inverter

VSS

Figure 9-2. Power-on reset Circuit

TVDD

(VDD Rising Time)

Voltage [V]

VDD

Va

VIH = 0.85 VDD

VIL = 0.4 VDD

Reset Pulse Width

Reset pulse

Time

If Va voltage(schmitt trigger input voltage) is under the 0.4VDD, Reset pulse signal is gernerated.

If Va voltage(schmitt trigger input voltage) is over than 0.4VDD, Reset pulse is not gernerated.

Figure 9-3. Timing Diagram for Power-on Reset Circuit

9-3

RESET and POWER-DOWN 2

S3C80F9B/C80G9B

NOTE

The system Reset operation depends on the interlocking work of the nReset pin, LVD circuit and Internal

POR. The LVD circuit is disabled when the operating mod is in stop mode. So although the voltage at V_DD

is rising up and passing V_LVD, the system reset by LVD circuit is not occurs in stop mode.

Refer to following table and figure for more information.

Table 9-1. Reset Condition not in STOP mode

Condition

The voltage level of reset pin

(Vreset)

Reset

System Reset

Slope of V_DD

V_DD

Source

Vreset > V_IH

Vreset < V_IH

Rising up from

V_DD< V_LVD

LVD circuit

System Reset occurs

No system Reset

V_DD≥ V_LVD

V_DD> V_LVD

V_DD< V_LVD

–

Transition from

“Vreset < V_IL” to “V_IH< Vreset”

V_DD> V_LVD

Standstill

Transition from

nReset pin

System Reset occurs

“Vreset < V_IL” to “V_IH< Vreset”

(V_DD> V_LVD

)

Table 9-2. Reset Condition in STOP mode

Condition Reset

System Reset

Slope of V_DD

V_DD

The voltage level of reset pin

(Vreset)

Source

Vreset > V_IH

Rising up from

No system Reset

V_DD≥ V_LVD

−

0.4 V_DD< V_DD

V_LVD

<

V_DD> V_LVDVreset < V_IH

–

No system Reset

V_DD< V_LVD

Transition from

“Vreset < V_IL” to “V_IH< Vreset”

Vreset > V_IH

Rising up from

V_DD< 0.4V_DD

Internal POR System Reset occurs

V_DD≥ V_LVD

V_DD> V_LVDVreset < V_IH

No system Reset

−

V_DD< V_LVD

Transition from

“Vreset < V_IL” to “V_IH< Vreset”

V_DD> V_LVD

Standstill

Transition from

“Vreset < V_IL” to “V_IH< Vreset”

nReset pin

System Reset occurs

(V_DD> V_LVD

)

9-4

S3C80F9B/C80G9B

RESET and POWER-DOWN 2

When "Vreset > VIH" and the operating status is in STOP mode, LVD circuit is disabled in the

S3C80G9B.

VDD

a

0.85VDD

VLVD

b

Va

b

c

Va

c

0.4VDD

Reset Pulse Width

RAM Retention

Voltage

NOTE:

Va is a schmitt trigger input signal of internal Power-on reset

a. System reset is not occurs, RAM data is retentioned

b. System reset is occurs by internal POR circuit, RAM data is retentioned.

c. System reset is occurs by internal POR circuit, RAM data is not retentioned.

Figure 9-4. Reset Timing Diagram for the S3C80G9B in STOP mode

9-5

RESET and POWER-DOWN 2

SYSTEM RESET OPERATION

S3C80F9B/C80G9B

System Reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal

CPU and peripheral modules. This procedure brings the S3C80G9B into a known operating status. To allow time

for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum

time interval after the power supply comes within tolerance. The minimum required Reset operation for a

oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are then Reset to

their default hardware values (see Tables 9-3).

In summary, the following sequence of events occurs during a Reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0, 1, 2 and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.

— Peripheral control and data register settings are disabled and reset to their default hardware values (see

Table 9-3).

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM

location 0100H (and 0101H) is fetched and executed.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the

basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic

timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can

disable it by writing '1010B' to the upper nibble of BTCON. But we recommend you should use it to

prevent the chip malfunction.

9-6

S3C80F9B/C80G9B

RESET and POWER-DOWN 2

HARDWARE RESET VALUES

Tables 9-3 list the Reset values for CPU and system registers, peripheral control registers, and peripheral data

registers following a reset operation. The following notation is used to represent Reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An 'x' means that the bit value is undefined after a reset.

— A dash ('–') means that the bit is either not used or not mapped (but a 0 is read from the bit position)

Table 9-3. Set 1 Register Values After Reset

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

7

0

1

0

x

6

0

1

0

x

5

0

1

0

x

4

0

1

0

x

3

0

1

0

x

2

0

1

0

x

−

1

0

1

0

−

0

1

0

−

Timer 0 counter (read-only)

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

208

209

210

211

212

213

214

215

1

0

1

Register pointer 1

RP1

Location D8H (SPH) is not mapped.

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register (read-only)

Interrupt mask register

SPL

IPH

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

x

0

x

0

x

0

x

–

0

–

0

x

0

x

–

0

x

0

x

0

x

0

x

0

1

0

x

0

x

0

1

0

x

0

x

0

x

0

x

0

IPL

IRQ

IMR

System mode register

SYM

PP

Register page pointer

Port 0 data register

P0

Port 1 data register

P1

Port 2 data register

P2

Port 3 data register

P3

Port 4 data register

P4

Port 2 interrupt enable register

Port 2 interrupt pending register

Port 0 pull-up enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

P2INT

P2PND

P0PUR

P0CONH

P0CONL

9-7

RESET and POWER-DOWN 2

S3C80F9B/C80G9B

Table 9-3. Set 1 Register Values After Reset (Continued)

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

7

0

1

0

1

0

6

0

1

0

1

0

5

0

1

0

1

0

4

0

1

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 2 pull-up enable register

Port 3 control register

P1CONH

P1CONL

P2CONH

P2CONL

P2PUR

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

P3CON

Port 4 control register

P4CON

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

P0INT

P0PND

CACON

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

T1DATAL

T1CON

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)

Timer 1 control register

Stop control register

STOPCON

Locations FCH is not mapped.

Basic timer counter

BTCNT

EMT

253

254

255

FDH

FEH

FFH

x

0

x

1

x

1

x

1

x

1

x

1

x

0

x

-

External memory timing register

Interrupt priority register

IPR

x

NOTES:

1. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a 1 to this bit during normal

operation, a system malfunction may occur.

2. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are

read/write addressable.

3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.

4. Interrupt pending flags are noted by shaded table cells.

9-8

S3C80F9B/C80G9B

RESET and POWER-DOWN 2

POWER-DOWN MODES

BACK-UP MODE

For reducing current consumption, S3C80G9B goes into Back-up mode in related to nReset pin or LVD circuit.

While external nReset pin is low state or a falling slope of V_DDis detected by LVD circuit on the point of V_LVD, chip

changes to the back-up mode, where CPU and peripheral operation were stopped due to oscillation stop and the

supply current is reduced to less than 25 µA at 5.0 V.

When the operating mode is in “STOP mode”, the LVD circuit is disabled to reduce the current consumption under

6uA instead of 25uA (at V_DD= 5.0 V). Therefor, although the voltage at V_DDis lower than V_LVD, the chip doesn’t

go into back-up mode when the operating state is in stop mode and nReset pin is High level (Vreset > V_IH).

In back-up mode, chip can not release stop state by any interrupt. The only way to release back-up mode is

system Reset operation by interactive work of nReset pin and LVD circuit. The system Reset of watchdog timer is

not occurred in back up mode.

Enable/Disable

VDD

LVD

Stop

Back-up mode

System Reset

STOPCON

nRESET/

Back-up mode

NF

Figure 9-5. Block diagram for Back-up mode in the S3C80G9B

9-9

RESET and POWER-DOWN 2

S3C80F9B/C80G9B

Voltage [V]

VDD

Slope of RESET &

VDD pin

Rising edge detected

(VDD >= VLVD)

VLVD

Low level

Reset Pulse generated,

oscillation starts

detect voltage

Falling edge detected,

oscillation stop.

(VDD < VLVD)

Normal Operation

Back up Mode

Normal Operation

NOTES:

1. In the S3C80G9B, the LVD cricuit is disabled when the operating state is in stop mode.

2. When the rising edge is detected by LVD circuit, Back-up mode is relesase (VLVD =< VDD)

3. When the falling edge is detected by LVD circuit, Back-up mode is activated (VLVD > VDD)

Figure 9-6. Timing Diagram For Back-Up Mode Input And Release by LVD

9-10

S3C80F9B/C80G9B

STOP MODE

RESET and POWER-DOWN 2

Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the

operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current

is reduced to less than 6 µA at 5.0 V. All system functions stop when the clock "freezes," but data stored in the

internal register file is retained. Stop mode can be released in one of two ways: by a system reset or by an

external interrupt.

After releasing from STOP mode, the value of stop control register (STOPCON) is cleared automatically.

)

PROGRAMMING TIP – To enter STOP mode

This example shows how to enter the stop mode.

ORG

0000H

; Reset address

•

JP

T,START

ENTER_STOP:

LD

STOPCON,#0A5H

STOP

NOP

RET

ORG

JP

0100H-3

T,START

ORG

0100H

; Reset address

START

MAIN

LD

•

BTCON,#03

; clear basic timer counter.

NOP

•

CALL

ENTER_STOP

; Enter the STOP mode

•

LD

JP

BTCON,#02H

T,MAIN

; clear basic timer counter.

•

9-11

RESET and POWER-DOWN 2

S3C80F9B/C80G9B

SOURCES TO RELEASE STOP MODE

Stop mode is released when following sources go active:

— System Reset by reset pin

— System Reset by internal POR

— External Interrupt

— SED & R circuit

Using nReset pin to Release Stop Mode

Stop mode is released when the system reset signal goes active by reset pin: all system and peripheral control

registers are reset to their default hardware values and the contents of all data registers are retained. When the

oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the

program instruction stored in ROM location 0100H.

Using POR to Release Stop Mode

Stop mode is released when the system Reset signal goes active by Power-on Reset (POR): all system and

peripheral control registers are Reset to their default hardware values and contents of all data registers are

unknown states. When the oscillation stabilization interval has elapsed, the CPU starts the system initialization

routine by fetching the program instruction stored in ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. For the S3C80G9B

microcontroller, we recommend using the INT0-9 interrupt at P0 and P2.

Please note the following conditions for Stop mode release:

— If you release Stop mode using an external interrupt, the current values in system and peripheral control

registers are unchanged.

— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation

stabilization interval. To do this, you must make the appropriate control and clock settings before entering

Stop mode.

— If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains

unchanged and the currently selected clock value is used.

The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service

routine, the instruction immediately following the one that initiated Stop mode is executed.

Using a SED & R (Stop Error Detect and Recovery )to Release Stop Mode

The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that

can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2. One is

releasing from stop status by switching the level of input port (P0 or P2) and the other is keeping the chip from the

stop mode when the chip is in abnormal status.

— Releasing from stop mode

When the level of a pin on Port0 and Port2 is switching, the chip is released from stop mode even though external

interrupt is disabled.

— Keeping the chip from entering abnormal - stop mode

This circuit detects the abnormal status by checking the port (P0 and P2) status. If the chip is in abnormal status it

keeps from entering stop mode.

NOTE

Do not use stop mode if you are using an external clock source because Xin input must be cleared

internally to V_SSto reduce current leakage.

9-12

S3C80F9B/C80G9B

IDLE MODE

RESET and POWER-DOWN 2

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some

peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but

the following peripherals, which remain active:

— Interrupt logic

— Timer 0

— Timer 1

— Counter A

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

1. Execute a reset. All system and peripheral control registers are reset to their default values. The reset

automatically selects the slowest clock (1/16) because of the hardware reset value for the CLKCON register.

If all interrupts are masked in the IMR register, a reset is the only way you can release Idle mode.

2. Activate any enabled interrupt; internal or external. When you use an interrupt to release Idle mode, the 2-bit

CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The

interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately

following the one which initiated Idle mode is executed.

NOTE

Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode. To

release Idle mode, you can use either an external interrupt or an internally-generated interrupt.

9-13

RESET and POWER-DOWN 2

S3C80F9B/C80G9B

RECOMMENDATION FOR UNUSUED PINS

To reduce overall power consumption, please configure unused pins according to the guideline description Table

9-4.

Table 9-4. Guideline for Unused Pins to Reduced Power Consumption.

Pin Name

Port 0

Recommend

• Set Input mode

• Enable Pull-up Resister

• No Connection for Pins

Example

• P0CONH ← # 00H or 0FFH

• P0CONL ← # 00H or 0FFH

• P0PUR ← # 0FFH

Port 1

• Set Open-Drain Output mode

• Set P1 Data Register to #00H.

• Disable Pull-up Resister

• P1CONH ← # 55H

• P1CONL ← # 55H

• P1 ← # 00H

• No Connection for Pins

Port 2

• Set Push-pull Output mode

• Set P2 Data Register to #00H.

• Disable Pull-up resister

• P2CONH ← # 0AAH

• P2CONL ← # 0AAH

• P2 ← # 00H

• No Connection for Pins

• P2PUR ← # 00H

P3.0–3.1

• Set Push-pull Output mode

• Set P3 Data Register to #00H.

• No Connection for Pins

• P3CON ← # 11010010B

• P3 ← # 00H

P3.2–3.3

P3.4–3.5

–

• No connection

• P3 ← # 00H

• Set P3 Data Register to #00H.

Port 4

TEST

• Set Push-pull Output mode

• Set P4 Data Register to #00H.

• P4CON ← # 0FFH

• P4 ← # 00H

• Connect to Vss.

–

9-14

S3C80F9B/C80G9B

RESET and POWER-DOWN 2

SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS

For more understanding, please see the below description Table 9-5.

Table 9-5. Summary of Each Mode.

Item/Mode

Back-up

Reset status

Stop

Approach

Condition

• External reset pin is low

level state

• External reset pin is on rising

edge.

• STOPCON ← # A5H

STOP

• V^DDis lower than V_LVD

when the operating state is

not in Stop mode

• The rising edge at V^DDis

detected by LVD circuit not in

Stop mode.

( LD STOPCON,#0A5H

STOP)

(When V_DD≥ V_LVD

)

• Internal Power-on reset

• WDT overflow signal is

activated

PORT

status

• All I/O port is floating status

except P3.2 and P3.3

• All port becomes input mode

but is blocked.

• All I/O port is floating status

except P3.2 and P3.3

• Disable all pull-up resister

except P3.2 and P3.3

• All port is keep the

previous status.

• Input port data is not

changed.

• Disable all pull-up resister

except P3.2 and P3.3

Control

Register

• All control register and

system register are initialized

as list of Table 9-3

• All control register and system

register are initialized as list of

Table 9-3.

–

Releasing

Condition

• External reset pin is high

(Rising edge)

• The rising edge of LVD

circuit is generated

• After passing an oscillation

warm-up time

• External interrupt

• SED & R Circuit.

• Internal Power-on reset

• System reset by reset

Others

• There is no current

• There can be input leakage

• It depend on control

consumption in chip.

current in chip.

program

9-15

S3C80F9B/C80G9B

I/O PORTS

10 I/O PORTS

OVERVIEW

The S3C80F9B/C80G9B microcontroller has three kinds of package and different I/O number relating to the

package type:

48-ELP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports

and P3 is a 6-bit port. 4 pins(12,24,36,48) are not used. This gives a total of 38 I/O pins.

44-QFP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports

and P3 is a 6-bit port. This gives a total of 38 I/O pins.

42-SDIP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports

and P3 is a 4-bit port. This gives a total of 36 I/O pins.

32-SOP package has four bit-programmable I/O ports, P0–P3. three ports, P0–P2, are 8-bit ports and P3 is a 2-bit

port. This gives a total of 26 I/O pins.

28-SOP package has four bit-programmable I/O ports, P0–P3. three ports, P0–P1, are 8-bit ports, P2 is 4-bit ports

and P3 is a 2-bit port. This gives a total of 22 I/O pins..

Each port is bit-programmable and can be flexibly configured to meet application design requirements. The CPU

accesses ports by directly writing or reading port registers. No special I/O instructions are required.

For IR applications, ports 0, 1, and 2 are usually configured to the keyboard matrix and port 3 is used to IR drive

pins.

Table 10-1,10-2 and 10-3 give you a general overview of S3C80F9B/C80G9B I/O port functions.

10-1

I/O PORTS

S3C80F9B/C80G9B

Table 10-1. S3C80F9B/C80G9B Port Configuration Overview (44-QFP/48ELP)

Port

Configuration Options

0

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges,

rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable

(P0INT) and pending control (P0PND); Pull-up resistors can be assigned to individual P0 pins

using P0PUR register settings. This port is dedicated for key input in IR controller application.

1

2

8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull

output. This port is dedicated for key output in IR controller application.

8-bit general-purpose I/O port; Input or push-pull output. The P2 pins, P2.0–P2.7, can be used

as external interrupt inputs and have noise filters. The P2INT register is used to enable/disable

interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up

resistors can be assigned to individual P2 pins using P2PUR register settings.

P3.0–P3.1

P3.2–P3.3

P3.0 is configured input functions (Input mode, with or without pull-up, for normal input or

T0CAP) or output functions (push-pull or open-drain output mode, for normal output or

T0PWM). P3.1 is configured input functions (Input mode, with or without pull-up, for normal

input) or output functions (push-pull or open-drain output mode, for normal output or REM

function). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED drive.

P3.2 is configured only input with pull-up mode(for normal input or T0CK function). P3.3 is

configured only input with pull-up mode (for normal input or T1CAP function). P3.3 can be used

for IR signal capture pin with T1CAP function.

P3.4–P3.5

P3.4–P3.5 are configured only open-drain output mode.

P3.7

4

P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.

Port 4 is configured for output only (push-pull or open-drain output mode). It can be used for key

output pins.

10-2

S3C80F9B/C80G9B

I/O PORTS

Table 10-2. S3C80F9B/C80G9B Port Configuration Overview (42-SDIP)

Configuration Options

Port

0

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges,

rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable

(P0INT) and pending control (P0PND); Pull-up resistors can be assigned to individual P0 pins

using P0PUR register settings. This port is dedicated for key input in IR controller application.

1

2

8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull

output. This port is dedicated for key output in IR controller application.

8-bit general-purpose I/O port; Input, or push-pull output. The P2 pins, P2.0–P2.7, can be used

as external interrupt inputs and have noise filters. The P2INT register is used to enable/disable

interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up

resistors can be assigned to individual P2 pins using P2PUR register settings.

P3.0–P3.1

P3.2–P3.3

P3.0 is configured input functions (Input mode, with or without pull-up, for normal input or

T0CAP) or output functions (push-pull or open-drain output mode, for normal output or

T0PWM). P3.1 is configured input functions (Input mode, with or without pull-up, for normal

input) or output functions (push-pull or open-drain output mode, for normal output or REM

function). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED drive.

P3.2 is configured only input with pull-up mode(for normal input or T0CK function). P3.3 is

configured only input with pull-up mode(for normal input or T1CAP function). P3.3 can be used

for IR signal capture pin with T1CAP function.

P3.7

4

P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.

Port 4 is configured for output only(push-pull or open-drain output mode). It can be used for key

output pins.

10-3

I/O PORTS

S3C80F9B/C80G9B

Table 10-3. S3C80F9B/C80G9B Port Configuration Overview (32-SOP)

Configuration Options

Port

0

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges,

rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable

(P0INT) and pending control (P0PND); Pull-up resistors can be assigned to individual P0 pins

using P0PUR register settings. This port is dedicated for key input in IR controller application.

1

2

8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull

output. This port is dedicated for key output in IR controller application.

8-bit general-purpose I/O port; Input, or push-pull output. The P2 pins, P2.0–P2.7, can be used

as external interrupt inputs and have noise filters. The P2INT register is used to enable/disable

interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up

resistors can be assigned to individual P2 pins using P2PUR register settings.

P3.0–P3.1

P3.7

2-bit I/O port; P3.0 and P3.1 are configured input functions (Input mode, with or without pull-up,

for T0CK, T0CAP or T1CAP) or output functions (push-pull or open-drain output mode, or for

REM and T0PWM). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED

drive.

P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.

Table 10-4. S3C80G9B Port Configuration Overview (28-SOP)

Configuration Options

Port

0

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling

edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt

enable/disable (P0INT) and pending control (P0PND); Pull-up resistors can be assigned to

individual P0 pins using P0PUR register settings. This port is dedicated for key input in IR

controller application.

1

2

8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull

output. This port is dedicated for key output in IR controller application.

4-bit general-purpose I/O port; Input, or push-pull output. The P2 pins, P2.0–P2.4, can be used

as external interrupt inputs and have noise filters. The P2INT register is used to enable/disable

interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up

resistors can be assigned to individual P2 pins using P2PUR register settings.

P3.0–P3.1

P3.7

2-bit I/O port; P3.0 and P3.1 are configured input functions (Input mode, with or without pull-up,

for T0CK, T0CAP or T1CAP) or output functions (push-pull or open-drain output mode, or for

REM and T0PWM). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED

drive.

P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.

10-4

S3C80F9B/C80G9B

I/O PORTS

PORT DATA REGISTERS

Table 10-4 gives you an overview of the register locations of all four S3C80F9B/C80G9B I/O port data registers.

Data registers for ports 0,1,2 and 4 have the general format shown in Figure 10-1.

NOTE

The data register for port 3, P3, contains 6-bits for P3.0–P3.5, and an additional status bit (P3.7) for

carrier signal on/off.

Table 10-5. Port Data Register Summary

Register Name

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Mnemonic

Decimal

224

Hex

E0H

E1H

E2H

E3H

E4H

Location

Set 1

R/W

P0

P1

P2

P3

P4

225

Set 1

226

Set 1

227

Set 1

228

Set 1

Because port 3 is a 6–bit I/O port, the port 3 data register only contains values for P3.0 – P3.5. The P3 register

also contains a special carrier on/off bit (P3.7). See the port 3 description for details. All other S3C80F9B/C80G9B

I/O ports are 8–bit.

S3C80F9B/C80G9B I/O Port Data Register Format (n = 0-4)

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pn.7

NOTE: Because port 3 is a 6-bit I/O port, the port 3 data

register only contains values for P3.0-P3.5.

The P3 register also contains a special carrier on/off bit

(P3.7). See the port 3 description for details.

All other S3C80F9B/C80G9B I/O ports are 8-bit.

Figure 10-1. S3C80F9B/C80G9B I/O Port Data Register Format

10-5

I/O PORTS

S3C80F9B/C80G9B

PULL-UP RESISTOR ENABLE REGISTERS

You can assign pull-up resistors to the pin circuits of individual pins in ports 0 and 2. To do this, you make the

appropriate settings to the corresponding pull-up resistor enable registers- P0PUR and P2PUR. These registers

are located in set 1 at locations E7H and EEH, respectively, and are read/write accessible using Register

addressing mode.

You can assign a pull-up to the port 1 pins, using basic port configuration setting in the P1CONH and P1CONL.

You can assign a pull-up to the port 3 pins, P3.0 and P3.1, in Input mode using basic port configuration setting in

the P3CON register.

P3.2–P3.3 is configured input with pull-up only pins.

Pull-up Register Enable Registers (PnPUR, where n = 0,2)

(Set 1, E7H, EEH), R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pull-up resistor enable bit:

0 = Disable pull-up resistor

1 = Enable pull-up resistor

Pn.7

NOTES:

1. Pull-up resistors can be assigned to the port 3 pins, P3.0 and P3.1,

by making the appropriate setting the port 3 control register P3CON.

2. Pull-up resistors can be assigned to the P1 pins, by making the

appropriate setting the port 1 control register P1CONL and P1CONH.

Figure 10-2. Pull-up Resistor Enable Registers (Ports 0 and 2 only)

10-6

S3C80F9B/C80G9B

BASIC TIMER and TIMER 0

11 BASIC TIMER and TIMER 0

MODULE OVERVIEW

The S3C80F9B/C80G9B has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter.

The 8-bit timer/counter is called timer 0.

BASIC TIMER (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic Reset mechanism in the event of a system malfunction, or

— To signal the end of the required oscillation stabilization interval after a Reset or a Stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (f

OSC

divided by 4096, 1024 or 128) with multiplexer

— 8-bit basic timer counter, BTCNT (set 1, FDH, read-only)

— Basic timer control register, BTCON (set 1, D3H, read/write)

TIMER 0

Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting:

— Interval timer mode

— Capture input mode with a rising or falling edge trigger at the P3.0 pin

— PWM mode

Timer 0 has the following functional components:

— Clock frequency divider (f

divided by 4096, 256 or 8 ) with multiplexer

— External clock input pin (T0CK)

OSC

— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)

— I/O pins for capture input (T0CAP) or match output

— Timer 0 overflow interrupt (IRQ1, vector FAH) and match/capture interrupt (IRQ1, vector FCH) generation

— Timer 0 control register, T0CON (set 1, D2H, read/write)

11-1

BASIC TIMER and TIMER 0

S3C80F9B/C80G9B

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer

counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,

address D3H, and is read/write addressable using Register addressing mode.

A Reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of

fOSC/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer

register control bits BTCON.7–BTCON.4. For improved reliability, using the Watch-dog timer function is

recommended in remote controllers and hand-held product applications.

Basic Timer Control Register (BTCON)

D3H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Watchdog timer enable bits:

1010B = Disable watchdog function

Others = Enable watchdog function

Divider clear bit for BT and T0:

0 = No effect

1 = Clear both dividers

Basic timer counter clear bits:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00 = fOSC/4096

01 = fOSC/1024

10 = fOSC/128

11 = Invalid selection

Figure 11-1. Basic Timer Control Register (BTCON)

11-2

S3C80F9B/C80G9B

BASIC TIMER and TIMER 0

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a Reset by setting BTCON.7–BTCON.4 to

any value other than '1010B'. (The '1010B' value disables the watchdog function.) A Reset clears BTCON to

'00H', automatically enabling the watchdog timer function. A Reset also selects the CPU clock (as determined by

the current CLKCON register setting),divided by 4096, as the BT clock.

A Reset whenever a basic timer counter overflow occurs. During normal operation, the application program must

prevent the overflow, and the accompanying Reset operation, from occurring. To do this, the BTCNT value must

be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation

will not be executed and a basic timer overflow will occur, initiating a Reset. In other words, during normal

operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always

broken by a BTCNT clear instruction. If a malfunction does occur, a Reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a Reset or when

Stop mode has been released by an external interrupt.

In Stop mode, whenever a Reset or an external interrupt occurs, the oscillator starts. The BTCNT value then

starts increasing at the rate of f_OSC/4096 (for Reset), or at the rate of the preset clock source (for an external

interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed

and to gate the clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when Stop mode is released:

1. During Stop mode, a power-on Reset or an external interrupt occurs to trigger the Stop mode release and

oscillation starts.

2. If a power-on Reset occurred, the basic timer counter will increase at the rate of f

/4096. If an external

OSC

interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.

4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.

TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt

— Clear timer 0 match/capture interrupt pending conditions

11-3

BASIC TIMER and TIMER 0

S3C80F9B/C80G9B

T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.

A Reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency

of fOSC/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal

operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address FAH. When a timer 0

overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer 0 match/capture interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a

match/capture interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a

timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending

condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.

Timer 0 Control Register (T0CON)

D2H, Set 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

00 = fOSC /4096

01 = fOSC /256

Timer 0 interrupt pending bit:

0 = No interrupt pending

0 = Clear pending bit (when write)

1 = Interrupt is pending

10 = fOSC /8

11 = External clock (P3.1/T0CK

or P3.2/T0CK) ^(note)

Timer 0 interrupt match/capture

enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 0 operating mode selection bits:

00 = Interval mode

01 = Capture mode (capture on rising edge,

counter running, OVF can occur)

10 = Capture mode (capture on falling edge,

counter running, OVF can occur)

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

11 = PWM mode (OVF interrupt can occur)

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

NOTE:

The external clock source of timer 0 is P3.1/T0CK in 32-pin package, or

P3.2/T0CK in 42/44-pin package.

Figure 11-2. Timer 0 Control Register (T0CON)

11-4

S3C80F9B/C80G9B

BASIC TIMER and TIMER 0

TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)

The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/

capture interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0,

but is assigned the separate vector address, FCH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.

The T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a

"0" to the T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)

and clears the counter.

If, for example, you write the value ‘10H’ to T0DATA and ‘0BH’ to T0CON, the counter will increment until it

reaches ‘10H’. At this point, the T0 interrupt request is generated, the counter value is Reset, and counting

resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).

IRQ0(INT)

Pending

(T0CON.0)

Interrupt

Enable/Disable

(T0CON.1)

R (Clear)

CLK

Counter

Match

CTL

P3.0

Comparator

Buffer Register

T0CON.5

T0CON.4

Match Signal

T0CON.3

Data Register

Figure 11-3. Simplified Timer 0 Function Diagram: Interval Timer Mode

11-5

BASIC TIMER and TIMER 0

S3C80F9B/C80G9B

Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the

value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at ‘FFH’, and then continues incrementing from ‘00H’.

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data

value is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as the data

value is greater than ( > ) the counter value. One pulse width is equal to t

× 256 (see Figure 11-4).

CLK

IRQ0 (INT)

Pending

(T0CON.0)

Interrupt

Enable/Disable

(T0CON.1)

Counter

IRQ0 (T0OVF)

CTL

CLK

Match

Comparator

Buffer Register

Data Register

P3.0/T0PWM

High level when data > counter

Low level when data< counter

T0CON.5

T0CON.4

Match Signal

T0CON.3

T0OVF

NOTE:

Interrupts are usually not used when timer 0 is configured to operate

in PWM mode.

Figure 11-4. Simplified Timer 0 Function Diagram: PWM Mode

11-6

S3C80F9B/C80G9B

Capture Mode

BASIC TIMER and TIMER 0

In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter

value into the T0 data register. You can select rising or falling edges to trigger this operation.

Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by

setting the value of the timer 0 capture input selection bit in the port 3 control register, P3CON.2, (set 1, bank 0,

F0H). When P3CON.2 is “1”, the T0CAP input is selected. When P3CON.2 is set to “0”, normal I/O port (P3.0) is

selected.

Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated

whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value

is loaded into the T0 data register.

By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,

you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 11-5).

T0CON.2

Counter

CLK

IRQ0 (T0OVF)

IRQ0 (T0INT)

Pending

(T0CON.0)

P3.0/T0CAP

Interrupt

Enable/Disable

(T0CON.1)

Data Register

T0CON.5

T0CON.4

Figure 11-5. Simplified Timer 0 Function Diagram: Capture Mode

11-7

BASIC TIMER and TIMER 0

S3C80F9B/C80G9B

Bit 1

RESET or STOP

Data Bus

Bits 3, 2

MUX

Basic Timer Control Register

(Write '1010xxxxB' to disable.)

Clear

1/4096

1/1024

1/128

8-Bit Up Counter

(BTCNT, Read-Only)

RESET

XIN

DIV

R

OVF

When BTCNT.4 is set after releasing from

RESET or STOP mode, CPU clock starts.

Bit 0

Bits 7, 6

Bit 2

Data Bus

OVF

IRQ0

(Timer 0 Overflow)

R

1/4096

1/256

1/8

Clear

Bit 3

Bit 1

Bit 0

8-Bit Up-Counter

(T0CNT)

X

IN

DIV

MUX

R

Match ⁽²⁾

P3.1/T0CK

or

P3.2/T0CK

(note 3)

IRQ0

8-Bit Compatator

(Timer 0

Match)

T0PWM

T0CAP

Bits 5, 4

Timer 0 Buffer

Register

Bits 5, 4

Match Signal

T0CON.3

T0OVF

Timer 0 Data

Register (T0DATA)

Basic Timer Control Register

Timer 0 Control Register

Data Bus

NOTES:

1. During a power-on reset operation, the CPU is idle during the required oscillation

stabilization interval (until bit 4 of the basic timer counter overflows).

2. It is available only in using internal mode.

3. The external clock source is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 42/44-pin pakcage.

Figure 11-6. Basic Timer and Timer 0 Block Diagram

11-8

S3C80F9B/C80G9B

BASIC TIMER and TIMER 0

)

PROGRAMMING TIP — Configuring the Basic Timer

This example shows how to configure the basic timer to sample specifications:

ORG

0100H

RESET

DI

LD

CLR

;

Disable all interrupts

Disable the watchdog timer

Non-divided clock

Disable global and fast interrupts

Stack pointer low byte → "0"

Stack area starts at 0FFH

BTCON,#0AAH

CLKCON,#18H

SYM

SPL

•

SRP

EI

•

#0C0H

;

Set register pointer → 0C0H

Enable interrupts

•

MAIN

LD

BTCON,#52H

;

Enable the watchdog timer

Basic timer clock: f /4096

OSC

;

Clear basic timer counter

NOP

•

JP

T,MAIN

•

11-9

BASIC TIMER and TIMER 0

S3C80F9B/C80G9B

)

PROGRAMMING TIP — Programming Timer 0

This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and

determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:

— Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds

— Oscillation frequency is 6 MHz

— General register 60H (page 0) → 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0 interrupt

ORG

VECTOR

ORG

0FAH

T0OVER

0FCH

;

Timer 0 overflow interrupt

Timer 0 match/capture interrupt

VECTOR

ORG

T0INT

0100H

RESET

DI

LD

CLR

;

Disable all interrupts

BTCON,#0AAH

CLKCON,#18H

SYM

Disable the watchdog timer

Select non-divided clock

Disable global and fast interrupts

Stack pointer low byte → "0"

Stack area starts at 0FFH

SPL

•

LD

T0CON,#4BH

;

Write ‘01001011B’

Input clock is f

/256

OSC

;

Interval timer mode

Enable the timer 0 interrupt

Disable the timer 0 overflow interrupt

Set timer interval to 4 milliseconds

(6 MHz/256) ÷ (93 + 1) = 0.25 kHz (4 ms)

LD

T0DATA,#5DH

#0C0H

SRP

EI

;

Set register pointer → 0C0H

Enable interrupts

•

T0INT

PUSH

SRP0

INC

ADD

ADC

RP0

#60H

R0

R2,R0

R3,R2

R4,R0

;

Save RP0 to stack

RP0 ← 60H

R0 ← R0 + 1

R2 ← R2 + R0

R3 ← R3 + R2 + Carry

R4 ← R4 + R0 + Carry

(Continued on next page)

11-10

S3C80F9B/C80G9B

BASIC TIMER and TIMER 0

)

PROGRAMMING TIP — Programming Timer 0 (Continued)

CP

R0,#32H

JR

BITS

;

50 × 4 = 200 ms

ULT,NO_200MS_SET

R1.2

Bit setting (61.2H)

NO_200MS_SET:

LD

POP

T0CON,#42H

RP0

;

Clear pending bit

Restore register pointer 0 value

T0OVER

IRET

;

Return from interrupt service routine

11-11

S3C80F9B/C80G9B

TIMER 1

12 TIMER 1

OVERVIEW

The S3C80F9B/C80G9B microcontroller has a 16-bit timer/counter called timer 1 (T1). For universal remote

controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal.

Timer 1 has the following components:

— One control register, T1CON (set 1, FAH, R/W)

— Two 8-bit counter registers, T1CNTH and T1CNTL (set 1, F6H and F7H, read-only)

— Two 8-bit reference data registers, T1DATAH and T1DATAL (set 1, F8H and F9H, R/W)

— A 16-bit comparator

You can select one of the following clock sources as the timer 1 clock:

— Oscillator frequency (f ) divided by 4, 8, or 16

OSC

— Internal clock input from the counter A module (counter A flip/flop output)

You can use Timer 1 in three ways:

— As a normal free run counter, generating a timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time

intervals.

— To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the

16-bit value written to the reference data registers.

— To generate a timer 1 capture interrupt (IRQ1, vector F6H) when a triggering condition exists at the P3.2 pin

for 42/44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as

the trigger).

In the S3C80F9B/C80G9B interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1

match or capture interrupt.

12-1

TIMER 1

S3C80F9B/C80G9B

TIMER 1 OVERFLOW INTERRUPT

Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the

16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is

generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter

value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.3, you can clear/reset

the 16-bit counter value at any time during program operation.

TIMER 1 CAPTURE INTERRUPT

Timer 1 can be used to generate a capture interrupt (IRQ1, vector F6H) whenever a triggering condition is

detected at the P3.0 pin for 32 pin package and P3.3 pin for 42/44 pin package. The T1CON.5 and T1CON.4 bit-

pair setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both

signal edges.

In capture mode, program software can poll the timer 1 match/capture interrupt pending bit, T1CON.0, to detect

when a timer 1 capture interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is

acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear

the interrupt pending condition by writing a “0” to T1CON.0.

T1CON.2

16-Bit Up Counter

CLK

IRQ1 (T1OVF)

IRQ1 (T1INT)

Pending

(T1CON.0)

P3.0 or P3.3 (note)

Interrupt

Enable/Disable

(T1CON.1)

Timer 1 Data

T1CON.5

T1CON.4

NOTE:

P3.0 is assigned as T1CAP function for 32 pin package and P3.3 is assigned as

T1CAP function for 42/44 pin package.

Figure 12-1. Simplified Timer 1 Function Diagram: Capture Mode

12-2

S3C80F9B/C80G9B

TIMER 1

TIMER 1 MATCH INTERRUPT

Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value

matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a match

condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and

up counting resumes from ‘00H’.

In match mode, program software can poll the timer 1 match/capture interrupt pending bit, T1CON.0, to detect

when a timer 1 match interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is

acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear

the interrupt pending condition by writing a “0” to T1CON.0.

IRQ1 (T1INT)

Pending

(T1CON.0)

Interrupt

Enable/Disable

(T1CON.1)

R (Clear)

16-Bit Up Counter

16-Bit Comparator

CLK

Match

CTL

P3.0 or P3.3

T1CON.5

T1CON.4

Timer 1 High/Low

Buffer Register

Match Signal

T1CON.3

Timer 1 Data High/Low

Buffer Register

Figure 12-2. Simplified Timer 1 Function Diagram: Interval Timer Mode

12-3

TIMER 1

S3C80F9B/C80G9B

T1CON.2

T1CON. 7-.6

IRQ1

OVF

CAOF (T-F/F)

f

OSC/4

OSC/8

Clear

T1CON.3

T1CON.1

16-Bit Up-Counter

(Read-Only)

MUX

R

f

OSC/16

Match (note)

MUX

16-Bit Compatator

T1CON.5-.4

T1CON.0

IRQ1

Timer 1 High/Low

Buffer Register

T1CON.3

Match Signal

T1OVF

Timer 1 Data

High/Low Register

Data Bus

NOTE: Match signal is occurrd only in interval mode.

Figure 12-3. Timer 1 Block Diagram

12-4

S3C80F9B/C80G9B

TIMER 1

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains

control settings for the following T1 functions:

— Timer 1 input clock selection

— Timer 1 operating mode selection

— Timer 1 16-bit down counter clear

— Timer 1 overflow interrupt enable/disable

— Timer 1 match or capture interrupt enable/disable

— Timer 1 interrupt pending control (read for status, write to clear)

A reset operation clears T1CON to ‘00H’, selecting f_OSCdivided by 4 as the T1 clock, configuring timer 1 as a

normal interval timer, and disabling the timer 1 interrupts.

Timer 1 Control Register (T1CON)

FAH, Set 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 1 input clock selection bits:

00 = fOSC/4

Timer 1 interrupt pending bit:

0 = No interrupt pending

01 = fOSC/8

10 = fOSC/16

0 = Clear pending bit (when write)

1 = Interrupt is pending

11 = Internal clock (T-F/F)

Timer 1 interrupt match/capture

enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 1 operating mode selection bits:

00 = Interval mode

01 = Capture mode (capture on rising edge,

counter running, OVF can occur)

10 = Capture mode (capture on falling edge,

counter running, OVF can occur)

11 = Capture mode (capture on rising and

Timer 1 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

falling edge, counter running, OVF can occur)

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Figure 12-4. Timer 1 Control Register (T1CON)

12-5

TIMER 1

S3C80F9B/C80G9B

Timer1 Counter High-byte Register

(T1CNTH) F6H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value: 00H

Timer 1 Counter Low-byte Register

(T1CNTL) F7H, Set 1, R

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value: 00H

Timer 1 Data High-byte Register

(T1DATAH) F8H, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

Reset Value: FFH

Timer 1 Data Low-byte Register

(T1DATAL) F9H, Set 1, R/W

.5

.4

.3

.2

.1

.0

LSB

Reset Value: FFH

Figure 12-5. Timer 1 Registers

12-6

S3C80F9B/C80G9B

COUNTER A

13 COUNTER A

OVERVIEW

The S3C80F9B/C80G9B microcontroller has an 8-bit counter called counter A. Counter A, which can be used to

generate the carrier frequency, has the following components (see Figure 13-1):

— Counter A control register, CACON

— 8-bit down counter with auto-reload function

— Two 8-bit reference data registers, CADATAH and CADATAL

Counter A has two functions:

— As a normal interval timer, generating a counter A interrupt (IRQ4, vector ECH) at programmed time intervals.

— To supply a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow

interrupt.

13-1

COUNTER A

S3C80F9B/C80G9B

CACON.6-.7

DIV 1

DIV 2

DIV 4

DIV 8

CLK

CACON.0

(CAOF)

To Other Block

(P3.1/REM)

MUX

16-Bit Down Counter

Repeat

Control

CACON.3

MUX

Interrupt

Control

IRQ2

(CAINT)

INT. GEN.

Counter A Data

Low Byte Register

CACON.2

CACON.4-.5

fOSC

Counter A Data

High Byte Register

Data Bus

NOTE: The value of the CADTAL register is loaded into the 8-bit counter when the

operation of the counter A stars. If a borrow occurs, the value of the

CADATAH register isloaded into the 8-bit counter. However, if the next borrow

occurs, the value of the CADATAL register is loaded into the 8-bit counter.

Figure 13-1. Counter A Block Diagram

13-2

S3C80F9B/C80G9B

COUNTER A

COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON

contains control settings for the following functions (see Figure 13-2):

— Counter A clock source selection

— Counter A interrupt enable/disable

— Counter A interrupt pending control (read for status, write to clear)

— Counter A interrupt time selection

Counter A Control Register (CACON)

F3H, Set 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Counter A input clock

selection bits:

00 = fOSC

Counter A output flip-flop control bit:

0 = T-F/F is low

1 = T-F/F is high

01 = fOSC/2

10 = fOSC/4

11 = fOSC/8

Counter A mode selection bit:

0 = One shot mode

1 = Repeating mode

Counter A interrupt time selection bits:

00 = Elapsed time for low data value

01 = Elapsed time for high data value

10 = Elapsed time for low and high data values

11 = Invalid setting

Counter A start/stop bit:

0 = Stop counter A

1 = Start counter A

Counter A interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

Figure 13-2. Counter A Control Register (CACON)

13-3

COUNTER A

S3C80F9B/C80G9B

Counter A Data High-byte Register

(CADATAH) F4H, Set 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value: FFH

Counter A Data Low-byte Register

(CADATAL) F4H, Set 1, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value: FFH

Figure 13-3. Counter A Registers

COUNTER A PULSE WIDTH CALCULATIONS

t

HIGH

t

LOW

t

LOW

To generate the above repeated waveform consisted of low period time, t_LOW, and high period time, t_HIGH

.

When CAOF = 0,

t_LOW= (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock.

t_HIGH= (CADATAH + 2) × 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock.

When CAOF = 1,

t_LOW= (CADATAH + 2) × 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock.

t_HIGH= (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock.

To make t_LOW= 24 us and t_HIGH= 15 us. F_OSC= 4 MHz, F_X= 4 MHz/4 = 1 MHz

[Method 1] When CAOF = 0,

t_LOW= 24 us = (CADATAL + 2) / F_X= (CADATAL + 2) x 1us, CADATAL = 22.

t_HIGH= 15 us = (CADATAH + 2) / F_X= (CADATAH + 2) x 1us, CADATAH = 13.

[Method 2] When CAOF = 1,

t_HIGH= 15 us = (CADATAL + 2) / F_X= (CADATAL + 2) x 1us, CADATAL = 13.

_LOW= 24 us = (CADATAH + 2) / F_X= (CADATAH + 2) x 1us, CADATAH = 22.

t

13-4

S3C80F9B/C80G9B

COUNTER A

0H

Counter A

Clock

CAOF = '0'

High

Low

High

CADATAL = 01-FFH

CADATAH = 00H

CAOF = '0'

CADATAL = 00H

CADATAH = 01-FFH

CAOF = '0'

CADATAL = 00H

CADATAH = 00H

CAOF = '1'

CADATAL = 00H

CADATAH = 00H

0H

100H

200H

Counter A

Clock

E0H

CAOF = '1'

CADATAL = DEH

CADATAH = 1EH

20H

CAOF = '0'

CADATAL = DEH

CADATAH = 1EH

E0H

80H

CAOF = '1'

CADATAL = 7EH

CADATAH = 7EH

80H

CAOF = '0'

CADATAL = 7EH

CADATAH = 7EH

80H

Figure 13-4. Counter A Output Flip-Flop Waveforms in Repeat Mode

13-5

COUNTER A

S3C80F9B/C80G9B

)

PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1

This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source,

and CADATAH and CADATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are:

8.795 us

17.59 us

37.9 kHZ 1/3 duty

— Counter A is used in repeat mode

— Oscillation frequency is 4 MHz (0.25 µs)

— CADATAH = 8.795 µs / 0.25 µs = 35.18, CADATAL = 17.59 µs / 0.25 µs = 70.36

— Set P3.1 C-Mos push-pull output and CAOF mode.

— 44 pin package

ORG

0100H

;

Reset address

START

DI

•

LD

CADATAL,#(70-2)

CADATAH,#(35-2)

;

Set 17.5 µs

Set 8.75 µs

LD

P3CON,#11110010B

CACON,#00000110B

Set P3 to C-Mos push-pull output.

Set P3.1 to REM output

Clock Source → Fosc

;

Disable Counter A interrupt.

Select repeat mode for Counter A.

; Start Counter A operation.

; Set Counter A Output Flip-flop(CAOF) high.

;

LD

P3,#80H

;

Set P3.7(Carrier On/Off) to high.

This command generates 38 kHz, 1/3duty pulse signal

through P3.1

•

13-6

S3C80F9B/C80G9B

COUNTER A

)

PROGRAMMING TIP — To generate a one pulse signal through P3.1

This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source,

and CADATAH and CADATAL to make a 40 µs width pulse. The program parameters are:

40 us

— Counter A is used in one shot mode

— Oscillation frequency is 4 MHz ( 1 clock = 0.25 µs)

— CADATAH = 40 µs / 0.25 µs = 160, CADATAL = 1

— Set P3.1 C-Mos push-pull output and CAOF mode.

— 44pin package

ORG

DI

0100H

;

Reset address

START

•

LD

CADATAH,# (160-2)

CADATAL,# 1

;

Set 40 µs

Set any value except 00H

LD

P3CON,#11110010B

CACON,#00000001B

Set P3 to C-Mos push-pull output.

Set P3.1 to REM output

Clock Source → Fosc

Disable Counter A interrupt.

Select one shot mode for Counter A.

; Stop Counter A operation.

; Set Counter A Output Flip-Flop (CAOF) high

LD

P3,#80H

;

Set P3.7(Carrier On/Off) to high.

•

Pulse_out: LD

CACON,#00000101B

;

Start Counter A operation

to make the pulse at this point.

After the instruction is executed, 0.75 µs is required

before the falling edge of the pulse starts.

•

13-7

S3C80F9B/C80G9B

ELECTRICAL DATA

14 ELECTRICAL DATA 1 (S3C80F9B)

OVERVIEW

In this section, S3C80F9B electrical characteristics are presented in tables and graphs. The information is

arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in Stop mode

— Stop mode release timing when initiated by an external interrupt

— Stop mode release timing when initiated by a Reset

— I/O capacitance

— A.C. electrical characteristics

— Input timing for external interrupts

— Input timing for RESET

— Oscillation characteristics

— Oscillation stabilization time

14-1

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 14-1. Absolute Maximum Ratings

(T = 25 °C)

A

Parameter

Symbol

Conditions

Rating

Unit

V_DD

Supply voltage

Input voltage

–

– 0.3 to + 6.5

V

V_IN

V_O

– 0.3 to V_DD+ 0.3

–

V

Output voltage

Output current High

All output pins

I_OH

One I/O pin active

All I/O pins active

– 18

– 60

mA

I_OL

Output current Low

One I/O pin active

Total pin current for ports 0, 1, and 2

Total pin current for port 3

–

+ 30

mA

+ 100

+ 40

T_A

Operating

temperature

– 25 to + 85

°C

T_STG

Storage temperature

–

– 65 to + 150

Table 14-2. D.C. Electrical Characteristics

(T = – 25 °C to + 85 °C, V_DD= 2.0 V to 5.0 V)

A

Parameter

Symbol

Conditions

F_OSC= 8 MHz

(Instruction clock = 2 MHz)

Min

Typ

Max

Unit

V_DD

Operating Voltage

2.0

–

5.0

V

V_IH1

All input pins except V_IH2and 0.8 V_DD

V_IH3

V_DD

Input High

Voltage

–

V

V_IH2

V_IH3

V_IL1

0.85 V_DD

V_DD– 0.3

0

V_DD

nRESET

XIN

All input pins except V_IL2

and V_IL3

0.2 V_DD

Input Low Voltage

–

V

V_IL2

V_IL3

0.2 V_DD

0.3

nRESET

XIN

V_OH1

V_DD= 2.4 V I_OH= – 6 mA

Port 3.1 only

V_DD– 0.7

Output High

Voltage

V_OH2

V_DD= 2.4 V, I_OH= – 2.2mA

P3.0, P2.0–2.3

V_DD0.7

–

14-2

S3C80F9B/C80G9B

ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

(T_A= – 25 °C to + 85 °C, V_DD= 2.0 V to 5.0 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_OH3

V_DD= 2.4 V,I_OH= – 1 mA

V_DD1.0

–

Output High

Voltage

–

0.5

1

V

Port0, Port1, P2.4-2.7 and Port4

V_OL1

V_OL2

V_OL3

I_LIH1

V_DD= 2.4 V, I_OL= 12 mA, port

Output Low

Voltage

–

0.4

–

V

3.1 only

V_DD= 2.4 V, I_OL= 5 mA

P3.0, P3.4-3.5, P2.0-2.3

I_OL= 2mA

Port 0, Port1, P2.4-2.7 and Port4

V_IN= V_DD

All input pins except X and

IN

X_OUT

Input High

Leakage Current

–

1

µA

I_LIH2

I_LIL1

V_IN= V_DD, X_INand X_OUT

20

V_IN= 0 V

Input Low

–

– 1

Leakage Current

All input pins except X_IN, X_OUT

I_LIL2

V_IN= 0 V

– 20

X_INand X_OUT

I_LOH

I_LOL

R_L1

V_OUT= V_DD

Output High

Leakage Current

–

1

µA

kΩ

All output pins

V_OUT= 0 V

Output Low

Leakage Current

– 1

95

All output pins

V_IN= 0 V, V_DD= 2.4 V

Pull-up

Resistors

44

55

°

T_A= 25 C, Ports 0–2, P3.2–3.3

14-3

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 14-2. D.C. Electrical Characteristics (Continued)

(T = – 25 °C to + 85 °C, V_DD= 2.0 V to 5.0 V)

A

Parameter

Symbol

Conditions

Operating mode

_DD= 5.0 V

Min

Typ

Max

Unit

I_DD1

Supply current

(note)

–

6

11

mA

V

8 MHz crystal

4 MHz crystal

4.5

1.8

9

I_DD2

Idle mode

3.5

V_DD= 5.0 V

8 MHz crystal

4 MHz crystal

1.6

18

3.0

25

I_DD3

Stop mode; V_DD= 5.0 V

–

uA

T

A

= 25 °C

12

4.5

1

15

8

V_DD= 3.6 V, T_A= 25 °C

V_DD= 2.4 V, T_A= 25 °C

V_DD= 0.7 V, T_A= 25 °C

1.5

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

Table 14-3. Characteristics of Low Voltage Detect circuit

(T = 25 °C)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Hysteresys Voltage of

–

100

300

mV

∆V

LVD (Slew Rate of LVD)

V_LVD

Low level detect voltage

–

2.00

2.20

2.40

V

Table 14-4. Data Retention Supply Voltage in Stop Mode

(T = – 25 °C to + 85 °C)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply

voltage

–

1.0

–

5.0

V

I_DDDR

V_DDDR= 1.0 V

Stop mode

Data retention supply

current

–

1

µA

14-4

S3C80F9B/C80G9B

ELECTRICAL DATA

Idle Mode

(Basic Timer Active)

Stop Mode

Data Retention Mode

VDD

Normal

Operating

Mode

VDDDR

Execution of

STOP Instrction

EXT INT

0.8VDD

0.2VDD

t

WAIT

Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt

Reset

Occur

Oscillation Stabilization Time

Stop Mode

Normal

Operating

Mode

VDD

Execution of

STOP Instrction

nRESET

tWAIT

NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 14-2. Stop Mode Release Timing When Initiated by a RESET

14-5

ELECTRICAL DATA

S3C80F9B/C80G9B

Reset

Occur

Oscillation Stabilization Time

Stop Mode

Normal

Operating

Mode

Back-up Mode

VDD

VLVD

VDDDR

t

WAIT

Execution of

STOP Instrction

Data Retention Time

NOTE

:

tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 14-3. Stop Mode Release Timing When Initiated by a LVD

Table 14-5. Input/Output Capacitance

(T_A= – 25 °C to + 85 °C , V_DD= 0 V)

Parameter

Input

capacitance

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

f = 1 MHz; unmeasured pins

are connected to V_SS

–

10

pF

C_OUT

C_IO

Output

capacitance

I/O capacitance

Table 14-6. A.C. Electrical Characteristics

(T = – 25 °C to + 85 °C)

A

Parameter

Symbol

t_INTH

t_INTL

Conditions

Min

Typ

Max

Unit

Interrupt input,

High, Low width

P0.0–P0.7, P2.3–P2.0

_DD= 5.0 V

200

300

–

ns

,

V

t_RSL

nRESET input

Low width

Input

V_DD= 5.0 V

1000

–

14-6

S3C80F9B/C80G9B

ELECTRICAL DATA

t

INTL

tINTH

0.8 VDD

0.2 VDD

NOTE

:

The unit tCPU means one CPU clock period.

Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3–P2.0)

Reset

Occur

Oscillation Stabilization Time

Normal

Back-up Mode

(Stop Mode)

Normal Operating Mode

Operating

Mode

VDD

nRESET

tWAIT

NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 14-5. Input Timing for RESET

14-7

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 14-7. Oscillation Characteristics

(T = – 25 °C + 85 °C)

A

Oscillator

Clock Circuit

Conditions

Min

Typ

Max

Unit

Crystal

CPU clock oscillation

frequency

1

–

8

MHz

XIN

C1

C2

XOUT

Ceramic

CPU clock oscillation

frequency

1

–

8

MHz

X

IN

C1

C2

XOUT

X

IN

input frequency

External clock

XIN

External

Clock

Open Pin

XOUT

Table 14-8. Oscillation Stabilization Time

(T = – 25 °C + 85 °C, V_DD= 4.5 V to 5.0 V)

A

Oscillator

Test Condition

f_OSC> 400 kHz

Min

Typ

Max

Unit

Main crystal

–

20

10

ms

Oscillation stabilization occurs when V_DDis

Main ceramic

–

ms

ns

equal to the minimum oscillator voltage

range.

X_INinput High and Low width (t_XH, t_XL

)

External clock

(main system)

25

–

500

2¹⁶/f_OSC

–

t_WAITwhen released by a reset ⁽¹⁾

Oscillator

stabilization

wait time

–

ms

t_WAITwhen released by an interrupt ⁽²⁾

NOTES:

1.

f

is the oscillator frequency.

OSC

2. The duration of the oscillation stabilization time (t

) when it is released by an interrupt is determined by the setting

WAIT

in the basic timer control register, BTCON.

14-8

S3C80F9B/C80G9B

ELECTRICAL DATA

Instruction

Clock

Instruction

Clock

A

2 MHz

8 MHz

6 MHz

1.25MHz

1 MHz

4 MHz

500 kHz

250 kHz

100 kHz

400 kHz

1

2

3

4

5

6

7

Supply Voltage (V)

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

A 2.0 V: 8MHz

Figure 14-6. Operating Voltage Range of S3C80F9B

14-9

S3C80F9B/C80G9B

ELECTRICAL DATA

15 ELECTRICAL DATA 2 (S3C80G9B)

OVERVIEW

In this section, S3C80G9B electrical characteristics are presented in tables and graphs. The information is

arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in Stop mode

— Stop mode release timing when initiated by an external interrupt

— Stop mode release timing when initiated by a Reset

— I/O capacitance

— A.C. electrical characteristics

— Input timing for external interrupts

— Input timing for nRESET

— Oscillation characteristics

— Oscillation stabilization time

15-1

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 15-1. Absolute Maximum Ratings

(T = 25 °C)

A

Parameter

Symbol

Conditions

Rating

Unit

V_DD

Supply voltage

Input voltage

–

– 0.3 to + 6.5

V

V_IN

V_O

– 0.3 to V_DD+ 0.3

–

V

Output voltage

Output current High

All output pins

I_OH

One I/O pin active

All I/O pins active

– 18

– 60

mA

I_OL

Output current Low

One I/O pin active

Total pin current for ports 0, 1, and 2

Total pin current for port 3

–

+ 30

mA

+ 100

+ 40

T_A

Operating

temperature

– 25 to + 85

°C

T_STG

Storage temperature

–

– 65 to + 150

Table 15-2. D.C. Electrical Characteristics

(T = – 25 °C to + 85 °C, V

DD

= 1.7 V to 3.6 V)

Conditions

A

Parameter

Symbol

V_DD

Min

Typ

Max

Unit

F_OSC= 4 MHz

Operating Voltage

1.7

–

3.6

V

(Instruction clock = 1 MHz)

V_IH1

All input pins except V_IH2and 0.8 V_DD

V_IH3

V_DD

Input High

voltage

–

V

V_IH2

V_IH3

V_IL1

0.85 V_DD

V_DD– 0.3

0

V_DD

NRESET

XIN

All input pins except V_IL2

and V_IL3

0.2 V_DD

Input Low voltage

–

V_IL2

V_IL3

0.2 V_DD

NRESET

XIN

0.3

V_OH1

V_DD= 2.4 V I_OH= – 6 mA

Port 3.1 only

V_DD– 0.7

Output High

voltage

–

V_OH2

V_DD= 2.4 V, I_OH= – 2.2mA

P3.0, P2.0–2.3

–

15-2

S3C80F9B/C80G9B

ELECTRICAL DATA

Table 15-2. D.C. Electrical Characteristics (Continued)

(T_A= – 25 °C to + 85 °C, V_DD= 1.7 V to 3.6 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_OH3

V_DD= 2.4 V, I_OH= – 1 mA

V_DD1.0

–

Output High

voltage

–

V

Port0, Port1, P2.4–2.7 and Port4

V_OL1

V_OL2

V_OL3

I_LIH1

V_DD= 2.4 V, I_OL= 12 mA, port

Output Low

voltage

–

0.4

–

0.5

1

V

3.1 only

V_DD= 2.4 V, I_OL= 5 mA

P3.0, P3.4–3.5, P2.0–2.3

I_OL= 2mA

Port 0, Port1, P2.4–2.7 and Port4

V_IN= V_DD

All input pins except X and

IN

X_OUT

Input High

leakage current

–

1

µA

I_LIH2

I_LIL1

V_IN= V_DD, X_INand X_OUT

20

V_IN= 0 V

Input Low

–

– 1

leakage current

All input pins except X_IN, X_OUT

I_LIL2

V_IN= 0 V

– 20

X_INand X_OUT

I_LOH

I_LOL

R_L1

V_OUT= V_DD

Output High

leakage current

–

1

µA

kΩ

All output pins

V_OUT= 0 V

Output Low

leakage current

– 1

95

All output pins

V_IN= 0 V, V_DD= 2.4 V

Pull-up resistors

44

55

T_A= 25 °C, Ports 0–2, P3.2–3.3

15-3

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 15-2. D.C. Electrical Characteristics (Continued)

(T = – 25 °C to + 85 °C, V = 1.7 V to 3.6 V)

A

DD

Symbol

Parameter

Conditions

Operating mode

_DD= 3.6 V

Min

Typ

Max

Unit

I_DD1

I_DD2

I_DD3

Supply current

(note)

–

4.5

9

3.0

6

mA

V

4 MHz crystal

Idle mode

1.6

1

V

_DD=3.6 V

4 MHz crystal

Stop mode;

–

uA

V_DD=3.6 V, T = 25 °C

A

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

Table 15-3. Characteristics of Low Voltage Detect circuit

(T = 25 °C)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Hysteresys Voltage of

LVD (Slew Rate of LVD)

–

100

300

mV

∆V

V_LVD

Low level detect voltage

–

1.70

1.90

2.10

V

Table 15-4. Data Retention Supply Voltage in Stop Mode

(T = – 25 °C to + 85 °C)

A

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply

voltage

–

1.0

–

3.6

V

I_DDDR

V_DDDR= 1.0 V

Stop mode

Data retention supply

current

–

1

µA

15-4

S3C80F9B/C80G9B

ELECTRICAL DATA

Idle Mode

(Basic Timer Active)

Stop Mode

Data Retention Mode

VDD

Normal

Operating

Mode

VDDDR

Execution of

STOP Instrction

EXT INT

0.8VDD

0.2VDD

t

WAIT

Figure 15-1. Stop Mode Release Timing When Initiated by an External Interrupt

Reset

Occur

Oscillation Stabilization Time

Stop Mode

Normal

Operating

Mode

VDD

Execution of

STOP Instrction

nRESET

tWAIT

NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 15-2. Stop Mode Release Timing When Initiated by a nRESET

15-5

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 15-5. Input/Output Capacitance

(T_A= – 25 °C to + 85 °C , V_DD= 0 V)

Parameter

Input

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

f = 1 MHz; unmeasured pins

–

10

pF

are connected to V

capacitance

SS

C_OUT

C_IO

Output

capacitance

I/O capacitance

Table 15-6. A.C. Electrical Characteristics

(T = – 25 °C to + 85 °C)

A

Parameter

Symbol

t_INTH

t_INTL

Conditions

Min

Typ

Max

Unit

Interrupt input,

High, Low width

P0.0–P0.7, P2.3–P2.0

V_DD= 3.6 V

200

300

–

ns

,

t_RSL

nRESET input

Low width

Input

1000

–

V

_DD= 3.6 V

15-6

S3C80F9B/C80G9B

ELECTRICAL DATA

t

INTL

tINTH

0.8 VDD

0.2 VDD

NOTE

:

The unit tCPU means one CPU clock period.

Figure 15-3. Input Timing for External Interrupts (Port 0, P2.3–P2.0)

Reset

Occur

Oscillation Stabilization Time

Back-up Mode

(Stop Mode)

Normal

Operating

Mode

Normal Operating Mode

VDD

nRESET

tWAIT

NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.

Figure 15-4. Input Timing for RESET

15-7

ELECTRICAL DATA

S3C80F9B/C80G9B

Table 15-7. Oscillation Characteristics

(T = – 25 °C + 85 °C)

A

Oscillator

Clock Circuit

Conditions

Min

Typ

Max

Unit

Crystal

CPU clock oscillation

frequency

1

–

4

MHz

XIN

C1

C2

XOUT

Ceramic

CPU clock oscillation

frequency

1

–

4

MHz

X

IN

C1

C2

XOUT

X

IN

input frequency

External clock

X

IN

External

Clock

Open Pin

XOUT

Table 15-8. Oscillation Stabilization Time

= 3.6 V )

DD

(T = – 25 °C + 85 °C, V

A

Oscillator

Test Condition

Min

Typ

Max

Unit

f_OSC> 400 kHz

Main crystal

–

20

ms

Oscillation stabilization occurs when V_DDis

Main ceramic

–

10

ms

ns

equal to the minimum oscillator voltage

range.

X_INinput High and Low width (t_XH, t_XL

)

External clock

(main system)

25

–

500

2¹⁶/f_OSC

–

t_WAITwhen released by a reset ⁽¹⁾

Oscillator

stabilization

wait time

–

ms

t_WAITwhen released by an interrupt ⁽²⁾

NOTES:

1.

f

is the oscillator frequency.

OSC

2. The duration of the oscillation stabilization time (t

) when it is released by an interrupt is determined by the setting

WAIT

in the basic timer control register, BTCON.

15-8

S3C80F9B/C80G9B

ELECTRICAL DATA

Instruction

Clock

Instruction

Clock

2 MHz

8 MHz

6 MHz

1.25MHz

1 MHz

A

4 MHz

500 kHz

250 kHz

100 kHz

400 kHz

1

2

3

4

5

6

7

Supply Voltage (V)

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

A 1.7 V: 4MHz

Figure 15-6. Operating Voltage Range of S3C80G9B

15-9

S3C80F9B/C80G9B

MECHANICAL DATA

16 MECHANICAL DATA

OVERVIEW

The S3C80F7/C80F9/C80G7/C80G9 microcontroller is currently available in a 28-pin SOP(Only for 80G9B) ,

32-pin SOP, 42-pin SDIP, 44-pin QFP and 48-ELP(Only for 80F9B) package.

#28

#15

28-SOP-375

#1

#14

+ 0.10

- 0.05

0.15

18.02 MAX

17.62

± 0.2

1.27

(0.56)

0.41 ± 0.1

NOTE: Dimensions are in millimeters

Figure 16-1. 28-SOP-375 Package Dimensions

NOTE: 28-SOP package is only used for S3C80G7/G9

16-1

MECHANICAL DATA

S3C80F9B/C80G9B

0-8

#32

#17

32-SOP-450A

+ 0.10

0.25 - 0.05

#1

#16

20.30 MAX

19.90 ± 0.20

0.10 MAX

1.27

(0.43)

0.40 ± 0.10

NOTE: Dimensions are in millimeters.

Figure 16-2. 32-Pin SOP Package Dimension

16-2

S3C80F9B/C80G9B

MECHANICAL DATA

#42

#22

0-15

42-SDIP-600

#1

#21

39.50 MAX

39.10

± 0.20

0.50

1.00

±

0.10

1.78

(1.77)

NOTE: Dimensions are in millimeters.

Figure 16-3. 42-Pin SDIP Package Dimension

16-3

MECHANICAL DATA

S3C80F9B/C80G9B

13.20

10.00

±

0.30

0.20

0-8

+ 0.10

- 0.05

0.15

0.10 MAX

44-QFP-1010B

#44

+ 0.10

- 0.05

#1

0.35

0.05 MIN

2.05

2.30 MAX

0.80

(1.00)

0.15 MAX

±

0.10

NOTE

: Dimensions are in millimeters.

Figure 16-4. 44-Pin QFP Package Dimension

16-4

S3C80F9B/C80G9B

MECHANICAL DATA

7.00

6.75

±

0.10

0.05

(3.740)

#1 PIN

INDEX

#48

#1

+

−

0.10

0.02

#1

0.50 BSC

(0.75)

0.20

0.10

BOTTOM VIEW

TOP VIEW

0.08

0.45

± 0.05

0.65REF

0 ~ 0.05

Figure 16-5. 48-Pin ELP Package Dimension

NOTE: 48-ELP package is only used for S3C80F9B

16-5

MECHANICAL DATA

S3C80F9B/C80G9B

NOTES

16-6

S3C8 SERIES MASK ROM ORDER FORM

Product description:

Device Number:

S3C80F9B

S3C80G9B

S3C8__________- ___________(write down the ROM code number)

Product Order Form:

Package

Pellet

Wafer

Package Type: __________

Package Marking (Check One):

Standard

Custom A

(Max 10 chars)

Custom B

(Max 10 chars each line)

@ YWW

Device Name

@ YWW

Device Name

SEC

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

Delivery Dates and Quantities:

Deliverable

ROM code

Required Delivery Date

Quantity

Comments

–

Not applicable

See ROM Selection Form

Customer sample

Risk order

See Risk Order Sheet

Please answer the following questions:

For what kind of product will you be using this order?

)

New product

Upgrade of an existing product

Other

Replacement of an existing product

If you are replacing an existing product, please indicate the former product name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Delivery on time

Development system

Used same micom before

Technical support

Quality of documentation

Samsung reputation

Mask Charge (US$ / Won):

Customer Information:

____________________________

Company Name:

___________________

________________________

(Person placing the order)

Telephone number

_________________________

__________________________________

(Technical Manager)

Signatures:

(For duplicate copies of this form, and for additional ordering information, please contact your local

Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3C8 SERIES REQUEST

FOR PRODUCTION AT CUSTOMER RISK

Customer Information:

Company Name:

Department:

________________________________________________________________

Telephone Number:

Date:

__________________________

Fax: _____________________________

Risk Order Information:

Device Number:

S3C80F9B

S3C80G9B

S3C8__________- ___________(write down the ROM code number)

Package:

Number of Pins: ____________

Package Type: _____________________

Intended Application:

Product Model Number:

________________________________________________________________

Customer Risk Order Agreement:

We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk

order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume

responsibility for any and all production risks involved.

Order Quantity and Delivery Schedule:

Risk Order Quantity:

Delivery Schedule:

_____________________ PCS

Delivery Date (s)

Quantity

Comments

Signatures:

_______________________________

(Person Placing the Risk Order)

_______________________________________

(SEC Sales Representative)

(For duplicate copies of this form, and for additional ordering information, please contact your local

Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)

S3C80F9B/C80G9B

MASK OPTION SELECTION FORM

Device Number:

S3C80F9B

S3C80G9B

S3C8__________- ___________(write down the ROM code number)

Diskette

PROM

Attachment (Check one):

Customer Checksum:

Company Name:

________________________________________________________________

Signature (Engineer):

Please answer the following questions:

)

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Industrials

Remocon

Caller ID

Home Appliance

Other

LCD Game

Office Automation

Please describe in detail its application

(For duplicate copies of this form, and for additional ordering information, please contact your local

Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)


型号：	S3C80F9BXX-LR
厂家：	SAMSUNG
描述：	Microcontroller, 8-Bit, FLASH, SAM87RC CPU, 8MHz, CMOS, PQCC48 微控制器
文件：	总289页 (文件大小：3763K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3C80F9BXX-LR [SAMSUNG]

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