S3C9432 [SAMSUNG]
SAM87Ri family of 8-bit single-chip CMOS microcontrollers; SAM87RI家族的8位单芯片CMOS微控制器
| 型号： | S3C9432 |
| 厂家： | 
SAMSUNG |
| 描述： | SAM87Ri family of 8-bit single-chip CMOS microcontrollers |
| 文件： | 总31页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C9432/C9434/P9434
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9432/C9434 MICROCONTROLLER
The S3C9432/C9434 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM87Ri CPU core. The S3C9432/C9434 is a versatile microcontroller, with its A/D
converter, timer, PWM, and SIO it can be used in a wide range of general purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9432/C9434 have 2K-bytes or 4K-
bytes of program memory on-chip (ROM) and 112-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
— Three configurable I/O ports (13 pins)
— Five interrupt sources with one vector and one interrupt level
— One 8-bit timer/counter with time interval mode
— Analog to digital converter with five input channels and 10-bit resolution
— One synchronous SIO module
— One 12-bit PWM output
The S3C9432/C9434 microcontroller is ideal for use in a wide range of electronic applications requiring simple
timer/counter, PWM, ADC, and SIO. S3C9432/C9434 is available in a 20/18/16-pin DIP and a 20-pin SOP
package.
OTP
The S3P9434 is an OTP (One Time Programmable) version of the S3C9432/C9434 microcontroller. The
S3P9434 has on-chip 4K-byte one-time-programmable EPROM instead of masked ROM. The S3P9434 is fully
compatible with the S3C9432/C9434, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9432/C9434/P9434
FEATURES
CPU
Timer/Counters
•
SAM87RI CPU core
•
•
One 8-bit basic timer for watchdog function
One 8-bit timer/counter for the time interval
mode
Memory
•
•
2/4K-byte internal program memory (ROM)
112-byte general purpose register area (RAM)
PWM Module
•
•
12-bit PWM 1-ch (Max: 250 kHz)
6-bit base + 6-bit extension frame
Instruction Set
•
•
41 instructions
A/D Converter
The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction.
•
•
Five analog input pins
10-bit conversion resolution
Buzzer Frequency Range
200 Hz to 20 kHz signal can be generated
Instruction Execution Time
•
•
•
600 ns at 10 MHz f
375 ns at 16 MHz f
(minimum cycles)
(minimum cycles)
OSC
OSC
Oscillation Frequency
•
•
•
1 MHz to 16 MHz external crystal oscillator
Maximum 16 MHz CPU clock
4 MHz RC oscillator
Interrupts
•
5 interrupt sources with one vector and one
level interrupt structure
Operating Temperature Range
General I/O
° °
- 40 C to + 85 C
•
•
•
•
Two I/O ports (Toatal 13 pins)
One output only port (port 2)
Bit programmable ports
Operating Voltage Range
3.0 V to 5.5 V
•
Serial I/O
OTP Interface Protocol Spec
Serial OTP
•
•
One synchronius serial I/O module
Selectable transmit and receive rates
•
Package Types
Built-in reset Circuit (LVD)
•
•
•
•
20-pin DIP-300
20-pin SOP-375
18-pin DIP-300
16-pin DIP-300
•
Low voltage detector for safe reset
1-2
S3C9432/C9434/P9434
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.0-P1.4
ADC0-ADC4
SCK, SO, SI, CLO
P0.0-P0.3
BUZ, PWM, INT0, INT1
Port 0
Port 1
Basic
Timer
XIN
OSC
XOUT
I/O Port and
Interrupt Control
P2.0/SCK
P2.1/SO
P2.2
P0.2/T0CK
P0.0/BUZ
Timer 0
BUZ
Port 2
P2.3
SCK (P1.3 or P2.0)
SO (P1.2 or P2.1)
SAM87RI CPU
SIO
SI (P1.1)
ADC0-ADC4
P0.1/PWM
ADC
PWM
2-KB ROM
4-KB ROM
112-Byte
Register File
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9432/C9434/P9434
PIN ASSIGNMENTS
VDD
20
19
18
17
16
15
14
13
12
11
VSS
XIN
1
2
3
4
5
6
7
8
9
10
P0.3/INT1 (SCL)
P1.0/ADC0 (SDA)
P1.1/ADC1/SI
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CL0
AVREF
XOUT
TEST (VPP)
S3C9432/C9434
P0.2/T0CK/INT0
P0.1/PWM
RESET
20-DIP
(Top View)
P0.0/BUZ
P2.0/SCK
P2.2
P2.1/SO
P2.3
Figure 1-2. Pin Assignment Diagram (20-Pin DIP Package)
1-4
S3C9432/C9434/P9434
PRODUCT OVERVIEW
VDD
20
19
18
17
16
15
14
13
12
11
VSS
XIN
1
2
3
4
5
6
7
8
9
10
P0.3/INT1
P1.0/ADC0
P1.1/ADC1/SI
P1.2/ADC2/SO
XOUT
TEST
S3C9432/C9434
P0.2/T0CK/INT0
P0.1/PWM
RESET
20-SOP
(Top View)
P1.3/ADC3/SCK
P1.4/ADC4/CLO
AVREF
P0.0/BUZ
P2.0/SCK
P2.2
P2.1/SO
P2.3
Figure 1-3. Pin Assignment Diagram (20-Pin SOP Package)
1-5
PRODUCT OVERVIEW
S3C9432/C9434/P9434
VDD
18
17
16
15
14
13
12
11
10
VSS
XIN
1
2
3
4
5
6
7
8
9
P0.3/INT1
P1.0/ADC0
P1.1/ADC1/SI
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CL0
AVREF
XOUT
TEST
S3C9432/C9434
P0.2/T0CK/INT0
P0.1/PWM
RESET
18-DIP
(Top View)
P0.0/BUZ
P2.1/SO
P2.0/SCK
Figure 1-4. Pin Assignment Diagram (18-Pin DIP Package)
VDD
16
15
14
13
12
11
10
9
VSS
XIN
1
2
3
4
5
6
7
8
P0.3/INT1
P1.0/ADC0
P1.1/ADC1/SI
XOUT
S3C9432/C9434
TEST
16-DIP
(Top View)
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CLO
AVREF
P0.2/T0CK/INT0
P0.1/PWM
RESET
P0.0/BUZ
Figure 1-5. Pin Assignment Diagram (16-Pin DIP Package)
1-6
S3C9432/C9434/P9434
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C9432/C9434 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
Share
Pins
Bit-programmable I/O port for Schmitt trigger
input or push-pull, open-drain output. Pull-up
resistors are assignable by software. Port 0 pins
can also be used as alternative function.
P0.0-P0.3
I/O
E
BUZ
PWM
INT0/T0CK
INT1
P1.0-P1.4
I/O
Bit-programmable I/O port for Schmitt trigger
input or push-pull, open-drain output. Pull-up
resistors are assignable by software. Port 1 pins
can also be used as alternative function.
E-1
ADC0-ADC4
SI
SO
SCK
CLO
P2.0-P2.3
O
–
Push-pull or open-drain output port. Pull up
resistors are assignable by software. Port 2.0-2.1
pins can also be used as alternative function.
E-2
–
SCK
SO
X , X
IN OUT
Crystal/ceramic, or RC oscillator signal for system
clock.
–
I
I
B
–
–
–
RESET
System RESET signal input pin.
TEST
Test signal input pin (for factory use only: must be
connected to VSS
)
V
V
–
–
Voltage input pin and ground
–
–
–
–
DD, SS
AVREF
AV
A/D converter reference voltage input and ground
Bonded to VSS internally
SS
SCK
I/O
O
Serial interface clock I/O
E-1
E-2
P1.3 or
P2.0
SO
Serial data output
E-1
E-2
P1.2 or
P2.1
SI
I
Serial data input
E-1
E-1
E
P1.1
P1.4
P0.0
CLO
BUZ
O
O
System clock output port
200 Hz- 20 kHz frequency output for buzzer
sound
PWM
O
I
12-bit PWM output
E
E
P0.1
INT0-INT1
External interrupt input port
P0.2
P0.3
T0CK
I
I
Timer 0 external clock input
A/D converter input
E
P0.2
ADC0-ADC4
E-1
P1.0-P1.4
1-7
PRODUCT OVERVIEW
S3C9432/C9434/P9434
PIN CIRCUITS
VDD
VDD
P-Channel
N-Channel
P-Channel
Out
Data
In
N-Channel
Output
DIsable
Figure 1-8. Pin Circuit Type C
Figure 1-6. Pin Circuit Type A
VDD
VDD
Pull-up
P-Channel
I/O
Enable
Pull-Up
Resistor
Data
Circuit
Type C
Output
DIsable
In
Data
Figure 1-7. Pin Circuit Type B
Figure 1-9. Pin Circuit Type D
1-8
S3C9432/C9434/P9434
PRODUCT OVERVIEW
VDD
VDD
Pull-up
Resistor
Open-Drain
VDD
Pull-up
Open-Drain
Resistor
VDD
Pull-up
Enable
P-CH
Pull-up
Enable
P-CH
Output
Data
I/O
N-CH
Output
Data
I/O
Output
N-CH
DIsable
Output
DIsable
Input
Figure 1-12. Pin Circuit Type E-2
Figure 1-10. Pin Circuit Type E
VDD
Pull-up
Resistor
Open-Drain
VDD
Pull-up
Enable
P-CH
Output
Data
I/O
N-CH
Output
DIsable
Digital
Input
Analog
Input
Figure 1-11. Pin Circuit Type E-1
1-9
S3C9432/C9434/P9434
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9432/C9434 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Input Timing Measurement Points
— Oscillator characteristics
— Oscillation stabilization time
— Operating Voltage Range
— Schmitt trigger input characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET
— A/D converter electrical characteristics
— LVD circuit characteristics
— LVD reset Timing
— Serial I/O timing characteristics
— Serial data transfer timing
14-1
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Supply voltage
Input voltage
Symbol
Conditions
Rating
Unit
VDD
VI
–
- 0.3 to + 6.5
V
- 0.3 to VDD + 0.3
- 0.3 to VDD + 0.3
- 25
All input ports
V
V
VO
IOH
Output voltage
Output current high
All output ports
One I/O pin active
mA
All I/O pins active
One I/O pin active
- 80
IOL
Output current low
+ 30
mA
All I/O pins active
–
+ 150
TA
°
Operating temperature
Storage temperature
- 40 to + 85
C
TSTG
°
C
–
- 65 to + 150
Table 14-2. DC Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VIH1
VDD= 3.0 to 5.5 V
0.8 VDD
VDD
Input high
voltage
Ports 0, 1, and
RESET
–
V
VIH2
VIL1
VIL2
VOH
XIN and XOUT
VDD - 0.1
–
VDD= 3.0 to 5.5 V
0.2 VDD
Input low
voltage
Ports 0, 1, and
RESET
–
V
XIN and XOUT
0.1
–
IOH = - 10 mA
ports 0, 1, 2
VDD= 4.5 to 5.5 V VDD - 1.5 VDD - 0.4
VDD= 4.5 to 5.5 V
Output high
voltage
V
V
VOL
IOL = 25 mA
port 0, 1, and 2
Output low
voltage
–
0.4
2.0
14-2
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-2. DC Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ILIH1
All inputs except ILIH2 VIN = VDD
Input high leakage
current
–
–
1
uA
ILIH2
ILIL1
XIN, XOUT
VIN = VDD
VIN = 0 V
20
-1
Input low leakage
current
All inputs except
–
–
uA
ILIL2 and RESET
ILIL2
ILOH
XIN, XOUT
All outputs
VIN = 0 V
-20
2
VOUT = VDD
Output high
leakage current
–
–
–
–
uA
uA
kW
ILOL
RP
VOUT = 0 V
VDD = 5 V
Output low
leakage current
All outputs
-2
VIN = 0 V
Ports 0-2
Pull-up resistors
Supply current
30
47
70
VDD = 5 V
100
–
200
11
350
20
RESET
IDD1
IDD2
IDD3
Run mode
16 MHz CPU clock
mA
VDD = 5V ± 10%
VDD = 3.3 V
8 MHz CPU clock
3
5
6
8
Idle mode
16 MHz CPU clock
–
–
VDD = 5V ± 10%
VDD = 3.3 V
8 MHz CPU clock
Stop mode
0.7
65
45
2.5
100
80
uA
VDD = 5V ± 10%
VDD = 3.3 V
NOTE: D.C electrical values for supply current (I , to I
) do not include current drawn through internal pull-up
DD3
DD
resisters, output port drive current and ADC module.
14-3
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-3. AC Electrical Characteristics
°
°
(TA = –40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
tINTH
tINTL
tRSL
Conditions
Min
Typ
Max
Unit
,
Interrupt input
high, low width
–
200
–
ns
INT0, INT1
VDD = 5V ± 10%
–
1
–
us
RESET input
Input
low width
VDD = 5V ± 10%
tINTL
tRSL
tINTH
0.8 VDD
0.2 VDD
Figure 14-1. Input Timing Measurement Points
14-4
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-4. Oscillator Characteristics
°
°
(T = - 40 C to + 85 C)
A
Oscillator
Clock Circuit
Test Condition
VDD = 4.5 to 5.5 V
Min
Typ
Max
Unit
Main crystal or
ceramic
1
1
–
–
16
8
MHz
XIN
XOUT
VDD = 3.0 to 4.5 V
C1
C2
External clock
RC oscillator
1
1
–
–
16
8
XIN
XOUT
VDD = 4.5 to 5.5 V
VDD = 3.0 to 4.5 V
–
–
4
2
–
–
VDD = 5 V, R = 10 KW
VDD = 3 V, R = 22 KW
XIN
XOUT
R
Table 14-5. Oscillation Stabilization Time
(T = - 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
°
°
A
Oscillator
Main crystal
Main ceramic
Test Condition
Min
–
Typ
Max
Unit
fOSC > 1.0 MHz
–
–
20
10
ms
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.
XIN input high and low width (tXH, tXL)
–
External clock
(main system)
25
–
–
216/fOSC
–
500
–
ns
tWAIT when released by a reset (1)
Oscillator
stabilization
ms
tWAIT when released by an interrupt (2)
wait time
–
–
NOTES:
1.
f
is the oscillator frequency.
OSC
t
2. The duration of the oscillator stabilization wait time,
settings in the basic timer control register, BTCON.
, when it is released by an interrupt is determined by the
WAIT
14-5
ELECTRICAL DATA
S3C9432/C9434/P9434
CPU Clock
16MHz
8MHz
4MHz
3MHz
2MHz
1MHz
1
2
2.73
4
5 5.5 6
7
Supply Voltage (V)
Figure 14-2. Operating Voltage Range
VOUT
VDD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
VIN
A
B
C
D
0.3 VDD
0.7 VDD
Figure 14-3. Schmitt Trigger Input Characteristics Diagram
14-6
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-6. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
A
Parameter
Symbol
Conditions
Stop mode
Min
Typ
Max
Unit
VDDDR
Data retention
supply voltage
2.0
–
5.5
V
IDDDR
Stop mode; VDDDR = 2.0 V
Data retention
supply current
–
0.1
5
uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Reset
Occurs
Oscillation
Stabilization Time
Stop Mode
Normal
Operating
Data Retention Mode
Mode
VDD
VDDDR
Execution Of
Stop Instrction
RESET
0.8 VDD
0.2 VDD
tWAIT
NOTE: tWAIT is the same as 4096 x 16 x 1/fosc
Figure 14-4. Stop Mode Release Timing When Initiated by a RESET
14-7
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-7. A/D Converter Electrical Characteristics
°
°
(T = - 40 C to + 85 C, VDD = 3.0 V to 5.5 V, VSS = 0 V)
A
Parameter
Symbol
Test Conditions
VDD = 5.12 V
Min
Typ
Max
Unit
Total accuracy
–
–
–
LSB
± 3
CPU clock = 10 MHz
AVREF = 5.12 V
AVSS = 0 V
Integral linearity
error
ILE
DLE
–
–
–
–
± 2
Differential
linearity error
–
–
± 1
± 1
Offset error of
top
EOT
EOB
tCON
VIAN
RAN
–
–
–
± 3
Offset error of
bottom
–
± 1
± 2
fOSC = 10 MHz
50x4/ fOSC
Conversion
time (1)
–
–
AVREF
–
ms
V
AVSS
2
Analog input
voltage
–
–
–
–
–
–
1
Analog input
impedance
–
MW
V
AVREF
AVSS
IADIN
IADC
VDD
VSS + 0.3
10
ADC reference
voltage
–
3.0
VSS
–
ADC reference
ground
–
V
AVREF = VDD = 5 V
Analog input
current
mA
mA
AVREF = VDD = 5 V
Analog block
current (2)
3
conversion time = 20 ms
AVREF = VDD = 3 V
0.5
1.5
mA
nA
conversion time = 20 ms
AVREF = VDD = 5 V
100
500
when power down mode
NOTES:
1. “Conversion time” is the time required from the moment a conversion operation starts until it ends.
2. is operating current during A/D conversion.
I
ADC
14-8
S3C9432/C9434/P9434
ELECTRICAL DATA
Table 14-8. LVD Circuit Characteristics
°
°
(T = - 40 C to + 85 C, VDD = 3.0 V to 5.5V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VDDH
Power-on reset
voltage high
3.0
5.5
V
VDDL
tr
Power-on reset
voltage low
0
2.6
3.0
V
(note)
Power supply
voltage rise time
10
0.5
us
toff
Power supply
voltage off time
sec
uA
uA
IDDPR
Power-on reset
circuit
65
45
100
80
VDD = 5 V ± 10 %
VDD = 3 V
consumption
current
16
NOTE: Oscillation stabilization time = 2 /fx (= 6.55 ms at fx = 10 MHz)
VDD
VDDH
VDDL
tOFF
tR
Figure 14-5. LVD Reset Timing
14-9
ELECTRICAL DATA
S3C9432/C9434/P9434
Table 14-9. Serial I/O Timing Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
SCK Cycle Time
Symbol
Conditions
Min
1000
Typ
Max
Unit
tCKY
–
–
ns
External SCK source
Internal SCK source
External SCK source
Internal SCK source
External SCK source
Internal SCK source
External SCK source
Internal SCK source
External SCK source
Internal SCK source
1000
tKH, tKL
500
–
–
–
–
–
–
–
SCK High, Low Width
tKCY/2 – 50
tSIK
250
250
400
400
–
SI Setup Time to SCK Low
SI Hold Time to SCK High
Output Delay for SCK to SO
tKSI
tKSO
300
250
NOTE: "SCK" means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output.
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
Input
tKSO
SO
Output Data
Figure 14-6. Serial Data Transfer Timing
14-10
S3C9432/C9434/P9434
ELECTRICAL DATA
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
fx = 16 MHz
fx = 10 MHz
fx = 8 MHz
0.0
1.0
2.0
3.0
4.0
5.0
VDD (V)
Figure 14-7. IDD1 vs VDD
14-11
ELECTRICAL DATA
S3C9432/C9434/P9434
VDD = 5.5 V
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
VDD = 5.0 V
VDD = 4.5 V
0.0
1.0
2.0
3.0
4.0
5.0
VOL (V)
Figure 14-8. IOL vs VOL
14-12
S3C9432/C9434/P9434
ELECTRICAL DATA
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
VDD = 5.5 V
VDD = 5.0 V
VDD = 4.5 V
0.0
1.0
2.0
3.0
4.0
5.0
VOH (V)
Figure 14-9. IOH vs VOH
14-13
S3C9432/C9434/P9434
MECHANICAL DATA
15 MECHANICAL DATA
OVERVIEW
The S3C9432/C9434 is available in a 20-pin SDIP package (Samsung: 20-DIP-300A), a 20-pin SOP package
(Samsung: 20-SOP-375), a 18-pin DIP package (Samsung: 18-DIP-300A). Package dimensions are shown in
Figure 15-1, 15-2, and 15-3.
#20
#11
0-15
20-DIP-300A
#1
#10
26.80 MAX
26.40 ± 0.20
0.46 ±
0.10
1.52 ±
0.10
2.54
(1.77)
NOTE: Dimensions are in millimeters.
Figure 15-1. 20-DIP-300A Package Dimensions
15-1
MECHANICAL DATA
S3C9432/C9434/P9434
0-8
#20
#11
20-SOP-375
+ 0.10
0.203 - 0.05
#1
#10
13.14 MAX
12.74 ± 0.20
0.10 MAX
1.27
(0.66)
+ 0.10
0.40 - 0.05
NOTE: Dimensions are in millimeters.
Figure 15-2. 20-SOP-375 Package Dimensions
15-2
S3C9432/C9434/P9434
MECHANICAL DATA
#18
#10
0-15
18-DIP-300A
#1
#9
23.35 MAX
22.95 ± 0.20
0.46 ±
0.10
1.52 ±
0.10
2.54
(1.32)
NOTE: Dimensions are in millimeters.
Figure 15-3. 18-DIP-300A Package Dimensions
15-3
MECHANICAL DATA
S3C9432/C9434/P9434
#16
#9
#1
#8
19.80
0.46
1.50
2.54
(0.81)
Figure 15-4. 16-DIP-300A Package Dimensions
15-4
S3C9432/C9434/P9434
S3P9434 OTP
16 S3P9434 OTP
OVERVIEW
The S3P9434 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9432/C9434 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9434 is fully compatible with the S3C9432/C9434, in function, in D.C. electrical characteristics, and in
pin configuration. Because of its simple programming requirements, the S3P9434 is ideal for use as an
evaluation chip for the S3C9432/C9434.
VDD/VDD
20
19
18
17
16
15
14
13
12
11
VSS/VSS
XIN
1
2
3
4
5
6
7
8
9
10
P0.3/INT1/SCLK
P1.0/ADC0/SDAT
P1.1/ADC1/SI
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CLO
AVREF
XOUT
VPP/TEST
P0.2/T0CK/INT0
P0.1/PWM
RESET /RESET
P0.0/BUZ
P2.0/SCK
P2.2
S3P9434
20-DIP
(Top View)
P2.1/SO
P2.3
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. Pin Assignment Diagram (20-Pin DIP Package)
16-1
S3P9434 OTP
S3C9432/C9434/P9434
VDD/VDD
20
19
18
17
16
15
14
13
12
11
VSS/VSS
XIN
1
2
3
4
5
6
7
8
9
10
P0.3/INT1/SCLK
P1.0/ADC0/SDAT
P1.1/ADC1/SI
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CLO
AVREF
XOUT
VPP/TEST
P0.2/T0CK/INT0
P0.1/PWM
RESET /RESET
P0.0/BUZ
P2.0/SCK
P2.2
S3P9434
20-SOP
(Top View)
P2.1/SO
P2.3
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. Pin Assignment Diagram (20-Pin SOP Package)
16-2
S3C9432/C9434/P9434
S3P9434 OTP
VDD/VDD
18
17
16
15
14
13
12
11
10
VSS/VSS
XIN
1
2
3
4
5
6
7
8
9
P0.3/INT1/SCLK
P1.0/ADC0/SDAT
P1.1/ADC1/SI
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CLO
AVREF
XOUT
VPP/TEST
S3C9432/C9434
P0.2/T0CK/INT0
P0.1/PWM
18-DIP
(Top View)
RESET /RESET
P0.0/BUZ
P2.1/SO
P2.0/SCK
NOTE:
The bolds indicate an OTP pin name.
Figure 16-3. Pin Assignment Diagram (18-Pin DIP Package)
16-3
S3P9434 OTP
S3C9432/C9434/P9434
VDD/VDD
16
15
14
13
12
11
10
9
VSS/VSS
XIN
1
2
3
4
5
6
7
8
P0.3/INT1/SCLK
P1.0/ADC0/SDAT
P1.1/ADC1/SI
P1.2/ADC2/SO
P1.3/ADC3/SCK
P1.4/ADC4/CLO
AVREF
XOUT
S3P9434
16-DIP
(Top View)
VPP/TEST
P0.2/T0CK/INT0
P0.1/PWM
RESET /RESET
P0.0/BUZ
NOTE:
The bolds indicate an OTP pin name.
Figure 16-4. Pin Assingment Diagram (16-Pin DIP Package)
16-4
S3C9432/C9434/P9434
Main Chip
S3P9434 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Pin Name
P0.3
Pin Name
Pin No.
I/O
Function
SDAT
SCLK
18 (20-pin)
16 (18-pin)
I/O
Serial data pin (output when reading, Input
when writing) Input and push-pull output
port can be assigned
P0.2
19 (20-pin)
17 (18-pin)
I
I
Serial clock pin (input only pin)
V
(TEST)
TEST
4
7
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
PP
I
I
Chip Initialization
RESET
RESET
V /V
DD SS
V
/V
20 (20-pin), 18 (18-pin)
1 (20-pin), 1 (18-pin)
Logic power supply pin.
DD SS
NOTE: ( ) means the SOP OTP pin number.
Table 16-2. Comparison of S3P9434 and S3C9432/C9434 Features
Characteristic
S3P9434
S3C9432/C9434
Program Memory
4 Kbyte EPROM
3.0 V to 5.5 V
2K/4K byte mask ROM
3.0 V to 5.5 V
Operating Voltage (V
)
DD
V
DD
= 5 V, V (TEST) = 12.5 V
PP
OTP Programming Mode
Pin Configuration
20 DIP/20 SOP/18 DIP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P9434, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
R/W
MODE
VPP
(TEST)
ADDRESS
(A15-A0)
REG/MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
EPROM program
EPROM verify
12.5 V
12.5 V
12.5 V
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-5
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