S3F9454XX-DH [SAMSUNG]
Microcontroller, 8-Bit, FLASH, SAM88RCRI CPU, 10MHz, CMOS, PDIP16;
| 型号： | S3F9454XX-DH |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, FLASH, SAM88RCRI CPU, 10MHz, CMOS, PDIP16 微控制器 光电二极管 |
| 文件： | 总190页 (文件大小：837K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
22-S3-C9444/F9444/C9454/F9454-200301
USER'S MANUAL
S3C9444/F9444/C9454/F9454
8-Bit CMOS
Microcontroller
Revision 2
S3C9444/F9444/C9454/F9454
8-BIT CMOS
MICROCONTROLLER
USER'S MANUAL
Revision 2
Important Notice
The information in this publication has been carefully
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and reasonable
attorney fees arising out of, either directly or
indirectly, any claim of personal injury or death that
may be associated with such unintended or
unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.
S3C9444/F9444/C9454/F9454 8-Bit CMOS Microcontroller
User's Manual, Revision 2
Publication Number: 22-S3-C9444/F9444/C9454/F9454-200301
© 2003 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BVQ1 Certificate No. FM9300). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 440-900
TEL: (0331) 209-1907
FAX: (0331) 209-1899
Home-Page URL: Http://www.samsungsemi.com/
Printed in the Republic of Korea
Preface
The S3C9444/F9444/C9454/F9454 Microcontroller User's Manual is designed for application designers and
programmers who are using the S3C9444/F9444/C9454/F9454 microcontroller for application development. It is
organized in two parts:
Part I Programming Model
Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, instruction set, and interrupt structure. It has six sections:
Chapter 1
Chapter 2
Chapter 3
Product Overview
Address Spaces
Addressing Modes
Chapter 4
Chapter 5
Chapter 6
Control Registers
Interrupt Structure
SAM88RCRI Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to the S3C9444/F9444/C9454/F9454 with a general
product description, and detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," explains the S3C9444/F9444/C9454/F9454 program and data memory, internal
register file, and mapped control registers, and explains how to address them. Chapter 2 also describes working
register addressing, as well as system and user-defined stack operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the six addressing modes that are supported by
the CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, "Interrupt Structure," describes the S3C9444/F9444/C9454/F9454 interrupt structure in detail and
further prepares you for additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for
all S3C9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed
descriptions of each instruction are presented in a standard format. Each instruction description includes one or
more practical examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the SAM88RCRI product family and are reading this manual for the first
time, we recommend that you first read chapter 1-3 carefully. Then, briefly look over the detailed information in
chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.
Part II contains detailed information about the peripheral components of the S3C9444/F9444/C9454/F9454
microcontrollers. Also included in Part II are electrical, mechanical, MTP, and development tools data. It has 10
chapters:
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Clock Circuit
RESET and Power-Down
I/O Ports
Basic Timer and Timer 0
8-bit PWM
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
A/D Converter
Electrical Data
Mechanical Data
S3F9444/F9454
Development Tools
Two order forms are included at the back of this manual to facilitate customer order
S3C9444/F9444/C9454/F9454 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection
Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales
Representative.
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
iii
Table of Contents
Part I — Programming Model
Chapter 1
Product Overview
SAM88RCRI Product Family ......................................................................................................................1-1
S3C9444/C9454 Microcontroller.................................................................................................................1-1
MTP............................................................................................................................................................1-1
Features .....................................................................................................................................................1-2
Block Diagram............................................................................................................................................1-3
Pin Assignments.........................................................................................................................................1-4
Pin Descriptions..........................................................................................................................................1-6
Pin Circuits .................................................................................................................................................1-7
Chapter 2
Address Spaces
Overview..........................................................................................................................................................................2-1
Program Memory (ROM)..............................................................................................................................................2-2
Register Architecture.....................................................................................................................................................2-5
Common Working Register Area (C0H–CFH)..........................................................................................................2-7
System Stack..................................................................................................................................................................2-8
Chapter 3
Addressing Modes
Overview..........................................................................................................................................................................3-1
Register Addressing Mode (R) ..........................................................................................................................3-2
Indirect Register Addressing Mode (IR)...........................................................................................................3-3
Indexed Addressing Mode (X) ...........................................................................................................................3-7
Direct Address Mode (DA)..................................................................................................................................3-10
Relative Address Mode (RA)..............................................................................................................................3-12
Immediate Mode (IM)...........................................................................................................................................3-12
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
v
Table of Contents (Continued)
Chapter 4
Control Registers
Overview.................................................................................................................................................... 4-1
Chapter 5
Interrupt Structure
Overview..........................................................................................................................................................................5-1
Interrupt Processing Control Points..................................................................................................................5-1
Enable/Disable Interrupt Instructions (EI, DI)..................................................................................................5-2
Interrupt Pending Function Types.....................................................................................................................5-2
Interrupt Priority....................................................................................................................................................5-2
Interrupt Source Service Sequence..................................................................................................................5-3
Interrupt Service Routines..................................................................................................................................5-3
Generating interrupt Vector Addresses............................................................................................................5-3
S3C9444/C9454 Interrupt Structure.................................................................................................................5-4
Chapter 6
SAM88RCRI Instruction Set
Overview..........................................................................................................................................................................6-1
Register Addressing ............................................................................................................................................6-1
Addressing Modes ...............................................................................................................................................6-1
Flags Register (FLAGS)......................................................................................................................................6-4
Flag Descriptions..................................................................................................................................................6-4
Instruction Set Notation.......................................................................................................................................6-5
Condition Codes...................................................................................................................................................6-9
Instruction Descriptions.......................................................................................................................................6-10
vi
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
Table of Contents (Continued)
Part II — Hardware Descriptions
Chapter 7
Clock Circuit
Overview..........................................................................................................................................................................7-1
Main Oscillator Logic ...........................................................................................................................................7-1
Clock Status During Power-Down Modes .......................................................................................................7-2
System Clock Control Register (CLKCON).....................................................................................................7-2
Chapter 8
RESET and Power-Down
System Reset..................................................................................................................................................................8-1
Overview................................................................................................................................................................8-1
Power-Down Modes ......................................................................................................................................................8-3
Stop Mode .............................................................................................................................................................8-3
Idle Mode ...............................................................................................................................................................8-3
Hardware Reset Values................................................................................................................................................8-4
Chapter 9
I/O Ports
Overview..........................................................................................................................................................................9-1
Port Data Registers..............................................................................................................................................9-2
Port 0 ......................................................................................................................................................................9-3
Port 1 ......................................................................................................................................................................9-7
Port 2 ......................................................................................................................................................................9-9
Chapter 10
Basic Timer and Timers
Module Overview............................................................................................................................................................10-1
Basic Timer (BT) ............................................................................................................................................................10-2
Basic Timer Control Register (BTCON)...........................................................................................................10-2
Basic Timer Function Description......................................................................................................................10-3
Timer 0.............................................................................................................................................................................10-7
Timer 0 Control Registers (T0CON) .................................................................................................................10-7
Timer 0 Function Description .............................................................................................................................10-8
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
vii
Table of Contents (Continued)
Chapter 11
8-Bit PWM
Overview..........................................................................................................................................................................11-1
Function description ......................................................................................................................................................11-1
PWM.......................................................................................................................................................................11-1
PWM Control Register (PWMCON)..................................................................................................................11-5
Chapter 12
A/D Converter
Overview..........................................................................................................................................................................12-1
Using A/D Pins for Standard digital Input ........................................................................................................12-2
A/D Converter Control Register (ADCON) ......................................................................................................12-2
Internal Reference Voltage Levels....................................................................................................................12-3
Conversion timing.................................................................................................................................................12-4
Internal A/D Conversion Procedure..................................................................................................................12-4
Chapter 13
Electrical Data
Overview.................................................................................................................................................... 13-1
Chapter 14
Mechanical Data
Overview.................................................................................................................................................... 14-1
Chapter 15
S3F9444/F9454 MTP
Overview..........................................................................................................................................................................15-1
Operating Mode Characteristics........................................................................................................................15-3
Chapter 16
Development Tools
Overview..........................................................................................................................................................................16-1
SHINE............................................................................................................................................... 16-1
SAMA Assembler .............................................................................................................................. 16-1
SASM86............................................................................................................................................ 16-1
HEX2ROM ........................................................................................................................................ 16-1
Target Boards ................................................................................................................................... 16-2
MTPs................................................................................................................................................. 16-2
TB9444/9454 Target Board............................................................................................................... 16-3
viii
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
List of Figures
Figure
Title
Page
Number
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
Block Diagram........................................................................................................................................1-3
Pin Assignment Diagram (20-Pin DIP/SOP Package)....................................................................1-4
Pin Assignment Diagram (16-Pin DIP Package) .............................................................................1-5
Pin Assignment Diagram (8-Pin DIP/SOP Package)......................................................................1-5
Pin Circuit Type A..................................................................................................................................1-7
Pin Circuit Type B..................................................................................................................................1-7
Pin Circuit Type C..................................................................................................................................1-7
Pin Circuit Type D..................................................................................................................................1-7
Pin Circuit Type E..................................................................................................................................1-8
Pin Circuit Type E-1 ..............................................................................................................................1-8
Pin Circuit Type E-2 ..............................................................................................................................1-9
2-1
2-2
2-3
2-4
2-5
Program Memory Address Space ......................................................................................................2-2
Smart Option...........................................................................................................................................2-3
Internal Register File Organization.....................................................................................................2-6
16-Bit Register Pairs .............................................................................................................................2-7
Stack Operations ...................................................................................................................................2-8
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Register Addressing..............................................................................................................................3-2
Working Register Addressing..............................................................................................................3-2
Indirect Register Addressing to Register File...................................................................................3-3
Indirect Register Addressing to Program Memory ..........................................................................3-4
Indirect Working Register Addressing to Register File...................................................................3-5
Indirect Working Register Addressing to Program or Data Memory............................................3-6
Indexed Addressing to Register File..................................................................................................3-7
Indexed Addressing to Program or Data Memory with Short Offset............................................3-8
Indexed Addressing to Program or Data Memory with Long Offset.............................................3-9
Direct Addressing for Load Instructions ............................................................................................3-10
Direct Addressing for Call and Jump Instructions............................................................................3-11
Relative Addressing ..............................................................................................................................3-12
Immediate Addressing..........................................................................................................................3-12
3-9
3-10
3-11
3-12
3-13
4-1
Register Description Format................................................................................................................4-4
5-1
5-2
5-3
S3C9-Series Interrupt Type.................................................................................................................5-1
Interrupt Function Diagram..................................................................................................................5-2
S3C9444/C9454 Interrupt Structure...................................................................................................5-4
6-1
System Flags Register (FLAGS) ........................................................................................................6-4
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
ix
List of Figures (Continued)
Figure
Title
Page
Number
Number
7-1
7-2
7-3
7-4
Main Oscillator Circuit (RC Oscillator with Internal Capacitor)......................................................7-1
Main Oscillator Circuit (Crystal/Ceramic Oscillator)........................................................................7-1
System Clock Control Register (CLKCON) ......................................................................................7-2
System Clock Circuit Diagram ............................................................................................................7-3
8-1
8-2
Reset Block Diagram ............................................................................................................................8-2
Timing for S3C9444/C9454 after RESET.........................................................................................8-2
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
Port Data Register Format...................................................................................................................9-2
Port 0 Circuit Diagram ..........................................................................................................................9-3
Port 0 Control Register (P0CONH, High Byte) ................................................................................9-4
Port 0 Control Register (P0CONL, Low Byte)..................................................................................9-5
Port 0 Interrupt Pending Registers (P0PND)....................................................................................9-6
Port 1 Circuit Diagram ..........................................................................................................................9-7
Port 1 Control Register (P1CON) .......................................................................................................9-8
Port 2 Circuit Diagram ..........................................................................................................................9-9
Port 2 Control Register (P2CONH, High Byte) ................................................................................9-10
Port 2 Control Register (P2CONL, Low byte) ..................................................................................9-11
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Basic Timer Control Register (BTCON) ............................................................................................10-2
Oscillation Stabilization Time on RESET..........................................................................................10-4
Oscillation Stabilization Time on STOP Mode Release .................................................................10-5
Timer 0 Control Registers (T0CON) ..................................................................................................10-7
Simplified Timer 0 Function Diagram (Interval Timer Mode).........................................................10-8
Timer 0 Timing Diagram.......................................................................................................................10-9
Basic Timer and Timer 0 Block Diagram...........................................................................................10-10
11-1
11-2
11-3
11-4
8-Bit PWM Basic Waveform ................................................................................................................11-3
8-Bit Extended PWM Waveform.........................................................................................................11-4
PWM Control Register (PWMCON)...................................................................................................11-5
PWM Functional Block Diagram.........................................................................................................11-6
12-1
12-2
12-3
12-4
12-5
A/D Converter Control Register (ADCON)........................................................................................12-2
A/D Converter Circuit Diagram ...........................................................................................................12-3
A/D Converter Data Register (ADDATAH/L)....................................................................................12-3
A/D Converter Timing Diagram...........................................................................................................12-4
Recommended A/D Converter Circuit for Highest Absolute Accuracy........................................12-5
x
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
List of Figures (Concluded)
Figure
Title
Page
Number
Number
13-1
13-2
13-3
13-4
13-5
Input Timing Measurement Points......................................................................................................13-4
Operating Voltage Range.....................................................................................................................13-6
Schmitt Trigger Input Characteristics Diagram ................................................................................13-6
Stop Mode Release Timing When Initiated by a RESET...............................................................13-7
LVR Reset Timing..................................................................................................................................13-9
14-1
14-2
14-3
14-4
14-5
20-DIP-300A Package Dimensions....................................................................................................14-1
20-SOP-375 Package Dimensions.....................................................................................................14-2
16-DIP-300A Package Dimensions....................................................................................................14-3
8-DIP-300 Package Dimensions.........................................................................................................14-4
8-SOP-225 Package Dimensions.......................................................................................................14-5
15-1
15-2
15-3
Pin Assignment Diagram (20-Pin Package) .....................................................................................15-1
Pin Assignment Diagram (16-Pin Package) .....................................................................................15-2
Pin Assignment Diagram (8-Pin Package)........................................................................................15-2
16-1
16-2
16-3
16-4
16-5
SMDS Product Configuration (SMDS2+)..........................................................................................16-2
TB9444/9454 Target Board Configuration........................................................................................16-3
DIP Switch for Smart Option................................................................................................................16-5
20-Pin Connector for TB9444/9454 ...................................................................................................16-6
S3C9444/C9454 Probe Adapter for 20-DIP Package.....................................................................16-6
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
xi
List of Tables
Table
Title
Page
Number
Number
1-1
2-1
4-1
S3C9454 Pin Descriptions...................................................................................................................1-6
Register Type Summary.......................................................................................................................2-5
System and Peripheral control Registers..........................................................................................4-2
6-1
6-2
6-3
6-4
6-5
6-6
Instruction Group Summary.................................................................................................................6-2
Flag Notation Conventions...................................................................................................................6-5
Instruction Set Symbols........................................................................................................................6-5
Instruction Notation Conventions........................................................................................................6-6
Opcode Quick Reference.....................................................................................................................6-7
Condition Codes ....................................................................................................................................6-9
8-1
Register Values after a Reset .............................................................................................................8-4
9-1
9-2
S3C9444/C9454 Port Configuration Overview.................................................................................9-1
Port Data Register Summary...............................................................................................................9-2
11-1
11-2
PWM Control and Data Registers ......................................................................................................11-2
PWM output "stretch" Values for Extension Data Register (PWMDATA.1–.0)..........................11-3
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
Absolute Maximum Ratings.................................................................................................................13-2
DC Electrical Characteristics...............................................................................................................13-3
AC Electrical Characteristics...............................................................................................................13-4
Oscillator Characteristics......................................................................................................................13-5
Oscillation Stabilization Time...............................................................................................................13-5
Data Retention Supply Voltage in Stop Mode..................................................................................13-7
A/D Converter Electrical Characteristics...........................................................................................13-8
LVD Circuit Characteristics..................................................................................................................13-9
15-1
15-2
15-3
Descriptions of Pins Used to Read/Write the Flash ROM..............................................................15-3
Comparison of S3F9444/F9454 and S3C9444/C9454 Features..................................................15-3
Operating Mode Selection Criteria .....................................................................................................15-3
16-1
16-2
16-3
Power Selection Settings for TB9444/9454......................................................................................16-4
The SMDS2+ Tool Selection Setting .................................................................................................16-4
Using Single Header Pins as the Input Path for External Trigger Sources ................................16-5
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
xiii
List of Programming Tips
Description
Chapter 2:
Page
Number
Address Spaces
Smart Option Setting.....................................................................................................................................................2-4
Addressing the Common Working Register Area....................................................................................................2-7
Standard Stack Operations Using PUSH and POP.................................................................................................2-9
Chapter 8:
RESET and Power-Down
Sample S3C9454 Initialization Routine......................................................................................................................8-6
Chapter 10:
Basic Timer and Timer 0
Configuring the Basic Timer.........................................................................................................................................10-6
Configuring Timer 0 (Interval Mode)...........................................................................................................................10-11
Chapter 11:
8-Bit PWM
Programming the PWM Module to Sample Specifications.....................................................................................11-7
Chapter 12:
A/D Converter
Configuring A/D Converter ...........................................................................................................................................12-6
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
xv
List of Register Descriptions
Register
Identifier
Full Register Name
Page
Number
ADCON
BTCON
CLKCON
FLAGS
A/D Converter Control Register................................................................................4-5
Basic Timer Control Register....................................................................................4-6
System Clock Control Register.................................................................................4-7
System Flags Register .............................................................................................4-8
Port 0 Control Register (High Byte).....................................................................................4-9
Port 0 Control Register (Low Byte)......................................................................................4-10
Port 0 Interrupt Pending Register .............................................................................4-11
Port 1 Control Register.............................................................................................4-12
Port 2 Control Register (High Byte).....................................................................................4-13
Port 2 Control Register (Low Byte)......................................................................................4-14
PWM Control Register..............................................................................................4-15
STOP Mode Control Register...................................................................................4-16
System Mode Register .............................................................................................4-16
Timer 0 Control Register ..........................................................................................4-17
P0CONH
P0CONL
P0PND
P1CON
P2CONH
P2CONL
PWMCON
STOPCON
SYM
T0CON
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
xvii
List of Instruction Descriptions
Instruction
Mnemonic
Full Instruction Name
Page
Number
ADC
ADD
AND
CALL
CCF
Add with Carry..........................................................................................................6-11
Add...........................................................................................................................6-12
Logical AND .............................................................................................................6-13
Call Procedure..........................................................................................................6-14
Complement Carry Flag ...........................................................................................6-15
Clear.........................................................................................................................6-16
Complement.............................................................................................................6-17
Compare...................................................................................................................6-18
Decrement................................................................................................................6-19
Disable Interrupts .....................................................................................................6-20
Enable Interrupts ......................................................................................................6-21
Idle Operation...........................................................................................................6-22
Increment .................................................................................................................6-23
Interrupt Return ........................................................................................................6-24
Jump ........................................................................................................................6-25
Jump Relative...........................................................................................................6-26
Load .........................................................................................................................6-27
Load Memory ...........................................................................................................6-29
Load Memory and Decrement ..................................................................................6-31
Load Memory and Increment....................................................................................6-32
CLR
COM
CP
DEC
DI
EI
IDLE
INC
IRET
JP
JR
LD
LDC/LDE
LDCD/LDED
LDCI/LDEI
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
xix
List of Instruction Descriptions (Continued)
Instruction
Mnemonic
Full Instruction Name
Page
Number
NOP
OR
No Operation ........................................................................................................... 6-33
Logical OR............................................................................................................... 6-34
Pop From Stack....................................................................................................... 6-35
Push To Stack ......................................................................................................... 6-36
Reset Carry Flag...................................................................................................... 6-37
Return...................................................................................................................... 6-38
Rotate Left............................................................................................................... 6-39
Rotate Left Through Carry ....................................................................................... 6-40
Rotate Right............................................................................................................. 6-41
Rotate Right Through Carry..................................................................................... 6-42
Subtract With Carry ................................................................................................. 6-43
Set Carry Flag.......................................................................................................... 6-44
Shift Right Arithmetic ............................................................................................... 6-45
Stop Operation......................................................................................................... 6-46
Subtract ................................................................................................................... 6-47
Test Complement Under Mask ................................................................................ 6-48
Test Under Mask ..................................................................................................... 6-49
Logical Exclusive OR............................................................................................... 6-50
POP
PUSH
RCF
RET
RL
RLC
RR
RRC
SBC
SCF
SRA
STOP
SUB
TCM
TM
XOR
xx
S3C9444/F9444/C9454/F9454 MICROCONTROLLER
S3C9444/F9444/C9454/F9454
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9444/C9454 MICROCONTROLLER
The S3C9444/C9454 single-chip 8-bit microcontroller is designed for useful A/D converter , SIO application field.
The S3C9444/C9454 uses powerful SAM88RCRI CPU and S3C9444/C9454 architecture. The internal register
file is logically expanded to increase the on-chip register space.
The S3C9444/C9454 has 2K/4K bytes of on-chip program ROM and 208 bytes of RAM. The S3C9444/C9454 is a
versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring
simple timer/counter, PWM. In addition, the S3C9444/C9454’s advanced CMOS technology provides for low
power consumption and wide operating voltage range.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Three configurable I/O ports (18 pins)
— Four interrupt sources with one vector and one interrupt level
— One 8-bit timer/counter with time interval mode
— Analog to digital converter with nine input channels and 10-bit resolution
— One 8-bit PWM output
The S3C9444/C9454 microcontroller is ideal for use in a wide range of electronic applications requiring simple
timer/counter, PWM, ADC. S3C9454 is available in a 20/16-pin DIP and a 20-pin SOP package. S3C9454 is
available in a 8-pin and a 8-pin SOP package.
MTP
The S3F9444/F9454 is an MTP (Multi Time Programmable) version of the S3C9444/C9454 microcontroller. The
S3F9444/F9454 has on-chip 4-Kbyte multi-time programmable flash ROM instead of masked ROM. The
S3F9444/F9454 is fully compatible with the S3C9444/C9454, in function, in D.C. electrical characteristics and in
pin configuration.
1-1
PRODUCT OVERVIEW
S3C9444/F9444/C9454/F9454
FEATURES
CPU
Timer/Counters
•
•
SAM88RCRI CPU core
•
•
One 8-bit basic timer for watchdog function
The SAM88RCRI core is low-end version of the
current SAM87 core.
One 8-bit timer/counter with time interval modes
A/D Converter
Memory
•
•
Nine analog input pins
10-bit conversion resolution
•
•
2/4-Kbyte internal program memory
208-byte general purpose register area
Oscillation Frequency
Instruction Set
•
•
•
1 MHz to 10 MHz external crystal oscillator
Maximum 10 MHz CPU clock
•
•
41 instructions
The SAM88RCRI core provides all the SAM87
core instruction except the word-oriented
instruction, multiplication, division, and some
one-byte instruction.
Internal RC: 3.2 MHz (typ.), 0.5 MHz (typ.) in
VDD = 5 V
Operating Temperature Range
Instruction Execution Time
400 ns at 10 MHz f (minimum)
° °
– 25 C to + 85 C
•
•
OSC
Operating Voltage Range
2.0 V (LVR Level) to 5.5 V
Interrupts
•
•
•
4 interrupt sources with one vector
One interrupt level
Smart Option
Package Types
General I/O
•
S3C9454:
•
•
Three I/O ports (Max 18 pins)
Bit programmable ports
–
–
–
20-DIP-300A
20-SOP-375
16-DIP-300A
8-bit High-speed PWM
•
S3C9444
–
–
8-DIP-300
8-SOP-225
•
•
8-bit PWM 1-ch (Max: 156 kHz)
6-bit base + 2-bit extension
Built-in reset Circuit
•
Low voltage detector for safe reset
1-2
S3C9444/F9444/C9454/F9454
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
X
IN
OSC
X
OUT
Port 0
Port 1
Port 2
Port I/O and
Interrupt Control
P0.7/ADC7
Basic
Timer
P1.0
P1.1
P1.2
Timer 0
ADC
88RCRI
SAMRI CPU
ADC0-ADC8
P0.6/PWM
P2.0/T0
P2.1
2 KB ROM
4 KB ROM
208 Byte
Register file
PWM
P2.6
NOTE:
P1.2 is used as input only
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9444/F9444/C9454/F9454
PIN ASSIGNMENTS
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
X
IN/P1.0
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
X
OUT/P1.1
RESET/P1.2
P2.0/T0
P2.1
P0.3/ADC3
S3C9454
P0.4/ADC4
(20-DIP-300A/
20-SOP-375)
P2.2
P0.5/ADC5
P2.3
P0.6/ADC6/PWM
P0.7/ADC7
P2.4
P2.5
P2.6/ADC8/CLO
Figure 1-2. Pin Assignment Diagram (20-Pin DIP/SOP Package)
1-4
S3C9444/F9444/C9454/F9454
PRODUCT OVERVIEW
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
X
IN/P1.0
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
X
OUT/P1.1
S3C9454
RESET/P1.2
P2.0/T0
P2.1
P0.3/ADC3
(16-DIP-300A)
P0.4/ADC4
P2.2
P0.5/ADC5
P2.3
P0.6/ADC6/PWM
Figure 1-3. Pin Assignment Diagram (16-Pin DIP Package)
V
SS
1
2
3
4
8
7
6
5
VDD
S3C9444
X
IN/P1.0
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
(8-DIP-300
8-SOP-225)
X
OUT/P1.1
RESET/P1.2
Figure 1-4. Pin Assignment Diagram (8-Pin DIP/SOP Package)
1-5
PRODUCT OVERVIEW
S3C9444/F9444/C9454/F9454
PIN DESCRIPTIONS
Table 1-1. S3C9454 Pin Descriptions
Pin Description
Pin
Name
In/Out
Pin
Type
Share
Pins
P0.0–P0.7
I/O
Bit-programmable I/O port for Schmitt trigger input or
push-pull output. Pull-up resistors are assignable by
software. Port0 pins can also be used as A/D converter
input, PWM output or external interrupt input.
E-1
ADC0–ADC7
INT0/INT1
PWM
XIN, XOUT
P1.0–P1.1
I/O
Bit-programmable I/O port for Schmitt trigger input or
push-pull, open-drain output. Pull-up resistors or pull-down
resistors are assignable by software.
E-2
P1.2
I
Schmitt trigger input port
B
E
RESET
P2.0–P2.6
I/O
Bit-programmable I/O port for Schmitt trigger input or push-
pull, open-drain output. Pull-up resistors are assignable by
software.
–
ADC8/CLO
T0
E-1
B
XIN, XOUT
–
Crystal/Ceramic, or RC oscillator signal for system clock.
P1.0–P1.1
RESET
I
Internal LVR or External RESET
P1.2
–
VDD, VSS
–
Voltage input pin and ground
CLO
O
I
System clock output port
External interrupt input port
8-Bit high speed PWM output
Timer0 match output
E-1
E-1
E-1
E-1
P2.6
P0.0, P0.1
P0.6
INT0–INT1
PWM
O
O
I
T0
P2.0
ADC0–ADC8
A/D converter input
E-1
E
P0.0–P0.7
P2.6
1-6
S3C9444/F9444/C9454/F9454
PRODUCT OVERVIEW
PIN CIRCUITS
VDD
P-channel
N-channel
IN
IN
Figure 1-6. Pin Circuit Type B
Figure 1-5. Pin Circuit Type A
VDD
VDD
Pull-up
Enable
Data
Out
Data
Circuit
Type C
I/O
Output
DIsable
Output
Disable
Digital
Input
Figure 1-7. Pin Circuit Type C
Figure 1-8. Pin Circuit Type D
1-7
PRODUCT OVERVIEW
S3C9444/F9444/C9454/F9454
VDD
Open-drain
Enable
Pull-up
enable
P2CONH
P2CONL
VDD
P-CH
N-CH
Alternative
M
U
X
Data
Output
I/O
P2.x
Output Disable
(Input Mode)
Digital
Input
Analog Input
Enable
ADC
Figure 1-9. Pin Circuit Type E
VDD
Pull-up
enable
VDD
P0CONH
P-CH
N-CH
Alternative
M
U
X
Data
Output
I/O
P0.x
Output Disable
(Input Mode)
Digital Input
Interrupt Input
Analog Input
Enable
ADC
Figure 1-10. Pin Circuit Type E-1
1-8
S3C9444/F9444/C9454/F9454
PRODUCT OVERVIEW
VDD
Open-drain
Enable
Pull-up
enable
VDD
P1.x
I/O
Output Disable
(Input Mode)
Pull-down
enable
Digital
Input
XIN
XOUT
Figure 1-11. Pin Circuit Type E-2
1-9
S3C9444/F9444/C9454/F9454
ADDRESS SPACES
2
ADDRESS SPACES
OVERVIEW
The S3C9444/C9454 microcontroller has two kinds of address space:
— Internal program memory (ROM)
— Internal register file
A 12-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the internal register file.
The S3C9444/C9454 have 2-Kbytes or 4-Kbytes of mask-programmable on-chip program memory: which is
configured as the Internal ROM mode, all of the 4-Kbyte internal program memory is used.
The S3C9444/C9454 microcontroller has 208 general-purpose registers in its internal register file. Twenty-six
bytes in the register file are mapped for system and peripheral control functions.
2-1
ADDRESS SPACES
S3C9444/F9444/C9454/F9454
PROGRAM MEMORY (ROM)
Normal Operating Mode
The S3C9444/C9454 have 2-Kbytes (locations 0H–07FFH) or 4-Kbytes (locations 0H–0FFFH) of internal mask-
programmable program memory.
The first 2-bytes of the ROM (0000H–0001H) are interrupt vector address.
Unused locations (0002H–00FFH except 3CH, 3DH, 3EH, 3FH) can be used as normal program memory.
3CH, 3DH, 3EH, 3FH is used smart option ROM cell.
The program reset address in the ROM is 0100H.
(Decimal)
4.095
(HEX)
1000H
4-Kbyte
Program
Memory
Area
2,047
07FFH
2-Kbyte
Program
Memory
Area
Program Start
256
0100H
64
60
2
0040H
003CH
0002H
0001H
0000H
Smart option ROM cell
Interrupt
Vector
1
0
Figure 2-1. Program Memory Address Space
2-2
S3C9444/F9444/C9454/F9454
ADDRESS SPACES
Smart Option
Smart option is the ROM option for starting condition of the chip.
The ROM addresses used by smart option are from 003CH to 003FH. The S3C9442/C9444/C9452/9454 only use
003EH, 003FH. Not used ROM address 003CH, 003DH should be initialized to be initialized to 00H. The default
value of ROM is FFH (LVR enable, internal RC oscillator).
ROM Address: 003CH
MSB
MSB
.7
.7
.6
.6
.5
.4
.3
.2
.1
.1
.0
.0
LSB
LSB
Must be initialized to 00H.
ROM Address: 003DH
.5
.4
.3
.2
Must be initialized to 00H.
ROM Address: 003EH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
LVR enable/disable bit:
0 = Disable
Not used
1 = Enable
LVR level selection bits:
11001 = 2.3 V
10010 = 3.0 V
01100 = 3.9 V
ROM Address: 003FH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used.
Oscillator selection bits:
00 = External crystal/
ceramic oscillator
01 = External RC
10 = Internal RC (0.5 MHz in VDD = 5 V)
11 = Internal RC (3.2 MHz in VDD = 5 V)
NOTES:
1. When you use external oscillator, P1.0, P1.1 must be set to output
port to prevent current consumption.
2. The value of unused bits of 3EH, 3FH is don't care.
3. When LVR is enabled, LVR level must be set to appropriate value,
not default value.
Figure 2-2. Smart Option
2-3
ADDRESS SPACES
S3C9444/F9444/C9454/F9454
+
PROGRAMMING TIP — Smart Option Setting
;
<< Interrupt Vector Address >>
ORG
0000H
Vector
00H, INT_9454
; S3C9454 has only one interrupt vector
;
;
<< Smart Option Setting >>
ORG
DB
003CH
00H
; 003CH, must be initialized to 0.
; 003DH, must be initialized to 0.
; 003EH, enable LVR (2.3 V)
DB
00H
DB
DB
0E7H
03H
; 003FH, Internal RC (3.2 MHz in V = 5 V)
DD
<< Reset >>
ORG
0100H
RESET;
DI
•
•
•
2-4
S3C9444/F9444/C9454/F9454
ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 64-bytes of the S3C9444/C9454's internal register file are addressed as working registers, system
control registers and peripheral control registers. The lower 192-bytes of internal register file(00H–BFH) is called
the general purpose register space. 234 registers in this space can be accessed; 208 are available for general-
purpose use.
For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by
additional register pages at the general purpose register space (00H–BFH: page0). This register file expansion is
not implemented in the S3C9444/C9454, however.
The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in
Table 2-1.
Table 2-1. Register Type Summary
Register Type
Number of Bytes
CPU and system control registers
11
15
Peripheral, I/O, and clock control and data registers
General-purpose registers (including the 16-bit
common working register area)
208
Total Addressable Bytes
234
2-5
ADDRESS SPACES
S3C9444/F9444/C9454/F9454
FFH
Peripheral Control
Registers
E0H
DFH
64 Bytes of
Common Area
System Control
Registers
D0H
CFH
Working Registers
C0H
BFH
General Purpose
Register File
and Stack Area
192 Bytes
00H
Figure 2-3. Internal Register File Organization
2-6
S3C9444/F9444/C9454/F9454
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
This16-byte address range is called common area. That is, locations in this area can be used as working registers
by operations that address any location on any page in the register file. Typically, these working registers serve as
temporary buffers for data operations between different pages. However, because the S3C9444/C9454 uses only
page 0, you can use the common area for any internal data operation.
The Register (R) addressing mode can be used to access this area
Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the
address of the first 8-bit register is always an even number and the address of the next register is an odd number.
The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant
byte is always stored in the next (+ 1) odd-numbered register.
MSB
Rn
LSB
n = Even address
Rn+1
Figure 2-4. 16-Bit Register Pairs
+
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples: 1. LD
0C2H,40H
; Invalid addressing mode!
Use working register addressing instead:
LD
R2,40H
; R2 (C2H) ¬ the value in location 40H
2. ADD
0C3H,#45H
; Invalid addressing mode!
Use working register addressing instead:
ADD R3,#45H ; R3 (C3H) ¬ R3 + 45H
2-7
ADDRESS SPACES
S3C9444/F9444/C9454/F9454
SYSTEM STACK
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations. The S3C9444/C9454 architecture supports
stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address is always decremented before a push operation and incremented after a
pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in
Figure 2-4.
High Address
PCL
PCL
PCH
Top of
PCH
Top of
stack
stack
Flags
Stack contents
after a call
instruction
Stack contents
after an
Low Address
interrupt
Figure 2-5. Stack Operations
Stack Pointer (SP)
Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,
the SP value is undetermined.
Because only internal memory space is implemented in the S3C9444/C9454, the SP must be initialized to an 8-bit
value in the range 00H–0C0H.
NOTE
In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This
means that a Stack Pointer access invalid stack area. We recommend that a stack pointer is initialized to
C0H to set upper address of stack to BFH.
2-8
S3C9444/F9444/C9454/F9454
ADDRESS SPACES
+
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD
SP,#0C0H
; SP ¬ C0H (Normally, the SP is set to C0H by the
; initialization routine)
•
•
•
PUSH
PUSH
PUSH
PUSH
•
SYM
R15
20H
R3
; Stack address 0BFH ¬ SYM
; Stack address 0BEH ¬ R15
; Stack address 0BDH ¬ 20H
; Stack address 0BCH ¬ R3
•
•
POP
POP
POP
POP
R3
; R3 ¬ Stack address 0BCH
; 20H ¬ Stack address 0BDH
; R15 ¬ Stack address 0BEH
; SYM ¬ Stack address 0BFH
20H
R15
SYM
2-9
S3C9444/F9444/C9454/F9454
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are
available for each instruction. The addressing modes and their symbols are as follows:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Relative Address (RA)
— Immediate (IM)
3-1
ADDRESSING MODES
S3C9444/F9444/C9454/F9454
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register
addressing differs from Register addressing because it uses an 16-byte working register space in the register file
and an 4-bit register within that space (see Figure 3-2).
Program Memory
Register File
OPERAND
8-Bit Register
File Address
dst
Point to one
register in register
file
OPCODE
One-Operand
Instruction
Value used in
Instruction Execution
(Example)
Sample Instruction:
DEC
CNTR
;
Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File
MSB point to
RP0 to RP1
RP0 or RP1
Selected
RP points to
start of
Program Memory
4-Bit
Working Register
working
register block
3 LSBs
dst
src
Point to the
working register
(1 of 8)
OPERAND
OPCODE
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD R1, R2
;
Where R1 and R2 are registers in the currently selected
working register area.
Figure 3-2. Working Register Addressing
3-2
S3C9444/F9444/C9454/F9454
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location.
Program Memory
Register File
ADDRESS
8-Bit Register
File Address
dst
Point to one
register in register
file
OPCODE
One-Operand
Instruction (Example)
Address of operand
used by instruction
OPERAND
Value used in
instruction execution
Sample Instruction:
RL
@SHIFT
;
Where SHIFT is the label of an 8-bit register ddress
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
S3C9444/F9444/C9454/F9454
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory
Example
REGISTER
PAIR
dst
Instruction
References
Program
Point to
register pair
OPCODE
16-bit
Memory
address
points to
program
memory
Program Memory
OPERAND
Value used in
instruction
Sample Instructions:
CALL
JP
@RR2
@RR2
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
S3C9444/F9444/C9454/F9454
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
CFH
.
.
.
.
Program Memory
4-Bit
4 LSBs
Working
Register
Address
OPERAND
dst
src
Point to the
working register
(1 of 16)
OPCODE
C0H
Sample Instruction:
OR R6, @R2
Value used in
instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C9444/F9444/C9454/F9454
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
CFH
.
.
.
.
Program Memory
4-Bit Working
Register Address
dst
src
Register
Pair
Next 3 Bits Point
to working
OPCODE
Example instruction
references either
program memory or
data memory
C0H
register pair
(1 of 8)
16-Bit
address
points to
program
memory
or data
memory
Program Memory
or
Data Memory
LSB Selects
Value used in
instruction
OPERAND
Sample Instructions:
LCD
LDE
LDE
R5,@RR6
R3,@RR14
@RR4, R8
; Program memory access
; External data memory access
; External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3C9444/F9444/C9454/F9454
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range
– 128 to + 127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external
program memory, and for external data memory, when implemented.
Register File
~
~
~
~
Value used in
instruction
OPERAND
+
Program Memory
X (OFFSET)
4 LSBs
dst
src
INDEX
Two-Operand
Instruction
Example
Point to one of the
working register
(1 of 16)
OPCODE
Sample Instruction:
LD
R0, #BASE[R1]
;
Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C9444/F9444/C9454/F9454
INDEXED ADDRESSING MODE (Continued)
Program Memory
Register File
XS (OFFSET)
4-Bit Working
NEXT 3 Bits
Register
Pair
dst
src
Register Address
Point to working
register pair
(1 of 8)
OPCODE
16-Bit
address
added to
offset
LSB Selects
+
16-Bit
8-Bit
Program Memory
or
Data memory
Value used in
instruction
OPERAND
16-Bit
Sample Instructions:
LDC
LDE
R4, #04H[RR2]
R4,#04H[RR2]
; The values in the program address (RR2 + #04H)
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C9444/F9444/C9454/F9454
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory
XLH (OFFSET)
Register File
XLL (OFFSET)
4-Bit Working
Register
Pair
NEXT 3 Bits
dst
src
Register Address
Point to working
register pair
(1 of 8)
OPCODE
16-Bit
address
added to
offset
LSB Selects
+
16-Bit
8-Bit
Program Memory
or
Datamemory
Value used in
instruction
OPERAND
16-Bit
Sample Instructions:
LDC
LDE
R4, #1000H[RR2]
R4, #1000H[RR2]
; The values in the program address (RR2 + #1000H)
are loaded into register R4.
; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
3-9
ADDRESSING MODES
S3C9444/F9444/C9454/F9454
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load
operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Address
Used
Program Memory
Upper Address Byte
Lower Address Byte
LSB Selects Program
dst/src
"0" or "1"
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
OPCODE
Sample Instructions:
LDC
LDE
R5,1234H ; The values in the program address (1234H)are loaded
into register R5.
R5,1234H ; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C9444/F9444/C9454/F9454
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Program
Memory
Address
Used
Lower Address Byte
Upper Address Byte
OPCODE
Sample Instructions:
JP
CALL
C,JOB1
DISPLAY
;
;
Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES
S3C9444/F9444/C9454/F9454
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
The instructions that support RA addressing is JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
PC Value
+
Displacement
OPCODE
Current Instruction
Signed
Displacement Value
Sample Instructions:
JR
ULT,$ + OFFSET
;
Where OFFSET is a value in the range + 127 to - 128
Figure 3-12. Relative Addressing
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand
field itself. Immediate addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The Operand value is in the instruction)
Sample Instruction: LD
R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
4
CONTROL REGISTERS
OVERVIEW
In this section, detailed descriptions of the S3C9444/C9454 control registers are presented in an easy-to-read
format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use
them as a quick-reference source when writing application programs.
System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the
standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More information
about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this
manual.
4-1
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
RESET value (Bit)
Table 4-1. System and Peripheral Control Registers
Register name
Mnemonic
Address & Location
Address
D0H
R/W
R
7
0
1
0
6
0
1
0
5
0
1
–
4
0
1
–
3
0
1
0
2
0
1
–
1
0
1
0
0
0
1
0
Timer 0 counter register
Timer 0 data register
Timer 0 control register
T0CNT
T0DATA
T0CON
D1H
R/W
R/W
D2H
Location D3H is not mapped
Clock control register
System flags register
CLKCON
FLAGS
D4H
D5H
R/W
R/W
0
x
–
x
–
x
0
x
0
–
–
–
–
–
–
–
Locations D6H–D8H are not mapped
Stack pointer register
SP
D9H
R/W
x
x
x
x
x
x
x
x
Location DAH is not mapped
MDS special register
MDSREG
BTCON
BTCNT
FTSTCON
SYM
DBH
DCH
DDH
DEH
DFH
R/W
R/W
R
0
0
0
–
–
0
0
0
–
–
0
0
0
0
–
0
0
0
0
–
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Basic timer control register
Basic timer counter
Test mode control register
System mode register
W
R/W
NOTES:
1. – : Not mapped or not used, x: Undefined
2. The factory test mode register, FTSTCON, is for factory use only. Its value should always be '00H' during the
normal operation.
4-2
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
Table 4-1. System and Peripheral Control Registers (Continued)
Register Name
Mnemonic
Address
Hex
R/W
Bit Values After RESET
7
0
–
–
6
0
–
0
5
0
–
0
4
0
–
0
3
0
–
0
2
0
0
0
1
0
0
0
0
0
0
0
Port 0 data register
P0
P1
P2
E0H
R/W
R/W
R/W
Port 1 data register
Port 2 data register
E1H
E2H
Locations E3H–E5H are not mapped
Port 0 control register (High byte)
Port 0 control register
P0CONH
P0CONL
P0PND
E6H
E7H
E8H
E9H
EAH
EBH
R/W
R/W
R/W
R/W
R/W
R/W
0
0
–
0
–
0
0
0
–
0
0
0
0
0
–
–
0
0
0
0
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 0 interrupt pending register
Port 1 control register
P1CON
Port 2 control register (High byte)
Port 2 control register (Low byte)
P2CONH
P2CONL
Locations ECH–F1H are not mapped
PWM data register
PWMDATA
PWMCON
STOPCON
F2H
F3H
F4H
R/W
R/W
R/W
0
0
0
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM control register
STOP .control register
Locations F5H–F6H are not mapped
A/D control register
ADCON
ADDATAH
ADDATAL
F7H
F8H
F9H
R/W
R
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
x
0
x
x
A/D converter data register ( High )
A/D converter data register ( Low )
R
Locations FAH–FFH are not mapped
NOTE: – : Not mapped or not used, x: Undefined
4-3
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
Bit number(s) that is/are appended to the
register name for bit addressing
Name of individual
bit or bit function
Register address
(hexadecimal)
Register
Full Register name
mnemonic
D5H
FLAGS - System Flags Register
.7
.6
.5
.4
.3
.2
.1
.0
Bit Identifier
RESET Value
Read/Write
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
0
R/W
0
R/W
.7
Carry Flag (C)
0
1
Operation dose not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit7
.6
Zero Flag
0
1
Operation result is a non-zero value
Operation result is zero
.5
Sign Flag
0
1
Operation generates positive number (MSB = "0")
Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
' - ' = Not used
Description of the
effect of specific
bit settings
RESET
value notation:
'-' = Not mapped or Not used
'x' = Undetermind value
'0' = Logic zero
'1' = Logic one
Addressing mode or
modes you can use to
modify register values
Bit number:
MSB = Bit 7
LSB = Bit 0
Figure 4-1. Register Description Format
4-4
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
ADCON— A/D Converter Control Register
F7H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7–.4
A/D Converter Input Pin Selection Bits
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ADC0 (P0.0)
ADC1 (P0.1)
ADC2 (P0.2)
ADC3 (P0.3)/ In S3C9444, connected with GND internally
ADC4 (P0.4)/ In S3C9444, connected with GND internally
ADC5 (P0.5)/ In S3C9444, connected with GND internally
ADC6 (P0.6)/ In S3C9444, connected with GND internally
ADC7 (P0.7)/ In S3C9444, connected with GND internally
ADC8 (P2.6)/ In S3C9444, connected with GND internally
Connected with GND internally
Connected with GND internally
Connected with GND internally
Connected with GND internally
Connected with GND internally
Connected with GND internally
Connected with GND internally
.3
End-of-Conversion Status Bit
0
1
A/D conversion is in progress
A/D conversion complete
(note)
.2–.1
Clock Source Selection Bit
0
0
1
1
0
1
0
1
f
f
f
f
/16 (f
£ 10 MHz)
OSC
OSC
OSC
OSC
OSC
/8 (f
£ 10 MHz)
£ 10 MHz)
£ 2.5 MHz)
OSC
/4 (f
/1 (f
OSC
OSC
.0
Conversion Start Bit
0
1
No meaning
A/D conversion start
NOTE: Maximum ADC clock input = 4 MHz.
4-5
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
BTCON — Basic Timer Control Register
DCH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7–.4
.3–.2
Watchdog Timer Function Enable Bit
1
0
1
0
Disable watchdog timer function
Enable watchdog timer function
Others
Basic Timer Input Clock Selection Code
f
f
f
/4096
/1024
/128
0
0
1
1
0
1
0
1
OSC
OSC
OSC
Invalid setting
.1
.0
Basic Timer 8-Bit Counter Clear Bit
0
1
No effect
Clear the basic timer counter value
Basic Timer Divider Clear Bit
0
1
No effect
Clear both dividers
NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared.
The bit is then cleared automatically to "0".
4-6
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
CLKCON— Clock Control Register
D4H
Bit Identifier
.7
0
.6
–
.5
–
.4
0
.3
0
.2
–
.1
–
.0
–
RESET Value
Read/Write
R/W
–
–
R/W
R/W
–
–
–
.7
Oscillator IRQ Wake-up Function Enable Bit
0
1
Enable IRQ for main system oscillator wake-up function
Disable IRQ for main system oscillator wake-up function
.6–.5
.4–.3
Not used for S3C9444/C9454
Divided by Selection Bits for CPU Clock frequency
Divide by 16 (f
/16)
0
0
1
1
0
1
0
1
OSC
Divide by 8 (f
/8)
OSC
Divide by 2 (f
/2)
OSC
Non-divided clock (f
)
OSC
.2–.0
Not used for S3C9444/C9454
4-7
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
FLAGS— System Flags Register
D5H
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
–
.2
–
.1
–
.0
–
RESET Value
Read/Write
R/W
R/W
R/W
R/W
–
–
–
–
.7
Carry Flag (C)
0
1
Operation does not generate a carry or borrow condition
Operation generates a carry-out or borrow into high-order bit 7
.6
Zero Flag (Z)
0
1
Operation result is a non-zero value
Operation result is zero
.5
Sign Flag (S)
0
1
Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V)
0
1
Operation result is £ + 127 or ³ – 128
Operation result is > + 127 or < – 128
.3–.0
Not used for S3C9444/C9454
4-8
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
P0CONH— Port 0 Control Register (High Byte)
E6H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7–.6
.5–.4
.3–.2
.1–.0
Port 0, P0.7/INT7 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
A/D converter input (ADC7); Schmitt trigger input off
Port 0, P0.6/ADC6/PWM Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Alternative function (PWM output)
Push-pull output
A/D converter input (ADC6); Schmitt trigger input off
Port 0, P0.5/ADC5 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
A/D converter input (ADC5); Schmitt trigger input off
Port 0, P0.4/ADC4 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
A/D converter input (ADC4); Schmitt trigger input off
4-9
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
P0CONL— Port 0 Control Register (Low Byte)
E7H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7–.6
.5–.4
.3–.2
.1–.0
Port 0, P0.3/INT3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input; pull-up enable
Push-pull output
A/D converter input (ADC3); Schmitt trigger input off
Port 0, P0.2/ADC2 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input; pull-up enable
Push-pull output
A/D converter input (ADC2); Schmitt trigger input off
Port 0, P0.1/ADC1/INT1 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input/falling edge interrupt input
Schmitt trigger input; pull-up enable/falling edge interrupt input
Push-pull output
A/D converter input (ADC1); Schmitt trigger input off
Port 0, P0.0/ADC0/INT0 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input/falling edge interrupt input
Schmitt trigger input; pull-up enable/falling edge interrupt input
Push-pull output
A/D converter input (ADC0); Schmitt trigger input off
4-10
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
P0PND— Port 0 Interrupt Pending Register
E8H
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
–
–
R/W
R/W
R/W
R/W
.7–.4
.3
Not used for the S3C9444/C9454
Port 0.1/ADC1/INT1 Interrupt Enable Bit
0
1
INT1 falling edge interrupt disable
INT1 falling edge interrupt enable
.2
Port 0.1/ADC1/INT1 Interrupt Pending Bit
0
0
1
1
No interrupt pending (when read)
Pending bit clear (when write)
Interrupt is pending (when read)
No effect (when write)
.1
.0
Port 0.0/ADC0/INT0 Interrupt Enable Bit
0
1
INT0 falling edge interrupt disable
INT0 falling edge interrupt enable
Port 0.0/ADC0/INT0 Interrupt Pending Bit
0
0
1
1
No interrupt pending (when read)
Pending bit clear (when write)
Interrupt pending (when read)
No effect (when write)
4-11
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
P1CON— Port 1 Control Register
E9H
Bit Identifier
.7
0
.6
0
.5
–
.4
–
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
–
–
R/W
R/W
R/W
R/W
.7
.6
Part 1.1 N-channel open-drain Enable Bit
0
1
Configure P1.1 as a push-pull output
Configure P1.1 as a n-channel open-drain output
Port 1.0 N-channel open-drain Enable Bit
0
1
Configure P1.0 as a push-pull output
Configure P1.0 as a n-channel open-drain output
.5–.4
.3–.2
Not used for S3C9444/C9454
Port 1, P1.1 Interrupt Pending Bits
0
0
1
1
0
1
0
1
Schmitt trigger input;
Schmitt trigger input; pull-up enable
Output
Schmitt trigger input; pull-down enable
.1–.0
Port 0, P1.0 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input;
Schmitt trigger input; pull-up enable
Output
Schmitt trigger input; pull-down enable
NOTE: When you use external oscillator, P1.0, P1.1 must be set to output port to prevent current consumption.
4-12
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
P2CONH— Port 2 Control Register (High Byte)
EAH
Bit Identifier
.7
–
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Not used for the S3C9444/C9454
.6–.4
Port 2, P2.6/ADC8/CLO Configuration Bits
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
x
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
ADC input
Push-pull output
Open-drain output; pull-up enable
Open-drain output
Alternative function; CLO output
.3–.2
.1–.0
Port 2, 2.5 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
Open-drain output
Port 2, 2.4 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
Open-drain output
NOTE: When noise problem is important issue, you had better not use CLO output.
4-13
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
P2CONL— Port 2 Control Register (Low Byte)
EBH
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7–.6
.5–.4
.3–.2
.1–.0
Part 2, P2.3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
Open-drain output
Port 2, P2.2 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
Open-drain output
Port 2, P2.1 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
Open-drain output
Port 2, P2.0 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input; pull-up enable
Schmitt trigger input
Push-pull output
T0 match output
4-14
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
PWMCON— PWM Control Register
E3H
Bit Identifier
.7
0
.6
0
.5
–
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
–
R/W
R/W
R/W
R/W
R/W
.7–.6
PWM Input Clock Selection Bits
f
f
f
f
/64
/8
0
0
1
1
0
1
0
1
OSC
OSC
OSC
OSC
/2
/1
.5
.4
Not used for S3C9444/C9454
PWMDATA Reload Interval Selection Bit
0
1
Reload from 8-bit up counter overflow
Reload from 6-bit up counter overflow
.3
.2
.1
.0
PWM Counter Clear Bit
0
1
No effect
Clear the PWM counter (when write)
PWM Counter Enable Bit
0
1
Stop counter
Start (Resume countering)
PWM Overflow Interrupt Enable Bit (8-Bit Overflow)
0
1
Disable interrupt
Enable interrupt
PWM Overflow Interrupt Pending Bit
0
0
1
1
No interrupt pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
No effect (when write)
NOTE: PWMCON.3 is not auto-cleared. You must pay attention when clear pending bit. (refer to page 11-8).
4-15
CONTROL REGISTERS
S3C9444/F9444/C9454/F9454
STOPCON— STOP Mode Control Register
E4H
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7–.0
Watchdog Timer Function Enable Bit
10100101 Enable STOP instruction
Other value Disable STOP instruction
NOTE: When STOPCON register is not #0A5H value, if you use STOP instruction, PC is changed to reset address.
SYM— System Mode Register
DFH
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
–
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
–
–
–
R/W
R/W
R/W
.7–.3
.2
Not used for S3C9444/C9454
Global Interrupt Enable Bit
0
1
Disable all interrupts
Enable all interrupt
.1–.0
Page Select Bits
0
0
1
1
0
1
0
1
Page 0
Page 1 (Not used for S3C9444/C9454)
Page 2 (Not used for S3C9444/C9454)
Page 3 (Not used for S3C9444/C9454)
4-16
S3C9444/F9444/C9454/F9454
CONTROL REGISTERS
T0CON— TIMER 0 Control Register
F4H
Bit Identifier
.7
0
.6
0
.5
–
.4
–
.3
0
.2
–
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
–
–
R/W
–
R/W
R/W
.7–.6
Timer 0 Input Clock Selection Bits
f
f
f
f
/256
/64
/8
0
0
1
1
0
1
0
1
OSC
OSC
OSC
OSC
/1
.5–.4
.3
Not used for the S3C9444/C9454
Timer 0 Counter Clear Bit
0
1
No effect
Clear the timer 0 counter (when write)
.2
.1
Not used for the S3C9444/C9454
Timer 0 Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
.0
Timer 0 Interrupt Pending Bit (Capture or match interrupt)
0
0
1
1
No interrupt pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
No effect (when write)
NOTE: T0CON.3 is not auto-cleared. You must pay attention when clear pending bit. (refer to page 10-12)
4-17
S3C9444/F9444/C9454/F9454
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt
sources can be serviced through an interrupt vector which is assigned in ROM address 0000H.
VECTOR
SOURCES
S1
0000H
0001H
S2
S3
Sn
NOTES:
1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).
2. The numbern of Sn value is expandable.
Figure 5-1. S3F9-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source.
The system-level control points in the interrupt structure are therefore:
— Global interrupt enable and disable (by EI and DI instructions)
— Interrupt source enable and disable settings in the corresponding peripheral control register(s)
5-1
INTERRUPT STRUCTURE
S3C9444/F9444/C9454/F9454
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
The system mode register, SYM (DFH), is used to enable and disable interrupt processing.
SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable
Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to
enable interrupt processing. Although you can manipulate SYM.2 directly to enable and disable interrupts during
normal operation, we recommend that you use the EI and DI instructions for this purpose.
INTERRUPT PENDING FUNCTION TYPES
When the interrupt service routine has executed, the application program's service routine must clear the
appropriate pending bit before the return from interrupt subroutine (IRET) occurs.
INTERRUPT PRIORITY
Because there is not a interrupt priority register in SAM88RCRI, the order of service is determined by a sequence
of source which is executed in interrupt service routine.
"EI" Instruction
Interrupt Pending
Register
S
R
Q
Execution
RESET
Interrpt priority
is determind by
software polling
method
Source Interrupts
Vector Interrupt
Cycle
Source Interrupt
Enable
Global Interrupt
Control (EI, DI instruction)
05005Figure 5-2. Interrupt Function Diagram
5-2
S3C9444/F9444/C9454/F9454
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request pending bit to "1".
2. The CPU generates an interrupt acknowledge signal.
3. The service routine starts and the source's pending flag is cleared to "0" by software.
4. Interrupt priority must be determined by software polling method.
INTERRUPT SERVICE ROUTINES
Before an interrupt request can be serviced, the following conditions must be met:
— Interrupt processing must be enabled (EI, SYM.2 = "1")
— Interrupt must be enabled at the interrupt's source (peripheral control register)
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The
CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.2 = "0")
to disable all subsequent interrupts.
2. Save the program counter and status flags to stack.
3. Branch to the interrupt vector to fetch the service routine's address.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores
the PC and status flags and sets SYM.2 to "1" (EI), allowing the CPU to process the next interrupt request.
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt
processing follows this sequence:
1. Push the program counter's low-byte value to stack.
2. Push the program counter's high-byte value to stack.
3. Push the FLAGS register values to stack.
4. Fetch the service routine's high-byte address from the vector address 0000H.
5. Fetch the service routine's low-byte address from the vector address 0001H.
6. Branch to the service routine specified by the 16-bit vector address.
5-3
INTERRUPT STRUCTURE
S3C9444/F9444/C9454/F9454
S3C9444/C9454 INTERRUPT STRUCTURE
The S3C9444/C9454 microcontroller has four peripheral interrupt sources:
— PWM overflow
— Timer 0 match
— P0.0 external interrupt
— P0.1 external interrupt
Vector
Pending Bits
T0CON.0
Enable/Disable
T0CON.1
Source
Timer 0 match
PWM Overflow
PWMCON.0
P0PND.2
PWMCON.1
P0PND.1
0000H
0001H
P0.0 External Interrupt
P0.1 External Interrupt
SYM.2
(EI, DI)
P0PND.0
P0PND.3
Figure 5-3. S3C9444/C9454 Interrupt Structure
5-4
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
6
SAM88RCRI INSTRUCTION SET
OVERVIEW
The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of
8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because
I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing,
rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction
set.
REGISTER ADDRESSING
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 13-bit program memory or data memory addresses. For
detailed information about register addressing, please refer to Chapter 2, "Address Spaces".
ADDRESSING MODES
There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and
Immediate (IM). For detailed descriptions of these addressing modes, please refer to Chapter 3, "Addressing
Modes".
6-1
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
Table 6-1. Instruction Group Summary
Operands Instruction
Mnemonic
Load Instructions
CLR
LD
dst
Clear
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst
Load
LDC
LDE
Load program memory
Load external data memory
LDCD
LDED
LDCI
LDEI
POP
PUSH
Load program memory and decrement
Load external data memory and decrement
Load program memory and increment
Load external data memory and increment
Pop from stack
src
Push to stack
Arithmetic Instructions
ADC
ADD
CP
dst,src
dst,src
dst,src
dst
Add with carry
Add
Compare
DEC
INC
Decrement
Increment
Subtract with carry
Subtract
dst
SBC
SUB
dst,src
dst,src
Logic Instructions
AND
COM
OR
dst,src
dst
Logical AND
Complement
dst,src
dst,src
Logical OR
XOR
Logical exclusive OR
6-2
S3C9444/F9444/C9454/F9454
Mnemonic
SAM88RCRI INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Program Control Instructions
CALL
IRET
JP
dst
Call procedure
Interrupt return
cc,dst
dst
Jump on condition code
Jump unconditional
Jump relative on condition code
Return
JP
JR
cc,dst
RET
Bit Manipulation Instructions
TCM
TM
dst,src
dst,src
Test complement under mask
Test under mask
Rotate and Shift Instructions
RL
dst
dst
dst
dst
dst
Rotate left
RLC
RR
Rotate left through carry
Rotate right
RRC
SRA
Rotate right through carry
Shift right arithmetic
CPU Control Instructions
CCF
DI
Complement carry flag
Disable interrupts
Enable interrupts
Enter Idle mode
No operation
EI
IDLE
NOP
RCF
SCF
STOP
Reset carry flag
Set carry flag
Enter stop mode
6-3
SAM88RCRI INSTRUCTION SET
FLAGS REGISTER (FLAGS)
S3C9444/F9444/C9454/F9454
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits,
FLAGS.4–FLAGS.7, can be tested and used with conditional jump instructions;
FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load
instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags
register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the
AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write
will occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS)
D5H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Carry flag (C)
Not mapped
Zero flag (Z)
Sign flag (S)
Overflow flag (V)
Figure 6-1. System Flags Register (FLAGS)
FLAG DESCRIPTIONS
3333Overflow Flag (FLAGS.4, V)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than – 128. It
is also cleared to "0" following logic operations.
Sign Flag (FLAGS.5, S)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A
logic zero indicates a positive number and a logic one indicates a negative number.
Zero Flag (FLAGS.6, Z)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that
test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.
Carry Flag (FLAGS.7, C)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7
position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.
Program instructions can set, clear, or complement the carry flag.
6-4
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag
C
Z
Description
Carry flag
Zero flag
S
V
0
Sign flag
Overflow flag
Cleared to logic zero
Set to logic one
1
*
Set or cleared according to operation
Value is unaffected
Value is undefined
–
x
Table 6-3. Instruction Set Symbols
Symbol
Description
Destination operand
dst
src
@
Source operand
Indirect register address prefix
Program counter
PC
FLAGS
#
Flags register (D5H)
Immediate operand or register address prefix
Hexadecimal number suffix
Decimal number suffix
Binary number suffix
H
D
B
opc
Opcode
6-5
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
Table 6-4. Instruction Notation Conventions
Description Actual Operand Range
Notation
cc
r
Condition code
See list of condition codes in Table 6-6.
Rn (n = 0–15)
Working register only
rr
Working register pair
RRp (p = 0, 2, 4, ..., 14)
R
Register or working register
Register pair or working register pair
reg or Rn (reg = 0–255, n = 0–15)
RR
reg or RRp (reg = 0–254, even number only, where
p = 0, 2, ..., 14)
Ir
IR
Indirect working register only
@Rn (n = 0–15)
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
IRR
Indirect register pair or indirect working
register pair
@RRp or @reg (reg = 0–254, even only, where
p = 0, 2, ..., 14)
X
Indexed addressing mode
#reg[Rn] (reg = 0–255, n = 0–15)
XS
Indexed (short offset) addressing mode
#addr[RRp] (addr = range – 128 to + 127, where
p = 0, 2, ..., 14)
XL
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0–8191, where
p = 0, 2, ..., 14)
DA
RA
Direct addressing mode
Relative addressing mode
addr (addr = range 0–8191)
addr (addr = number in the range + 127 to – 128 that is
an offset relative to the address of the next instruction)
IM
Immediate addressing mode
#data (data = 0–255)
6-6
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
0
1
2
3
4
5
6
7
U
P
P
E
R
DEC
R1
DEC
IR1
ADD
r1,r2
ADD
r1,Ir2
ADD
R2,R1
ADD
IR2,R1
ADD
R1,IM
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
R1
RLC
IR1
ADC
r1,r2
ADC
r1,Ir2
ADC
R2,R1
ADC
IR2,R1
ADC
R1,IM
INC
R1
INC
IR1
SUB
r1,r2
SUB
r1,Ir2
SUB
R2,R1
SUB
IR2,R1
SUB
R1,IM
JP
IRR1
SBC
r1,r2
SBC
r1,Ir2
SBC
R2,R1
SBC
IR2,R1
SBC
R1,IM
OR
r1,r2
OR
r1,Ir2
OR
R2,R1
OR
IR2,R1
OR
R1,IM
POP
R1
POP
IR1
AND
r1,r2
AND
r1,Ir2
AND
R2,R1
AND
IR2,R1
AND
R1,IM
N
I
COM
R1
COM
IR1
TCM
r1,r2
TCM
r1,Ir2
TCM
R2,R1
TCM
IR2,R1
TCM
R1,IM
PUSH
R2
PUSH
IR2
TM
r1,r2
TM
r1,Ir2
TM
R2,R1
TM
IR2,R1
TM
R1,IM
B
B
L
E
LD
r1, x, r2
RL
R1
RL
IR1
LD
r2, x, r1
CP
r1,r2
CP
r1,Ir2
CP
R2,R1
CP
IR2,R1
CP
R1,IM
LDC
r1, Irr2, xL
CLR
R1
CLR
IR1
XOR
r1,r2
XOR
r1,Ir2
XOR
R2,R1
XOR
IR2,R1
XOR
R1,IM
LDC
r2, Irr2, xL
RRC
R1
RRC
IR1
LDC
r1,Irr2
LD
r1, Ir2
H
E
X
SRA
R1
SRA
IR1
LDC
r2,Irr1
LD
IR1,IM
LD
Ir1, r2
RR
R1
RR
IR1
LDCD
r1,Irr2
LDCI
r1,Irr2
LD
R2,R1
LD
R2,IR1
LD
R1,IM
LDC
r1, Irr2, xs
CALL
IRR1
LD
IR2,R1
CALL
DA1
LDC
r2, Irr1, xs
6-7
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
8
9
A
B
C
D
E
F
U
P
LD
r1,R2
LD
r2,R1
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
1
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
P
E
R
2
3
4
5
N
I
6
IDLE
STOP
DI
7
B
B
L
E
8
9
EI
A
B
C
D
E
F
RET
IRET
RCF
SCF
CCF
NOP
H
E
X
LD
r1,R2
LD
r2,R1
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
6-8
S3C9444/F9444/C9454/F9454
CONDITION CODES
SAM88RCRI INSTRUCTION SET
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after
a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6-6. Condition Codes
Binary
0000
Mnemonic
Description
Flags Set
F
T
C
–
–
Always false
Always true
Carry
1000
(1)
C = 1
C = 0
Z = 1
Z = 0
S = 0
S = 1
V = 1
V = 0
Z = 1
Z = 0
0111
(1)
NC
Z
No carry
Zero
1111
(1)
0110
(1)
NZ
Not zero
Plus
1110
PL
1101
0101
0100
1100
MI
Minus
OV
NOV
EQ
NE
GE
LT
Overflow
No overflow
Equal
(1)
0110
(1)
Not equal
1110
1001
0001
1010
0010
Greater than or equal
Less than
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
GT
LE
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
(1)
UGE
ULT
UGT
ULE
1111
(1)
C = 1
0111
1011
0011
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
NOTES:
1. It indicates condition codes that are related to two different mnemonics but which test the same flag.
For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6-9
SAM88RCRI INSTRUCTION SET
INSTRUCTION DESCRIPTIONS
S3C9444/F9444/C9454/F9454
This section contains detailed information and programming examples for each instruction in the SAM87Ri
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The
following information is included in each instruction description:
— Instruction name (mnemonic)
— Full instruction name
— Source/destination format of the instruction operand
— Shorthand notation of the instruction's operation
— Textual description of the instruction's effect
— Specific flag settings affected by the instruction
— Detailed description of the instruction's format, execution time, and addressing mode(s)
— Programming example(s) explaining how to use the instruction
6-10
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
ADC — Add with Carry
ADC
dst,src
Operation:
dst ¬ dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected.
Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits
the carry from the addition of low-order operands to be carried into the addition of high-order
operands.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
12
13
r
r
r
lr
dst
src
3
3
6
6
14
15
R
R
R
IR
dst
6
16
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
ADC
ADC
ADC
ADC
ADC
R1,R2
®
®
®
®
®
R1 = 14H, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#11H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and
the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H
and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6-11
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
ADD — Add
ADD
dst,src
Operation:
dst ¬ dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is
of the opposite sign; cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
02
03
r
r
r
lr
dst
src
3
3
6
6
04
05
R
R
R
IR
dst
6
06
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD
ADD
ADD
ADD
ADD
R1,R2
®
®
®
®
®
R1 = 15H, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#25H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register
R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register
R1.
6-12
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
AND — Logical AND
AND
dst,src
Operation:
dst ¬ dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in
the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
52
53
r
r
r
lr
dst
src
3
3
6
6
54
55
R
R
R
IR
dst
6
56
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND
AND
AND
AND
AND
R1,R2
®
®
®
®
®
R1 = 02H, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#25H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand
03H with the destination operand value 12H, leaving the value 02H in register R1.
6-13
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
CALL — Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
¬
¬
¬
¬
¬
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to
return to the original program flow. RET pops the top of the stack back into the program counter.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
opc
dst
3
14
F6
DA
dst
2
12
F4
IRR
Examples:
Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H:
CALL
1521H
®
SP = 0B0H
(Memory locations 00H = 1AH, 01H = 4AH, where 4AH
is the address that follows the instruction.)
CALL
@RR0
®
SP = 0B0H (00H = 1AH, 01H = 49H)
In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack.
The stack pointer now points to memory location 00H. The PC is then loaded with the value
1521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack location
01H (because the two-byte instruction format was used). The PC is then loaded with the value
1521H, the address of the first instruction in the program sequence to be executed.
6-14
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
CCF — Complement Carry Flag
CCF
Operation:
C ¬ NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero;
if C = "0", the value of the carry flag is changed to logic one.
Flags:
C: Complemented.
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
EF
Example:
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H),
changing its value from logic zero to logic one.
6-15
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
CLR — Clear
CLR
dst
Operation:
dst ¬ "0"
The destination location is cleared to "0".
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
B0
B1
R
IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
00H
®
®
Register 00H = 00H
@01H
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
6-16
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
COM — Complement
COM
dst
Operation:
dst ¬ NOT dst
The contents of the destination location are complemented (one's complement); all "1s" are
changed to "0s", and vice-versa.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
60
61
R
IR
Examples:
Given: R1 = 07H and register 07H = 0F1H:
COM
COM
R1
®
®
R1 = 0F8H
R1 = 07H, register 07H = 0EH
@R1
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6-17
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
CP — Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.
Flags:
C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of
the result is of the same as the sign of the source operand; cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
A2
A3
r
r
r
lr
dst
src
3
3
6
6
A4
A5
R
R
R
IR
dst
6
A6
R
IM
Examples:
1. Given: R1 = 02H and R2 = 03H:
CP R1,R2
®
Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the
value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the
R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative,
C and S are "1".
2. Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
LD
R1,R2
UGE,SKIP
R1
SKIP
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C =
"1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.
6-18
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
DEC — Decrement
DEC
dst
Operation:
dst ¬ dst – 1
The contents of the destination operand are decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, dst value is – 128 (80H) and result value is
+ 127 (7FH); cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
00
01
R
IR
Examples:
Given: R1 = 03H and register 03H = 10H:
DEC
DEC
R1
®
®
R1 = 02H
Register 03H = 0FH
@R1
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by
one, leaving the value 0FH.
6-19
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
DI — Disable Interrupts
DI
Operation:
SYM (2) ¬ 0
Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt
processing. Interrupt requests will continue to set their respective interrupt pending bits, but the
CPU will not service them while interrupt processing is disabled.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
8F
Example:
Given: SYM = 04H:
DI
If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register
and clears SYM.2 to "0", disabling interrupt processing.
6-20
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
EI — Enable Interrupts
EI
Operation:
SYM (2) ¬ 1
An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be
serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled
(by executing a DI instruction), it will be serviced when you execute the EI instruction.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
9F
Example:
Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the
statement "EI" sets the SYM register to 04H, enabling all interrupts. (SYM.2 is the enable bit for
global interrupt processing.)
6-21
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
IDLE — Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
6F
–
–
Example:
The instruction
IDLE
NOP
NOP
NOP
stops the CPU clock but not the system clock.
6-22
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
INC — Increment
INC
dst
Operation:
dst ¬ dst + 1
The contents of the destination operand are incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is dst value is + 127 (7FH) and result is – 128 (80H);
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
dst | opc
opc
1
4
rE
r
r = 0 to F
dst
2
4
4
20
21
R
IR
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
INC
INC
R0
®
®
®
R0 = 1CH
00H
@R0
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC
R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value
of register 1BH from 0FH to 10H.
6-23
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
IRET — Interrupt Return
IRET
IRET
Operation:
FLAGS ¬ @SP
SP ¬ SP + 1
PC ¬ @SP
SP ¬ SP + 2
SYM(2) ¬ 1
This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts.
Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
IRET
(Normal)
Bytes
Cycles
Opcode
(Hex)
opc
1
10
12
BF
6-24
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
JP — Jump
JP
cc,dst
dst
(Conditional)
JP
(Unconditional)
Operation:
If cc is true, PC ¬ dst
The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the PC.
Flags: No flags are affected.
(1)
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(2)
cc | opc
dst
3
8
ccD
DA
cc = 0 to F
opc
dst
2
8
30
IRR
NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the
op code are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
JP
C,LABEL_W
@00H
®
®
LABEL_W = 1000H, PC = 1000H
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents
of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-25
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
JR — Jump Relative
JR
cc,dst
Operation:
If cc is true, PC ¬ PC + dst
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed (See list of condition
codes).
The range of the relative address is + 127, – 128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(note)
cc | opc
dst
2
6
ccB
RA
cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the op code are each
four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H:
JR
C,LABEL_X
®
PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program instruction
following the JR would be executed.
6-26
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
LD — Load
LD
dst,src
Operation:
dst ¬ src
The contents of the source are loaded into the destination. The source's contents are unaffected.
No flags are affected.
Flags:
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
IM
R
dst | opc
src | opc
opc
src
dst
2
4
4
rC
r8
r
r
2
2
3
3
4
r9
R
r
r = 0 to F
dst | src
4
4
C7
D7
r
lr
r
Ir
opc
src
dst
src
6
6
E4
E5
R
R
R
IR
opc
dst
6
6
E6
D6
R
IM
IM
IR
opc
opc
opc
src
dst
x
3
3
3
6
6
6
F5
87
97
IR
r
R
x [r]
r
dst | src
src | dst
x
x [r]
6-27
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
LD — Load
LD
(Continued)
Examples:
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
R0,#10H
®
®
®
®
®
®
®
®
®
®
®
®
R0 = 10H
R0,01H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
01H,R0
R1,@R0
@R0,R1
R0 = 01H, R1 = 0AH, register 01H = 0AH
Register 00H = 20H, register 01H = 20H
Register 02H = 20H, register 00H = 01H
Register 00H = 0AH
00H,01H
02H,@00H
00H,#0AH
@00H,#10H
@00H,02H
R0,#LOOP[R1]
#LOOP[R0],R1
Register 00H = 01H, register 01H = 10H
Register 00H = 01H, register 01H = 02, register 02H = 02H
R0 = 0FFH, R1 = 0AH
Register 31H = 0AH, R0 = 01H, R1 = 0AH
6-28
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
LDC/LDE — Load Memory
LDC/LDE
dst,src
Operation:
dst ¬ src
This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory. The
assembler makes "Irr" or "rr" values an even number for program memory and odd an odd
number for data memory.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
1.
2.
3.
4.
5.
opc
opc
opc
opc
opc
dst | src
src | dst
dst | src
src | dst
dst | src
2
10
C3
D3
E7
F7
A7
r
Irr
2
3
3
4
10
12
12
14
Irr
r
XS
XS
XL
r
XS [rr]
r
XS [rr]
r
XL
XL
XL [rr]
L
H
H
XL
6.
7.
opc
opc
opc
opc
src | dst
dst | 0000
src | 0000
dst | 0001
src | 0001
4
4
4
4
4
14
14
14
14
14
B7
A7
B7
A7
B7
XL [rr]
r
DA
r
L
DA
DA
DA
DA
DA
DA
DA
DA
r
L
L
L
L
H
H
H
H
8.
DA
r
9.
DA
r
10.
opc
DA
NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2. For formats 3 and 4, the destination address "XS [rr]" and the source address "XS [rr]" are each one
byte.
3. For formats 5 and 6, the destination address "XL [rr]" and the source address "XL [rr]" are each two
bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set
of values, used in formats 9 and 10, are used to address data memory.
6-29
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
LDC/LDE — Load Memory
LDC/LDE
(Continued)
Examples:
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory
locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH,
and 1104H = 98H:
LDC
LDE
LDC
R0,@RR2
R0,@RR2
@RR2,R0
; R0 ¬ contents of program memory location 0104H
; R0 = 1AH, R2 = 01H, R3 = 04H
; R0 ¬ contents of external data memory location 0104H
; R0 = 2AH, R2 = 01H, R3 = 04H
(note)
; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3 ® no change
LDE
LDC
@RR2,R0
; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3 ® no change
R0,#01H[RR4]
; R0 ¬ contents of program memory location 0061H
; (01H + RR4),
; R0 = AAH, R2 = 00H, R3 = 60H
LDE
LDC
LDE
LDC
LDE
R0,#01H[RR4]
#01H[RR4],R0
#01H[RR4],R0
; R0 ¬ contents of external data memory location 0061H
; (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H
(note)
; 11H (contents of R0) is loaded into program memory location
; 0061H (01H + 0060H)
; 11H (contents of R0) is loaded into external data memory
; location 0061H (01H + 0060H)
R0,#1000H[RR2] ; R0 ¬ contents of program memory location 1104H
; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
R0,#1000H[RR2] ; R0 ¬ contents of external data memory location 1104H
; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC
LDE
R0,1104H
R0,1104H
; R0 ¬ contents of program memory location 1104H, R0 = 88H
; R0 ¬ contents of external data memory location 1104H,
; R0 = 98H
(note)
LDC
LDE
1105H,R0
1105H,R0
; 11H (contents of R0) is loaded into program memory location
; 1105H, (1105H) ¬ 11H
; 11H (contents of R0) is loaded into external data memory
; location 1105H, (1105H) ¬ 11H
NOTE: These instructions are not supported by masked ROM type devices.
6-30
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
LDCD/LDED — Load Memory and Decrement
LDCD/LDED dst,src
Operation:
dst ¬ src
rr ¬ rr – 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes "Irr" an even number for program memory and an odd number for data memory.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E2
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:
LDCD
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is decremented by one
; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ¬ RR6 – 1)
LDED
R8,@RR6
; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is decremented by one (RR6 ¬ RR6 – 1)
; R8 = 0DDH, R6 = 10H, R7 = 32H
6-31
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
LDCI/LDEI— LOAD MEMORY AND INCREMENT
LDCI/LDEI
Operation:
dst,src
dst ¬ src
rr ¬ rr + 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes
"Irr" even for program memory and odd for data memory.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E3
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)
; R8 = 0CDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)
; R8 = 0DDH, R6 = 10H, R7 = 34H
6-32
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
NOP — No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
FF
Example:
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution
time.
6-33
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
OR — Logical OR
OR
dst,src
Operation:
dst ¬ dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
42
43
r
r
r
lr
dst
src
3
3
6
6
44
45
R
R
R
IR
dst
6
46
R
IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and
register 08H = 8AH:
OR
OR
OR
OR
OR
R0,R1
®
®
®
®
®
R0 = 3FH, R1 = 2AH
R0,@R2
00H,01H
01H,@00H
00H,#02H
R0 = 37H, R2 = 01H, register 01H = 37H
Register 00H = 3FH, register 01H = 37H
Register 00H = 08H, register 01H = 0BFH
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,
the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result
(3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing modes
and formats.
6-34
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
POP — Pop From Stack
POP
dst
Operation:
dst ¬ @SP
SP ¬ SP + 1
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags: No flags affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
50
51
R
IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register
0BBH = 55H:
POP
POP
00H
®
®
Register 00H = 55H, SP = 0BCH
@00H
Register 00H = 01H, register 01H = 55H, SP = 0BCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H"
loads the contents of location 0BBH (55H) into destination register 00H and then increments the
stack pointer by one. Register 00H then contains the value 55H and the SP points to location
0BCH.
6-35
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
PUSH — Push To Stack
PUSH
src
Operation:
SP ¬ SP – 1
@SP ¬ src
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
src
2
8
8
70
71
R
IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H:
PUSH
40H
®
Register 40H = 4FH, stack register 0BFH = 4FH,
SP = 0BFH
PUSH
@40H
®
Register 40H = 4FH, register 4FH = 0AAH, stack register
0BFH = 0AAH, SP = 0BFH
In the first example, if the stack pointer contains the value 0C0H, and general register 40H the
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then
loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH
and SP points to location 0BFH.
6-36
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
RCF — Reset Carry Flag
RCF
RCF
Operation:
C ¬ 0
The carry flag is cleared to logic zero, regardless of its previous value.
C: Cleared to "0".
Flags:
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
CF
Example:
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
6-37
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
RET — Return
RET
Operation:
PC ¬ @SP
SP ¬ SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end of
a procedure entered by a CALL instruction. The contents of the location addressed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that
is addressed by the new program counter value.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
8
AF
10
Example:
Given: SP = 0BCH, (SP) = 101AH, and PC = 1234:
RET PC = 101AH, SP = 0BEH
®
The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of
the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's
low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 0BEH.
6-38
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
RL — Rotate Left
RL
dst
Operation:
C ¬ dst (7)
dst (0) ¬ dst (7)
dst (n + 1) ¬ dst (n), n = 0–6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
90
91
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
RL
00H
®
®
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
@01H
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.
6-39
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
RLC — Rotate Left Through Carry
RLC
dst
Operation:
dst (0) ¬ C
C ¬ dst (7)
dst (n + 1) ¬ dst (n), n = 0–6
The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
10
11
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
RLC
00H
®
®
Register 00H = 54H, C = "1"
@01H
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC
00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the
initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The
MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-40
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
RR — Rotate Right
RR
dst
Operation:
C ¬ dst (0)
dst (7) ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
E0
E1
R
IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
RR
00H
®
®
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
@01H
In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
6-41
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
RRC — Rotate Right Through Carry
RRC
dst
Operation:
dst (7) ¬ C
C ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7
(MSB).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
C0
C1
R
IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
RRC
00H
®
®
Register 00H = 2AH, C = "1"
@01H
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces
the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH
(00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".
6-42
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
SBC — Subtract With Carry
SBC
dst,src
Operation:
dst ¬ dst – src – c
The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.
Flags:
C: Set if a borrow occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of
the result is the same as the sign of the source; cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
32
33
r
r
r
lr
dst
src
3
3
6
6
34
35
R
R
R
IR
dst
6
36
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
SBC
SBC
SBC
SBC
SBC
R1,R2
®
®
®
®
®
R1 = 0CH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#8AH
R1 = 05H, R2 = 03H, register 03H = 0AH
Register 01H = 1CH, register 02H = 03H
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
6-43
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
SCF — Set Carry Flag
SCF
Operation:
Flags:
C ¬ 1
The carry flag (C) is set to logic one, regardless of its previous value.
C: Set to "1".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
DF
Example:
The statement
SCF
sets the carry flag to logic one.
6-44
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
SRA — Shift Right Arithmetic
SRA
dst
Operation:
dst (7) ¬ dst (7)
C ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7 6
0
C
Flags:
C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
D0
D1
R
IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
SRA
00H
®
®
Register 00H = 0CD, C = "0"
@02H
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag
and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the
value 0CDH (11001101B) in destination register 00H.
6-45
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
STOP — Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,
peripheral registers, and I/O port control and data registers are retained. Stop mode can be
released by an external reset operation or External interrupt input. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has
elapsed.
Flags: No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
7F
–
–
Example:
The statement
LD
STOPCON, #0A5H
STOP
NOP
NOP
NOP
halts all microcontroller operations. When STOPCON register is not #0A5H value, if you use
STOP instruction, PC is changed to reset address.
6-46
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
SUB — Subtract
SUB
dst,src
Operation:
dst ¬ dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags:
C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of
the result is of the same as the sign of the source operand; cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
22
23
r
r
r
lr
dst
src
3
3
6
6
24
25
R
R
R
IR
dst
6
26
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
R1,R2
®
®
®
®
®
®
R1 = 0FH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#90H
01H,#65H
R1 = 08H, R2 = 03H
Register 01H = 1EH, register 02H = 03H
Register 01H = 17H, register 02H = 03H
Register 01H = 91H; C, S, and V = "1"
Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.
6-47
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
TCM — Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
62
63
r
r
r
lr
dst
src
3
3
6
6
64
65
R
R
R
IR
dst
6
66
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TCM
TCM
TCM
TCM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "1"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
TCM
00H,#34
®
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.
6-48
S3C9444/F9444/C9454/F9454
SAM88RCRI INSTRUCTION SET
TM — Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
72
73
r
r
r
lr
dst
src
3
3
6
6
74
75
R
R
R
IR
dst
6
76
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TM
TM
TM
TM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "0"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM
00H,#54H
®
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for
a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero
and can be tested to determine the result of the TM operation.
6-49
SAM88RCRI INSTRUCTION SET
S3C9444/F9444/C9454/F9454
XOR — Logical Exclusive OR
XOR
dst,src
Operation:
dst ¬ dst XOR src
The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever
the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
B2
B3
r
r
r
lr
dst
src
3
3
6
6
B4
B5
R
R
R
IR
dst
6
B6
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
XOR
XOR
XOR
XOR
XOR
R0,R1
®
®
®
®
®
R0 = 0C5H, R1 = 02H
R0,@R1
00H,01H
00H,@01H
00H,#54H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H, register 02H = 23H
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains the
value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value
and stores the result (0C5H) in the destination register R0.
6-50
S3C9444/F9444/C9454/F9454
CLOCK CIRCUIT
7
CLOCK CIRCUIT
OVERVIEW
By smart option (3FH.1–.0 in ROM), user can select internal RC oscillator or external oscillator. In using internal
oscillator, XIN (P1.0), XOUT (P1.1) can be used by normal I/O pins. An internal RC oscillator source provides a
typical 3.2 MHz or 0.5 MHz (in V = 5 V) depending on smart option.
DD
An external RC oscillation source provides a typical 4 MHz clock for KS86C4502/C4504. An internal capacitor
supports the RC oscillator circuit. An external crystal or ceramic oscillation source provides a maximum 10 MHz
clock. The X and X
pins connect the oscillation source to the on-chip clock circuit. Simplified external RC
IN
OUT
oscillator and crystal/ceramic oscillator circuits are shown in Figures 7-1 and 7-2. When you use external
oscillator, P1.0, P1.1 must be set to output port to prevent current consumption
XIN
C1
C2
R
S3C9444/C9454
S3C9444/C9454
XOUT
XOUT
Figure 7-1. Main Oscillator Circuit
(RC Oscillator with Internal Capacitor)
Figure 7-2. Main Oscillator Circuit
(Crystal/Ceramic Oscillator)
MAIN OSCILLATOR LOGIC
To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator
circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the
CPU to efficiently process logic operations.
7-1
CLOCK CIRCUIT
S3C9444/F9444/C9454/F9454
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:
— In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file
and current system register values are retained. Stop mode is released, and the oscillator started, by a reset
operation or by an external interrupt with RC-delay noise filter (for KS86C4502/C4504, INT0-INT1).
— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The
current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is
retained. Idle mode is released by a reset or by an interrupt (external or internally-generated).
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:
— Oscillator IRQ wake-up function enable/disable (CLKCON.7)
— Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3)
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
f
/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU
OSC
clock speed to f
, f
/2 or f
/8.
OSC
OSC OSC
System Clock Control Register (CLKCON)
D4H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main system
oscillator wake-up function in
power mode.
1 = Disable IRQ for main system
oscillator wake-up function in
power down mode.
Not used for
S3C9444/C9454
Divide-by selection bits for
CPU clock frequency:
00 = fosc/16
01 = fosc/8
10 = fosc/2
11 = fosc (non-divided)
Not used for
S3C9444/C9454
Figure 7-3. System Clock Control Register (CLKCON)
7-2
S3C9444/F9444/C9454/F9454
CLOCK CIRCUIT
Smart option
(3F.1-0 in ROM)
Stop
Instruction
CLKCON.4-.3
Internal RC
oscillator (3.2 MHz)
Oscillator
Stop
Internal RC
oscillator (0.5 MHz)
1/2
1/8
M
U
X
Selected
OSC
MUX
CPU Clock
P2.6/CLO
External crystal/
ceramic oscillator
Oscillator
Wake-up
1/16
External RC
oscillator
Noise
Filter
CLKCON.7
P2CONH.6-.4
INT Pin
NOTE:
An external interrupt (with RC-delay noise filter) can be used to release stop mode
and "wake-up" the main oscillator.
In the S3C9444/C9454, the INT0-INT1 external interrupts are of this type.
Figure 7-4. System Clock Circuit Diagram
7-3
S3C9444/F9444/C9454/F9454
RESET and POWER-DOWN
8
RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW
By smart option (3EH.7 in ROM), user can select internal RESET (LVR) or external RESET. In using internal
RESET (LVR), RESET pin (P1.2) can be used by normal I/O pin.
The S3C9444/C9454 can be RESET in four ways:
— by external power-on-reset
— by the external reset input pin pulled low
— by the digital watchdog peripheral timing out
— by Low Voltage reset (LVR)
During a external power-on reset, the voltage at V is High level and the RESET pin is forced to Low level. The
DD
RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This
brings the S3C9444/C9454 into a known operating status. To ensure correct start-up, the user should take care
that reset signal is not released before the V level is sufficient to allow MCU operation at the chosen frequency.
DD
The RESET pin must be held to Low level for a minimum time interval after the power supply comes within
tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation
16
stabilization time for a reset is approximately 6.55 ms (@ 2 /f
, f
= 10 MHz).
OSC OSC
When a reset occurs during normal operation (with both V and RESET at High level), the signal at the RESET
DD
pin is forced Low and the reset operation starts. All system and peripheral control registers are then set to their
default hardware reset values (see Table 8-1).
The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction. If
watchdog timer is not refreshed before an end-of-counter condition (overflow) is reached, the internal reset will be
activated.
The on-chip Low Voltage reset, features static Reset when supply voltage is below a reference value (Typ. 2.3,
3.0, 3.9 V). Thanks to this feature, external reset circuit can be removed while keeping the application safety. As
long as the supply voltage is below the reference value, there is a internal and static RESET. The MCU can start
only when the supply voltage rises over the reference value.
8-1
RESET and POWER-DOWN
S3C9444/F9444/C9454/F9454
NOTE
To program the duration of the oscillation stabilization interval, you must make the appropriate settings to
the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the
basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you
can disable it by writing "1010B" to the upper nibble of BTCON.
MCU Initialization Sequence
The following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0–2 are set to input mode
— Peripheral control and data registers are disabled and reset to their initial values (see Table 8-1).
— The program counter is loaded with the ROM reset address, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location
0100H (and 0101H) is fetched and executed.
Smart option
(3EH.7)
RESET
MUX
Internal RESET
LVR RESET
Watchdog RESET
Figure 8-1. Reset Block Diagram
Oscillation Stabilization wait time (6.55 ms/at 10 MHz)
RESET Input
Operation Mode
Idle Mode
Normal Mode or
Power-Down Mode
RESET Operation
Figure 8-2. Timing for S3C9444/C9454 after RESET
8-2
S3C9444/F9444/C9454/F9454
RESET and POWER-DOWN
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than
100 mA. All system functions are halted when the clock "freezes", but data stored in the internal register file is
retained. Stop mode can be released in one of two ways: by a RESET signal or by an external interrupt.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal is released and returns to High level. All system and peripheral
control registers are then reset to their default values and the contents of all data registers are retained. A reset
operation automatically selects a slow clock (f
/16) because CLKCON.3 and CLKCON.4 are cleared to "00B".
OSC
After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by fetching
the 16-bit address stored in ROM locations 0100H and 0101H.
Using an External Interrupt to Release Stop Mode
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external
interrupts cannot be used). External interrupts INT0-INT1 in the KS86C4502/C4504 interrupt structure meet this
criteria. And, internal interrupt using external clock (timer, SIO etc) can be used to release stop mode also.
Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control
registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4
register values remain unchanged, and the currently selected clock value is used. If you use an external interrupt
for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you
must put the appropriate value to BTCON register before entering Stop mode.
The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine,
the instruction immediately following the one that initiated Stop mode is executed.
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select
peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt
logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.
There are two ways to release Idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects a slow clock (f
/16) because CLKCON.3
OSC
and CLKCON.4 are cleared to "00B". If interrupts are masked, a reset is the only way to release Idle mode.
2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle
mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction
immediately following the one that initiated Idle mode is executed.y
NOTES
1. Only external interrupts that are not clock-related can be used to release stop mode. To release Idle
mode, however, any type of interrupt (that is, internal or external) can be used.
2. Before enter the STOP or IDLE mode, the ADC must be disabled. Otherwise, the STOP or IDLE
current will be increased significantly.
8-3
RESET and POWER-DOWN
S3C9444/F9444/C9454/F9454
HARDWARE RESET VALUES
Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers
following a reset operation in normal operating mode.
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An "x" means that the bit value is undefined following a reset.
— A dash ("–") means that the bit is either not used or not mapped.
Table 8-1. Register Values after a Reset
Register name
Mnemonic
Address & Location
RESET value (Bit)
Address
D0H
R/W
R
7
0
1
0
6
0
1
0
5
0
1
–
4
0
1
–
3
0
1
0
2
0
1
–
1
0
1
0
0
0
1
0
Timer 0 counter register
Timer 0 data register
Timer 0 control register
T0CNT
T0DATA
T0CON
D1H
R/W
R/W
D2H
Location D3H is not mapped
Clock control register
System flags register
CLKCON
FLAGS
D4H
D5H
R/W
R/W
0
x
–
x
–
x
0
x
0
–
–
–
–
–
–
–
Locations D6H–D8H are not mapped
Stack pointer register
SP
D9H
R/W
x
x
x
x
x
x
x
x
Location DAH is not mapped
MDS special register
MDSREG
BTCON
BTCNT
FTSTCON
SYM
DBH
DCH
DDH
DEH
DFH
R/W
R/W
R
0
0
0
–
–
0
0
0
–
–
0
0
0
0
–
0
0
0
0
–
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Basic timer control register
Basic timer counter
Test mode control register
System mode register
W
R/W
NOTE: – : Not mapped or not used, x: undefined
8-4
S3C9444/F9444/C9454/F9454
Register Name
RESET and POWER-DOWN
Table 8-1. Register Values After a Reset (Continued)
Mnemonic
Address
Hex
R/W
Bit Values After RESET
7
0
–
–
6
0
–
0
5
0
–
0
4
0
–
0
3
0
–
0
2
0
0
0
1
0
0
0
0
0
0
0
Port 0 data register
Port 1 data register
Port 2 data register
P0
P1
P2
E0H
R/W
R/W
R/W
E1H
E2H
Locations E3H–E5H are not mapped
Port 0 control register (High byte)
Port 0 control register
P0CONH
P0CON
P0PND
E6H
E7H
E8H
E9H
EAH
EBH
R/W
R/W
R/W
R/W
R/W
R/W
0
0
–
0
–
0
0
0
–
0
0
0
0
0
–
–
0
0
0
0
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 0 interrupt pending register
Port 1 control register
P1CON
P2CONH
P2CONL
Port 2 control register (High byte)
Port 2 control register (Low byte)
Locations ECH–F1H are not mapped
PWM data register
PWM control register
STOP control register
PWMDATA
PWMCON
STOPCON
F2H
F3H
F4H
R/W
R/W
R/W
0
0
0
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Locations F5H–F6H are not mapped
A/D control register
ADCON
ADDATAH
ADDATAL
F7H
F8H
F9H
R/W
R
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
x
0
x
x
A/D converter data register (High)
A/D converter data register (Low)
R
Locations FAH–FFH are not mapped
NOTE: – : Not mapped or not used, x: undefined
8-5
RESET and POWER-DOWN
S3C9444/F9444/C9454/F9454
+
PROGRAMMING TIP — Sample S3C9454 Initialization Routine
;--------------<< Interrupt Vector Address >>
ORG
0000H
VECTOR
00H,INT_9454
; S3C9454 has only one interrupt vector
;--------------<< Smart Option >>
ORG
DB
DB
DB
DB
003CH
00H
00H
0E7H
03H
; 003CH, must be initialized to 0
; 003DH, must be initialized to 0
; 003EH, enable LVR (2.3 V)
; 003FH, internal RC (3.2 MHz in V = 5 V )
DD
;--------------<< Initialize System and Peripherals >>
ORG
DI
0100H
RESET:
; disable interrupt
LD
LD
LD
BTCON,#10100011B
CLKCON,#00011000B
SP,#0C0H
; Watch-dog disable
; Select non-divided CPU clock
; Stack pointer must be set
LD
LD
LD
LD
LD
P0CONH,#10101010B
P0CONL,#10101010B
P1CON,#00001010B
P2CONH,#01001010B
P2CONL,#10101010B
;
; P0.0–P0.7 push-pull output
; P1.0–P1.1 push-pull output
;
; P2.0–P2.6 push-pull output
;--------------<< Timer 0 settings >>
LD
LD
T0DATA,#50H
T0CON,#01001010B
; CPU = 11.0592 MHz, interrupt interval = 2 msec
; f
/256, Timer 0 interrupt enable
OSC
;--------------<< Clear all data registers from 00h to 5Fh >>
LD
R0,#0
; RAM clear
RAM_CLR: CLR
@R0
R0
R0,#0BFH
ULE,RAM_CLR
;
;
;
INC
CP
JP
;--------------<< Initialize other registers >>
·
·
·
EI
; Enable interrupt
8-6
S3C9444/F9444/C9454/F9454
RESET and POWER-DOWN
+
PROGRAMMING TIP — Sample S3C9454 Initialization Routine (Continued)
;--------------<< Main loop >>
MAIN:
NOP
LD
; Start main loop
; Enable watchdog function
; Basic counter (BTCNT) clear
BTCON,#02H
KEY_SCAN
LED_DISPLAY
JOB
·
·
CALL
·
;
;
;
·
·
CALL
·
·
·
CALL
·
·
·
JR
T,MAIN
;
;
;--------------<< Subroutines >>
KEY_SCAN: NOP
·
·
·
RET
LED_DISPLAY: NOP
;
;
·
·
·
RET
JOB:
NOP
·
·
·
RET
8-7
RESET and POWER-DOWN
S3C9444/F9444/C9454/F9454
+
PROGRAMMING TIP — Sample S3C9454 Initialization Routine (Continued)
;--------------<< Interrupt Service Routines >> ; Interrupt enable bit and pending bit check
INT_9454: TM
T0CON,#00000010B
Z,NEXT_CHK1
T0CON,#00000001B
NZ,INT_TIMER0
; Timer0 interrupt enable check
;
; If timer0 interrupt was occurred,
; T0CON.0 bit would be set.
JR
TM
JP
NEXT_CHK1:
TM
JR
TM
JP
PWMCOM,#00000010B ; PWM overflow interrupt enable check
Z,NEXT_CHK2
;
;
;
P0PND,#00000001B
NZ,PWMOVF_INT
NEXT_CHK2:
TM
JR
TM
JP
P0PND,#00000010B
Z,NEXT_CHK3
P0PND,#00000001B
NZ,INT0_INT
; INT0 interrupt enable check
;
;
;
NEXT_CHK3:
TM
JP
P0PND,#00001000B
Z,END_INT
; INT1 interrupt enable check
;
TM
JP
P0PND,#00000100B
NZ,INT1_INT
;
;
IRET
; Interrupt return
END_INT
; IRET
;--------------< Timer0 interrupt service routine >
INT_TIMER0:
·
;
·
AND
IRET
T0CON,#11110110B
; Pending bit clear
; Interrupt return
;--------------< PWM overflow interrupt service routine >
PWMOVF_INT:
·
·
AND
IRET
PWMCON,#11110110B ; Pending bit clear
; Interrupt return
8-8
S3C9444/F9444/C9454/F9454
RESET and POWER-DOWN
+
PROGRAMMING TIP — Sample S3C9454 Initialization Routine (Continued)
;--------------< External interrupt0 service routine >
INT0_INT:
·
·
AND
IRET
P0PND,#11111110B
; INT0 Pending bit clear
; Interrupt return
;--------------< External interrupt1 service routine >
INT1_INT:
·
·
AND
IRET
P0PND,#11111011B
; INT1 Pending bit clear
; Interrupt return
·
·
END
;
8-9
S3C9444/F9444/C9454/F9454
I/O PORTS
9
I/O PORTS
OVERVIEW
The S3C9444/C9454 has three I/O ports: with 18 pins total. You access these ports directly by writing or reading
port data register addresses.
All ports can be configured as LED drive. (High current output: typical 10 mA)
Table 9-1. S3C9444/C9454 Port Configuration Overview
Port
Function Description
Programmability
0
Bit-programmable I/O port for schmitt trigger input or push-pull output.
Pull-up resistors are assignable by software. Port 0 pins can also be used
as alternative function. (ADC input, external interrupt input).
Bit
1
2
Bit-programmable I/O port for schmitt trigger input or push-pull, open-drain
output. Pull-up or pull-down resistors are assignable by software. Port 1
pins can also oscillator input/output or reset input by smart option. P1.2 is
input only.
Bit
Bit
Bit-programmable I/O port for schmitt trigger input or push-pull, open-drain
output. Pull-up resistor are assignable by software. Port 2 can also be
used as alternative function (ADC input, CLO, T0 clock output)
9-1
I/O PORTS
S3C9444/F9444/C9454/F9454
PORT DATA REGISTERS
Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data
registers for ports 0-2 have the structure shown in Figure 9-1.
Table 9-2. Port Data Register Summary
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Mnemonic
Hex
E0H
E1H
E2H
R/W
R/W
R/W
R/W
P0
P1
P2
NOTE: A reset operation clears the P0–P2 data register to "00H".
I/O Port n Data Register (n = 0-2)
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pn.7
Figure 9-1. Port Data Register Format
9-2
S3C9444/F9444/C9454/F9454
PORT 0
I/O PORTS
Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull output mode. In
addition, you can configure a pull-up resistor to individual pins using control register settings.
It is designed for high-current functions such as LED direct drive. Part 0 pins can also be used as alternative
functions (ADC input, external interrupt input and PWM output).
Two control resisters are used to control Port 0: P0CONH (E6H) and P0CONL (E7H).
You access port 0 directly by writing or reading the corresponding port data register, P0 (E0H).
VDD
Pull-up
enable
Pull-up register
(50 kW typical)
VDD
P0CONH
M
U
X
PWM
In/Out
P0 Data
Output DIsable
(input mode)
D1
D0
Input Data
MUX
Circuit type A
External
Interrupt Input
Noise
Filter
To ADC
MODE
Output
Input
Input Data
NOTE: I/O pins have protection diodes
through VDD and VSS.
D0
D1
Figure 9-2. Port 0 Circuit Diagram
9-3
I/O PORTS
S3C9444/F9444/C9454/F9454
Port 0 Control Register (High Byte)
E6H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
[.7-.6] Port, P0.7/ADC7 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = A/D converter input (ADC7); schmitt trigger input off
[.5-.4] Port 0, P0.6/ADC6/PWM Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Alternative function (PWM output)
1 0 = Push-pull output
1 1 = A/D converter input (ADC6); schmitt trigger input off
[.3-.2] Port 0, P0.5/ADC5 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = A/D converter input (ADC5); schmitt trigger input off
[.1-.0] Port 0, P0.4/ADC4 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = A/D converter input (ADC4); schmitt trigger input off
Figure 9-3. Port 0 Control Register (P0CONH, High Byte)
9-4
S3C9444/F9444/C9454/F9454
I/O PORTS
Port 0 Control Register (Low Byte)
E7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
[.7-.6] Port 0, P0.3/ADC3 Configuration Bits
0 0 = Schmitt trigger input
0 1 = Schmitt trigger input; pull-up enable
1 0 = Push-pull output
1 1 = A/D converter input (ADC3); Schmitt trigger input off
[.5-.4] Port 0, P0.2/ADC2 Configuration Bits
0 0 = Schmitt trigger input
0 1 = Schmitt trigger input; pull-up enable
1 0 = Push-pull output
1 1 = A/D converter input (ADC2); Schmitt trigger input off
[.3-.2] Port 0, P0.1/ADC1/INT1 Configuration Bits
0 0 = Schmitt trigger input/falling edge interrupt input
0 1 = Schmitt trigger input; pull-up enable/falling edge interrupt input
1 0 = Push-pull output
1 1 = A/D converter input (ADC1); Schmitt trigger input off
[.1-.0] Port 0, P0.0/ADC0/INT0 Configuration Bits
0 0 = Schmitt trigger input/falling edge interrupt input
0 1 = Schmitt trigger input; pull-up enable/falling edge interrupt input
1 0 = Push-pull output
1 1 = A/D converter input (ADC0); Schmitt trigger input off
Figure 9-4. Port 0 Control Register (P0CONL, Low Byte)
9-5
I/O PORTS
S3C9444/F9444/C9454/F9454
Port 0 Interrupt Pending Register
E8H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
[.7-.4] Not used for S3C9444/C9454
[.3] Port 0.1/ADC1/INT1, Interrupt Enable Bit
0 = INT1 falling edge interrupt disable
1 = INT1 falling edge interrupt enable
[.2] Port 0.1/ADC1/INT1, Interrupt Pending Bit
0 = No interrupt pending (when read)
0 = Pending bit clear (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
[.1] Port 0.0/ADC0/INT0, Interrupt Enable Bit
0 = INT0 falling edge interrupt disable
1 = INT0 falling edge interrupt enable
[.0] Port 0.0/ADC0/INT0, Interrupt Pending Bit
0 = No interrupt pending (when read)
0 = Pending bit clear (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
Figure 9-5. Port 0 Interrupt Pending Registers (P0PND)
9-6
S3C9444/F9444/C9454/F9454
PORT 1
I/O PORTS
Port 1, is a 3-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input
mode, push-pull output mode or n-channel open-drain output mode). In addition, you can configure a pull-up and
pull-down resistor to individual pin using control register settings. It is designed for high-current functions such as
LED direct drive.
P1.0, P1.1 are used for oscillator input/output by smart option. Also, P1.2 is used for RESET pin by smart option.
One control register is used to control port 1: P1CON (E9H).
You address port 1 bits directly by writing or reading the port 1 data register, P1 (E1H). When you use external
oscillator, P1.0, P1.1 must be set to output port to prevent current consumption.
VDD
Pull-up register
(50 k
W typical)
Pull-up
enable
Open-drain
VDD
Smart option
MUX
P1 Data
In/Out
Output DIsable
(input mode)
D1
MUX
Input Data
D0
Circuit type A
XIN, XOUT or RESET
Pull-down
Enable
Pull-down register
(50 k typical)
W
MODE
Output
Input
Input Data
NOTE: I/O pins have protection diodes
D0
D1
through V DD and VSS.
Figure 9-6. Port 1 Circuit Diagram
9-7
I/O PORTS
S3C9444/F9444/C9454/F9454
Port 1 Control Register
E9H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
[.7] Port 1.1 N-channel open-drain Enable Bit
0 = Configure P1.1 as a push-pull output
1 = Configure P1.1 as a n-channel open-drain output
[.6] Port 1.0 N-channel open-drain Enable Bit
0 = Configure P1.0 as a push-pull output
1 = Configure P1.0 as a N-channel open-drain output
[.5-.4] Not used for S3C9444/C9454
[.3-.2] Port 1, P1.1 Configuration Bits
0 0 = Schmitt trigger input;
0 1 = Schmitt trigger input; pull-up enable
1 0 = Push-pull output
1 1 = Schmitt trigger input; pull-down enable
[.1-.0] Port 1, P1.1 Configuration Bits
0 0 = Schmitt trigger input;
0 1 = Schmitt trigger input; pull-up enable
1 0 = Push-pull output
1 1 = Schmitt trigger input; pull-down enable
NOTE: When you use external oscillator, P1.0, P1.1 must be set to
output port to prevent current consumption.
Figure 9-7. Port 1 Control Register (P1CON)
9-8
S3C9444/F9444/C9454/F9454
PORT 2
I/O PORTS
Port 2 is a 7-bit I/O port with individually configurable pins. It can be used for general I/O port (schmitt trigger input
mode, push-pull output mode or N-channel open-drain output mode). You can also use some pins of port 2 ADC
input, CLO output and T0 clock output. In addition, you can configure a pull-up resistor to individual pins using
control register settings. It is designed for high-current functions such as LED direct drive.
You address port 2 bits directly by writing or reading the port 2 data register, P2 (E2H). The port 2 control register,
P2CONH and P2CONL is located at addresses EAH, EBH respectively.
VDD
Pull-up
enable
Pull-up register
(50 kW typical)
Open-drain
VDD
P2CONH/L
CLO, T0
P0 Data
M
U
X
In/Out
Output DIsable
(input mode)
D1
MUX
Input Data
to ADC
D0
Circuit type A
NOTE: I/O pins have protection diodes
MODE
Output
Input
Input Data
through VDD and VSS.
D0
D1
Figure 9-8. Port 2 Circuit Diagram
9-9
I/O PORTS
S3C9444/F9444/C9454/F9454
Port 2 Control Register (High Byte)
EAH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
[.7] Not sued for S3C9444/C9454
[.6-.4] Port 2, P2.6/ADC8/CLO Configuration Bits
0 0 0 = Schmitt trigger input; pull-up enable
0 0 1 = Schmitt trigger input
0 1 x = ADC input
1 0 0 = Push-pull output
1 0 1 = Open-drain output; pull-up enable
1 1 0 = Open-drain output
1 1 1 = Alternative function; CLO output
[.3-.2] Port 2, P2.5 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = Open-drain output
[.1-.0] Port 2, P2.4 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = Open-drain output
NOTE: When noise problem is important issue, you had better not
use CLO output
Figure 9-9. Port 2 Control Register (P2CONH, High Byte)
9-10
S3C9444/F9444/C9454/F9454
I/O PORTS
Port 2 Control Register (Low Byte)
EBH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
[.7-.6] Port 2, P2.3 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = Open-drain output
[.5-.4] Port 2, P2.2 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = Open-drain output
[.3-.2] Port 2, P2.1 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = Open-drain output
[.1-.0] Port 2, P2.0 Configuration Bits
0 0 = Schmitt trigger input; pull-up enable
0 1 = Schmitt trigger input
1 0 = Push-pull output
1 1 = T0 match output
Figure 9-10. Port 2 Control Register (P2CONL, Low Byte)
9-11
S3C9444/F9444/C9454/F9454
BASIC TIMER and TIMER 0
10 BASIC TIMER and TIMER 0
MODULE OVERVIEW
The S3C9444/C9454 has two default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called
timer 0.
Basic Timer (BT)
You can use the basic timer (BT) in two different ways:
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (f
divided by 4096, 1024, or 128) with multiplexer
OSC
— 8-bit basic timer counter, BTCNT (DDH, read-only)
— Basic timer control register, BTCON (DCH, read/write)
Timer 0
Timer 0 has the following functional components:
— Clock frequency divider (f
divided by 4096, 256, 8, or f
) with multiplexer
OSC
OSC
— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit data register (T0DATA)
— Timer 0 control register (T0CON)
10-1
BASIC TIMER and TIMER 0
S3C9444/F9444/C9454/F9454
BASIC TIMER (BT)
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function.
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of
f
/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register
OSC
control bits BTCON.7–BTCON.4.
The 8-bit basic timer counter, BTCNT, can be cleared during normal operation by writing a "1" to BTCON.1. To
clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to BTCON.0.
Basic Timer Control Register (BTCON)
DCH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Divider clear bit for basic
timer and timer 0:
0 = No effect
Watchdog timer enable bits:
1010B = Disable watchdog function
Other value = Enable watchdog
function
1 = Clear both dividers
Basic timer counter clear bits:
0 = No effect
1 = Clear basic timer counter
Basic timer input clock selection bits:
00 = fosc/4096
01 = fosc/1024
10 = fosc/128
11 = Invalid selection
NOTE: When you write a 1 to BTCON.0 (or BTCON.1), the basic timer
divider (or basic timer counter) is cleared. The bit is then cleared
automatically to 0.
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
S3C9444/F9444/C9454/F9454
BASIC TIMER and TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than "1010B" (The "1010B" value disables the watchdog function). A reset clears BTCON to
"00H", automatically enabling the watchdog timer function. A reset also selects the oscillator clock divided by 4096
as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be
cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
Stop mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of f
/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
OSC
When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the
clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, a external power-on reset or an external interrupt occurs to trigger the Stop mode release
and oscillation starts.
2. If a external power-on reset occurred, the basic timer counter will increase at the rate of fOSC/4096. If an
external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock
source.
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.
4. When a BTCNT.4 is set, normal CPU operation resumes.
Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release
10-3
BASIC TIMER and TIMER 0
S3C9444/F9444/C9454/F9454
Oscillation Stabilization Time
Normal Operating mode
0.8 VDD
VDD
Reset Release Voltage
RESET
trst ~ RC
~
Internal
Reset
Release
0.8 VDD
Oscillator
(XOUT)
Oscillator Stabilization Time
BTCNT
clock
10000B
BTCNT
value
00000B
tWAIT = (4096x16)/fOSC
Basic timer increment and
CPU operations are IDLE mode
NOTE: Duration of the oscillator stabilization wait time, t WAIT, when it is released by a
Power-on-reset is 4096 x 16/fOSC.
tRST RC (R and C are value of external power on reset)
~
~
Figure 10-2. Oscillation Stabilization Time on RESET
10-4
S3C9444/F9444/C9454/F9454
BASIC TIMER and TIMER 0
Normal
Operating
Mode
STOP Mode
Oscillation Stabilization Time
Normal
Operating
Mode
VDD
STOP
Instruction
Execution
STOP Mode
Release Signal
External
Interrupt
RESET
STOP
Release
Signal
Oscillator
(XOUT)
BTCNT
clock
10000B
BTCNT
Value
00000B
tWAIT
Basic Timer Increment
NOTE: Duration of the oscillator stabilzation wait time, t WAIT, it is released by an
interrupt is determined by the setting in basic timer control register, BTCON.
BTCON.3
BTCON.2
tWAIT
tWAIT (When fOSC is 10 MHz)
0
0
1
1
0
1
0
1
(4096 x 16)/fosc
(1024 x 16)/fosc
(128 x 16)/fosc
Invalid setting
6.55 ms
1.64 ms
0.2 ms
Figure 10-3. Oscillation Stabilization Time on STOP Mode Release
10-5
BASIC TIMER and TIMER 0
S3C9444/F9444/C9454/F9454
+
PROGRAMMING TIP — Configuring the Basic Timer
This example shows how to configure the basic timer to sample specification.
ORG
0000H
VECTOR
00H,INT_9454
; S3C9454 has only one interrupt vector
;--------------<< Smart Option >>
ORG
DB
DB
DB
DB
003CH
00H
00H
0E7H
03H
; 003CH, must be initialized to 0
; 003DH, must be initialized to 0
; 003EH, enable LVR (2.3 V)
; 003FH, internal RC (3.2 MHz in V = 5 V)
DD
;--------------<< Initialize System and Peripherals >>
ORG
0100H
RESET:
DI
LD
LD
·
; Disable interrupt
; Select non-divided CPU clock
; Stack pointer must be set
CLKCON,#00011000B
SP,#0C0H
·
LD
BTCON,#02H
; Enable watchdog function
; Basic timer clock: f
/4096
OSC
; Basic counter (BTCNT) clear
·
·
·
EI
; Enable interrupt
;--------------<< Main loop >>
MAIN:
·
LD
BTCON,#02H
; Enable watchdog function
; Basic counter (BTCNT) clear
·
·
·
JR
T,MAIN
;
;--------------<< Interrupt Service Routines >>
INT_9454:
·
; Interrupt enable bit and pending bit check
·
;
·
; Pending bit clear
;
IRET
·
·
END
;
10-6
S3C9444/F9444/C9454/F9454
BASIC TIMER and TIMER 0
TIMER 0
TIMER 0 CONTROL REGISTERS (T0CON)
The timer 0 control register, T0CON, is used to select the timer 0 operating mode (interval timer) and input clock
frequency, to clear the timer 0 counter, and to enable the T0 match interrupt. It also contains a pending bit for T0
match interrupts.
A reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency
of fOSC /4096, and disables the T0 match interrupts. The T0 counter can be cleared at any time during normal
operation by writing a "1" to T0CON.3.
Timer 0 Control Register
D3H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 input clock selection bits:
00 = fosc/4096
01 = fosc/256
10 = fosc/8
11 = fosc
Timer 0 interrupt pending bit:
0 = No T0 interrupt pending (when read)
0 = Clear T0 pending bit (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
Timer 0 interrupt enable bit:
0 = Disable T0 interrupt
1 = Enable T0 interrupt
Not used for S3C9444/C9454
Not used for S3C9444/C9454
Timer 0 counter clear bit:
0 = No effect
1 = Clear the Timer 0 counter (when write)
Figure 10-4. Timer 0 Control Registers (T0CON)
10-7
BASIC TIMER and TIMER 0
S3C9444/F9444/C9454/F9454
TIMER 0 FUNCTION DESCRIPTION
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector
00H) and then clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment
until it reaches "10H". At this point, the Timer 0 interrupt request is generated, the counter value is reset and
counting resumes.
T0CON.3
Counter (T0CNT)
Comparator
R (clear)
CLK
Timer 0 counter clear
Match
PND
IRQ0 (T0INT)
Data Register (T0DATA)
T0CON.1
Interrupt Enable/Disable
NOTE:
T0CON.3 is not auto-cleared, you must pay attention when clear pending bit
(refer to P10-12)
Figure 10-5. Simplified Timer 0 Function Diagram (Interval Timer Mode)
10-8
S3C9444/F9444/C9454/F9454
BASIC TIMER and TIMER 0
Match Match Match
Match Match Match Match
Compare Value
(T0DATA)
Up Counter Value
(T0CNT)
00H
Clear Clear
Count start
T0CON.3 1
Clear
T0DATA
Value change
Counter Clear
(T0CON.3)
Interrupt Request
(T0CON.0)
T0 Match Output
(P2.0)
Figure 10-6. Timer 0 Timing Diagram
10-9
BASIC TIMER and TIMER 0
S3C9444/F9444/C9454/F9454
Bit 1
RESET or
STOP
Basic Timer Control Register
(Write '1010xxxxB' to disable.)
Bits 3, 2
MUX
MUX
Data Bus
Clear
1/4096
RESET
8-Bit Up Counter
(BTCNT, Read-Only)
OVF
1/1024
1/128
XIN
DIV
R
When BTCNT.4 is set after
releasing from RESET or STOP
mode, CPU clock starts.
Bit 0
Data Bus
Bits 7, 6
MUX
R
1/4096
1/256
1/8
Clear
Bit 3
Bit 1
Bit 0
T0CNT (D0H)
(Read-Only)
DIV
XIN
1
Match
8-Bit Comparator
T0DATA Buffer
IRQ0
P2.0
P2CONL.1-.0
Bit 3
Match Signal
T0DATA (D1H)
(Read/Write)
Basic Timer Control Register
Timer 0 Control Register
Data Bus
NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval
(until bit 4 the basic timer counter is set).
Figure 10-7. Basic Timer and Timer 0 Block Diagram
10-10
S3C9444/F9444/C9454/F9454
BASIC TIMER and TIMER 0
+
PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode)
The following sample program sets Timer 0 to interval timer mode.
ORG
0000H
VECTOR
00H,INT_9454
; S3C9454 has only one interrupt vector
ORG
DB
DB
DB
DB
003CH
00H
00H
0E7H
03H
; 003CH, must be initialized to 0
; 003DH, must be initialized to 0
; 003EH, enable LVR (2.3 V)
; 003FH, internal RC (3.2 MHz in V = 5 V)
DD
ORG
0100H
RESET:
DI
; Disable interrupt
; Watchdog disable
; Select non-divided CPU clock
; Set stack pointer
;
; P0.0–0.7 push-pull output
; P1.0–P1.1 push-pull output
;
LD
LD
LD
LD
LD
LD
LD
LD
BTCON,#10100011B
CLKCON,#00011000B
SP,#0C0H
P0CONH,#10101010B
P0CONL,#10101010B
P1CON,#00001010B
P2CONH,#01001010B
P2CONL,#10101010B
; P2.0–P2.6 push-pull output
;--------------<< Timer 0 settings >>
LD
LD
T0DATA,#50H
T0CON,#01001010B
; CPU = 11.0592 MHz, interrupt interval = 2 msec
; f
/256, Timer0 interrupt enable
OSC
·
·
·
EI
; Enable interrupt
; Start main loop
;--------------<< Main loop >>
MAIN:
NOP
·
·
·
CALL
·
LED_DISPLAY
JOB
; Sub-block module
·
·
CALL
; Sub-block module
·
·
·
JR
T,MAIN
;
10-11
BASIC TIMER and TIMER 0
S3C9444/F9444/C9454/F9454
+
PROGRAMMING TIP1 – Configuring Timer 0 (Interval Mode) (Continued)
LED_DISPLAY: NOP
;
;
;
;
;
·
·
·
RET
JOB:
NOP
·
;
;
;
;
;
·
·
RET
;--------------<< Interrupt Service Routines >>
INT_9454:
TM
JR
T0CON,#00000010B
Z,NEXT_CHK1
; Interrupt enable check
;
TM
JP
T0CON,#00000001B
NZ,INT_TIMER0
; If timer 0 interrupt was occurred,
; T0CON.0 bit would be set.
NEXT_CHK1:
INT_TIMER0:
·
; Interrupt enable bit and pending bit check
·
;
;
;
·
IRET
; Timer 0 interrupt service routine
·
·
·
AND
IRET
T0CON,#11110110B
;
;
Pending bit clear
·
·
END
;
10-12
S3C9444/F9444/C9454/F9454
8-BIT PWM
11 8-BIT PWM (PULSE WIDTH MODULATION)
OVERVIEW
This microcontroller has the 8-bit PWM circuit. The operation of all PWM circuit is controlled by a single control
register, PWMCON.
The PWM counter is a 8-bit incrementing counter. It is used by the 8-bit PWM circuits. To start the counter and
enable the PWM circuits, you set PWMCON.2 to "1". If the counter is stopped, it retains its current count value;
when re-started, it resumes counting from the retained count value. When there is a need to clear the counter you
set PWMCON.3 to "1".
You can select a clock for the PWM counter by set PWMCON.6–.7. Clocks which you can select are f
/64,
OSC
f
/8, f
/2, f
/1.
OSC
OSC
OSC
FUNCTION DESCRIPTION
PWM
The 8-bit PWM circuits have the following components:
— 6-bit comparator and extension cycle circuit
— 6-bit reference data register (PWMDATA.7–.2)
— 2-bit extension data register (PWMDATA.1–.0)
— PWM output pins (P0.6/PWM)
PWM counter
To determine the PWM module's base operating frequency, the upper 6-bits of counter is compared to the PWM
data (PWMDATA.7–.2). In order to achieve higher resolutions, the lower 2-bits of the counter can be used to
modulate the "stretch" cycle. To control the "stretching" of the PWM output duty cycle at specific intervals, the
lower 2-bits of counter value is compared with the PWMDATA.1–.0.
11-1
8-BIT PWM
S3C9444/F9444/C9454/F9454
PWM data and extension registers
PWM (duty) data registers, located in F2H, determine the output value generated by each 8-bit PWM circuit.
To program the required PWM output, you load the appropriate initialization values into the 6-bit reference data
register (PWMDATA.7–.2) and the 2-bit extension data register (PWMDATA.1–.0). To start the PWM counter, or
to resume counting, you set PWMCON.2 to "1".
A reset operation disables all PWM output. The current counter value is retained when the counter stops. When
the counter starts, counting resumes at the retained value.
PWM clock rate
The timing characteristics of PWM output is based on the f
determined by the setting of PWMCON.6–.7.
clock frequency. The PWM counter clock value is
OSC
Table 11-1. PWM Control and Data Registers
Register Name
Mnemonic
PWMDATA.7–.2
PWMDATA.1–.0
PWMCON
Address
F2H.7–.2
F2H.1–.0
F3H
Function
PWM data registers
6-bit PWM basic cycle frame value
2-bit extension ("stretch") value
PWM control registers
PWM counter stop/start (resume), and
PWM counter clock settings
PWM function Description
The PWM output signal toggles to Low level whenever the lower 6-bit of counter matches the reference data
register (PWMDATA.7–.2). If the value in the PWMDATA.7–.2 register is not zero, an overflow of the lower 6-bits
of counter causes the PWM output to toggle to High level. In this way, the reference value written to the reference
data register determines the module's base duty cycle.
The value in the upper 2-bits of counter is compared with the extension settings in the 2-bit extension data register
(PWMDATA.1–.0). This lower 2-bits of counter value, together with extension logic and the PWM module's
extension data register , is then used to "stretch" the duty cycle of the PWM output. The "stretch" value is one
extra clock period at specific intervals, or cycles (see Table 11-2).
If, for example, the value in the extension data register is '01B', the 2nd cycle will be one pulse longer than the
other 3 cycles. If the base duty cycle is 50 %, the duty of the 2nd cycle will therefore be "stretched" to
approximately 51% duty. For example, if you write 10B to the extension data register, all odd-numbered pulses will
be one cycle longer. If you write 11H to the extension data register, all pulses will be stretched by one cycle except
the 4th pulse. PWM output goes to an output buffer and then to the corresponding PWM output pin. In this way,
you can obtain high output resolution at high frequencies.
11-2
S3C9444/F9444/C9454/F9454
8-BIT PWM
Table 11-2. PWM output "stretch" Values for Extension Data Register (PWMDATA.1–.0)
PWMDATA Bit (Bit1–Bit0)
"Stretched" Cycle Number
00
01
10
11
–
2
1, 3
1, 2, 3
0H
40H
80H
PWM
Clock:
4 MHz
000000xxB
000001xxB
250 ns
250 ns
PWM
Data
Register
Values:
(PWMDATA)
100000xxB
111111xxB
8 ms
8 ms
250 ns
Figure 11-1. 8-Bit PWM Basic Waveform
11-3
8-BIT PWM
S3C9444/F9444/C9454/F9454
0H
40H
PWM Clock: 4 MHz
000010xxB
500 ns
PWMDATA
: 0000 1001B
Basic Extended
waveform waveform
1st 2nd 3th 4th 1st 2nd 3th 4th
0H
40H
4 MHz
750 ns
Figure 11-2. 8-Bit Extended PWM Waveform
11-4
S3C9444/F9444/C9454/F9454
8-BIT PWM
PWM CONTROL REGISTER (PWMCON)
The control register for the PWM module, PWMCON, is located at register address F3H. PWMCON is used the 8-
bit PWM modules. Bit settings in the PWMCON register control the following functions:
— PWM counter clock selection
— PWM data reload interval selection
— PWM counter clear
— PWM counter stop/start (or resume) operation
— PWM counter overflow (8-bit counter overflow) interrupt control
A reset clears all PWMCON bits to logic zero, disabling the entire PWM module.
PWM Control Register (PWMCON)
F3H, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
PWM input clock
selection bits:
00 = fOSC/64
01 = fOSC/8
PWM OVF interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition (when write)
1 = Interrupt pending
10 = fOSC/2
11 = fOSC/1
PWM OVF interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Not used for
S3C9444/C9454
PWM counter enable bit:
0 = Stop counter
1 = Start (resume countering)
PWMDATA reload
interval selection bit:
0 : reload from 8-bit up
counter overflow
1: reload from 6-bit up
counter overflow
PWM counter clear bit:
0 = No effect
1 = Clear the PWM counter
Figure 11-3. PWM Control Register (PWMCON)
11-5
8-BIT PWM
S3C9444/F9444/C9454/F9454
fOSC/8
fOSC
fOSC/64 fOSC/2
MUX
PWMCON.6-.7
From 8-bit up counter (7:6)
From 8-bit up counter (5:0)
2-bit
6-bit
Counter
Counter
PWMCON.2
"1" When REG > Count
"1" When REG = Count
6-bit
Comparator
P0.6/PWM
6-bit Data
Buffer
Extension
Control Logic
Extension Data
Buffer
F2H
bit7-2
6-bit Data
Register (F2H)
F2H
bit1-0
PWM Extension
Data Register
PWMCON.3 (clear)
8 or 6-bit up counter overflow
DATA BUS (7:0)
Figure 11-4. PWM Functional Block Diagram
11-6
S3C9444/F9444/C9454/F9454
8-BIT PWM
+
PROGRAMMING TIP — Programming the PWM Module to Sample Specifications
;--------------<< Interrupt Vector Address >>
ORG
0000H
VECTOR
00H,INT_9454
; S3C9454 has only one interrupt vector
;--------------<< Smart Option >>
ORG
003CH
DB
00H
00H
0E7H
03H
; 003CH, must be initialized to 0.
; 003DH, must be initialized to 0.
; 003EH, enable LVR (2.3 V)
DB
DB
DB
; 003FH, internal RC (3.2 MHz in V = 5 V)
DD
;--------------<< Initialize System and Peripherals >>
ORG
DI
LD
·
0100H
RESET:
; disable interrupt
; Watchdog disable
BTCON,#10100011B
·
LD
LD
P0CONH,#10011010B
PWMCON,#00000110B ; f
; Configure P0.6 PWM output
/64, counter/interrupt enable
OSC
LD
·
PWMDATA,#80H
;
·
EI
; Enable interrupt
;--------------<< Main loop >>
MAIN:
;
;
;
;
;
;
·
·
·
·
JR
t,MAIN
;--------------<< Interrupt Service Routines >>
INT_9454:
·
; Interrupt enable bit and pending bit check
TM
JR
TM
JP
PWMCON,#00000010B ; Interrupt enable check
Z,NEXT_CHK1
PWMCON,#00000001B ; Interrupt pending bit check
NZ,INT_PWM ; PWMCON's pending bit set --> PWM interrupt
;
NEXT_CHK1:
·
·
·
IRET
;
11-7
8-BIT PWM
S3C9444/F9444/C9454/F9454
+
PROGRAMMING TIP — Programming the PWM Module to Sample Specifications (Continued)
INT_PWM:
; PWM interrupt service routine
·
·
·
AND
PWMCON,#11110110B ; pending bit clear
IRET
;
·
·
END
11-8
S3C9444/F9444/C9454/F9454
A/D CONVERTER
12 A/D CONVERTER
OVERVIEW
The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
one of the nine input channels to equivalent 10-bit digital values. The analog input level must lie between the V
DD
and V values. The A/D converter has the following components:
SS
— Analog comparator with successive approximation logic
— D/A converter logic
— ADC control register (ADCON)
— Nine multiplexed analog data input pins (ADC0–ADC8)
— 10-bit A/D conversion data output register (ADDATAH/L):
To initiate an analog-to-digital conversion procedure, you write the channel selection data in the A/D converter
control register ADCON to select one of the nine analog input pins (ADCn, n = 0–8) and set the conversion start or
enable bit, ADCON.0. The read-write ADCON register is located at address F7H.
During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the
approximate half-way point of an 10-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time.
You can dynamically select different channels by manipulating the channel selection bit value (ADCON.7–4) in the
ADCON register. To start the A/D conversion, you should set a the enable bit, ADCON.0. When a conversion is
completed, ACON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the
ADDATA register where it can be read. The A/D converter then enters an idle state. Remember to read the
contents of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the
next conversion result.
NOTE
Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog
level at the ADC0–ADC8 input pins during a conversion procedure be kept to an absolute minimum. Any
change in the input level, perhaps due to circuit noise, will invalidate the result.
12-1
A/D CONVERTER
S3C9444/F9444/C9454/F9454
USING A/D PINS FOR STANDARD DIGITAL INPUT
The ADC module's input pins are alternatively used as digital input in port 0 and P2.6.
A/D CONVERTER CONTROL REGISTER (ADCON)
The A/D converter control register, ADCON, is located at address F7H. ADCON has four functions:
— Bits 7-4 select an analog input pin (ADC0–ADC8).
— Bit 3 indicates the status of the A/D conversion.
— Bits 2-1 select a conversion speed.
— Bit 0 starts the A/D conversion.
Only one analog input channel can be selected at a time. You can dynamically select any one of the ten analog
input pins (ADC0–ADC8) by manipulating the 4-bit value for ADCON.7–ADCON.4.
A/D Converter Control Register (ADCON)
F7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
A/D Conversion input pin selection bits
Conversion start bit:
0 = No effect
1 = A/D conversion start
0000
ADC0 (P0.0)
0001
0010
0011
0100
0101
0110
0111
1000
1001
...
ADC1 (P0.1)
ADC2 (P0.2)
ADC3 (P0.3)
ADC4 (P0.4)
ADC5 (P0.5)
ADC6 (P0.6)
ADC7 (P0.7)
ADC8 (P2.6)
Conversion speed selection bits: (note)
00 = fOSC/16 (fOSC < 10 MHz)
01 = fOSC/8 (fOSC < 10 MHz)
10 = fOSC/4 (fOSC < 10 MHz)
11 = fOSC/1 (fOSC < 4 MHz)
Connected with GND internally
...
1111
Connected with GND internally
End-of-conversion (ECO) status bit:
0 = A/D conversion is in progress
1 = A/D conversion complete
NOTE:
Maximum ADC clock input = 4 MHz
Figure 12-1. A/D Converter Control Register (ADCON)
12-2
S3C9444/F9444/C9454/F9454
A/D CONVERTER
INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input
level must remain within the range V to V
SS
DD.
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 V
DD.
- A/D Converter Control Register
ADCON (F7H)
ADCON.0 (ADEN)
ADCON.7-.4
Control
Circuit
Clock
Selector
ADCON.3
(EOC Flag)
M
U
L
T
I
ADCON.2-.1
ADC0/P0.0
ADC1/P0.1
ADC2/P0.2
Successive
+
-
Approximation
Circuit
Analog
Comparator
P
L
E
X
E
R
ADC7/P0.7
ADC8/P2.6
Conversion Result
VDD
VSS
ADDATAH ADDATAL
D/A Converter
(F8H)
(F9H)
To data bus
Figure 12-2. A/D Converter Circuit Diagram
MSB
.7
-
.6
-
.5
-
.4
-
.3
-
.2
-
.1
.1
.0
.0
LSB
LSB
ADDATAH
ADDATAL MSB
Figure 12-3. A/D Converter Data Register (ADDATAH/L)
12-3
A/D CONVERTER
S3C9444/F9444/C9454/F9454
ADC0N.0
Conversion
1
50 ADC clock
Start
ECO
ADDATA
9
8
7
6
5
4
3
2
1
0
Privious
Value
ADDATAH (8-bit) + ADDATAL (2-bit)
Valid
data
Set-up time
10 clock
40 clock
Figure 12-4. A/D Converter Timing Diagram
CONVERSION TIMING
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: With an 10 MHz CPU
clock frequency, one clock cycle is 400 ns (4/fosc). If each bit conversion requires 4 clocks, the conversion rate is
calculated as follows:
4 clocks/bit ´ 10-bits + step-up time (10 clock) = 50 clocks
50 clock ´ 400 ns = 20 ms at 10 MHz, 1 clock time = 4/f
(assuming ADCON.2–.1 = 10)
OSC
INTERNAL A/D CONVERSION PROCEDURE
1. Analog input must remain between the voltage range of V and V
SS
DD.
2. Configure the analog input pins to input mode by making the appropriate settings in P0CONH, P0CONL and
P2CONH registers.
3. Before the conversion operation starts, you must first select one of the nine input pins (ADC0–ADC8) by
writing the appropriate value to the ADCON register.
4. When conversion has been completed, (50 clocks have elapsed), the EOC flag is set to “1”, so that a check
can be made to verify that the conversion was successful.
5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), then the
ADC module enters an idle state.
6. The digital conversion result can now be read from the ADDATAH and ADDATAL register.
12-4
S3C9444/F9444/C9454/F9454
A/D CONVERTER
VDD
XIN
Analog
Input Pin
ADC0-ADC8
XOUT
101
S3C9444/C9454
VSS
Figure 12-5. Recommended A/D Converter Circuit for Highest Absolute Accuracy
12-5
A/D CONVERTER
S3C9444/F9444/C9454/F9454
+
Programming Tip– Configuring A/D Converter
ORG 0000H
VECTOR 00H,INT_9454
; S3C9454 has only one interrupt vector
ORG
003CH
DB
DB
DB
DB
00H
00H
0E7H
03H
; 003CH, must be initialized to 0
; 003DH, must be initialized to 0
; 003EH, enable LVR (2.3 V)
; 003FH, internal RC (3.2 MHz in V = 5 V)
DD
ORG
DI
LD
·
0100H
RESET:
; disable interrupt
; Watchdog disable
BTCON,#10100011B
·
·
LD
LD
LD
EI
P0CONH,#11111111B
P0CONL,#11111111B
P2CONH,#00100000B
; Configure P0.4–P0.7 AD input
; Configure P0.0–P0.3 AD input
; Configure P2.6 AD input
; Enable interrupt
;--------------<< Main loop >>
MAIN:
·
·
·
CALL
AD_CONV
; Subroutine for AD conversion
·
·
·
JR
t,MAIN
;
AD_CONV:
LD
ADCON,#00000001B
; Select analog input channel ® P0.0
; select conversion speed ® f
/16
OSC
; set conversion start bit
NOP
NOP
; If you select conversion speed to f
/16
OSC
NOP
; at least three nop must be included
12-6
S3C9444/F9444/C9454/F9454
A/D CONVERTER
+
Programming Tip– Configuring A/D Converter (Continued)
CONV_LOOP: TM
ADCON,#00001000B
Z,CONV_LOOP
R0,ADDATAH
; Check EOC flag
JR
LD
; If EOC flag=0, jump to CONV_LOOP until EOC flag=1
; High 8 bits of conversion result are stored
; to ADDATAH register
LD
LD
R1,ADDATAL
; Low 2 bits of conversion result are stored
; to ADDATAL register
; Select analog input channel ® P0.1
ADCON,#00010011B
; Select conversion speed ® f
/8
OSC
; Set conversion start bit
CONV_LOOP2:TM
ADCON,#00001000B
Z,CONV_LOOP2
R2,ADDATAH
; Check EOC flag
JR
LD
LD
·
R3,ADDATAL
·
·
RET
;
INT_9454:
·
; Interrupt enable bit and pending bit check
·
;
·
; Pending bit clear
;
IRET
·
·
END
12-7
S3C9444/F9444/C9454/F9454
ELECTRICAL DATA
13 ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9444/C9454 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Input Timing Measurement Points
— Oscillator characteristics
— Oscillation stabilization time
— Operating Voltage Range
— Schmitt trigger input characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET
— A/D converter electrical characteristics
— LVR circuit characteristics
— LVR reset Timing
13-1
ELECTRICAL DATA
S3C9444/F9444/C9454/F9454
Table 13-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
VDD
VI
Supply voltage
Input voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 25
V
All ports
V
V
VO
IOH
Output voltage
Output current high
All output ports
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 80
+ 30
IOL
Output current low
mA
All I/O pins active
–
+ 150
TA
Operating temperature
Storage temperature
– 40 to + 85
°C
°C
TSTG
–
– 65 to + 150
13-2
S3C9444/F9444/C9454/F9454
ELECTRICAL DATA
Table 13-2. DC Electrical Characteristics
(TA = – 25 C to + 85 C, VDD = 2.0 V to 5.5 V)
°
°
Parameter
Input high
voltage
Symbol
Conditions
Min
Typ
Max
Unit
VIH1
VDD= 2.0 to 5.5 V
0.8 VDD
VDD
Ports 0, 1, 2 and
RESET
–
V
VIH2
VIL1
XIN and XOUT
VDD- 0.1
–
VDD= 2.0 to 5.5 V
0.2 VDD
Input low
voltage
Ports 0, 1, 2 and
RESET
–
V
VIL2
VOH
XIN and XOUT
0.1
–
IOH = – 10 mA
VDD= 4.5 to 5.5 V
VDD= 4.5 to 5.5 V
VDD-1.5 VDD- 0.4
Output high
voltage
V
V
ports 0, 1, 2
IOL = 25 mA
VOL
Output low
voltage
–
–
0.4
–
2.0
1
port 0, 1, and 2
All input except
ILIH2
ILIH1
VIN = VDD
Input high
leakage current
uA
ILIH2
ILIL1
XIN, XOUT
VIN = VDD
IN = 0 V
20
–1
V
Input low
All input except
–
–
uA
ILIL2 and RESET
leakage current
ILIL2
ILOH
XIN, XOUT
VIN = 0 V
–20
2
VOUT = VDD
Output high
leakage current
All output pins
–
–
–
–
uA
uA
kΩ
ILOL
RP
VOUT = 0 V
VDD = 5 V
VDD = 5 V
Output low
leakage current
All output pins
VIN = 0 V
–2
100
100
10
Pull-up resistors
25
25
–
50
50
5
Ports 0, 1, 2
VIN = 0 V
RP
Pull-down
resistors
Ports 1
Run mode
10 MHz CPU clock
3 MHz CPU clock
IDD1
VDD = 4.5 to 5.5 V
Supply current
mA
uA
VDD = 2.0 V
2
2
5
4
IDD2
VDD = 4.5 to 5.5 V
Idle mode
10 MHz CPU clock
3 MHz CPU clock
–
–
VDD = 2.0 V
0.5
0.1
1.5
5
IDD3
VDD = 4.5 to 5.5 V
(LVR disable)
Stop mode
°
TA = 25 C
DD = 4.5 to 5.5 V
(LVR enable)
V
100
30
200
60
°
TA = 25 C
DD = 2.6 V
(LVR enable)
V
°
TA = 25 C
) current, current by ADC module is not included.
DD2
NOTE: In STOP (I
), IDLE (I
DD3
13-3
ELECTRICAL DATA
S3C9444/F9444/C9454/F9454
Table 13-3. AC Electrical Characteristics
(TA = – 25 C to + 85 C, VDD = 2.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
INT0, INT1
VDD = 5 V ± 10 %
Min
Typ
Max
Unit
tINTL
Interrupt input
low width
–
200
–
ns
tRSL
RESET input
low width
–
1
–
us
Input
VDD = 5 V ± 10 %
t
INTL
tINTH
0.8 VDD
0.2 VDD
XIN
Figure 13-1. Input Timing Measurement Points
13-4
S3C9444/F9444/C9454/F9454
ELECTRICAL DATA
Table 13-4. Oscillator Characteristics
°
°
(T = – 25 C to + 85 C)
A
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
VDD = 4.5 to 5.5 V
Main crystal or
ceramic
1
–
10
MHz
XIN
C1
XOUT
C2
V
V
DD = 2.7 to 4.5 V
DD = 2.0 to 2.7 V
1
1
1
–
–
–
6
3
MHz
MHz
MHz
VDD = 4.5 to 5.5 V
External clock
(Main System)
10
XIN
XOUT
V
V
DD = 2.7 to 4.5 V
DD = 2.0 to 2.7 V
1
1
–
–
–
4
6
3
–
MHz
MHz
MHz
VDD = 4.75 to 5.25 V
Tolerance:10 %
External RC
oscillator
–
V
DD = 4.75 to 5.25 V
Internal RC
Oscillator
3.2
0.5
Table 13-5. Oscillation Stabilization Time
(T = – 25 C to + 85 C, VDD = 3.0 V to 5.5 V)
°
°
A
Oscillator
Main crystal
Test Condition
Min
Typ
Max
Unit
fOSC > 1.0 MHz
–
–
–
20
10
ms
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.
Main ceramic
–
ms
X
IN input high and low width (tXH, tXL
tWAIT when released by a reset (1)
WAIT when released by an interrupt (2)
)
External clock
(main system)
25
–
–
216/fOSC
–
500
–
ns
ms
ms
Oscillator
stabilization
wait time
–
–
t
NOTES:
1.
f
is the oscillator frequency.
OSC
t
2. The duration of the oscillator stabilization wait time,
settings in the basic timer control register, BTCON.
, when it is released by an interrupt is determined by the
WAIT
13-5
ELECTRICAL DATA
S3C9444/F9444/C9454/F9454
CPU Clock
10 MHz
6 MHz
4 MHz
3 MHz
2 MHz
1 MHz
1
2
2.7 3
4 4.5 5 5.5 6
7
Supply Voltage (V)
Figure 13-2. Operating Voltage Range
VOUT
VDD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
A
B
C
D
VIN
0.3 VDD
0.7 VDD
Figure 13-3. Schmitt Trigger Input Characteristics Diagram
13-6
S3C9444/F9444/C9454/F9454
ELECTRICAL DATA
Table 13-6. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 25 C to + 85 C, VDD = 2.0 V to 5.5 V)
A
Parameter
Symbol
Conditions
Stop mode
Min
Typ
Max
Unit
VDDDR
Data retention
supply voltage
2.0
–
5.5
V
IDDDR
Stop mode; VDDDR = 2.0 V
Data retention
supply current
–
0.1
5
uA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
RESET
Oscillation
Occurs
Stabilization
Time
Stop Mode
Data Retention Mode
VDD
Normal
Operating
Mode
VDDDR
Execution Of
Stop Instrction
RESET
t
WAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC
Figure 13-4. Stop Mode Release Timing When Initiated by a RESET
13-7
ELECTRICAL DATA
S3C9444/F9444/C9454/F9454
Table 13-7. A/D Converter Electrical Characteristics
(T = – 25 C to + 85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V)
°
°
A
Parameter
Symbol
Test Conditions
VDD = 5.12 V
Min
Typ
Max
Unit
Total accuracy
–
–
–
LSB
± 3
CPU clock = 10 MHz
VSS = 0 V
Integral linearity
error
ILE
–
–
–
–
″
± 2
± 1
Differential linearity
error
DLE
″
Offset error of top
EOT
EOB
–
–
″
″
± 1
± 1
± 3
± 2
Offset error of
bottom
tCON
VIAN
RAN
fOSC = 10 MHz
Conversion
time (1)
–
VSS
2
20
–
–
VDD
–
µs
V
Analog input
voltage
–
–
Analog input
impedance
–
MΩ
µA
mA
IADIN
IADC
VDD = 5 V
VDD = 5 V
VDD = 3 V
Analog input
current
–
–
10
3
Analog block
current (2)
–
1
0.5
1.5
V
DD = 5 V
–
100
500
nA
power down mode
NOTES:
1. “Conversion time” is the time required from the moment a conversion operation starts until it ends.
2.
I
is operating current during A/D conversion.
ADC
13-8
S3C9444/F9444/C9454/F9454
ELECTRICAL DATA
Table 13-8. LVR Circuit Characteristics
(T = – 25 C, VDD = 2.0 V to 5.5 V)
°
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VLVR
Low voltage reset
–
–
2.3
3.0
3.9
V
VHYS
tR
LVR hysteresis voltage
–
0.3
–
V
(note)
Power supply voltage
rise time
10
us
tOFF
Power supply voltage
off time
0.5
s
16
NOTE:
2 /fx ( = 6.55 ms at fx = 10 MHz)
t
OFF
tR
VDD
VLVR,MAX
V
HYS
HYS
VLVR
V
VLVR,MIN
Figure 13-5. LVR Reset Timing
13-9
S3C9444/F9444/C9454/F9454
MECHANICAL DATA
14 MECHANICAL DATA
OVERVIEW
The S3C9454 is available in a 20-pin DIP package (Samsung: 20-DIP-300A), a 20-pin SOP package (Samsung:
20-SOP-375), a 16-pin DIP package (Samsung: 16-DIP-300A). Package dimensions are shown in Figure 15-1,
15-2, and 15-3.
The S3C9444 is available in a 8-pin DIP package (SAMSUNG 8-DIP-300A), a 8-pin SOP package (SAMSUNG 8-
SOP-225).
Package dimensions are shown in figure 14-4 and 14-5.
#20
#11
0-15
20-DIP-300A
#1
#10
26.80 MAX
26.40
±
0.20
0.46
1.52
±
±
0.10
0.10
2.54
(1.77)
NOTE: Dimensions are in millimeters.
Figure 14-1. 20-DIP-300A Package Dimensions
14-1
MECHANICAL DATA
S3C9444/F9444/C9454/F9454
0-8
#20
#11
20-SOP-375
+ 0.10
0.203 - 0.05
#1
#10
13.14 MAX
12.74 ±
0.20
0.10 MAX
1.27
(0.66)
+ 0.10
0.40 - 0.05
NOTE: Dimensions are in millimeters.
Figure 14-2. 20-SOP-375 Package Dimensions
14-2
S3C9444/F9444/C9454/F9454
MECHANICAL DATA
#16
#9
0-15
16-DIP-300A
#1
#8
19.80 MAX
19.40 ± 0.20
0.46 ± 0.10
1.50 ± 0.10
2.54
(0.81)
NOTE: Dimensions are in millimeters.
Figure 14-3. 16-DIP-300A Package Dimensions
14-3
MECHANICAL DATA
S3C9444/F9444/C9454/F9454
#8
#5
0-15
8-DIP-300
#1
#4
9.60 MAX
9.20
±
0.20
2.54
(0.79)
0.46
1.52
±
±
0.10
0.10
NOTE: Dimensions are in millimeters.
Figure 14-4. 8-DIP-300 Package Dimensions
14-4
S3C9444/F9444/C9454/F9454
MECHANICAL DATA
0-8
#8
#5
8-SOP-225
+ 0.10
0.15 - 0.05
#1
#4
5.13 MAX
4.92
±
0.20
0.10 MAX
1.27
(0.56)
0.41 ± 0.10
NOTE: Dimensions are in millimeters.
Figure 14-5. 8-SOP-225 Package Dimensions
14-5
S3C9444/F9444/C9454/F9454
S3F9444/F9454 MTP
15 S3F9444/F9454 MTP
OVERVIEW
The S3F9444/F9454 single-chip CMOS microcontroller is the MTP (Multi Time Programmable) version of the
S3C9444/C9454 microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is
accessed by serial data format.
The S3F9444/F9454 is fully compatible with the S3C9444/C9454, in function, in D.C. electrical characteristics, and
in pin configuration. Because of its simple programming requirements, the S3F9444/F9454 is ideal for use as an
evaluation chip for the S3C9444/C9454.
VDD/VDD
20
19
18
17
16
15
14
13
12
11
VSS/VSS
XIN/P1.0
XOUT/P1.1
VPP/RESET/P1.2
T0/P2.0
P2.1
1
2
3
4
5
6
7
8
9
10
P0.0/ADC0/INT0/SCL
P0.1/ADC1/INT1/SDA
P0.2/ADC2
P0.3/ADC3
S3F9454
P0.4/ADC4
P0.5/ADC5
P2.2
P0.6/ADC6/PWM
P0.7/ADC7
P2.3
P2.4
P2.6/ADC8/CLO
P2.5
NOTE:
The bolds indicate MTP pin name.
Figure 15-1. Pin Assignment Diagram (20-Pin Package)
15-1
S3F9444/F9454 MTP
S3C9444/F9444/C9454/F9454
16
15
14
13
12
11
10
9
VDD/VDD
VSS/VSS
XIN/P1.0
1
2
3
4
5
6
7
8
P0.0/ADC0/INT0/SCL
P0.1/ADC1/INT1/SDA
P0.2/ADC2
XOUT/P1.1
VPP/RESET/P1.2
T0/P2.0
S3F9454
P0.3/ADC3
P0.4/ADC4
P2.1
P0.5/ADC5
P2.2
P0.6/ADC6/PWM
P2.3
NOTE:
The bolds indicate MTP pin name.
Figure 15-2. Pin Assignment Diagram (16-Pin Package)
VDD/VDD
SS/VSS
1
2
3
4
8
7
6
5
V
P0.0/ADC0/INT0/SCL
P0.1/ADC1/INT1/SDA
P0.2/ADC2
X
IN/P1.0
S3F9444
X
OUT/P1.1
V
PP/RESET/P1.2
NOTE:
The bolds indicate MTP pin name.
Figure 15-3. Pin Assignment Diagram (8-Pin Package)
15-2
S3C9444/F9444/C9454/F9454
S3F9444/F9454 MTP
Table 15-1. Descriptions of Pins Used to Read/Write the Flash ROM
Main Chip
Pin Name
During Programming
I/O
Pin Name
Pin No.
18 (20-pin)
Function
P0.1
SDA
I/O
Serial data pin (output when reading, Input
when writing) Input and push-pull output port
can be assigned
14 (16-pin)
P0.0
SCL
19 (20-pin)
15 (16-pin)
I
I
Serial clock pin (input only pin)
V
4
Power supply pin for flash ROM cell writing
(indicates that MTP enters into the writing
mode). When 12.5 V is applied, MTP is in
writing mode and when 5 V is applied,
MTP is in reading mode. (Option)
RESET, P1.2
PP
V
/V
V
/V
20 (20-pin), 16 (16-pin)
1 (20-pin), 1 (16-pin)
I
Logic power supply pin.
DD SS
DD SS
Table 15-2. Comparison of S3F9444/F9454 and S3C9444/C9454 Features
Characteristic
S3F9444/F9454
4 Kbyte Flash ROM
2.0 V to 5.5 V
S3C9444/C9454
Program Memory
2K/4K byte mask ROM
2.0 V to 5.5 V
Operating Voltage (V
)
DD
V
= 5 V, V = 12.5 V
OTP Programming Mode
DD
PP
Pin Configuration
20 DIP/20 SOP/16 DIP/8 DIP/8 SOP
User Program multi time Programmed at the factory
EPROM Programmability
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V pin of the S3F9444/F9454 Flash ROM programming mode is entered. The
PP
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table
15-3 below.
Table 15-3. Operating Mode Selection Criteria
V
V
Address
(A15–A0)
R/W
Mode
REG/MEM
DD
PP
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
Flash ROM read
Flash ROM program
Flash ROM verify
12.5 V
12.5 V
12.5 V
Flash ROM read protection
NOTE: "0" means Low level; "1" means High level.
15-3
S3C9444/F9444/C9454/F9454
DEVELOPMENT TOOLS
16 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for
S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.
Samsung also offers support software that includes debugger, assembler, and a program for setting options.
SHINE
Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help.
It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized,
moved, scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates
object code in standard hexadecimal format. Assembled program code includes the object code that is used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an
auxiliary definition (DEF) file with device specific information.
SASM86
The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a
source file containing assembly language statements and translates into a corresponding source code, object
code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked
with other object files and loaded into memory.
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value "FF" is filled into the unused ROM area upto the maximum ROM size of the target device
automatically.
16-1
DEVELOPMENT TOOLS
TARGET BOARDS
S3C9444/F9444/C9454/F9454
Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters
are included with the device-specific target board.
MTPs
Multi times programmable microcontrollers (MTPs) are under development for S3C9444/C9454 microcontroller.
IBM-PC AT or Compatible
RS-232C
SMDS2+
Target
Application
System
PROM/OTP Writer Unit
RAM Break/Display Unit
Trace/Timer Unit
Probe
Adapter
TB9444/9454
POD
Target
Board
SAM8 Base Unit
EVA
Chip
Power Supply Unit
Figure 16-1. SMDS Product Configuration (SMDS2+)
16-2
S3C9444/F9444/C9454/F9454
DEVELOPMENT TOOLS
TB9444/9454 TARGET BOARD
The TB9444/9454 target board is used for the S3C9444/C9454 microcontrollers. It is supported by the SMDS2+
development systems.
TB9444/9454
To User_VCC
Off
On
RESET
Idle
+
Stop
+
25
CN1
1
J101
1
20
128 QFP
S3E9450
EVA Chip
1
24
10
11
External
Triggers
8 pin DIP switch
CH1
CH2
SMDS
SMDS2+
SM1333A
Figure 16-2. TB9444/9454 Target Board Configuration
16-3
DEVELOPMENT TOOLS
S3C9444/F9444/C9454/F9454
Comments
Table 16-1. Power Selection Settings for TB9444/9454
Operating Mode
"To User_Vcc" Settings
The SMDS2+ main board
To user_Vcc
supplies V to the target
CC
off
on
External
VCC
TB9444/9454
board (evaluation chip) and
the target system.
Target
System
VSS
VCC
SMDS2+
The SMDS2+ main board
To user_Vcc
supplies V only to the target
CC
External
VCC
TB9444/9454
off
on
board (evaluation chip). The
target system must have its
own power supply.
Target
System
VSS
VCC
SMDS2+
NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:
SMDS2+ Selection (SAM8)
In order to write data into program memory that is available in SMDS2+, the target board should be selected to be
for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
Table 16-2. The SMDS2+ Tool Selection Setting
"SW1" Setting
SMDS SMDS2+
Operating Mode
R/W*
SMDS2+
R/W*
Target
System
16-4
S3C9444/F9444/C9454/F9454
DEVELOPMENT TOOLS
Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources
Target Board Part
Comments
Connector from
External Trigger
Sources of the
External
Triggers
Application System
Ch1
Ch2
You can connect an external trigger source to one of the two
external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint
and trace functions.
ON
OFF
3EH.7 3EH.6 3EH.5 3EH.4 3EH.3 3EH.2 3FH.1 3FH.0
ON
OFF
Low
High
NOTE:
About EVA chip, smart option is determined by DIP switch
not software.
Figure 16-3. DIP Switch for Smart Option
16-5
DEVELOPMENT TOOLS
S3C9444/F9444/C9454/F9454
J101
VSS
P1.0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
P0.0/ADC0/INT0
P0.1/ADC1/INT1
P0.2/ADC2
P1.1
RESET/P1.2
T0/P2.0
P2.1
P0.3/ADC3
P0.4/ADC4
P2.2
P0.5/ADC5
P2.3
P0.6/ADC6/PWM
P0.7/ADC7
P2.4
P2.5
P2.6/ADC8/CLO
Figure 16-4. 20-Pin Connector for TB9444/9454
Target Board
Target System
J101
20
1
1
20
Part Name: AS20D
Order Cods: SM6304
10 11
10 11
Figure 16-5. S3C9444/C9454 Probe Adapter for 20-DIP Package
16-6
相关型号：
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