S3P1860-SK_技术文档

1. S3C1840

S3C1840

DESCRIPTION

S3C1840, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip

ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset

circuit generates reset pulse every certain period, and every halt mode termination time. The S3C1840

microcontroller has been designed for use in small system control applications that require a low-power, cost -

sensitive design solution. In addition, the S3C1840 has been optimized for remote control transmitter.

FEATURES

ROM Size

Four Transmission Frequencies

·

1,024 bytes

·

fxx/12 (1/4 duty), fxx/12 (1/3 duty), fxx/8 (1/2

duty), and no-carrier frequency

RAM Size

Supply Voltage

·

32 nibbles

·

1.8 V-3.6 V (250 kHz £ f_OSC£ 3.9 MHz)

2.2 V-3.6 V (3.9 MHz < f_OSC£ 6 MHz)

Instruction Set

·

39 instructions

Power Consumption

Instruction Cycle Time

13.2 msec at fxx = 455 kHz

·

Halt mode: 1 mA (maxium)

·

Normal mode: 0.5 mA (typical)

Input Ports

Two 4-bit ports (24 pins)/one 4-bit port, one 2-bit

ports (20 pins)

Operating temperature

– 20 °C to 85 °C

·

Package Type

Output Ports

One 4-bit port, seven 1-bit ports (24 pins)/one 4-

bit port, five1-bit ports (20 pins)

·

24 SOP, 20 DIP, 20 SOP

·

Oscillator Frequency divide select

·

Mask Option: fxx = f_OSCor f_OSC/8

Built-in Oscillator

Crystal/ceramic resonator

·

Built-in Reset Circuit

·

Built-in Power-on reset and auto reset circuit for

generating reset pulse every 131072/fxx (288

ms at fxx = 455 kHz)

1-1

S3C1840

BLOCK DIAGRAM

P2.1 - P2.6

Internal P2.13

8

6

P2-Output Latch

5

ROM

64 x 16 x 8-bits

4

16

RAM

6

L Decoder

16 x 2 x 4-bits

PA

PC

2

4

1

PB

4

H

3-Level Stack

4

L

ALU & A

4

P1.0 - P1.3

P0.0 - P0.3

P3.0 - P3.3

4

MUX

SF

Internal P2.9 and P2.10

4

P3 Output Register

(PR)

Internal

P2.0

fXX/8 (1/2)

fXX/12 (1/3)

XX

Auto Reset

DIV

OSC

f

/12 (1/4)

HALT

Internal P2.12

No Carrier

P2.0/REM

I

X

O

X

Figure 1-1. Block diagram

1-2

S3C1840

PIN CONFIGURATION (24 SOP)

VDD

VSS

XI

1

2

24

23

22

21

20

19

18

17

16

15

14

13

P2.0/REM

TEST

P2.1

3

XO

P2.6

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P1.2

P1.3

4

P2.2

5

P2.3

6

S3C1840

P2.4

7

P2.5

8

P3.0

9

P3.1

10

11

12

P3.2

P3.3

Figure 1-2. Pin Configuration (24 SOP)

Table 1-1. PIN Description for 24 PINS

Name

Number

Type

Description

I/O Circuit

Type

P0.0-P0.3

P1.0-P1.3

P2.0 REM

5, 6, 7, 8

Input

4-bit input port when P2.13 is low

4-bit input port when P2.13 is high

A

B

9, 10, 11, 12

23

Output

1-bit individual output for remote carrier

frequency ⁽¹⁾

P2.2-P2.5

P2.1, P2.6

P3.0-P3.3

TEST

20, 19, 18, 17

21, 4

Output

1-bit individual output port

C

D

C

–

16, 15, 14, 13

22

Output

Input

4-bit parallel output port

Input pin for test (Normally connected to V_SS

)

X_I

2

Input

Oscillation clock input

Oscillation clock output

Power supply

–

X_O

3

Output

V_DD

V_SS

24

1

–

Ground

NOTES:

1. The carrier can be selected by software as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier

frequency.

2. Package type can be selected as 24 SOP in the ordering sheet.

1-3

S3C1840

PIN CONFIGURATION (20 DIP, 20 SOP)

VDD

VSS

XI

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

P2.0/REM

TEST

P2.1

XO

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P3.3

P2.2

S3C1840

P2.3

P2.4

P3.0

P3.1

P3.2

Figure 1-3. Pin Configuration (20 DIP, 20 SOP)

Table 1-2. Pin Description for 20 Pins

Name

Number

Type

Description

I/O Circuit

Type

P0.0-P0.3

P1.0-P1.1

P2.0/REM

4, 5, 6, 7

Input

4-bit input port when P2.13 is low

2-bit input port when P2.13 is high

A

B

8, 9

19

Output

1-bit individual output for remote carrier

frequency ⁽¹⁾

P2.2-P2.4

P2.1

16, 15, 14

Output

1-bit individual output port

C

D

C

–

17

P3.0-P3.3

TEST

13, 12, 11, 10

18

Output

Input

4-bit parallel output port

Input pin for test (Normally connected to V_SS

)

X_I

2

Input

Oscillation clock input

Oscillation clock output

Power supply

–

X_O

3

Output

V_DD

V_SS

20

1

–

Ground

NOTES:

1. The carrier can be selected by software as fxx/12 (1/3 duty), fxx/12 (1/4 duty), fxx/8 (1/2 duty), or no-carrier

frequency.

2

Package type can be selected as 20 DIP, or 20 SOP in the ordering sheet.

1-4

S3C1840

I/O CIRCUIT SCHEMATICS

VDD

P-CH

Data

30 -150 k

W

Output

N-CH

Data

Disable^(note)

Input

VSS

NOTE:

If data disable signal is active, halt mode,

the output becomes low state.

VSS

Figure 1-4. I/O Circuit Type A

Figure 1-5. I/O Circuit Type B

VDD

Data

Output

N-CH

Data

Disable^(note)

Output

N-CH

Data

VSS

NOTE:

If data disable signal is active, halt mode,

the output becomes low state.

Figure 1-7. I/O Circuit Type D

Figure 1-6. I/O Circuit Type C

1-5

S3C1840

Table 1-3. Absolute Maximum Ratings

Parameters

Symbols

Ratings

Units

V_DD

Supply Voltage

– 0.3 to 6

V

V_I

– 0.3 to V_DD+ 0.3

Input Voltage

V_O

Output Voltage

T_SLD

T_STG

Soldering Temperature

Storage Temperature

260 (10 sec)

– 55 to 125

°C

Table 1-4. DC Characteristics

(V_DD= 3 V, T_A= 25 °C)

Parameters

Symbols

Test Conditions

Min

Typ

Max

Units

V_DD

Supply Voltage

1.8

3.0

3.6

V

250kHz£ f_OSC£3.9MHz

2.2

3.0

–

3.9MHz< f_OSC£6MHz

T_A

Operating Temperature

High-Level Input Voltage

–

– 20

85

°C

V_IH1

0.7 V_DD

V_DD

All input pins except

X_IN

–

V

V_IH2

V_IL1

X_IN

V_DD-0.3

0

V_DD

–

V

0.3 V_DD

Low-Level Input Voltage

All input pins except

X_IN

V_IL2

I_OH1

I_OL1

I_OL2

X_IN

0

–

0.3

– 14

4.5

V

V_O= 2.0 V

V_O= 0.4 V

High-Level Output Current P2.0

Low-Level Output Current P2.0

– 6.0

1.5

– 9

3.0

1.0

mA

Low-Level

P3 Output

0.5

2.0

Output

P2.1-P2.3

P2.4-P2.6

1.5

0.5

3.0

1.0

4.5

2.0

Current

1-6

S3C1840

Table 1-4. DC Characteristics (Continued)

(V_DD= 3 V, T_A= 25 °C)

Parameters

Symbols

Test Conditions

V_I= V_DD

Min

Typ

Max

Units

I_LIH1

High-Level Input Leakage Current

–

3

uA

All input pins

except X_IN

I_LIH2

I_LIL1

I_LOH

X_IN

–

– 0.6

–

3

– 3

–

10

– 10

3

X_IN

Low-level Input Leakage Current

V_O= V_DD

High-level Output Leakage

Current

uA

All output pins

except P2.0

V_DD= 3 V

Pull-up Resistance of Input Port

Average Supply Current

R

30

–

70

150

1.0

KW

V_I= 0 V

I_DD

V_DD= 3 V

0.5

mA

Crystal/resonator

Non-divide option

f_OSC= 1 MHz

Dvide-8 option

f_OSC= 6 MHz

I_DDH

f_OSC= 0

HALT Current

–

1.0

uA

Clock Frequency

fxx

Crystal/ceramic

250

–

1000

kHz

f_OSC

Oscillator Frequency

Non-divide option

Crystal/ceramic

Divide-8 option

2000

6000

1-7

S3C1840

FUCTIONAL DESCRIPTION

Program Memory (ROM)

The S3C1840's program memory consists of a 1024-byte ROM, organized in 16 pages. Each page is 64 bytes

long. (See Figure 1-10).

ROM addressing is supported by a 10-bit register made up of two sub-registers: a 4-bit Page Address register

(PA), and a 6-bit Program Counter (PC).

Pages 0 through 15 (FH) can each access 64 (3FH) bytes.

ROM addressing occurs as follows: The 10-bit register selects one of the ROM's 1024-bytes. A new address is

then loaded into the PC register during each instruction cycle.

Unless a transfer-of -control instruction such as JP,CALL, or RET is encountered, the PC is loaded with the next

sequential 6-bit address in the page, PC + 1. In this case, the next address of 3FH would be 00H.

Only the PAGE instruction can change the Page Buffer (PB) to a specified value.

When a JP or CALL instruction is executed, and if the Status Flag is set to "1", the contents of the PB are loaded

into the PA register. If the Status Flag is "0", however, the JP or CALL is executed like NOP instruction in an

instruction cycle and the Status Flag is set to "1". After that, program execution proceeds.

Page-In Addressing

All instructions, including, JP and CALL, can be executed by page. (See Figure 1-8). When the Status Flag is

"1", a JP or CALL causes a program to branch to its address (operand) in a page.

PA

PB

PC

4

address to be jumped ; if SF = 1

Figure 1-8. Page-In Addressing

Page-To-Page Addressing

When a PAGE instruction occurs, and if the Status Flag is "1", a JP or CALL instruction will cause a program to

branch to its address (operand) across the page (See Figure 1-9).

PA

PB

PC

4

PB

PC

PA

#n ; PAGE #n

address to be jumped ; if SF = 1

PB

NOTE: If SF = 0 then PC

PC + 1

Figure 1-9. Page-to-Page Addressing

1-8

S3C1840

PA

PC

4-bit

0

6-bit

The 10-bit register points one of 1024 bytes at addresses 0000H to 0F3FH.

After reset, it points to 0FXXH for execution in the first instruction cycle. it then becomes 0F00H in the

next instruction cycle.

ROM Address

000

Page 0

03F

100

Page 1

13F

200

Page 2

23F

300

Page 3

33F

400

Page 4

43F

500

Page 5

53F

600

RESET Address 0F00

Page 15

0F3F

0FFF

: Not built-in chip

Figure 1-10. S3C1840 Program Memory Map

1-9

S3C1840

DATA MEMORY (RAM)

The S3C1840's data memory consists of a 32-nibble RAM which is organized into two files of 16 nibbles each

(See Figure 1-11).

RAM addressing is implemented by a 7-bit register, HL.

It's upper 3-bit register (H) selects one of two files and its lower 4-bit register (L) selects one of 16 nibbles in the

selected file.

Instructions which manipulate the H and L registers are as follow:

Select a file :

MOV

NOT

H,#n

H

; H ¬ #n, where n must be 0,4

; Complement MSB of H register

Select a nibble in a selected file :

MOV

INCS

DECS

L,A

L,A,@HL

L,#N

L

; L ¬ A

; L ¬ M (H,L)

; L ¬ #n, where 0 £ n £ 0FH

; L ¬ L + 1

; L ¬ L - 1

RAM Address

00

File 0

0F

H

L

3-bit

4-bit

The 7-bit HL register pair points to one of the 32 nibbles.

H register selects one of two files; 0, 4

L register selects one of 16 nibbles; 0 to 0FH

After reset, the HL register pair becomes to unknown state.

40

4F

File 4

: Not built-in chip

7F

Figure 1-11. S3C1840 Data Memory Map

1-10

S3C1840

REGISTER DESCRIPTIONS

Stack Register (SR)

Three levels of subroutine nesting are supported by a three-level stack as shown in Figure 1-12.

Each subroutine call (CALL) pushes the next PA and PC address into the stack. The latest stack to be stored will

be overwritten and lost. Each return instruction (RET) pops the stack back into the PA and PC registers.

SR

PA

PC

: Push Operation (CALL)

: Pop Operation (RET)

Figure 1-12. Stack Operations

Page Address Register (PA), Page Buffer Register (PB)

The Page Address Register (PA) and Page Buffer Register (PB) are 4-bit registers. The PA always specifies the

current page.

A page select instruction (PAGE #n) loads the value "n" into the PB. When JP or CALL instruction is executed,

and if the Status Flag (SF) is set to 1, the contents of PB are loaded into PA. If SF is "0", however, the JP or

CALL is executed like NOP instruction and SF is set to "1". The contents of PB don't be loaded. Figure 1-13

illustrates this concept.

Common Bus

4

PB

PAGE #n

; PB

; PA

n

4

PA

JP xxx (CALL xxx)

PB

if SF = 1

Figure 1-13. PA, PB Operations

1-11

S3C1840

Arithmetic Logic Unit (ALU), Accumulator (A)

The SMCS-51 CPU contains an ALU and its own 4-bit register (accumulator) which is the source and destination

register for most I/O, arithmetic, logic, and data memory access operations.

Arithmetic functions and logical operations will set the status flag (SF) to "0" or "1".

Status Latch (SL)

The Status latch (SL) flag is an 1-bit flip-flop register. Only the "CPNE L,A" instruction can change the value of

SL.

If the result of a "CPNE L,A" instruction is true, the SL is set to "1"; If not true, to "0".

Status Flag : SF

The Status Flag (SF) is a 1-bit flip-flop register which enables programs to conditionally skip an instruction. All

instructions, including JP and CALL, are executed when SF is "1".

But if SF is "0", the program executes NOP instruction instead of JP or CALL and resets SF to "1". Then,

program execution proceeds. The following instructions set the SF to "0":

·

Arithmetic Instructions

ADDS

INCS

SUBS

DECS

A, #n

A,@HL

A,2HL

A

; if no carry

L

A,@HL

A

L

·

Compare Instructions

CPNE

CPNZ

CPNE

CPNZ

CPBT

@HL,A

@HL

L,#n

L,A

A,@HL

P0

; if M(H,L) = (A)

; if M(H,L) = 0

; if (L) = #

; if (L) = (A)

; if (A) > M(H,L)

; if (P0) = 0

@HL,b

; if M (H,L,b) ¹ 1

·

Data Transfer Instructions

MOV

@HL+,A

@HL_,A

; if no carry

; if borrow

Logical Instructions

NOTI

A

; if (A) ¹ 0 after operation

1-12

S3C1840

INPUT PORTS : P0, P1

The P0 and P1 input ports have internal pull-up 30-150 kW resistors, (See I/O circuit type A), each multiplexed to

a common bus (See Figure 1-14). If the P2.13 pin is programmed to low, then port 0 is selected as the input port.

Otherwise, if the P2.13 pin high, port 1 is selected.

P0.0-P0.3

4

Common Bus

MUX

P1.0-P1.3

P2.13 (Internal)

Figure 1-14. S3C1840 Input Port

OUTPUT PORTS : P2, P3

The P2 and P3 output ports can be configured as push-pull (P2.0/REM only) and open drain (P2.1-P2.6, P3.0-

P3.3) as follows:

·

Standard push-pull : A CMOS push-pull buffer with N-channel transistor to ground in conjunction with a P-

channel transistor to V_DD, compatible with CMOS and TTL. (See I/O Circuit Type B).

N-channel open drain : An N-channel transistor to ground, compatible with CMOS and TTL.

(see I/O Circuit Type C and D).

P2.0, P2.2-P2.5 and P3.0-P3.3 pins become low state in halt mode.

The L register specifies P2 output pins (P2.0/REM-P2.6, P2.9-P2.10, P2.12, and P2.13) individually as follows:

·

SETB P2.(L) : Set port 2 bits to correspond to L-register contents.

CLRB P2.(L) : Clear port 2 bits to correspond to L-register contents.

·

P3 output pins P3.0-P3.3 are parallel output pins.

For the S3C1840, only the 4-bit accumulator outputs its value to the P3 port by the output instruction "OUT P3,

@SL+ A" (the value of the Status Latch (SL) does not matter).

1-13

S3C1840

TRANSMISSION CARRIER FREQUENCY

One of four carrier frequencies can be selected and transmitted through the P2.0/REM pin by programming the

internal P2.9, P2.10 and P2.0 pins (See Table 1-5). Figure 1-16 shows a simplified diagram of the various

transmission circuits.

Table 1-5. Carrier Frequency Selection Table

P2.10

P2.9

Carrier Frequency of P2.0/REM Pin

fxx/12, 1/3 duty

0

1

0

1

0

1

fxx/8, 1/2 duty

fxx/12, 1/4 duty

No carrier

1-14

S3C1840

fXX/8, 1/2 Duty

fXX/12, 1/3 Duty

fXX/12, 1/4 Duty

VDD (No Carry)

4 x 1

MUX

P2.0/REM

Internal P2.9

Internal P2.10

Internal P2.0

System Clock

Frequency

Internal P2.0

P2.0/REM

(fXX/12, 1/3 duty)

P2.0/REM

(fXX/8, 1/2 duty)

P2.0/REM

(fXX/12, 1/4 duty)

P2.0/REM

(No carry)

Figure 1-15. Diagram of Transmission Circuits

1-15

S3C1840

HALT MODE

The HALT mode is used to reduce power consumption by stopping the clock and holding the states of all internal

operations fixed. This mode is very useful in battery-powered instruments. It also holds the controller in wait

status for external stimulus to start some event. The S3C1840 can be halted by programming the P2.12 pin high,

and by forcing P0 input pins (P0.0-P0.3) to high and P1 input pins (P1.0-P1.3) to high, concurrently (See Figure

1-16). When in HALT mode, the internal circuitry does not receive any clock signal, and all P2, P3 output pins

become low states. However, P2.1 and P2.6 pins retain their programmed values until the device is re-started as

follows:

·

Forcing any P0 and P1 input pins to low : system reset occurs and it continues to operate from the reset

address.

An oscillation stabilization time of 13 msec in fxx = 455 kHz crystal oscillation is needed for stability (See Figure

1-17).

VDD

Internal P2.12

4

P0.3-P0.0

P1.3-P1.0

Internal HALT

System reset

Figure 1-16. Block Diagram of HALT Logic

HALT

X'tal

HALT mode

Normal Mode

13 msec (Minimum) 120 msec (Typical)

Figure 1-17. Release Timing for HALT or RESET to Normal Mode in Crystal Oscillation

1-16

S3C1840

RESET

All reset operations are internal in the S3C1840. It has an internal power-on reset circuit consisting of a 7 pF

capacitor and a 1 MW resistor (See Figure 1-18). The controller also contains an auto-reset circuit that resets the

chip every 131,072 oscillator clock cycles (288 ms at a fxx = 455 kHz clock frequency). The auto-reset counter is

cleared by the rising edge of a internal P2.0 pin, by HALT, or by the power-on reset pulse (See Figure 1-19).

Therefore, no clocks are sent to the counter and the time-out is suspended in HALT mode. When a reset occurs

during program execution, a transient condition occurs. The PA register is immediately initialized to 0FH. The

PC, however, is not reset to 0H until one instruction cycle later. For example, if PC is 1AH when a reset pulse is

generated, the instruction at 0F1AH is executed, followed by the instruction at 0F00H.

After a reset, approximately 13 msec is needed before program execution proceeds (assuming fxx = 455 kHz

ceramic oscillation).

Upon initialization, registers are set as follows:

·

PC register to 0 in next instruction cycle

PA and PB registers to 0FH (15th page)

SF and SL registers to 1

HL registers to unknown state

All internal/external output pins (P3.0-P3.3, P2.0/REM-P2.6, P2.9, P2.10, P2.12 and P2.13) to low.

S3C1840

VDD

7 pF

1 MW

VSS

Figure 1-18. S3C1840's Power-on Reset Circuit

1-17

S3C1840

Internal HALT

Power-on Reset

CLR

fxx

System Reset

Auto-Reset Counter

CLK

Internal HALT

Internal P2.0

The Auto-Reset Counter is cleared every 131,072/fxx (288 msec if fxx is 455 KHz).

Figure 1-19. Auto Reset Block Diagram

OSC DIVIDE OPTION CIRCUIT

The OSC Divide Option Circuit provides a maximum 1MHz fxx system clock. f_OSCwhich is generated in

oscillation circuit is divided eight or non-divide in this circuit to produce fxx. This dividing ratio will be chosen by

mask option. (See Figure 1-20)

f_OSC: Oscillator clock

fxx : System clock (f_OSCor f_OSC/8)

f_CPU: CPU clock (f_CPU= fxx/6)

1 instruction cycle clock

XI

f_OSC

OSC

DIVIDE-8

XO

fXX

Mask Option

Figure 1-20. S3C1840 OSC Divide Option Circuit

1-18

S3C1840

PACKAGE DIMENSIONS

0-8

#24

#13

24-SOP-375

+ 0.10

0.15 - 0.05

#1

#12

15.74 MAX

15.34 ± 0.20

0.10 MAX

1.27

(0.69)

+ 0.10

0.38 - 0.05

NOTE: Dimensions are in millimeters.

Figure 1-21. 24-SOP-375

1-19

S3C1840

0-8

#20

#11

20-SOP-375

+ 0.10

0.203 - 0.05

#1

#10

13.14 MAX

12.74 ± 0.20

0.10 MAX

1.27

(0.66)

+ 0.10

0.40 - 0.05

NOTE: Dimensions are in millimeters.

Figure 1-22. 20-SOP-375

1-20

S3C1840

0-8

#20

#11

20-SOP-300

+ 0.10

0.20 - 0.05

#1

#10

14.10 MAX

13.70 ± 0.20

0.10 MAX

1.27

(1.14)

+ 0.10

0.40 - 0.05

NOTE: Dimensions are in millimeters.

Figure 1-23. 20-SOP-300

1-21

S3C1840

#20

#11

0-15

20-DIP-300A

#1

#10

26.80 MAX

26.40 ± 0.20

0.46 ± 0.10

1.52 ± 0.10

2.54

(1.77)

NOTE: Dimensions are in millimeters.

Figure 1-24. 20-DIP-300A

1-22

5. INSTRUCTION SET

S3C1840/C1850/C1860/P1860

INSTRUCTION SET

INSTRUCTION SET DESCRIPTION

Abbreviations and symbols table specifies internal architecture, instruction operand and operational symbols.

As mentioned before, JP and CALL instructions are executed normally only when SF is high. If SF is low, the

program executes NOP instruction instead of them and sets SF to high. And then, the program executes a next

instruction. In addition, JPL and CALL are long jump and long call instructions which consists of PAGE and

JP/CALL instructions.

Table 5-1. Abbreviations and Symbols

Symbol

Description

L register (4 bits)

Symbol

SF

P3

Description

L

Status Flag

P4-output

A

Accumulator (4 bits)

The contents of the L register

The contents of the accumulator

Status latch (1 bit)

(L)

(A)

SL

PB

PA

P2

PC

SR

H

P0

P0 input (4 bits)

D

Any binary number

Destination operand

Carry Flag

DST

C

Page buffer register (4 bits)

Page address register (4bits)

P2-output

SRC

REG

¬

Source operand

Register

Program counter

Transfer

Stack register

Addition or increment by 1

Equal or less than

The complement of the contents

+

H register

£

M

RAM addressed by H and L registers

(

)

(H)

The contents of the H register

@

Indirect register address prefix

Constant n (immediate 3or 4-bit data)

Is exchanged with

M (H,L) The contents of the RAM addressed by H,L

#n

b

Bit address of the RAM [(H,L)] addressed

by H,L

«

Not equal to

Subtract or decrement by 1

¹

-

5-1

INSTRUCTION SET

S3C1840/C1850/C1860/P1860

Table 5-2. Instruction Set Summary

Description

Mnemonic

Operand

MOV Instructions

MOV

MOVZ

XCH

L,A

A,L

Move A to register L

Move L register to A

@HL,A

A,@HL

L,@HL

@HL+,A

@HL-,A

L,#n

Move A to indirect data memory

Move indirect data memory to A

Move indirect data memory to register L

Move A to indirect data memory and increment register L

Move A to indirect data memory and decrement register L

Move immediate data to register L

H,#n

Move immediate data to register H

@HL+,#n

@HL,A

#n

Move immediate data to indirect data memory and increment register L

Move A to indirect data memory and clear A

Exchange A with indirect data memory

PAGE

Set PB register to n

Program Control Instructions

CPNE

CPNZ

CPNE

CPLE

CPNZ

CPBT

JP

@HL,A

@HL

L,A

L,#n

A,@HL

P0

@HL,b

dst

Compare A to indirect data memory and set SF if not equal

Set SF if indirect data memory

Compare A to register L, set SF and SL if not equal

Compare immediate data to register L and set SF if not equal

Set SF if A is less than or equal to indirect data memory

Test indirect data memory bit and set SF if indirect bit is one

Jump if SF flag is set

CALL

RET

Call subroutine if SF is set

Return from subroutine

I/O Instructions

SETB

CLRB

IN

P2.(L)

A,P0

Set bit

Clear bit

Input P0 to A

OUT

P3,@SL+A

Output A to P4-PLA output port

Logical Instructions

NOTI

NOT

CLR

A

H

A

Complement A and increment A

Complement MSB of H register

Clear

Arithmetic Instructions

ADDS

SUBS

INCS

DECS

Add indirect data memory to A

Add immediate data to A

Subtract A from indirect data memory

Increment indirect data memory and load the result in A

Increment register L

A,@HL

A,#n

A,@HL

L

Increment A

Decrement A

A

Decrement indirect data memory and load the result in A

Decrement register L

A,@HL

L

Bit Manipulation Instruction

SETB

CLRB

@HL.b

Set indirect data memory bit

Clear indirect data memory bit

5-2

S3C1840/C1850/C1860/P1860

INSTRUCTION SET

Upper Nibble (Hex)

Lower Nibble (Hex)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

CPNE CPLE CPNE XCH DECS INCS ADDS DECS

IN

NOT OUT

H

CLRB SETB CPNZ RET

0

1

2

3

4

P3,@SL+A

@HL,A A,@HL

L,A

@HL,A

L

A,@HL A,@HL A,P0

P2.(L) P2.(L)

P0

PAGE

#n

MOV MOV MOV MOV MOV MOV MOVZ MOV MOV

@HL+,A @HL,A @HL,A

H,#n

L,A

A,@HL L,@HL

A,L @HL-,A

SETB

@HL.b

CLRB

@HL.b

CPBT

@HL.b

SUBS NOTI INCS CPNZ

A,@HL

A

A,@HL @HL

MOV

L,#n

CPNE

L,#n

5

6

MOV

@HL+#N

INCS ADDS

DECS ADDS

CLR

A

7

8

A

A,#n

A

A,#n

JP

9

JP

A

B

C

D

E

F

JP

CALL

Figure5-1. KS51 Opcode Map

5-3

INSTRUCTION SET

MOV L,A

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

0 0 1 0

0 0 0 0

The contents of the accumulator are moved to register L.

The contents of the source operand are not affected.

Operation:

Flags:

(L) ¬ (A)

SF : Set to one

SL : Unaffected

Example:

CLR

A

; Clear the contents of A

; Move 0H to REG L

MOV

L,A

MOV A,L

Binary Code:

Description:

0 0 1 0

0 0 1 1

The contents of register L are moved to the accumulator.

The contents of the source operand are not affected.

Operation:

Flags:

(A) ¬ (L)

SF : Set to one

SL : Unaffected

Example:

MOV

L,#3H

A,L

; Move 3H to REG L

; Move 0H to A

MOV @HL,A

Binary Code:

Description:

0 0 1 0

0 1 1 1

The contents of the accumulator are moved to the data memory whose address is

specified by registers H and L.

The contents of the source operand are not affected.

Operation:

Flags:

M [(H,L)] ¬ (A)

SF : Set to one

SL : Unaffected

Example:

CLR

A

; Clear the contents of A

; Move 0H to REG H

MOV

H,#0H

L,#3H

@HL,A

; Move 3H to REG L

; Move 0H to RAM address 03H

5-4

S3C1840/C1850/C1860/P1860

MOV A,@HL

INSTRUCTION SET

Binary Code:

Description:

0 0 1 0

0 0 0 1

The contents of the data memory addressed by registers H and L are moved to

accumulator.

The contents of the source operand are not affected.

Operation:

Flags:

(A) ¬ M [(H,L)]

SF : Set to one

SL : Unaffected

Example:

Assume HL contains 04H

MOV

A,@HL

; Move contents of RAM addressed 04H to A

MOV L,@HL

Binary Code:

Description:

0 0 1 0

The contents of the data memory addressed by registers H and L are moved to register L.

The contents of the source operand are not affected.

Operation:

Flags:

(L) ¬ M [(H,L)]

SF : Set to one

SL : Unaffected

Example:

Assume Hl contains 04H

MOV

CPNE

JP

L,@HL

L,#5H

XX

; Move contents of RAM address 4H to REG L

; Compare 5H to REG L values

; jump to XX if REG L value is not 5H

; Jump to YY if REG L value is 5H

JP

YY

MOV @HL+,A

Binary Code:

Description:

0 0 1 0

0 1 0 1

The contents of the accumulator are moved to the data memory addressed by registers

H,L;

L register contents are incremented by one.

The contents of the source operand are not affected.

Operation:

Flags:

M [(H,L)] ¬ (A), L ¬ L + 1

SF : Set if carry occurs; cleared otherwise

SL : Unaffected

Example:

MOV

CLR

H,#0H

L,#0FH

A

MOV

@HL+A

; Move 0H to RAM address 0FH and increment REG L value

by one

JP

PRT

; jump to PRT, since there is a carry from increment

5-5

INSTRUCTION SET

MOV @HL-A

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

0 0 1 0

0 1 0 0

The contents of accumulator are moved to the data memory addressed by registers H,L;

L register contents are decremented by one.

The contents of the source operand are not affected.

Operation:

Flags:

M [(H,L)] ¬ (A), L ¬ L - 1

SF : Set if no borrow; cleared otherwise

SL : Unaffected

Example:

MOV

CLR

MOV

JP

H,#0H

L,#3H

A

@HL-,A

ABC

MOV L,#N

Binary Code:

Description:

0 1 0 0

d d d d

The 4-bit value specified by n (data) is loaded into register L.

The contents of the source operand are not affected.

Operation:

Flags:

(L) ¬ #n

SF : Set to one

SL : Unaffected

Example:

MOV

L,#8H

; 8H is moved to REG L

MOV H,#n

Binary Code:

Description:

0 0 1 0

1 d d d

The 3-bit value specified by n (data) is moved to register H.

The contents of the source operand are not affected.

Operation:

Flags:

(H) ¬ #n

SF : Set to one

SL : Unaffected

Example:

MOV

H,#4H

; 4H is moved into REG H

5-6

S3C1840/C1850/C1860/P1860

MOV @HL+,#n

INSTRUCTION SET

Binary Code:

Description:

0 1 1 0

d d d d

The 4-bit value specified by n (data) is moved to data memory addressed by registers H,L;

L register contents are incremented by one.

The contents of the source operand are not affected.

Operation:

Flags:

M [(H,L)] ¬ #n, L ¬ L + 1

SF : Set to one

SL : Unaffected

Example:

MOV

H,#0H

L,#7H

@HL+,#9H

; Move 9H to RAM address 07H and increment REG L value

by one, then REG L contains 8H

MOVZ @HL,A

Binary Code:

Description:

0 0 1 0

0 1 1 0

The contents of the accumulator are moved to the data memory addressed by registers

H,L;

accumulator contents are cleared to zero.

Operation:

Flags:

M [(H,L)] ¬ (A), (A) ¬ 0

SF : Set to one

SL : Unaffected

Example:

MOV

MOVZ

MOV

SETB

L,#3H

A,L

@HL,A

L,A

; Move 3H to indirect RAM and clear A to zero

; Move 0H to REG L

P2.(L)

; Set P2.0 to 1

XCH @HL,A

Binary Code:

Description:

0 0 0 0

0 0 1 1

This instruction exchanges the contents of the data memory addressed by registers H and

L with the accumulator contents.

Operation:

Flags:

M [(H,L)] « (A)

SF : Set to one

SL : Unaffected

Example:

MOV

CLR

H,#0H

L,#6H

A

; Clear A to zero

ADDS

XCH

A,#5H

@HL,A

; Add 5H to A

; Exchange 5H with contents of RAM address 06H

5-7

INSTRUCTION SET

PAGE #n

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

Operation:

Flags:

0 0 0 1

d d d d

The immediate 4-bit value specified by n (data) is loaded into the PB register.

(PB) ¬ #n

SF : Set to one

SL : Unaffected

Example:

PAGE

JP

#3H

AN

; Move 3H to page buffer

; Jump to label AN located at page 3 if SF is one;

otherwise, it is skipped

CPNE @HL,A

Binary Code:

Description:

0 0 0 0

The contents of accumulator are compared to the contents of indirect data memory; an

appropriate flag is set if their values are not equal.

The contents of both operands are unaffected by the comparison.

Operation:

Flags:

M [(H,L)] ¹ (A)

SF : Set if not equal, cleared otherwise

SL : Unaffected

Example:

CLR

ADDS

MOV

CPNE

JP

A

A,#3H

H,#0H

L,#6H

@HL,A

OA

; Acc value 3H is compared to contents of RAM address 06H

; Jump to OA if values of RAM address 06H are not 3h

; Jump to OB if values of RAM address 06H are 3H

JP

OB

5-8

S3C1840/C1850/C1860/P1860

CPNZ @HL

INSTRUCTION SET

Binary Code:

Description:

0 0 1 1

1 1 1 1

This instruction compares the magnitude of indirect data memory with zero, and the

appropriate flag is set if their values are not equal, i.e., if the contents of indirect data

memory are not zero.

The contents of operand are unaffected by the comparison.

Operation:

Flags:

M [(H,L)] ¹ 0

SF : Set if not zero, cleared otherwise

SL : Unaffected

Example:

Assume the contents of RAM address are 4H

CPNZ

JP

@HL

EQ

; Compare 4H with zero

; Jump to EQ because the result is not equal

JP

WAIT

CPNE L,A

Binary Code:

Description:

0 0 0 0

0 0 1 0

The contents of the accumulator are compared to the contents of register L; the

appropriate flags are set if their values are not equal.

The contents of both operands are unaffected by the comparison.

Operation:

Flags:

(L) ¹ (A)

SF : Set if not equal, cleared otherwise

SL : Set if not equal, cleared otherwise

Example:

Assume REG L contains 5H, A contains 4H

CPNE

JP

L,A

K1

K2

; Compare A to REG L values

; Jump to K1 because the result is not equal

JP

5-9

INSTRUCTION SET

CPNE L,#n

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

0 1 0 1

d d d d

This instruction compare the immediate 4 bit data n with the contents of register L, and

sets an appropriate flag if their values are not equal.

The contents of both operands are unaffected by the comparison.

Operation:

Flags:

(L) ¹ #n

SF : Set if not equal, cleared otherwise

SL : Unaffected

Example:

CLR

A

ADDS

MOV

CPNE

JP

A,#4H

L,A

L,#5H

K3

; Compare immediate data 5H to REG L values

; Jump to K3 because the result is not equal

CPNE A,@HL

Binary Code:

Description:

0 0 0 0

0 0 0 1

The contents of indirect data memory are compared to the contents of the accumulator.

Appropriate flags are set if the contents of the accumulator are less than or equal to the

contents of indirect data memory.

The contents of both operands are unaffected by the comparison.

Operation:

Flags:

(A) £ M [(H,L)]

SF : Set if less than or equal to, cleared otherwise

SL : Unaffected

Example:

Assume RAM address holds 8H

CPLE

JP

A,@HL

MAR

; Compare 8H to A values

; Jump to MAR if 0H £ A £ 8H

; Jump to BPR if 9H £ A £ 0FH

JP

BPR

5-10

S3C1840/C1850/C1860/P1860

CPNZ P0

INSTRUCTION SET

Binary Code:

Description:

0 0 0 0

1 1 1 0

The instruction compares the contents of Port 0 with zero. Appropriate flags are set if their

values are not equal, i.e., if the contents of Port 0 are not zero.

The contents of the operand are unaffected by the comparison.

Operation:

Flags:

(P0) ¹ 0

SF : Set if not zero, cleared otherwise

SL : Unaffected

Example:

MOV

CLRB

CPNZ

JP

L,#0DH

P2.(L)

P0

; Clear P2.13, i.e., select P0 input

; Compare P0 to zero

KEYIN

NOKEY

; Jump to KEYIN if P0 ¹ 0

; Jump to NOKEY if P0 = 0

JP

CPBT @HL,b

Binary Code:

Description:

0 0 1 1

1 0 d d

CPBT tests indirect data memory bit and sets appropriate flags if the bit value is one.

The contents of operand are unaffected by the test.

Operation:

Flags:

M [(H,L)] = 1

SF : Set if one, cleared otherwise

SL : Unaffected

Example:

MOV

CPBT

JP

H,#0H

L,#0BH

@HL,3

Q1

; Test RAM address 0BH bit 3

; Jump to Q1 if RAM address bit 3 is 1

; Jump to Q2 if RAM address bit 3 is 0

JP

Q2

5-11

INSTRUCTION SET

JP dst

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

1 0 d d

d d d d

The JP transfers program control to the destination address if the SF is one.

The conditional jump replaces the contents of the program counter with the address

indicated and transfers control to that location.

Had the SF flag not been set, control would have proceeded with the next instruction.

Operation:

Flags:

If SF = 1 ; PC ¬ (W), PA ¬ PB

SF : Set to one

SL : Unaffected

Example:

JP

SUTIN1

; This instruction will cause program execution to branch to the

instruction at label SUTIN; SUTIN1 must be within the current

page

CALL dst

Binary Code:

Description:

1 1 d d

d d d d

If the SF flag is set to 1, this instruction calls a subroutine located at the indicated address,

and then pushes the current contents of the program counter to the top of the stack. The

program counter value used is the address of the first instruction following the CALL ins.

The specified destination address is then loaded into the program counter and points to the

first instruction of a procedure. At the end of the procedure, the return (RET) instruction

can be used to return to the original program flow.

Operation:

Flags:

If SF = 1 ; SRi ¬ PC + 1, PSRi ¬ PA

PC ¬ I (W), PA ¬ PB

SF : Set to one

SL : Unaffected

Example:

CALL

ACD1

; CALL subroutine located at the label ACD1 where ACD1

must be within the current page

RET

Binary Code:

Description:

0 0 0 0

1 1 1 1

This instruction is normally used to return to the previously executing procedure at the end

of a procedure entered by a CALL instruction. The contents of the location addressed by

the stack pointer are popped into the program counter. The next statement executed is that

addressed by the new contents of the program counter.

Operation:

Flags:

PC ¬ Sri, PB ¬ PSRi

PA ¬ PB

SF : Set to one

SL : Unaffected

Example:

RET

; Return from subroutine

5-12

S3C1840/C1850/C1860/P1860

SETB P2.(L)

INSTRUCTION SET

Binary Code:

Description:

0 0 0 0

1 1 0 1

This instruction sets the Port 2 bit addressed by register L without affecting any other bits in

the destination.

Operation:

Flags:

P2.(L) ¬ 1

SF : Set to one

SL : Unaffected

Example:

MOV

L,#0H

P2.(L)

SETB

; Set P2.0 to 1

CLRB P2.(L)

Binary Code:

Description:

0 0 0 0

1 1 0 0

This instruction clears the Port 2 bit addressed by register L without affecting any other bits

in the destination.

Operation:

Flags:

P2.(L) ¬ 0

SF : Set to one

SL : Unaffected

Example:

MOV

L,#0H

P2.(L)

CLRB

; Clear P2.0 to 0

IN A,P0

Binary Code:

Description:

Operation:

Flags:

0 0 0 0

1 0 0 0

Data present on Port n is transferred (read) to the accumulator.

(A) ¬ (Pn) (n = 0,1)

SF : Set to one

SL : Unaffected

Example:

IN

A,P0

L,A

; Input port 0 data to Acc

MOV

CPNE

JP

L,#3H

OX

; Jump to OX if port 0 data ¹ 3H

JP

QP

; Jump to QP if port 0 data = 3H

5-13

INSTRUCTION SET

OUT P3,@SL+A

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

Operation:

Flags:

0 0 0 0

1 0 1 0

The contents of the accumulator and SL are transferred to the P3 Output register.

(P3 Output register) ¬ (A) + (SL)

SF : Set to one

SL : Unaffected

Example:

CLR

OUT

A

P3,@SL+A

; Zero output on port 3

NOTI

A

Binary Code:

Description:

0 0 1 1

1 1 0 1

The contents of the accumulator are complemented; all 1 bits are changed to 0, and vice-

versa, and then incremented by one.

Operation:

Flags:

(A) ¬ (A), (A) ¬ (A) +1

SF : Set if the result is zero, cleared otherwise

SL : Unaffected

Example:

CLR

A

ADDS

NOTI

A,#7H

A

; Complement 7H (0111B) and increment the result by one;

the instruction NOTI A then leaves 9H (1001B) in A

5-14

S3C1840/C1850/C1860/P1860

INSTRUCTION SET

NOT

H

Binary Code:

Description:

Operation:

0 0 0 0

1 0 0 1

The MSB of register H is complemented,

(H) ¬ (H)

Flags:

SF : Set to one

SL : Unaffected

Example:

MOV

NOT

H,#4H

H

; Complement 4H (100B), then it leaves 00H (000B) in REG H

CLR

A

Binary Code:

Description:

Operation:

Flags:

0 1 1 1

1 1 1 1

The contents of the accumulator are cleared to zero (all bits set on zero).

(A) ¬ 0

SF : Set to one

SL : Unaffected

Example:

CLR

A

; A value are cleared to zero

ADDS A,@HL

Binary Code:

Description:

0 0 0 0

0 1 1 0

ADDS adds the contents of indirect data memory to accumulator, leaving the result in the

accumulator.

The contents of the source operand are unaffected.

Operation:

Flags:

(A) ¬ M [(H,L)] + (A)

SF : Set if a carry occurred, cleared otherwise

SL : Unaffected

Example:

Assume RAM address holds 5H

CLR

A

; Clear A to zero

ADDS

A,@HL

; This instruction will leaves 5H in A

5-15

INSTRUCTION SET

ADDS A,#n

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

0 1 1 1

d d d d

The specified 4-bit data n is added to the accumulator and the sum is stored in the

accumulator.

Operation:

Flags:

(A) ¬ (A) + #n

SF : Set if a carry occurred, cleared otherwise

SL : Unaffected

Example:

CLR

A

; Clear A to zero

ADDS

A,#4H

; Add 4H to A, it leaves 4H in A

SUBS A,@HL

Binary Code:

Description:

0 0 1 1

1 1 0 0

SUBS subtracts the contents of accumulator from the contents of indirect data memory,

leaving the result in the accumulator.

The contents of source operand are unaffected.

Operation:

Flags:

(A) ¬ M [(H,L)] - (A)

SF : Set if no borrow occurred, cleared otherwise

SL : Unaffected

Example:

Assume RAM address holds 0CH

MOV

SUBS

L,#8H

A,L

A,@HL

; Subtract A from 0CH; it will leave 4H in A

INCS A,@HL

Binary Code:

Description:

0 0 1 1

1 1 1 0

The contents of indirect data memory are incremented by one and the result is loaded into

the accumulator.

The contents of indirect data memory are unaffected.

Operation:

Flags:

(A) ¬ M [(H,L)] + 1

SF : Set if a carry occurred, cleared otherwise

SL : Unaffected

Example:

Assume RAM address holds 6H

CLR

A

; Clear A to zero

INCS

A,@HL

; Increment 6H by one and leave 7H in A

5-16

S3C1840/C1850/C1860/P1860

INSTRUCTION SET

INCS

L

Binary Code:

Description:

Operation:

Flags:

0 0 0 0

0 1 0 1

The contents of the L register are incremented by one.

(L) ¬ (L) + 1

SF : Set if a carry occurred, cleared otherwise

SL : Unaffected

Example:

MOV

INCS

L,#5H

L

; Increment REG L value 5H by one

INCS

A

Binary Code:

Description:

Operation:

Flags:

0 1 1 1

0 0 0 0

The contents of the accumulator are incremented by one.

(A) ¬ (A) + 1

SF : Set if no borrow occurred, cleared otherwise

SL : Unaffected

Example:

MOV

INCS

L,#5H

A,L

A

; Increment 5H by one

DECS

A

Binary Code:

Description:

Operation:

Flags:

0 1 1 1

The contents of the accumulator are decremented by one.

(A) ¬ (A) - 1

SF : Set if a carry occurred, cleared otherwise

SL : Unaffected

Example:

MOV

DECS

L,#0BH

A,L

A

; The instruction leaves the value 0AH in A

5-17

INSTRUCTION SET

DECS A,@HL

S3C1840/C1850/C1860/P1860

Binary Code:

Description:

0 0 0 0

0 1 1 1

The contents of the data memory addressed by the H and L registers are decremented by

one and the result is loaded in the accumulator.

But the contents of data memory are not affected.

Operation:

Flags:

(A) ¬ M [(H,L)] - 1

SF : Set if a carry occurred, cleared otherwise

SL : Unaffected

Example:

Assume RAM address holds 5h

MOV

DECS

L,#0AH

A,L

A,@HL

; Decrement the value 5H by one, and the result value 4H is

loaded in A

DECS

L

Binary Code:

Description:

Operation:

Flags:

0 0 0 0

0 1 0 0

The contents of the L register are decremented by one.

(L) ¬ (L) - 1

SF : Set if no borrow occurred, cleared otherwise

SL : Unaffected

Example:

MOV

L,#3H

L

DECS

; This instruction leaves the value 2H in REG L

SETB @HL,b

Binary Code:

Description:

0 0 1 1

0 0 d d

This instruction sets indirect data memory bit addressed by registers H and L without

affecting any other bits in the destination.

Operation:

Flags:

b ¬ 1 (b = 0,1,2,3)

SF : Set to one

SL : Unaffected

Example:

MOV

SETB

H,#0H

L,#5H

@HL.2

; Set RAM address 05H bit 2 to 1

5-18

S3C1840/C1850/C1860/P1860

DECS A,@HL

INSTRUCTION SET

Binary Code:

Description:

0 0 1 1

0 1 d d

This instruction clears the indirect data memory bit addressed by registers H and L without

affecting any other bits in the destination.

Operation:

Flags:

b ¬ 1 (b = 0,1,2,3)

SF : Set to one

SL : Unaffected

Example:

MOV

CLRB

H,#0H

L,#5H

@HL.3

; Clear RAM address 05H bit 3 to zero

5-19

6. DEVELOPMENT TOOLS

S3C1840/C1850/C1860/P1860

DEVELOPMENT TOOLS

SMDS

The Samsung Microcontroller Development System, SMDS is a complete PC-based development environment

for S3C1840/C1850/C1860 microcontroller. The SMDS is powerful, reliable, and portable. The SMDS tool set

includes a versatile debugging utility, trace with built-in logic analyzer, and performance measurement

applications.

Its window-oriented program development structure makes SMDS easy to use. SMDS has three components:

— IBM PC- compatible SMDS software, all device-specific development files, and the SAMA assembler.

— Development system kit including main board, personality board, SMDS manual, and target board adapter,

if required.

— Device-specific target board.

SMDS PRODUCT VERSIONS

As of the date of this publication, two versions of the SMDS are being supported:

— SMDS Version 4.8 (S/W) and SMDS Version 3.6 (H/W); last release: January, 1994.

— SMDS2 Version 5.3 (S/W) and SMDS2 Version 1.3 (H/W); last release: November, 1995.

The new SMDS2 Version 1.3 is intended to replace the older Version 3.6 SMDS. The SMDS2 contains many

enhancements to both hardware and software. These development systems are also supported by the personality

boards of Samsung's microcontroller series: S3C1, S3C7, and S3C8.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format.

Compiled program code includes the object code that is used for ROM data and required SMDS program control

data. To compile programs, SAMA requires a source file and an auxiliary definition (DEF) file with device-specific

information.

TARGET BOARDS AND PIGGYBACKS

Target boards are available for S3C1840/C1850/C1860 microcontroller. All required target system cables and

adapters are included with the device-specific target board.

Piggyback chips are provided to customers in limited quantities for S3C1840/C1850 microcontroller. The

S3C1840/C1850 piggyback chips, PB51840-20 and PB51840/51850-24 are now available.

6-1

DEVELOPMENT TOOLS

S3C1840/C1850/C1860/P1860

PB51840-20 is 20 DIP piggyback chip for 20 DIP, 20 SOP package device of S3C1840 microcontroller.

PB51840/51850-24 is 24DIP piggyback chip for 24 SOP package device of S3C1840/C1850 microcontroller.

SMDS2

RS-232C

IBM-PC

or

Internal Bus

Compatiable

5-Volt

Power

Supply

Personality

Board

Main Board

Front

Panel

Board

POD

Target

Application

System

Target Board

Target Cable

Figure 6-1. SMDS Product Configuration (SMDS2)

6-2

S3C1840/C1850/C1860/P1860

DEVELOPMENT TOOLS

TB51840/51850A TARGET BOARD

The TB51840/51850A target board is used for the S3C1840/C1850/C1860 microcontroller. It is supported by the

SMDS2 development system only.

TB51840/51850A/51860

To User_Vcc

Off

On

U5

U4

Reset 1

U1

25

U5

1

64

U6

64 SDIP

KS51899

EVA CHIP

CN1

32

33

P2.1

P2.3

+

P2.2

+

P2.0

J101

1

+

RA1

P2.6

+

P2.5

+

P2.4

+

J102

RA2

P2

OFF

ON

RA3

SM1243A

Figure 6-2. TB51840/51850A Target Board Configuration

6-3

DEVELOPMENT TOOLS

S3C1840/C1850/C1860/P1860

Table 6-1. Power Selection Settings for TB51840/51950A

Operating Mode

'To User_Vcc' Settings

Comments

The SMDS2 supplies V_CCto

the target board (evaluation

chip) and the target system.

To User_Vcc

OFF

ON

Target

System

TB51840/

51850A

VCC

VSS

VCC

SMDS2

The SMDS2 supplies V_CConly

To User_Vcc

to the target board (evaluation

chip). The target system must

have its own power supply.

External

VCC

OFF

ON

Target

System

TB51840/

51850A

VSS

VCC

SMDS2

LED 2.0-LED 2.6:

These LEDs are used to display value of the P2.0-P2.6. It will be turn on, if the value is Low.

P2 Option Switch:

Switch ON: You can see the port value using the LED display.

Switch OFF: You can't see the port value. That is, the LED won't be turn ON by the port value.

6-4

S3C1840/C1850/C1860/P1860

DEVELOPMENT TOOLS

J101

1

2

3

4

5

6

7

8

9

24

23

22

21

20

19

18

17

16

15

14

VSS

XIN

VSS

XIN

XOUT

P2.6

P0.0

P0.1

P0.2

P0.3

XOUT

P2.6

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P1.0

P1.1

10

11

P1.2

P1.3

P1.2

P1.3

12

13

Figure 6-3. 24 DIP Socket for TB51840/51850A (S3C1840/C1850, 24 SOP)

Target Board

J101

Target System

1

24

1

24

Target Cable for 24 DIP Package

Part Name: AS24D

Order Code: SM6303

12

13

12

13

Figure 6-4. TB51840/51850A Cable for 24 DIP Package

6-5

DEVELOPMENT TOOLS

S3C1840/C1850/C1860/P1860

J102

VSS

XIN

1

2

11

12

13

14

15

16

17

18

19

20

VDD

P2.0/REM

TEST

P2.1

XOUT

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P3.3

3

4

5

P2.2

6

P2.3

7

P2.4

8

P3.0

9

P3.1

10

P3.2

Figure 6-5. 20 DIP Socket for TB51840A (S3C1840/C1860, 20 DIP, 20 SOP)

Target Board

J101

Target System

1

20

1

20

Target Cable for 20 DIP Package

Part Name: AS20D

Order Code: SM6304

10

11

10

11

Figure 6-6. TB51840A Cable for 20 DIP Package

6-6

7. REMOTE CONTROL Tx. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

DESCRIPTION OF THE S3C1840/C1850/C1860 MCUS

The S3C1840/C1850/C1860 4-bit single-chip CMOS microcontroller is designed using the reliable SMCS-51 CPU

core with on-chip ROM and RAM. An auto-reset circuit generates a RESET pulse in regular intervals, and can be

used to initiate a Halt mode release. The S3C1840/C1850/C1860 microcontroller is intended for use in small

system control applications that require a low-power and cost-sensitive design solution. In addition, the

S3C1840/C1850/C1860 has been optimized for remote control transmitters.

FEATURES

Table 7-1. S3C1840/C1850/C1860 Features

Feature

S3C1840

1024 bytes

S3C1850

1024 bytes

S3C1860

1024 bytes

ROM

RAM

32 x 4 bits

Carrier frequency

Operating voltage

fxx/12, fxx/8, no carrier

250 kHz £ f_OSC£ 3.9 MHz

250 kHz £ f_OSC£ 3.9MHz

250 kHz £ f_OSC£ 3.9 MHz

1.8 V to 3.6 V,

3.9 MHz < f_OSC< 6 MHz

2.2 V to 3.6 V

Low-Level Output

Current P2.0 (IOL1)

Typ. 3.0mA (at VO=0.4V) Typ. 210mA (at VO=0.4V) Typ. 280mA (at VO=0.4V)

Typ. 260mA (at VO=0.5V) Typ. 320mA (at VO=0.5V)

Package

Piggyback

OTP

24 SOP, 20 SOP/DIP

24 SOP

20 SOP/DIP

O

x

O

x

O

(S3P1860:divide-8 only)

Tr. for I.R.LED drive

x

Built-in

Power on reset circuit Built-in

x

Oscillation Start and

reset circuit (OSR)

x

Built-in

Table 7-2. S3C1840/C1850/C1860 Package Types ^(note)

24 pins

Item

20 pins

Package

24 SOP-375

20 DIP-300A

20 SOP-300

20 SOP-375

NOTE : The S3C1850 has 24 pin package type only and S3C1860/S3P1860 has 20 pin package type only.

7-1

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

Table 7-3. S3C1840/C1850/C1860 Functions

Description

Automatic reset by Halt mode When Halt mode is released, the chip is reset after an oscillator stabilization

release

interval of 9 ms. (fxx = 455 kHz)

Output pin state retention

function

When the system enters Halt Mode,

P3.0-P3.3, P2.0, and P2.2-P2.5 go low level in 24 pins.

P3.0-P3.3, P2.0, and P2.2-P2.4 go low level in 20 pins.

But the P2.0 is floating state in S3C1850/C1860. (NOTE)

Auto-reset

With oscillation on and with no change to the IP2.0 output pin, a reset is

activated every 288 ms at fxx = 455 kHz.

Osc. Stabilization time

Other functions

CPU instructions are executed after oscillation stabilization time has elapsed.

Carrier frequency generator. Halt wake-up function.

NOTE : The S3C1850 has 24 pin package type only and S3C1860 has 20 pin package type only.

RESET

The S3C1840/C1850 has three kinds of reset operations:

— POR (Power-On Reset)

— Auto-reset

— Automatic reset by Halt release

The S3C1860 has three kinds of reset operations;

— OSR (Oscillation Start and Reset)

— Auto-reset

— Automatic reset by Halt release

Power-On Reset Circuits

VDD

2.2 V

7 pF

1 M

RESET

0.3 VDD

W

Reset Time

Figure 7-1. Power-On Reset Circuits

7-2

S3C1840/C1850/C1860/P1860

Auto-Reset

REMOTE CONTROL TX. APPLICATION NOTE

The auto-reset function resets the CPU every 131,072 oscillator cycles (288 ms at fxx = 455 kHz). The auto-reset

counter is cleared when a rising edge is detected at IP2.0, or by a HALT or RESET pulse.

Normal Mode:

After a reset, the program restart

from 0F00H after one instruction in

0FxxH is executed.('F' is page

number and 'xx' is the next

instruction of HALT instruction)

IP2.12 = 1, Non-Active Input Pin

Abnormal

status

Halt Release Signal

Halt

Normal Mode

V_DD

XO

f_XX= 455 kHz

Osc. Stabilization Time

(9 ms)

Osc. Circuit

Wait Time

(3-4 ms)

Auto-reset

counter

Osc. Stabilization counter starts

Overflow

Chip restarts and auto-reset

counter is incremented.

IP2.0 IP2.0

Chip holds it's internal status.

Upon entering Halt mode, the auto-reset counter is

cleared to zero.

Systerm reset occurs when the auto-reset counter

overflows. The program restarts from 0F00hH

Chip restarts and the auto-reset counter is incremented

(Reset by internal POR or OSR)

Figure 7-2. Auto-Reset Counter Function

NOTE : The OSR(Oscillation Start and reset) is not implemented for the S3C1840/C1850.

7-3

REMOTE CONTROL TX. APPLICATION NOTE

Automatic Reset by Halt Mode Release

S3C1840/C1850/C1860/P1860

This function resets the CPU by releasing Halt mode. The CPU is reset to its initial operating status and program

execution starts from the reset address.

Halt Mode and Automatic Reset by Halt Release

Halt mode is used to reduce power consumption by stopping the oscillation and holding the internal state. Halt

mode can be entered by forcing IP2.12 to high level (remaining input pins are non-active).

Before entering Halt mode, programmer should pre-set all key strobe output pins to active state even though Halt

mode causes some pins to remain active.

For the 24 pins, P3.0-P3.3, P2.0, P2.2- P2.4, and P2.5 are sent low and for 20 pins, P3.0-P3.3, P2.0, P2.2-P2.4

are sent low, but the P2.0 is floating state in S3C1850/C1860.. Forcing any key input port to active state causes

the clock oscillation logic to start system initialization.

At this time, the system is reset after the oscillation stabilization time elapses. A system reset causes program

execution to start from address 0F00H.

Normal Mode:

After a reset, the program

restarts from 0F00H after one

instruction in 0FxxH is

executed.('F' is page number

and 'xx' is the instruction

immediately following the

HALT instruction.)

Halt Release Signal

IP2.12 = 1, Non-Active Input Pin

Normal Mode

Halt

XO

Osc. Circuit

Wait Time

(3-4 ms)

Osc. Stabilization Timer

(9 ms)

fxx = 455 kHz)

Osc. Stabilization Timer Start

Figure 7-3. Reset Timing Diagram

7-4

S3C1840/C1850/C1860/P1860

HALT mode programming

REMOTE CONTROL TX. APPLICATION NOTE

The S3C1840/C1850/C1860 can enter Halt mode by setting the IP2.12 pin to high level and forcing P0 and P1

input to a normal state. If IP 2.12 is high and any input is active, the chip cannot enter Halt mode. Therefore, the

next instruction is executed, which must be a clear command for IP2.12.

MOV L,#5

KEYOLO

DECS L

CPNE L,#1

CLRB P2.(L)

; P2.5,4,3,2, ¬ Low

JP

KEYOLO

CLR

A

; ACC. ¬ #0h

OUT P3,@SL+A

MOV L,#0DH

CLRB P2.(L)

; P3.0,1,2,3, ¬ Low

; Select the P0 input

; P0 input check

IN

INCS

JP

A,P0

A

.+2

JP

KEYCHK

; If any key pressed in P0, jump to KEYCHK routine

; Select the P1 input

SETB P2.(L)

timea IN

A,P0

A

+ 2

INCS

JP

; P1 input check

timeb JP

KEYCHK

; If any key pressed in P1, jump to KEYCHK routine

; No key pressed

; Halt mode

MOV L,#0CH

SETB P2.(L)

; When no key is pressed, the chip enters Halt mode. Pressing any key while in Halt mode causes the chip to be

initialized and restarted from the reset address.

; If any key is pressed between time A and time B, the following instruction is executed.

MOV L,#0CH

CLRB P2,(L)

; These two instructions remove the condition of re-entering

; Halt mode.

7-5

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

RESET and HALT Logic Diagram

IP2.12

4

P0

P1

Internal HALT

Internal POR or

OSR^(note)

System RESET

Auto-Reset

Counter

fOSC

CLK

Internal HALT

IP 2.0

NOTE:

Internal POR is implemented for S3C1840/C1850 and OSR is implemented for S3C1860.

Figure 7-4. RESET and HALT Logic Diagram

7-6

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

OUTPUT PIN DESCRIPTION

Indicator LED Drive Output

To drive the indicator LED, the programmer should use P2.1 of the S3C1840/C1850/C1860 (which have higher

current drive capability than other pins) in order to retain the pre-programmed status during Halt mode. Be careful

to turn on the LED when a reset signal is generated. Because a reset signal sends all of the internal and external

output pins to low level, the programmer must set LED output P2.1 to high state using a reset subroutine.

P2.1

Figure 7-5. LED Drive Output Circuit

Strobe Output Option

To active the optional strobe output function for TV and VCR remocon applications, the programmer must use

the option selection strobe output pin (P2.6).

This pin has lower current drive capability than other pins and retain the pre-programmed status while in Halt

mode. Be careful to turn on the option strobe output pin when a reset signal is generated. Because the reset

sends all internal and external output pins to low level, the option strobe output pin should always be non-active

state (H-Z). The pin should be active only when you are checking option status to reduce current consumption.

Table 7-4. Strobe Output Option

Pin usage

P3.0-P3.3, P2.2-P2.5

P2.1

Key Output

LED Drive

Option Selection

00

0

X

00

0

X

0

P2.6

0

00

NOTE: X = not allowed

0 = good

00 = better

7-7

REMOTE CONTROL TX. APPLICATION NOTE

Output Pin Circuit Type

S3C1840/C1850/C1860/P1860

Low output retention function in Halt mode is

used for key strobe output only

P3.0-P3.3, P2.2-P2.5

Halt

0

Data

Port

0

1

X

DATA

HALT

0

H-Z

0

P2.6: For option pin or key-out

P2.1: For LED drive pin or key-out

P2.1, P2.6

Halt

X

Data

Port

0

1

X

H-Z

DATA

Figure 7-6. Output Pin Circuits

7-8

S3C1840/C1850/C1860/P1860

Soft Ware Delay Routine

REMOTE CONTROL TX. APPLICATION NOTE

To obtain a constant time value, the S3C1840/C1850/C1860 use a software delay routine (there is not an internal

timer interrupt). One instruction cycle is six oscillator clocks. Using a ceramic resonator with a constant

frequency, you can calculate the time delay as follows:

t = 6/fxx Number of Instructions

Where t: Elapsed time and fxx: System clock.

Programming Tip

To program a 1-ms delay: 1 ms = 6/455 kHz x n, where fxx = 455 kHz

Therefore, n = 75.8 = 76 instructions

DLY1MS

CLR

A

ADDS

MOV

DECS

JP

A,#0BH

H,#0

A

; Two instructions

DLY

; Dummy instruction

DLY

; DLY loop: 6 instructions

;2 + (ACC + 1) x instructions in loop = 2 + (11 + 1) x 6 = 74

CLR

A

; Two instructions.

; Total number of instructions for DLY1MS is 76.

NOTE

In order to lengthen the delay time, you can use an arithmetic instruction combination of L register and

Accumulator. The L register causes the address lower pointer to access RAM space and the output port pointer to

control the P2 (individual/serial output) port status.

— RAM manipulation instruction: RAM address pointer.

MOV

ADDS

A,@HL

CPNE @HL,A

SETB @HL.b

— P2 output control instruction: P2 pointer.

SETB P2.(L) CLRB P2.(L)

7-9

REMOTE CONTROL TX. APPLICATION NOTE

PROGRAMMING GUIDELINES

S3C1840/C1850/C1860/P1860

When programming S3C1840/C1850/C1860 microcontroller, please follow the guidelines presented in this

subsection.

PCB Artwork

For remote control applications, turning the I.R.LED on and off may cause variations in transmission current

ranging from a few hundred mA to a few hundred mA. This current variation generates overshoot and undershoot

noise on the power line, causing a system malfunction.

VDD

Remocon

Signal

To reduce noise and to stabilize the chip's operation, we recommend that the application designer reduce

overshooting of the I.R.LED drive current and design PCB for the remote controller as follows: (The noise level

should be limited to around 0.5 V_P-P, where V_P-Pis the peak-to-peak voltage)

— Oscillation circuit should be located as near as possible to the chip.

— PCB pattern for V_DD/V_SSshould be as wide and short as possible.

— I.R.LED drive TR and I.R.LED should be located as far as possible from the chip.

— Power supply battery and power capacitor should be located as near as possible to the chip.

— The ground pattern of the TEST pin (Ground of I.R.LED drive TR) and V_SSpin should be separated and

connected directly with the battery terminal.

— The ceramic capacitor (0.1uF or 0.01uF) and power capacitor(over 47uF) is recommended to use noise filter.

7-10

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

GND

VDD

C2

C1=47uF

C4=0.1uF

V

X

SS

IN

OUT

VDD

P2.0

Test

C1=47uF

C3

C2

C3

SS

IN

DD

V

X

V

P2.0

OUT Test

GND

VDD

Recommended Artwork for S3C1850/C1860

Unacceptable Artwork for S3C1850/C1860

7-11

REMOTE CONTROL TX. APPLICATION NOTE

SMDS

S3C1840/C1850/C1860/P1860

When a breakpoint or single-step instruction is executed in area of PAGE and JP or CALL instruction, the JP or

CALL may jump to the wrong address, We therefore recommend using a JPL or CALL instruction (instead of

PAGE and JP or PAGE and CALL) to avoid this problems. Note that JP and CALL are 2-byte instructions.

Programming Guidelines for Reset Subroutine

1. We recommend that you initialize a H register to either "0" or "4"

2. Do not write the instructions CALLL (PAGE + CALL) or JPL (PAGE + JP) to the reset address 0F00H. In

other words, do not use a PAGE instruction at 0F00H.

3. Turn off the LED output pin.

4. To reduce current consumption, do not set the option output pin to active state.

5. Pre-set the remocon carrier frequency (to fxx/12, fxx/8, and so on) before remocon signal transmission.

6. Because the program is initialized by an auto-reset or Halt mode release, even in normal operating state, do

not pre-set all RAM data. If necessary, pre-set only the RAM area you need.

7. Be careful to control output pin status because some pins are automatically changed to active state.

8. To enter Halt mode, the internal port, IP2.12, should be set to high level and all of the input pins should be

set to normal state.

9. To release Halt mode, an active level signal is supplied to input pins. If pulse width is less than 9 ms at

fxx = 455 kHz, nothing happens and program re-enters Halt mode. That is, the external circuit should

maintain the input pulse over a 9-ms interval in order to release Halt mode. After Halt mode is released, the

hardware is reset. The hardware reset sends all internal and external output pins low (except P2.0 in

S3C1850/C1860) and clears the stack to zero. However, H,L and A registers retain their previous status.

10. If a rising edge is not generated at IP2.0, reset signal occurs every 288 ms at fxx = 455 kHz. To prevent an

auto-reset, IP2.0 should be forced low and then high at regular intervals (within 288 ms at fxx = 455 kHz).

7-12

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840 Application Circuit Example

VDD

+3 V

C4

C1

R2

D2

+

D1

R1

-

VDD P2.0/ TEST P2.1 P2.2 P2.3 P2.4 P2.5 P3.0 P3.1 P3.2 P3.3

REM

SAMSUNG

S3C1840-xx

VSS

XI

XO P2.6 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3

K0

K1

K2

K3

K4

K5

K6

K7

C1

K8

K9

K16

K17

K18

K19

K20

K21

K22

K23

C3

K24

K25

K26

K27

K28

K29

K30

K31

C4

K32

K33

K34

K35

K36

K37

K38

K39

C5

K40

K41

K42

K43

K44

K45

K46

K47

C6

K48

K49

K50

K51

K52

K53

K54

K55

C7

K56

K57

K58

K59

K60

K61

K62

K63

C8

C2

C3

K10

K11

K12

K13

K14

K15

C2

R1: 1-0.45

W

R2: 100

C1: 4.7

W

mF/6.3 V

C2, C3: 100 pF

C4: 0.1

m

F

D1: I.R.LED

D2: INDICATOR LED

Resonator: 455 kHz

K

C

OR

Figure 7-7. S3C1840 Applicatrion Circuit Example

7-13

REMOTE CONTROL TX. APPLICATION NOTE

S3C1850 Application Circuit Example

S3C1840/C1850/C1860/P1860

VDD

+3 V

C4

C1

R

+

D1

-

D2

VDD P2.0/ TEST P2.1 P2.2 P2.3 P2.4 P2.5 P3.0 P3.1 P3.2 P3.3

REM

SAMSUNG

S3C1850-xx

VSS

XI

XO P2.6 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3

K0

K1

K2

K3

K4

K5

K6

K7

C1

K8

K9

K16

K17

K18

K19

K20

K21

K22

K23

C3

K24

K25

K26

K27

K28

K29

K30

K31

C4

K32

K33

K34

K35

K36

K37

K38

K39

C5

K40

K41

K42

K43

K44

K45

K46

K47

C6

K48

K49

K50

K51

K52

K53

K54

K55

C7

K56

K57

K58

K59

K60

K61

K62

K63

C8

C2

C3

K10

K11

K12

K13

K14

K15

C2

R: 100

C1: 4.7

C2,C3: 100 pF

C4: 0.1

W

m

F/6.3 V

mF

D1: I.R.LED

D2: INDICATOR LED

Resonator: 455 kHz

K

C

OR

Figure 7-8. S3C1850 Application Circuit Example

7-14

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

S3C1860 Application Circuit Example

VDD

+3 V

C4

C1

R1

D1

R2

+

-

D2

VDD P2.0/ TEST P2.1 P2.2 P2.3 P2.4 P3.0 P3.1 P3.2

REM

SAMSUNG

S3C1860-xx

VSS

XI

XO P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P3.3

K0

K1

K2

K3

K4

K5

K6

K7

K8

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K30

K31

K32

K33

K34

K35

K36

K37

K38

K39

K40

K41

C3

C2

K9

K10

K11

K12

K13

R1: 1-5

R2: 100

W

C1: 47

C2,C3: 100 pF

C4: 0.1

D1: I.R.LED

D2: INDICATOR LED

mF/6.3 V

mF

K

Figure 7-9. S3C1860 Application Circuit Example

7-15

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

Program Flowchart (This program is only apply to S3C1840)

START

RESET

All key strobe output pins

are active

Yes

Any key input?

HALT

No

MAIN

All key strobe output pins

are non-active

KEYSCAN

Only one key strobe pin is active

One key input?

No

Double Key & No Key

Yes

No

Debounce Time = 0?

Yes

DATCUS

Data & Custom Code Generator

Yes

SIGNAL Tx.

Continous key?

Transmit Two

Waveforms

Transmit Repeat

Waveforms

Reset Debounce Time

MAIN

Figure 7-10. Program Flowchart 1

7-16

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850 KEYSCAN FUNCTION

Description

This program has an 8 x 9 key matrix, which consists of input P0 and P1 and output P2 and P3. Because pull-up

resistors are connected, the normal state for all input pins is high level. The operating method for the keyscan

function is as follows:

— All output pins remain active state ( = low).

— If key is pressed, set all output pins to non-active state and rotate the pins to set only a pin to active state

during debounce time.

— If key is pressed more than one or if no key is pressed, go to reset label.

— If a new key is pressed, reset debounce time, continuous flag, and key-in flag.

RAM Assignment

H register selects #0

HL

00H

01H

05H

09H

O_INP0

N_INP0

O_INP1

N_INP1

O_OUTP N_OUTP I_TWICE DEBOCNT CONKEY

KFLG

O_INP0:

The old value of P0

The new value of P0

The old value of P1

The new value of P1

N_INP0:

O_INP1:

N_INP1:

O_OUTP:

N_OUTP:

I_TWICE:

The old value of output port

The new value of output port

Double number increment

DEBOCNT: Debounce time

CONKEY: Continuous key flag

KFLG:

key input flag

7-17

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

Program Flowchart (This program is only apply to S3C1840)

518KSCAN

RESET

P2.1 & 2.6

High

; Close indicator LED & option pin

PORT3, P2.2-P2.5

Low

; Active strobe output pins

O_INP0, O_INP1, O_OUTP

DEBOCNT, CONKEY

#0FH

#0

; Initial variable

; Check port 0 input

No

Port 0 = #0FH

Yes

Port 1 = #0FH

Yes

; Check port1 input

P2.12

High

Low

; Halt mode & Halt mode release

H

#0

MAIN

; H register selects #0

PORT3, P2.2-P2.5

High

; Non-active strobe output pins

N_OUTP, KFLG

#0, I_TWICE

#1

Yes

N_OUTP.2 = #1

STROBE:

SERIAL:

; Only one output pin is low level

No

P2.5

Port 3

High

Low

P2.2-P2.5

Low

; PARALL

A

Figure 7-11. Program Flowchart 2

7-18

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

A

Yes

Key In:

Port 0:

Port 0 = #0FH

Port 1:

Yes

No

Port 0

N_INP0

Port 1 = #0FH

No

#0FH

No

Port 1 = #0FH

N_INP0

NORMAL

Yes

; NO KEY

N_INP1

L

#0FH

N_INP0

N_INP1

L

Port 1

N_INP1

Keycheck

A

A + #1

A

A + #1

Yes

Overflow?

No

RESET

No

A

A - #1

A

A - #1

RESET

; Double Key

N_INP0

A

N_INP1 A

; Double Key

DBCOMP:

;Compare old data to new data

N_OUTP

O_OUTP

No

a

N_OUTP = O_INP0

Yes

STROBE

INCS N_OUTP

Normal:

N_INP0

O_INP0

No

N_OUTP = #8

Yes

N_INP0 = O_INP0

Yes

No Key

RESET

KFLG = #1

Yes

N_INP1

O_INP1

P3.3

High

Yes

N_INP1 = O_INP1

No

DECS DEBOCNT

;New key &

debounce time

setting

DEBOCNT

CONKEY

#2

#0

No

FSTKEY:

SETKEY:

DEBOCNT = #0

Yes

MAIN

RET

;Key input setting

KFLG

a

#1

; Check the end

of debounce time

Figure 7-12. Program Flowchart 3

7-19

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850 Keycheck Subroutine

S3C1840/C1850/C1860/P1860

KEYCHEK

A

#0FH

L = #0EH

A + #1

No

A

No

L = #0DH

Yes

A

A + #2

No

L = #0BH

Yes

A

A + #3

No

L= #07H

Yes

A

A + #4

RET

Figure 7-13. S3C1840/C1850 Keycheck Subroutine

7-20

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

;*********************************************

ORG

0F00H

;*********************************************

; If reset occurs, PA register is immediately initialized to #0FH

RESET

MOV

SETB

MOV

SETB

L,#1

P2.(L)

L,#6

; close indicator LED

;

; non-select P2.6

;

P2.(L)

PRTCLR

CLR

A

;

OUT

MOV

CLRB

DECS

CPNE

JP

P3,@SL + A

; low all the output ports

; (except P2.0, P2.1, P2.6)

;

L,#5

P2.(L)

L

L,#1

.-3

;;; initial all of the variables --------------------------------------------------

;;; ® input ports are connected with pull-up resistor

;;; ® Therefore, normal state ® high

MOV

H,#0

; H register selects file #0

; port0 is #0fh

L,#O_INP0

@HL+,#0FH

L, #O_INP1

@HL +,#0FH

L, #O_OUTP

@HL+,#0FH

L,#DEBOCNT

@HL+,#0

; port1 is #0fh

; the strobe out is #0fh

; debounce count is #0

; continuous key is #0

L,#CONKEY

@HL+,#0

;;; check each input port (=key input) ------------------------------------

MOV

CLRB

IN

L,#0DH

P2.(L)

A,P0

; check port0

;

MOV

CPNE

JP

MOV

SETB

IN

MOV

CPNE

JP

L,A

;

L,#0FH

DELAYP0

L,#0DH

P2.(L)

A,P0

L,A

L,#0FH

J_MAIN

; check port1

;

;;; halt mode, after halt mode release, go to reset ------------------

MOV

SETB

CLRB

JP

L,#0CH

P2.(L)

; halt mode

; halt mode release

RESET

7-21

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

PRTSET

CLR

A

;

ADDS

OUT

MOV

SETB

DECS

CPNE

JP

A,#0FH

P3,@SL+A

L,#5

P2.(L)

L

; high all the output ports

; (P3, P2.2-P2.5)

;

L,#1

.- 3

; If P2.0 is high, data Tx.

; and auto reset counter clear

RET

DELAYP0 MOV

H #0

MAIN

; for the match of delay time

MOV

;

J_MAIN

JPL

;

;*********************************************

ORG

JPL

0000H

RESET

;*********************************************

MAIN

MOV

H,#0

; H regisster selects file #0

; useful when continous pulse Tx.

;

CALLL

PRTSET

; high all the output ports

;;; initial useful variable in main routine ------------------------------------

MOV

L,#N_OUTP

@HL+,#0

L,#1_TWICE

@HL+,#1

L,#KFLG

; N_OUTP ¬ #0

;

; I_TWICE (double increment) ¬ #1

;

; KFLG ¬ #0 (input key flag)

;

@HL+,#0

;; select output pin by one and one ---------------------------------

STROBE

MOV

CPBT

JP

MOV

INCS

SETB

INCS

CLRB

JPL

L,#N_OUTP

@HL.2

PARALL

L,@HL

L

P2.(L)

L

P2.(L)

KEYIN

; If N_OUTP.2 is set, go to parall (parallel port)

; otherwise, go to serial (serial port)

;

; low P2.2-P2.5

;

SERIAL

PARALL

MOV

SETB

L,#5

P2.(L)

; high P2.5

;

7-22

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

;;;*********************************************

;;; A ¬ #0h

;;; A ¬ A-1_TWICE

;;; output P3

;;; I_TWICE ¬ I_TWICE + I_TWICE

;;; ;*********************************************

CLR

A

; A ¬ #0FH

ADDS

MOV

XCH

SUBS

OUT

SUBS

MOV

ADDS

MOVZ

JPL

A, #0FH

L, #1_TWICE

@HL,A

A,@HL

P3,@SL+A

A,@HL

@HL,A

A,@HL

@HL,A

KEYIN

;

; A ¬ A-I_TWICE

;

; low port3

;

; recover I_TWICE

;

; I_TWICE ¬ I_TWICE + I_TWICE

;;;*********************************************

;; check double key at each port

;; if a key pressed, do adds instruction

;; otherwise, induce overflow occurrence

;;;*********************************************

KEYCHEK CLR

ADDS

A

A,#0FH

L,#0EH

.+2

A,#1

L,#0DH

.+2

A,#2

L,#0BH

.+2

A,#3

L,#7

; A ¬ #0fh

; A ¬ #0

; A ¬ #1

; A ¬ #2

; A ¬ #3

CPNE

JP

ADDS

CPNE

JP

ADDS

CPNE

JP

ADDS

CPNE

JP

.+2

A,#4

ADDS

RET

;

; *********************************************

ORG

JPL

0100H

RESET

; *********************************************

KEYIN

MOV

CLRB

L,#0DH

P2.(L)

;;; select port0 ---------------------------------

IN

A, P0

MOV

CPNE

JP

L,A

L,#0FH

PORT0

PORT1

; is key pressed in port0 ?

JP

7-23

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

PORT0

MOV

SETB

IN

L,#N_INP0

@HL,A

L,#ODH

P2.(L)

; setting at N_INP0

;

A,P0

;

MOV

CPNE

JP

L,A

L,#0FH

DBKEY

;

; If also port1 input a key,

; it is double key

MOV

CALLL

ADDS

JP

DECS

MOV

MOVZ

JPL

L,#N_INP1

@HL+,#0FH

L,#N_INP0

L,@HL

KEYCHEK

A,#1

DBKEY

A

L,#N_INP0

@HL,A

DBCOMP

; Only N_INP0 input

; but N_INP1 is set to #0fh

;

; if overflow occurs, it is double key

; because input value ranges

; from #0 to #3

; N_INP0 ¬ A

;;; select port1 ---------------------------------

PORT1

MOV

SETB

IN

L,#0DH

P2.(L)

A,P0

MOV

CPNE

JP

L,A

L,#0FH

.+3

; is key pressed in port 1?

JPL

NORMAL

L,#N_INP0

@HL+,#0FH

L,#N_INP1

@HL,A

L,A

KEYCHEK

A,#1

DBKEY

A

; no key, go to NORMAL

; setting N_INP0 to #0fh

; Only N_INP1 input

;

MOV

CALLL

ADDS

JP

;

; L ¬ N_INP1

; if overflow occurs, go to double key

;

; because input value ranges from

#0 to #3

DECS

MOV

MOVZ

JPL

L,#N_INP1

@HL,A

DBCOMP

; N_INP1 ¬ A

;;; if double key occurs, go to reset ---------------------------------

DBKEY

JPL

RESET

;

7-24

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

; *********************************************

ORG

JPL

0200H

RESET

; *********************************************

;;; compare for the recognition of a new key----------------------

DBCOMP

MOV

H,#N_OUTP

A,@HL

; compare N_OUTP to

O_OUTP

MOV

L,#O_OUTP

XCH

CPNE

@HL,A

JP

FSTKEY

L,#N_INP0

A,@HL

MOV

XCH

CPNE

JP

; compare N_INP0 to O_INP0

L,#O_INP0

@HL,A

FSTDLY

L,#N_INP1

A,@HL

MOV

XCH

CPNE

JP

; compare N_INP1 to O_INP1

L,#O_INP1

@HL,A

FSTKEY

SETKEY

JP

FSTDLY

MOV

H,#0

; for match of delay time

;;; when new key input ----------------------------

FSTKEY

MOV

L,#DEBOCNT

@HL+,#2

; DEBOCNT ¬ #2

; CONKEY ¬ #0

; KFLG ¬ #1

L,#CONKEY

@HL+,#0

SETKEY

L,#KFLG

@HL+,#1

7-25

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

; *********************************************

;;; increase N_OUTP

;;; check N_OUTP is equal to #8

;;; check no key (= DEBOCNT)

; *********************************************

NORMAL

MOV

INCS

MOVZ

ADDS

CPNE

JP

L,#N_OUTP

A,@HL

@HL,A

A,#8

; increase N_OUTP

; A ¬ #8

@HL,A

J_STRO

L,#KFLG

@HL.0

; compare N_OUTP to A

; go to stroble label

;

MOV

CPBT

JP

; check key flag

ONKEY

RESET

JPL

; no key

ONKEY

CLR

ADDS

OUT

MOV

DECS

XCH

CPNZ

JP

A

A,#0FH

P3,@SL + A

L,#DEBOCNT

A,@HL

; set port3 to ‘1’

; decrease DEBOCNT

@HL,A

@HL

; compare DEBOCNT TO #0

J1_MAIN

KEYSCAN

MAIN

JPL

J1_MAIN

J_STRO

JPL

STROBE

7-26

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850 CODE GENERATION

Description

This program generates data code and custom code. The custom code is determined according to diodes

between input ports and output pin (P2.6). The data code is as follows:

RAM

DAT0 (D0-D3), DAT1 (D4-D7)

RAM

DAT0 (D0-D3), DAT1_0 (D4-D7)

D0 D1 D2 D3 D4 D5 D6 D7

KEY0

KEY1

KEY0

KEY1

0

1

0

1

0

.

KEY31

KEY32

KEY33

1

0

1

0

1

0

1

0

1

0

1

0

KEY31

KEY32

KEY33

1

0

1

0

1

0

1

0

1

0

1

0

.

KEY63

1

0

1

0

KEY63

1

0

RAM Assignment

H register selects #4

HL

40H

41H

45H

DAT1

49H

DAT3_0

CUS0

CUS1

CUS2

CUS3

DAT0

DAT2

DAT3

DAT1_0

CUS0;

Custom code (c0-c3)

Custom code (c4-c7)

CUS1:

CUS2:

CUS3:

DAT0:

DAT1:

:

The complement of CUS0

The complement of CUS1

Data code (d0-d3)]

Data code (d4-d7)

® 32 key: 00000010, 63 key: 1111010

The complement of DAT0

DAT2:

DAT3:

DAT1_0

:

The complement of DAT1

Data code (d4-d7)

® 32 key: 00000100, 63 key: 1111100

The complement of DAT1_0

DAT3_0

7-27

REMOTE CONTROL TX. APPLICATION NOTE

Program Flowchart

S3C1840/C1850/C1860/P1860

518CODE

H <- #4

P2.6 <- LOW

; Select option pin

P2.13 <- LOW

; Custom code production

produce CUS0 & CUS2

P2.13 <- HIGH

produce CUS1 & CUS3

P2.6 <- HIGH

; Close option pin

; Indicator LED

P2.1 <- LOW

DAT0 <- O_INP0

N

DAT0 = #0FH

Y

DAT1 <- #4

DAT1_0 <- #2

DAT1 <- #0

DAT1_0 <- #0

DAT_P0:

DAT_P1:

R_SHIFT:

DAT0 <- O_INP1

Y

L <- DAT0

DAT0 shifts three times to left

N

CARRY ?

Y

S_CARRY:

A_OUTP:

INCS DAT1 & DAT1_0

DAT0 <- DAT0+O_OUTP

DAT2 <- the complement of

DAT0

DAT3 <- the complement of

DAT1

; Check the end of

debounce time

DAT1_0 <- the complement of

DAT3_0

RET

Figure 7-14. Program Flowchart 4

7-28

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

;*********************************************

ORG

JPL

0300H

RESET

;*********************************************

;;; select only a key ------------------------------------------------

KEYSCAN MOV

H,#4

;;; product custom code -------------------------------------------

MOV

CLRB

MOV

CLRB

IN

L,#6

; P2.6 ¬ low

P2.(L)

L,#0DH

P2.(L)

A,P0

; check custom code

;

MOV

NOTI

DECS

MOV

SETB

IN

L,#CUS2

@HL,A

A

; CUS2 is the complement of CUS0

;

A

L,#CUS0

@HL,A

L,#0DH

P2.(L)

A,P0

; CUS3 is the complement of CUS1

;

MOV

L,#CUS3

MOV

ADDS

@HL,A

A,@HL

;

NOTI

DECS

MOV

A

;

A

;

L,#CUS1

@HL,A

L,#6

;

MOVZ

MOV

;

; high P2.6

SETB

MOV

P2.(L)

L,#1

; the indicator LED of a key input

CLRB

P2.(L)

;;; product data code -------------------------------------------------

MOV

MOVZ

ADDS

CPNE

JP

H,#0

L,#O_INP0

A,@HL

H,#4

; DAT0 ¬ O_INP0

L,#DAT0

@HL,A

A,#0FH

@HL,A

DAT_P0

; A ¬ #0fh

; does input key exist in port0?

7-29

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

DAT_P1

MOV

L,#DAT1

@HL+,#04H

; input key exists in port1

; DAT1 ¬ DAT1 + #4

MOV

MOVZ

JPL

L,#DAT1_0

@HL+,#02H

H,#0

; DAT1_0 ¬ DAT1_0 + #2

; DAT0 ¬ O_INP1

L,#O_INP1

A,@HL

H,#4

;

L,#DAT0

@HL,A

R_SHIFT

L,#DAT1

@HL+,#0

L,#DAT1_0

@HL+,#0

L,#DAT0

H,#4

;

DAT_P0

MOV

JPL

; clear DAT1 & DAT1_0

; delay time

H,#4

;

H,#4

R_SHIFT

;

;*********************************************

ORG

JPL

0400H

RESET

;*********************************************

R_SHIFT

MOV

A,@HL

@HL,A

A,@HL

; DAT0 shifts three times to the left

ADDS

MOV

;

ADDS

MOV

ADDS

@HL,A

A,@HL

;

JP

S_CARRY

N_CARRY

S_CARRY MOV

L,#DAT1

@HL,A

A

;if carry occurs, increase DAT1 & DAT1_0

XCH

INCS

XCH

MOV

XCH

INCS

XCH

JP

;

@HL,A

L,#DAT1_0

@HL,A

A

@HL,A

A_OUTP

7-30

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

N_CARRY MOV

H,#0

; if carry doesn't occur, delay time

MOV

H,#0

;

A_OUTP

MOV

ADDS

MOV

NOTI

DECS

MOV

MOVz

MOV

NOTI

DECS

MOV

MOVZ

MOV

NOTI

DECS

MOV

JPL

H,#0

L,#O_OUTP

A,@HL

H,#4

; DAT0 ¬ DAT0 + O_OUTP

;

L,#DAT0

@HL,A

A

;

A

; DAT2 ¬ complement of DAT0

L,#DAT2

@HL,A

L,#DAT1

A,@HL

A

; DAT3 ¬ complement of DAT1

A

L,#DAT3

@HL,A

L,#DAT1_0

A,@HL

A

L,#DAT3_0

@HL,A

TX

; DAT3_0 ¬ complement of DAT 1_0

7-31

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

S3C1840/C1850 SIGNAL TRANSMISSION

Description

This program is for signal transmissions in SAMSUNG standard format. If one key is pressed, two frames are

transmitted consecutively. The repeat pulse is transmitted until key-off. The frame interval is 60 ms.

Each frame consists of leader code, custom code, and data code:

— Leader code (high level for 4.5 ms and low level for 4.5 ms)

— 12-bit custom code

— 8-bit data code

Transmission Waveform

60 ms

Frame Waveform

4.5 ms 4.5 ms

Leader code

custom code (c0-c11)

data code (d0-d7)

Data Pulse

0.56 ms

data '0'

0.56 ms

data '1'

1.125 ms

2.25 ms

Figure 7-15. Transmission Waveforms

RAM Assignment

This part is the same as for keyscan and code generation.

7-32

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840 Program Flowchart (This program is only apply to S3C1840)

518SAMTX

; select carrier frequency

P2.9 & 2.10

CUS4

LOW

; c8

#0

P2.0

HIGH for 4.5 msec

LOW for 4.5 msec

Output Custom & Data Code

P2.0

HIGH for .56 msec

LOW delay as many as

low number

DEBOCNT

#1

No

CONKEY + #0

Yes

; Repeat waveform transmission

; Until key off

CONKEY

#1

Delay for 60 msec

MAIN

; Repeat one more time

Figure 7-16. S3C1840 Program Flowchart 5

7-33

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

;*********************************************

ORG

JPL

0500H

RESET

;*********************************************

TX

MOV

CLRB

MOV

CLRB

L,#9

; select farrier frequency

; 37.9 kHz, 1/3 duty

; clear P2.9 & 2.10

P2.(L)

L,#0AH

P2.(L)

SIGOUT

MOV

MOB

L,#CUS4

@HL+,#0

; custom code (c8-c11) ¬ #0

; if device is KS51910, c8 ¬ #1

;;; output head pulse --------------------------------------------------

MOV

L,#0

; high for delay time 4.5 msec

; low for delay time 4.5 msec

SETB

CALLL

MOV

P2.(L)

D4_5

L,#0

CLRB

CALLL

P2.(L)

D4_5D

;;; output custom code (c0-c11) & data code (d0-d7)

MOV

CALLL

MOV

CALLL

MOV

CALLL

MOV

CALLL

MOV

CALLL

MOV

DECS

JP

L,#CUS0

DATGEN

L,#CUS1

DATGEN

L,#CUS4

DATGEN

L,#DAT0

DATGEN

L,#DAT1_0

DATGEN

L,#1

; custom code (c0-c3)

; custom code (c4-c7)

; custom code (c8-c11)

; data code (d0-d3)

; data code (d4-d7)

L

.-1

MOV

SETB

CALLL

MOV

CLRB

JPL

L,#0

; EOB (end of bit)

; high for .56msec

P2.(L)

D_560F

L,#0

P2.(L)

LOWCHEK

7-34

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

;*********************************************

ORG

JPL

0600H

RESET

;*********************************************

;;; check low code of custom code & data code --------------------------------

LOWCHEK MOV

CALL

L,#CUS0

LCHEK

; custom code (c0-c3)

MOV

L,#CUS1

LCHEK

; custom code (c4-c7)

; custom code (c8-c11)

; data code (d0-d3)

CALL

MOV

L,#CUS4

LCHEK

CALL

MOV

L,#DAT0

LCHEK

CALL

MOV

L,#DAT1_01

A,L

; the maximum value of upper bit is #3

; data code (d4-d7)

MOV

CALL

LCHEK_1

; check from the second bit

;== notice ===========================================================

; If value of DAT1_0 is greater than #3, programmer must change instruction

; CALLLCHEK_1 to other instruction such as CALLCHECK_2 or CALL

; LCHEK. And you must check the fram interval (= 60 msec)

;===================================================================

;;; re-setting debounce count to #1-------------------------------------

SETDBT

MOV

H,#0

L,#DEBOCNT

@HL+,#1

; DEBOCNT ¬ #1

;---------------------------------------------------------------------------------

;;; If conkey flag isn’t ‘0’, transmit repeat pulse

;;; otherwise, after setting, transmit again (two frames)

;---------------------------------------------------------------------------------

CONCHEK MOV

MOV

H,#0

L,#CONKEY

@HL

; CONKEY == #0?

CPNZ

JP

; If CONKEY is #0, CONKEY ¬ #1

; transmit frame again

LJ_MAIN

@HL+,#1

D4_5D

D2_25

D1_125

L,#0CH

H,#4

MOV

CALLL

MOV

; time is 60 msec per frame

MOV

H,#4

DECS

JP

L

.-3

JPL

SIGOUT

7-35

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

;;; output repeat pulse ----------------------------------------------------------

LJ_MAIN

CALL

JPL

D1_125

MAIN

;;; output delay time as many as low numbers ----------------------------

LCHEK

MOV

CPBT

JP

A,L

@HL,3

LCHEK_2

D2_25D

L,A

; if @hl.3 is low, call d2_25d.

; if @hl.2 is low, call d2_25d.

; if @hl.1 is low, call d2_25d.

; if @hl. 0 is low, call d2_25d.

CALLL

MOV

CPBT

JP

LCHEK_2

LCHEK_1

LCHEK_0

@HL.2

LCHEK_1

D2_25D

L,A

CALLL

MOV

CPBT

JP

@HL.1

LCHEK_0

D2_25D

L,A

CALLL

MOV

CPBT

JP

@HL.0

LCHEK_R

D2_25D

CALLL

LCHEK_R RET

;

;*********************************************

ORG

0700H

JPL

RESET

;*********************************************

;; custom code & data code generation -------------------------------------

DATGEN

MOV

CALL

CPBT

CALL

A,L

D_560

@HL.0

D2_25

D1_125

; high for .56 msec

; if @hl.0 is high, low for 2.25 msec.

; otherwise, low for 1.125 msec.

7-36

S3C1840/C1850/C1860/P1860

REMOTE CONTROL TX. APPLICATION NOTE

CALL

CPBT

CALL

CPBT

CALL

CPBT

CALL

RET

D_560

; high for .56 msec

@HL.1

D2_25

D1_125

D_560

@HL.2

D2_25

D1_125

D_560

@HL.3

D2_25

D1_125D

; if @hl.1 is high, low for 2.25 msec.

; otherwise, low for 1.125 msec.

; high for .56 msec

; if @hl.2 is high, low for 2.25 msec.

; otherwise, low for 1.125 msec.

; high for .56 msec

; if @hl.3 is high, low for 2.25 msec.

; otherwise, low for 1.125 msec.

;;; delay time subroutine by programming -----------------------------------

D_560

;

MOV

L,#0

SETB

P2,(L)

MOV

DECS

JP

L,#0CH

H,#4

L

.-2

MOV

H,#4

;

MOV

CLRB

MOV

RET

MOV

JP

L,#0

P2.(L)

L,A

D4_5D

D4_5

L,#02H

.+2

; delay time 4.5 msec

MOV

DECS

JP

L,#06H

L

-1

MOV

CLR

ADDS

MOV

DECS

JP

L,#05H

A

A,#0BH

H,#4

A

D_A

.-2

DECS

JP

L

.-6

7-37

REMOTE CONTROL TX. APPLICATION NOTE

S3C1840/C1850/C1860/P1860

D2_25D

D2_25

MOV

JP

L,#0EH

.+2

MOV

DECS

JP

L,#0FH

H,#4

L

.-2

D1_125

D1_125D

D_560F

MOV

JP

L,#0AH

.+6

MOV

JP

L,#08H

.+4

MOV

DECS

JP

L,#0BH

H,#4

L

; delay time .56 msec (for EOB)

.-2

RET

;

org

jpl

0800h

reset

org

jpl

0900h

reset

org

jpl

oaooh

reset

org

jpl

obooh

reset

org

jpl

ocooh

reset

org

jpl

odooh

reset

org

jpl

oeooh

reset

;

;******************* The END of S3C1840 SAMSUNG FORMAT TX. **************************

7-38


型号：	S3P1860-SK
厂家：	SAMSUNG
描述：	Microcontroller, 4-Bit, OTPROM, 6MHz, CMOS, PDSO20, SOP-20 微控制器
文件：	总91页 (文件大小：327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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