S3P7565-QX_技术文档

S3C7565/P7565

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

OVERVIEW

The S3C7565/P7565 single-chip CMOS microcontroller is designed for high performance in the application for

Caller-ID, Telephone using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangable Microcontrollers).

Featuring a DTMF generator, up-to-960-dot LCD direct drive capability, one 8-bit timer/counter and flexible two

8-bit timer/counters, and serial I/O interface, the S3C7565/P7565 offer an excellent design solution for a wide

variety of applications requiring DTMF, LCD support.

Up to 43 (including COM/SEG) pins in the 100-pin QFP package can be dedicated to I/O. Nine vectored

interrupts provide a fast response to internal and external events. In addition the advanced CMOS technology a

of the S3C7565/P7565 ensures low power consumption with a wide operating voltage range.

OTP

The S3C7565 microcontroller is also available in OTP (One Time Programmable) version, S3P7565.

S3P7565 microcontroller has an on-chip 16 K-byte one-time-programmable EPROM instead of masked ROM.

The S3P7565 is comparable to S3C7565, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW

S3C7565/P7565

FEATURES SUMMARY

Memory

8-bit Serial I/O Interface

•

8-bit transmit/receive mode

8-bit receive mode

•

16K ´ 8-bit ROM

5,120 ´ 4-bit RAM (excluding LCD RAM)

LSB-first or MSB-first transmission selectable

I/O Pins

LCD Controller/Driver

•

Input only:4pins (Not including COM/SEG)

6pins (Including COM/SEG)

•

60 SEG x 16 COM terminals

8, 12 and 16 com selectable

COM 8–15: shared with port

SEG40–59: shared with port

Two kinds of LCD bias resistor value

•

I/O:15pins (Not including COM/SEG)

43pins (Including COM/SEG)

Memory-Mapped I/O Structure

Data memory bank 15

8-bit Basic Timer

•

Bit Sequential Carrier

•

Supports 16-bit serial data transfer in arbitrary

format

•

Four interval timer functions

Watchdog timer

Interrupts

•

Four external interrupt vectors

8-bit Timer/Counter

Five internal interrupt vectors

Two quasi-interrupts

•

Programmable 8-bit timer

External event counter

Power-Down Modes

Arbitrary clock frequency output

External clock signal divider

•

Idle mode (only CPU clock stops)

Stop mode (main system oscillation stops)

Subsystem clock stop mode

16-Bit Timer/Counter

•

Programmable 16-bit timer

External event counter

Oscillation Sources

•

RC, Crystal or Ceramic for system clock

Oscillation frequency: 0.4–6.0 MHz

CPU clock divider circuit (by 4, 8, or 64)

Arbitrary clock frequency output

External clock signal divider

Configurable as two 8-bit Timers

Serial I/O interface clock generator

Instruction Execution Times

•

1.12, 2.23, 17.88 µs at 3.58 MHz

0.67, 1.33, 10.7 µs at 6.0 MHz

122 µs at 32.768 kHz (subsystem)

Watch Timer

•

Time interval generation: 0.5 s, 3.9 ms

at 32.768 kHz

Operating Temperature

•

4 frequency outputs to BUZ pin (0.5, 1, 2, 4 kHz)

at 32.768 kHz

°

•

– 40 C to 85 C

Operating Voltage Range

Comparator

•

1.8 V to 5.5 V (except DTMF and Comparator)

2 V to 5.5 V (include DTMF)

•

4-channel mode: Internal reference (4-bit

resolution); 16-step variable reference voltage

4.0 V to 5.5 V (include Comparator)

•

3-channel mode: External reference

Package Type

100-pin QFP (1420C)

DTMF Generator

•

16 dual-tone for tone dialing

1-2

S3C7565/P7565

PRODUCT OVERVIEW

BLOCK DIAGRAM

P7.0/SEG55/CIN0

P7.1/SEG54/CIN1

P7.2/SEG53/CIN2

P7.3/SEG52/CIN3

Basic

Timer

Watchdog

Timer

Comparator

Input Port 1

I/O Port 2

X

IN

X

OUT

RESET

XT

P1.0-P1.3/

INT0-INT4

Watch

Timer

P2.0/CLO

P2.1/VLC1

P2.2

Interrupt

Control

Block

Instruction

Register

VLC1

Clock

P3.0/TCLO0

P3.1/TCLO1

P3.2/TCL0

P3.3/TCL1

COM0-COM7

LCD

Driver/

Controller

I/O Port 3

P4.0-P5.3/

COM8-COM15

SEG0-SEG39

Program

Counter

Internal

Interrupts

P4.0-P4.3/

COM8-COM11

P10.3-P6.0/

SEG40-SEG59

I/O Port 4

I/O Port 5

P5.0-P5.3/

COM12-COM15

Serial I/O

I/O Port 0

Instruction Dcoder

P6.0-P6.3

SEG59-SEG56/

KS4-KS7

Program

Status Word

I/O Port 6

I/O Port 7

P0.0/SCK/KO

P0.1/SO/K1

P0.2/SI/K2

Arithmetic

and

Logic Unit

P7.0/SEG55/CIN0

P7.1/SEG54/CIN1

P7.2/SEG53/CIN2

P7.3/SEG52/CIN3

P0.3/BUZ/K3

Stack

Pointer

DTMF

Generator

DTMF

P8.0/SEG51/LCDCK

P8.1/SEG50/LCDSY

P8.2/SEG49

I/O Port 8

I/O Port 9

P8.3/SEG48

5K x 4-bit

RAM

16-Bit

P9.0-P9.3/

SEG47-SEG44

8-Bit

Timer/

Counter

Timer/Counter

(Two 8Bit

Timer/Counter)

P10.0-P10.3/

SEG43-SEG40

16KB ROM

I/O Port 10

Figure 1-1. S3C7565 Block Diagram

1-3

PRODUCT OVERVIEW

S3C7565/P7565

PIN ASSIGNMENTS

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

P10.3/SEG40

P10.2/SEG41

P10.1/SEG42

P10.0/SEG43

P9.3/SEG44

P9.2/SEG45

P9.1/SEG46

P9.0/SEG47

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

1

2

3

4

5

6

7

8

9

DTMF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P0.0/SCK/K0

P0.1/SO/K1

P0.2/SI/K2

P0.3/BUZ/K3

VDD

VSS

XOUT

XIN

TEST

XTIN

XTOUT

P8.3/SEG48

P8.2/SEG49

P8.1/SEG50/LCDSY

P8.0/SEG51/LCDCK

P7.3/SEG52/CIN3

P7.2/SEG53/CIN2

P7.1/SEG54/CIN1

P7.0/SEG55/CIN0

P6.3/SEG56/K7

P6.2/SEG57/K6

P6.1/SEG58/K5

RESET

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

P2.0/CLO

P2.1/VLC1

P2.2

P3.0/TCLO0

Figure 1-2. S3C7565 Pin Assignments (100-QFP Package)

1-4

S3C7565/P7565

PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C7565 Pin Descriptions

Description

Pin Name

P0.0

P0.1

P0.2

P0.3

Pin Type

I/O

Share Pin

4-bit I/O port.

SCK/K0

SO/K1

SI/K2

1-bit and 4-bit read/write and test is possible.

Individual pins are software configurable as input or

output.

Individual pins are software configurable as open-drain or

push-pull output.

BUZ/K3

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P1.0

P1.1

P1.2

P1.3

I

4-bit input port.

1-bit and 4-bit read and test is possible.

4-bit pull-up resistors are software assignable.

INT0

INT1

INT2

INT4

P2.0

P2.1

P2.2

I/O

Same as port 0 except that port 2 is a 3-bit I/O port.

Same as port 0.

CLO

V_LC1

P3.0

P3.1

P3.2

P3.3

TCLO0

TCLO1

TCL0

TCL1

P4.0–P4.3

P5.0–P5.3

I/O

4-bit I/O ports.

COM8–COM11

COM12–COM15

1-, 4-bit or 8-bit read/write and test is possible.

Individual pins are software configurable as input or

output.

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P6.0–P6.3

I/O

Same as P4, P5.

SEG59–

SEG56/K4–K7

P7.0–P7.3

P8.0–P8.1

SEG55/CIN0–

SEG52/CIN3

Input ports.

SEG51/LCDCK

SEG50/LCDSY

1, 4-bit or 8-bit read and test is possible.

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

These pins can not be used as push-pull output. Refer to

the NOTES of table 10-3. Port Mode Group Flags.

P8.2–P8.3

I/O

Same as P4, P5.

SEG49

SEG48

P9.0–P9.3

SEG47–SEG44

SEG43–SEG40

P0.0/K0

P10.0–P10.3

I/O

Same as P4, P5.

Serial I/O interface clock signal.

SCK

SO

I/O

Serial data output.

P0.1/K1

1-5

PRODUCT OVERVIEW

S3C7565/P7565

Share Pin

Table 1-1. S3C7565 Pin Descriptions (Continued)

Pin Name

Pin Type

Description

Serial data input.

SI

I/O

I

P0.2/K2

BUZ

0.5, 1, 2, or 4 kHz frequency output for buzzer sound.

P0.3/K3

INT0, INT1

External interrupts. The triggering edge for INT0 and

INT1 is selectable.

P1.0, P1.1

INT2

INT4

I

Quasi-interrupt with detection of rising or falling edges.

P1.2

P1.3

External interrupt with a detection of rising and falling

edge.

CLO

I/O

Clock output .

P2.0

P3.0

P3.1

P3.2

P3.3

TCLO0

TCLO1

TCL0

TCL1

Timer/counter 0 clock output.

Timer/counter 1 clock output.

External clock input for timer/counter 0.

External clock input for timer/counter 1.

CIN0

CIN1

CIN2

CIN3

4-Channel comparator input

CIN0–CIN2: comparator input only

CIN3: comparator input or external reference input

P7.0/SEG55

P7.1/SEG54

P7.2/SEG53

P7.3/SEG52

DTMF

O

DTMF output

–

P8.0/SEG51

P8.1/SEG50

–

LCDCK

I/O

O

LCD clock output

LCDSY

LCD synchronization clock output.

LCD common signal output.

COM0–COM7

COM8–COM11

COM12–COM15

SEG0–SEG39

SEG40–SEG59

K0–K3

I/O

P4.0–P4.3

P5.0–P5.3

–

O

LCD segment signal output.

I/O

P10.3–P6.0

P0.0–P0.3

P6.0–P6.3

–

External interrupt (triggering edge is selectable)

K4–K7

V_DD

–

I

Main power supply.

V_SS

Ground.

–

Reset signal.

–

RESET

V_LC1

–

I

LCD power supply.

P2.1

X_IN

X

OUT

Crystal, Ceramic or RC oscillator pins for system clock.

Crystal oscillator pins for subsystem clock.

–

,

XT_IN, XT_OUT

TEST

Chip test input pin.

Hold GND when the device is operating.

NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

1-6

S3C7565/P7565

PRODUCT OVERVIEW

Table 1-2. Supplemental S3C7565 Pin Data

Pin Names

Share Pins

I/O Type

Circuit Type

RESET Value

P0.0–P0.3

I/O

Input

E-4

SCK/K0, SO/K1,

SI/K2, BUZ/K3

P1.0–P1.3

INT0, INT1 and

INT2, INT4

I

Input

A-4

P2.0

P2.1

CLO

V_LC1

I/O

Input

E-4

E-7

P2.2

–

I/O

Input

E-4

E-2

P3.0–P3.1

P3.2–P3.3

TCLO0, TCLO1

TCL0, TCL1

E-4

P4.0–P4.3

P5.0–P5.3

COM8–COM11

COM12–COM15

H-24

I/O

H-25

H-26

P6.0–P6.3

SEG59/K4–

SEG56/K7

Input

P7.0–P7.2

SEG55/CIN0–

SEG53/CIN2

P7.3

SEG52/CIN3

I/O

Input

H-27

H-28

H-24

P8.0–P8.1

P8.2–P8.3

P9.0–P9.3

P10.0–P10.3

COM0–COM7

SEG0–SEG39

DTMF

SEG51–SEG50

Input

SEG49–SEG48

Input

SEG47–SEG44

Input

SEG43–SEG40

Input

–

O

–

High

H-3

G-7

–

High

High impedance

–

V_DD

V_SS

–

I

–

B

–

RESET

V_LC1

–

I

X_IN

X

OUT

,

XT_INXT

,

OUT

TEST

1-7

PRODUCT OVERVIEW

S3C7565/P7565

PIN CIRCUIT DIAGRAMS

VDD

Pull-Up

Resistor

P-Channel

N-Channel

In

Schmitt Trigger

Figure 1-3. Pin Circuit Type A

Figure 1-5. Pin Circuit Type B

VDD

Pull-Up

Resistor

P-CH

Pull-Up

Data

Resistor

Enable

Out

N-CH

Output

DIsable

In

Schmitt Trigger

Figure 1-4. Pin Circuit Type A-4

Figure 1-6. Pin Circuit Type C

1-8

S3C7565/P7565

PRODUCT OVERVIEW

VDD

Pull-up

Resistor

PNE

VDD

Pull-up

Resistor

Enable

P-CH

I/O

Data

N-CH

Output

DIsable

Figure 1-7. Pin Circuit Type E-2

VDD

Pull-up

Resistor

PNE

VDD

Pull-up

Resistor

Enable

P-CH

N-CH

I/O

Data

Output

DIsable

Schmitt Trigger

Figure 1-8. Pin Circuit Type E-4

1-9

PRODUCT OVERVIEW

S3C7565/P7565

VDD

Pull-up

Resistor

PNE

VDD

Pull-up

Resistor

Enable

P-CH

I/O

Data

Output

DIsable

N-CH

Digital

Input

VLCEN

VLC1

Figure 1-9. Pin Circuit Type E-7

1-10

S3C7565/P7565

PRODUCT OVERVIEW

VLC1

VLC2

VLC3

COM/SEG

VLC4

VLC5

VLC6

Figure 1-10. Pin Circuit Type H-3

1-11

PRODUCT OVERVIEW

S3C7565/P7565

VLC1

VLC2

VLC3

SEG/COM

Data

Out

Output

DIsable

VLC4

VLC5

VSS

Figure 1-11. Pin Circuit Type H-23

1-12

S3C7565/P7565

PRODUCT OVERVIEW

VDD

Pull-up

Resistor

Pull-up

Resistor

Enable

COM/SEG

LCD_ON

Circuit

Type H-23

Data

Circuit

Type C

I/O

Output

DIsable

Figure 1-12. Pin Circuit Type H-24

V

DD

Pull-up

Resistor

Pull-up

Resistor

Enable

COM/SEG

LCD_ON

Circuit

Type H-23

Data

Circuit

Type C

I/O

Output

DIsable

Figure 1-13. Pin Circuit Type H-25

1-13

PRODUCT OVERVIEW

S3C7565/P7565

VDD

Pull-up

Resistor

Pull-up

Resistor

Enable

P-CH

COM/SEG

LCD_ON

Circuit

Type H-23

Data

Circuit

Type C

I/O

Output

DIsable

Analog

Input SEL

Digital In

Analog In

Figure 1-14. Pin Circuit Type H-26

1-14

S3C7565/P7565

PRODUCT OVERVIEW

VDD

Pull-up

Resistor

Pull-up

Resistor

Enable

P-CH

COM/SEG

Circuit

LCD OUT EN

Type H-23

Data

Circuit

Type C

I/O

Output

DIsable

Analog

Input SEL

Digital In

External

REF SEL

Analog In

External

REF In

Figure 1-15. Pin Circuit Type H-27

1-15

PRODUCT OVERVIEW

S3C7565/P7565

VDD

Pull-up

Resistor

Pull-up

Resistor

Enable

COM/SEG

LCD_ON

Circuit

Type H-23

LCDCK/CLDSY

Circuit

Type C

LCDCK/LCDSY

Enable

I/O

Output

DIsable

Figure 1-16. Pin Circuit Type H-28

-

DTMF Out

+

Disable

Figure 1-17. Pin Circuit Type G-7

1-16

S3C7565/P7565

ADDRESS SPACES

2

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

The ROM maps for the S3C7565 devices are mask programmable at the factory. In its standard configuration,

the device's 16,384 ´ 8-bit program memory has three areas that are directly addressable by the program counter

(PC):

Table 2-1. Program Memory Address Ranges

ROM Area Function

Vector address area

Address Ranges

0000H–000FH

0010H–001FH

0020H–007FH

0080H–3FFFH

Area Size (in Bytes)

16

General-purpose program memory

REF instruction look-up table area

General-purpose program memory

96

16, 256

VECTOR ADDRESSES AREA

A 16-byte vector address area of the ROM is used to store the vector addresses for executing system resets and

interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable

memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines.

16-byte vector addresses are organized as follows:

EMB

PC7

ERB

PC6

PC13

PC5

PC12

PC4

PC11

PC3

PC10

PC2

PC9

PC1

PC8

PC0

To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the

next page explain how to do this.

REF INSTRUCTIONS

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF

instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte

instructions, and 3-byte instructions which are stored in the look-up table. Unused look-up table addresses can be

used as general-purpose ROM.

2-1

ADDRESS SPACES

S3C7565/P7565

GENERAL-PURPOSE MEMORY AREAS

The 16-byte area at the ROM locations 0010H–001FH and the 16,256-byte area at the ROM locations

0080H–3FFFH are used as general-purpose program memory. Unused locations in the vector address area and

the REF instruction look-up table areas can be used as general-purpose program memory. However, care must

be taken not to overwrite live data when writing programs that use special-purpose areas of the ROM.

0000H

7

6

5

4

3

2

1

0

Vector Address Area

(16 bytes)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

000EH

RESET

INTB/INT4

INT0

000FH

0010H

General Purpose Area

(16 bytes)

001FH

0020H

INT1

Instruction Reference Area

(96 bytes)

007FH

0080H

INTS

INTT0/INTT1B

INTT1 (INTT1A)

INTK

General Purpose Area

(16,256 bytes)

3FFFH

Figure 2-1. ROM Address Structure

Figure 2-2. Vector Address Map

2-2

S3C7565/P7565

ADDRESS SPACES

+

PROGRAMMING TIP — Defining Vectored Interrupts

The following examples show you several ways you can define the vectored interrupt and instruction reference

areas in program memory:

1. When all vector interrupts are used:

ORG

0000H

;

VENT0

VENT1

VENT2

VENT3

VENT4

VENT5

VENT6

VENT7

1,0,RESET

0,0,INTB

0,0,INT0

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

0,0,INTK

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address

; EMB ¬ 0, ERB ¬ 0; Jump to INT0 address

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address

; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTK address

2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations

must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG

0000H

;

VENT0

VENT1

ORG

1,0,RESET

0,0,INTB

0006H

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address

; INT0 interrupt not used

VENT3

VENT4

0,0,INT1

0,0,INTS

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address

;

ORG

000CH

; INTT0 interrupt not used

VENT6

VENT7

0,0,INTT1

0,0,INTK

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address

; EMB ¬ 0, ERB ¬ 0; Jump to INTK address

;

ORG

0010H

2-3

ADDRESS SPACES

S3C7565/P7565

+

PROGRAMMING TIP — Defining Vectored Interrupts (Continued)

3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not

written by a ORG instruction as in Example 2, a CPU malfunction will occur:

ORG

0000H

;

VENT0

VENT1

VENT3

VENT4

VENT5

VENT6

VENT7

1,0,RESET

0,0,INTB

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

0,0,INTK

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address for INT0

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address for INT1

; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address for INTS

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address for INTT0

; EMB ¬ 0, ERB ¬ 0; Jump to INTK address for INTT1

;

ORG

0010H

General-purpose ROM area

In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but

VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU

malfunction to occur.

2-4

S3C7565/P7565

ADDRESS SPACES

INSTRUCTION REFERENCE AREA

Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in

addresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or

look-up table. Locations in the REF look-up table may contain two one-byte instructions, a single two-byte

instruction, or three-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are

referencing must always be an even number. To reference a JP or CALL instruction, it must be written to the

reference area in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are

three ways to the REF instruction:

By using REF instructions to execute instructions larger than one byte. In summary, there are three ways you can

use the REF instruction:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,

— Branching to any location by referencing a branch instruction stored in the look-up table,

— Calling subroutines at any location by referencing a call instruction stored in the look-up table.

+

PROGRAMMING TIP — Using the REF Look-Up Table

Here is one example of how to use the REF instruction look-up table:

ORG

0020H

;

JMAIN

KEYCK

WATCH

INCHL

TJP

BTSF

TCALL

LD

INCS

•

MAIN

; 0, MAIN

; 1, KEYFG CHECK

; 2, Call CLOCK

KEYFG

CLOCK

@HL,A

HL

; 3, (HL) ¬

A

•

ABC

LD

ORG

EA,#00H

0080

; 47, EA ¬ #00H

;

MAIN

NOP

•

REF

KEYCK

JMAIN

WATCH

INCHL

; BTSF KEYFG (1-byte instruction)

; KEYFG = 1, jump to MAIN (1-byte instruction)

; KEYFG = 0, CALL CLOCK (1-byte instruction)

; LD @HL,A

; INCS HL

REF

ABC

; LD EA,#00H (1-byte instruction)

•

2-5

ADDRESS SPACES

S3C7565/P7565

DATA MEMORY (RAM)

OVERVIEW

In its standard configuration, the data memories has four areas:

— 32 ´ 4-bit working register area

— 224 ´ 4-bit general-purpose area in bank 0 which is also used as the stack area

— 20 pages with 256 x 4-bit in bank1

·

19 pages for general purpose area (00H–12H page)

1 page for LCD Display data memory (13H page)

— 128 ´ 4-bit area in bank 15 for memory-mapped I/O addresses

To make it easier to reference, the data memory area has three memory banks — bank 0, bank 1 and bank 15.

The select memory bank instruction (SMB) is used to select the bank you want as working data memory. Data

stored in the RAM locations are 1-bit, 4-bit, and 8-bit addressable.

Initialization values for the data memory area are not defined by hardware and must therefore be initialized by

program software after a power RESET. However, when RESET signal is generated in power-down mode, the

data memory contents are held.

BANK1 PAGE SELECTION REGISTER (PASR)

PASR is an 8-bit register for selecting a page in bank1, and is mapped to the RAM address, F8AH–F8BH.

It should be read or written by an 8-bit RAM control instruction only and the MSB 3 bits should be “0”. PASR

retains the existing value as long as any change is not required, and the RESET value is 0. Therefore, when it

returns to bank1 from other bank (bank0 or bank15) without changing the contents of PASR, the previously

specified page is selected. PASR must not be changed in the interrupt service routine because its value cannot

be recovered as the original value when the routine is finished.

2-6

S3C7565/P7565

ADDRESS SPACES

3

2

1

0

000H

020H

Working

Registers

Bank 0

(EMB=1, SMB=0)

General-

Purpose

and Stack

Registers

0FFH

100H

General-

Purpose

Registers

100H

Bank 1

(EMB=1, SMB=1)

100H

Page

(01H)

100H

1FFH

Page

(02H)

100H

Page

(03H)

100H

Page

(04H)

Page

(00H)

Page

(05H)

Page

(06H)

Page

(07H)

Page

(1BH)

1FFH

F80H

1FFH

Page

1FFH

(1CH)

1FFH

Page

(1EH)

1FFH

(1DH)

1FFH

Peripheral

Hardware

Register

Bank15

(EMB=1, SMB=15

or EMB=0)

1FFH

FFFH

S

E

S

E

S

E

S

E

S

E

S

E

S

E

S

E

S

E

S

E

S

E

S

E

G G G G G G G G

G G G G

56 57 58 59

0

1 2 3 4 5 6 7

b0 b1 b2 b3 b0 b1 b2 b3

b0 b1 b2 b3

10EH

COM0

COM1

COM2

COM3

100H

110H

120H

130H

101H

111H

121H

131H

11EH

12EH

13EH

Display

Data

Registers

Page (13H)

COM12

COM13

COM14

COM15

1C0H

1D0H

1E0H

1F0H

1CEH

1DEH

1EEH

1FEH

1CEH

1DEH

1EEH

1FEH

Figure 2-3. Data Memory (RAM) Map

2-7

ADDRESS SPACES

S3C7565/P7565

Memory Banks 0, 1, 2, and 15

Bank 0

Bank 1

(000H–0FFH)

(100H–1FFH)

The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;

the next 224 nibbles (020H–0FFH) can be used both as stack area and as

general-purpose data memory. Use the stack area for implementing subroutine

calls and returns, and for interrupt processing.

Bank 1 has the data memory of 20 pages, the first 19 pages for general-

purpose data memory are comprised of 256 x 4-bits, and the 20th page for

LCD display data memory consists of 240 x 4-bits.

The S3C7565 uses specially a page selection register (PASR) for selecting one

of these 20 pages.

Bank 15

(F80H–FFFH)

The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed

RAM locations for each peripheral hardware address are mapped into this area.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the

EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or

indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and bank 15.

With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all

three data memory banks can be accessed according to the current SMB value.

For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to

address RAM locations, remember to use the even-numbered register address as the instruction operand.

Working Registers

The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2,

and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.

Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag

bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for

indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable

to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.

LCD Data Register Area

Bit values for LCD segment data are stored in data memory bank 1 (13H page). Register locations in this area

that are not used to store LCD data can be assigned to general-purpose use.

2-8

S3C7565/P7565

ADDRESS SPACES

Table 2-2. Data Memory Organization and Addressing

Addresses

000H–01FH

020H–0FFH

100H–1FFH

Register Areas

Working registers

Bank

EMB Value

SMB Value

0

0, 1

0

Stack and general-purpose registers

General-purpose registers (the first19 pages):

LCD display data memory (the 20th page)

1

F80H–FFFH

I/O-mapped hardware registers

15

0, 1

15

+

PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1

Clear banks 0 and 1 of the data memory area:

RAMCLR

BITS

SMB

LD

EMB

0

HL,#10H

A,#0H

; Clear RAM (010H–0FFH)

LD

RMCL0

LD

INCS

JR

@HL,A

HL

RMCL0

; Clear all page in memory bank 1

SMB

LD

SMB

LD

15

EA,#13H

PASR,EA

1

A,#0H

PACL0

LD

INCS

JR

@HL,A

HL

PACL0

SMB

LD

DECS

JR

15

EA,PASR

EA

PACL1

PACL2

JR

PACL1

PALL2

LD

JPS

PASR,EA

PACL0

•

2-9

ADDRESS SPACES

S3C7565/P7565

WORKING REGISTERS

Working registers, mapped to RAM address 000H–01FH in data memory bank 0, are used to temporarily store

intermediate results during program execution, as well as pointer values used for indirect addressing. Unused

registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-

bit units or, using paired registers, as 8-bit units.

000H

001H

002H

A

E

L

003H

H

X

Working

Register

Bank 0

004H

005H

006H

007H

008H

W

Z

Data

Memory

Bank 0

Y

Register

Bank 1

A ...Y

00FH

010H

Register

Bank 2

017H

018H

Register

Bank 3

01FH

Figure 2-4. Working Register Map

2-10

S3C7565/P7565

ADDRESS SPACES

Working Register Banks

For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,

and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection

instruction (SRB n) and by setting the status of the register bank enable flag (ERB).

Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service

routines. Following this convention helps to prevent possible data corruption during program execution due to

contention in register bank addressing.

Table 2-3. Working Register Organization and Addressing

ERB Setting

SRB Settings

Selected Register Bank

3

0

2

0

1

x

0

1

0

x

0

1

0

1

0

1

Always set to bank 0

Bank 0

Bank 1

Bank 2

Bank 3

NOTE: “x” means don't care.

Paired Working Registers

Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and

A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data

manipulation.

The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z

always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit

registers or four 8-bit double registers in each of the four working register banks.

(MSB)

(LSB)

(MSB)

(LSB)

Y

W

H

Z

X

L

E

A

Figure 2-5. Register Pair Configuration

2-11

ADDRESS SPACES

S3C7565/P7565

Special-Purpose Working Registers

Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also

be used as a 1-bit accumulator.

8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register

serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working

registers as program loop counters by letting you transfer a value to the L register and increment or decrement it

using a single instruction.

Y

1-Bit Accumulator

4-Bit Accumulator

8-Bit Accumulator

A

EA

Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator

Recommendation for Multiple Interrupt Processing

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

2-12

S3C7565/P7565

ADDRESS SPACES

+

PROGRAMMING TIP — Selecting the Working Register Area

The following examples show the correct programming method for selecting working register area:

1. When ERB = "0":

VENT2

1,0,INT0

; EMB ¬ 1, ERB ¬ 0, Jump to INT0 address

;

INT0

PUSH

SRB

PUSH

SMB

LD

INCS

LD

POP

IRET

SB

2

HL

WX

YZ

EA

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

EA

YZ

WX

HL

SB

; PUSH current SMB, SRB

; Instruction does not execute because ERB = "0"

; PUSH HL register contents to stack

; PUSH WX register contents to stack

; PUSH YZ register contents to stack

; PUSH EA register contents to stack

; POP EA register contents from stack

; POP YZ register contents from stack

; POP WX register contents from stack

; POP HL register contents from stack

; POP current SMB, SRB

The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an

interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and

SRB values, as shown in Example 2 below.

2. When ERB = "1":

VENT2

1,1,INT0

; EMB ¬ 1, ERB ¬ 1, Jump to INT0 address

;

INT0

PUSH

SRB

SMB

LD

INCS

LD

POP

IRET

SB

2

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

SB

; Store current SMB, SRB

; Select register bank 2 because of ERB = "1"

; Restore SMB, SRB

2-13

ADDRESS SPACES

S3C7565/P7565

STACK OPERATIONS

STACK POINTER (SP)

The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data

memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control

instructions. When addressing the SP, bit 0 must always remain cleared to logic zero.

F80H

F81H

SP3

SP7

SP2

SP6

SP1

SP5

"0"

SP4

There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack

(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the

last data to be written to the stack.

The program counter contents and program status word are stored in the stack area prior to the execution of a

CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out)

type. The stack area is located in general-purpose data memory bank 0.

During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine

has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.

The SP can address stack registers in bank 0 (addresses 000H–0FFH) regardless of the current value of the

enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register

areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same

register(s).

Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack

pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.

NOTE

A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or

interrupt routines are used continuously, the stack area should be set in accordance with the maximum

number of subroutine levels. To do this, estimate the number of nibbles that will be used for the

subroutines or interrupts and set the stack area correspondingly.

+

PROGRAMMING TIP — Initializing the Stack Pointer

To initialize the stack pointer (SP):

1. When EMB = "1":

SMB

LD

15

EA,#00H

SP,EA

; Select memory bank 15

; Bit 0 of SP is always cleared to "0"

; Stack area initial address (0FFH) ¬ (SP) – 1

2. When EMB = "0":

LD

EA,#00H

SP,EA

; Memory addressing area (00H–7FH, F80H–FFFH)

2-14

S3C7565/P7565

ADDRESS SPACES

PUSH OPERATIONS

Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the

stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number

determined by the type of push operation and then points to the next available stack location.

PUSH Instructions

A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are

referenced by the stack pointer: one for the upper register value and another for the lower register. After the

PUSH has executed, the SP is decremented by two and points to the next available stack location.

CALL Instructions

When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit

stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag

are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up

to the number of levels permitted in the stack.

Interrupt Routines

An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the

stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is

decremented by six and points to the next available stack location. During an interrupt sequence, subroutines

may be nested up to the number of levels which are permitted in the stack area.

Interrupt

(When INT is acknowledged,

SP SP - 6)

PUSH

(After PUSH, SP

CALL, LCALL

(After CALL or LCALL, SP

SP - 2)

SP - 6)

SP - 6

PC11 - PC8

PC14 - PC12

PC3 - PC0

PC7 - PC4

PC11 - PC8

PC14 - PC12

PC3 - PC0

PC7 - PC4

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP

0

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP

0

SP - 2

SP - 1

SP

Lower Register

Upper Register

0

EMB ERB

PSW

IS1

C

IS0 EMB ERB

PSW

SC2 SC1 SC0

0

Figure 2-7. Push-Type Stack Operations

2-15

ADDRESS SPACES

POP OPERATIONS

S3C7565/P7565

For each push operation there is a corresponding pop operation to write data from the stack back to the source

register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET;

for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined

by the type of operation and points to the next free stack location.

POP Instructions

A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and

SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register.

After the POP has executed, the SP is incremented by two and points to the next free stack location.

RET and SRET Instructions

The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP

to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and

the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack

location.

IRET Instructions

The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six

4-bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET

has executed, the SP is incremented by six and points to the next free stack location.

POP

SP + 2)

RET or SRET

(SP SP + 6)

IRET

SP + 6)

(SP

SP

Lower Register

Upper Register

PC11 - PC8

PC14 - PC12

PC3 - PC0

PC7 - PC4

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC14 - PC12

PC3 - PC0

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC7 - PC4

0

EMB ERB

PSW

IS1

C

IS0 EMB ERB

PSW

SC2 SC1 SC0

0

Figure 2-8. Pop-Type Stack Operations

2-16

S3C7565/P7565

ADDRESS SPACES

BIT SEQUENTIAL CARRIER (BSC)

The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM

control instructions. RESET clears all BSC bit values to logic zero.

Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing

(memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit

data by moving the bit location sequentially and then incrementing or decrementing the value of the L register.

BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names

BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately.

If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L

register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.

Table 2-4. BSC Register Organization

Name

BSC0

BSC1

BSC2

BSC3

Address

FC0H

Bit 3

Bit 2

Bit 1

Bit 0

BSC0.3

BSC1.3

BSC2.3

BSC3.3

BSC0.2

BSC1.2

BSC2.2

BSC3.2

BSC0.1

BSC1.1

BSC2.1

BSC3.1

BSC0.0

BSC1.0

BSC2.0

BSC3.0

FC1H

FC2H

FC3H

+

PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data

To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:

BITS

SMB

LD

SMB

LD

LDB

INCS

JR

EMB

15

EA,#37H

BSC0,EA

EA,#59H

BSC2,EA

0

L,#0H

C,BSC0.@L

P3.0,C

L

;

; BSC0 ¬ A, BSC1 ¬

;

; BSC2 ¬ A, BSC3 ¬

E

;

AGN

; P3.0 ¬

C

AGN

RET

2-17

ADDRESS SPACES

S3C7565/P7565

PROGRAM COUNTER (PC)

A 14-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a

reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address.

Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the

1-byte REF instruction which is used to reference instructions stored in the ROM.

PROGRAM STATUS WORD (PSW)

The program status word (PSW) is an 8-bit word that defines system status and program execution status and

which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW

values are mapped as follows:

(MSB)

IS1

(LSB)

ERB

SC0

FB0H

FB1H

IS0

EMB

SC1

C

SC2

The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific

bit or bits being addressed. The PSW can be addressed during program execution regardless of the current

value of the enable memory bank (EMB) flag.

Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the

interrupt has been processed, the PSW values are popped from the stack back to the PSW address.

When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the

carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all

cleared to logical zero.

Table 2-5. Program Status Word Bit Descriptions

PSW Bit Identifier

IS1, IS0

Description

Interrupt status flags

Enable memory bank flag

Enable register bank flag

Carry flag

Bit Addressing

Read/Write

R/W

1, 4

1

EMB

R/W

ERB

1

R/W

C

1

R/W

SC2, SC1, SC0

Program skip flags

8

R

2-18

S3C7565/P7565

ADDRESS SPACES

INTERRUPT STATUS FLAGS (IS0, IS1)

PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1

flags directly using 1-bit RAM control instructions.

By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process

multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit

determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status

flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined

by the IPR.

When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically

incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET

instruction, IS0 and IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings.

Table 2-6. Interrupt Status Flag Bit Settings

IS1

Value

IS0

Value

Status of Currently

Executing Process

Effect of IS0 and IS1 Settings

on Interrupt Request Control

0

1

0

1

All interrupt requests are serviced.

Only high-priority interrupt(s) as determined in the

interrupt priority register (IPR) are serviced.

1

0

1

2

–

No more interrupt requests are serviced.

Not applicable; these bit settings are undefined.

Since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter-

rupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI in-

struction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI

instruction to re-enable interrupt processing.

+

PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing

The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:

INTB

DI

; Disable interrupt

; IS1 ¬

; Allow interrupts according to IPR priority level

; Enable interrupt

BITR

BITS

EI

IS1

IS0

0

2-19

ADDRESS SPACES

EMB FLAG (EMB)

S3C7565/P7565

The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit

data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1, or 15.

When the EMB flag is "0", the data memory address space is restricted to 0F80H–0FFFH of data memory bank

15 and addresses 000H–07FH of bank 0, regardless of the SMB register contents. When the EMB flag is set to

"1", the addressing area of data memory is expanded and all of data memory space can be accessed by using

the appropriate SMB and PASR value.

+

PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks

EMB flag settings for memory bank selection:

1. When EMB = "0" and PASR = “0”:

SMB

LD

SMB

LD

SMB

LD

1

; Non-essential instruction since EMB = "0"

A,#9H

90H,A

34H,A

0

90H,A

34H,A

15

; (F90H) ¬ A, bank 15 is selected

; (034H) ¬ A, bank 0 is selected

; Non-essential instruction since EMB = "0"

; (F90H) ¬ A, bank 15 is selected

; (034H) ¬ A, bank 0 is selected

; Non-essential instruction, since EMB = "0"

; (020H) ¬ A, bank 0 is selected

; (F90H) ¬ A, bank 15 is selected

20H,A

90H,A

LD

2. When EMB = "1" and PASR = “0”:

SMB

LD

SMB

LD

SMB

LD

1

; Select memory bank 1

A,#9H

90H,A

34H,A

0

90H,A

34H,A

15

; (190H) ¬ A, page 0 of bank 1 is selected

; (134H) ¬ A, page 0 of bank 1 is selected

; Select memory bank 0

; (090H) ¬ A, bank 0 is selected

; (034H) ¬ A, bank 0 is selected

; Select memory bank 15

20H,A

90H,A

; Program error, but assembler does not detect it

; (F90H) ¬ A, bank 15 is selected

LD

2-20

S3C7565/P7565

ADDRESS SPACES

ERB FLAG (ERB)

The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the

ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank

selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area,

regardless of the current value of the register bank selection register (SRB).

When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This

automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in

program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is

executed.

During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW

bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored

interrupt are defined using VENTn instructions.

+

PROGRAMMING TIP — Using the ERB Flag to Select Register Banks

ERB flag settings for register bank selection:

1. When ERB = "0":

SRB

1

; Register bank 0 is selected (since ERB = "0", the

SRB is configured to bank 0)

; Bank 0 EA ¬ #34H

; Bank 0 HL ¬ EA

; Register bank 0 is selected

; Bank 0 YZ ¬ EA

LD

SRB

LD

SRB

LD

EA,#34H

HL,EA

2

YZ,EA

3

; Register bank 0 is selected

; Bank 0 WX ¬ EA

WX,EA

2. When ERB = "1":

SRB

LD

SRB

LD

SRB

LD

1

; Register bank 1 is selected

; Bank 1 EA ¬ #34H

EA,#34H

HL,EA

2

YZ,EA

3

; Bank 1 HL ¬ Bank 1 EA

; Register bank 2 is selected

; Bank 2 YZ ¬ BANK2 EA

; Register bank 3 is selected

; Bank 3 WX ¬ Bank 3 EA

WX,EA

2-21

ADDRESS SPACES

S3C7565/P7565

SKIP CONDITION FLAGS (SC2, SC1, SC0)

The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set

and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read

instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed.

CARRY FLAG (C)

The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving

a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations

involving bit-addressed data memory.

If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry

flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained

during power-down mode, but when normal operating mode resumes, its value is undefined.

The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other

bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2-7, affect the carry flag.

Table 2-7. Valid Carry Flag Manipulation Instructions

Operation Type

Instructions

Carry Flag Manipulation

Set carry flag to "1".

Direct manipulation

SCF

RCF

CCF

Clear carry flag to "0" (reset carry flag).

Invert carry flag value (complement carry flag).

Test carry and skip if C = "1".

BTST C

LDB (operand) ⁽¹⁾, C

LDB C, (operand) ⁽¹⁾

BAND C, (operand) ⁽¹⁾

Bit transfer

Load carry flag value to the specified bit.

Load contents of the specified bit to carry flag.

Boolean manipulation

AND the specified bit with contents of carry flag and save

the result to the carry flag.

BOR C, (operand) ⁽¹⁾

BXOR C, (operand) ⁽¹⁾

OR the specified bit with contents of carry flag and save

the result to the carry flag.

XOR the specified bit with contents of carry flag and save

the result to the carry flag.

INTn ⁽²⁾

IRET

Interrupt routine

Save carry flag to stack with other PSW bits.

Return from interrupt

Restore carry flag from stack with other PSW bits.

NOTES:

1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.

2. “INTn” refers to the specific interrupt being executed and is not an instruction.

2-22

S3C7565/P7565

ADDRESS SPACES

+

PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator

1. Set the carry flag to logic one:

SCF

; C ¬ 1

LD

EA,#0C3H

; EA ¬ #0C3H

LD

ADC

HL,#0AAH

EA,HL

; HL ¬ #0AAH

; EA ¬ #0C3H + #0AAH + #1H, C ¬

1

2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0:

LD

H,#3H

; Set the upper four bits of the address to the H register

; value

LDB

BAND

LDB

C,@H + 0FH.3

C,P3.3

P5.0,C

; C ¬ bit 3 of 3FH

; C ¬ C AND P3.3

; Output result from carry flag to P5.0

2-23

ADDRESS SPACES

S3C7565/P7565

NOTES

2-24

S3C7565/P7565

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is

set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the

addressable area in the RAM is restricted to specific locations.

The EMB flag works in connection with the select memory bank instruction, SMBn. You will recall that the SMBn

instruction is used to select RAM bank 0, 1, or 15. The SMB setting is always contained in the upper four bits of a

12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to the

memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1, or

15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations are

addressable at all times, regardless of the current EMB flag setting.

Here are a few guidelines to keep in mind regarding data memory addressing:

— When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped

hardware component can be used as the operand in place of the actual address location.

— Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing.

— With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the

instruction specifies a register which contains the operand's address.

3-1

ADDRESSING MODES

S3C7565/P7565

Addressing

Mode

DA

DA.b

@HL

@H+DA.b

@WX

@WL

mema.b memb.@L

RAM

Areas

EMB = 0 EMB = 1 EMB = 0 EMB = 1

X

000H

Working

Registers

01FH

020H

07FH

080H

SMB = 0

Bank 0

(General

Registers

and Stack)

0FFH

100H

Bank 1

(General

SMB = 1

Registers and

Display Registers)

1FFH

F80H

FB0H

FBFH

FC0H

Bank 15

(Peripheral

Hardware

Registers)

SMB = 15

FF0H

FFFH

NOTES:

1. 'X' means don't care.

2. Blank columns indicate RAM areas that are not addressable, given the addressing method, and

enable memory bank (EMB) flag setting shown in the column headers.

3. Bank 1 consists of gerneral registers (0H-12H pages), and Display registers (13H page)

Figure 3-1. RAM Address Structure

3-2

S3C7565/P7565

ADDRESSING MODES

EMB AND ERB INITIALIZATION VALUES

The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt

vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to

the EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector

address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine.

When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the

interrupt routine has completed.

At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by

using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR)

despite the current SMB setting.

+

PROGRAMMING TIP — Initializing the EMB and ERB Flags

The following assembly instructions show how to initialize the EMB and ERB flag settings:

ORG

0000H

; ROM address assignment

VENT0 1,0,RESET

VENT1 0,1,INTB

VENT2 0,1,INT0

VENT3 0,1,INT1

VENT4 0,1,INTS

VENT5 0,1,INTT0

VENT6 0,1,INTT1

VENT7 0,1,INTK

; EMB ¬ 1, ERB ¬ 0, branch RESET

; EMB ¬ 0, ERB ¬ 1, branch INTB

; EMB ¬ 0, ERB ¬ 1, branch INT0

; EMB ¬ 0, ERB ¬ 1, branch INT1

; EMB ¬ 0, ERB ¬ 1, branch INTS

; EMB ¬ 0, ERB ¬ 1, branch INTT0

; EMB ¬ 0, ERB ¬ 1, branch INTT1

; EMB ¬ 0, ERB ¬ 1, branch INTK

•

RESET BITR

EMB

3-3

ADDRESSING MODES

S3C7565/P7565

ENABLE MEMORY BANK SETTINGS

EMB = "1"

When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by

the select memory bank (SMB) value (0, 1, or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and

indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows:

If SMB = 0,

If SMB = 1,

If SMB = 15,

000H–0FFH

100H–1FFH

F80H–FFFH

EMB = "0"

When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of

the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is

used.

If EMB = "0", the addressable area is restricted to locations 000H–07FH in bank 0 and to locations F80H–FFFH

in bank 15 for direct addressing. For indirect addressing, only locations 000H–0FFH in bank 0 are addressable,

regardless of SMB value.

To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to

"1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of

ROM address 0000H.

EMB-Independent Addressing

At any time, several areas of the data memory can be addressed independent of the current status of the EMB

flag. These exceptions are described in Table 3-1.

Table 3-1. RAM Addressing Not Affected by the EMB Value

Address

Addressing Method

Affected Hardware

Program Examples

000H–0FFH

4-bit indirect addressing using WX

and WL register pairs;

Not applicable

LD

A,@WX

8-bit indirect addressing using SP

PUSH

POP

FB0H–FBFH

FF0H–FFFH

1-bit direct addressing

PSW, SCMOD,

IEx, IRQx, I/O

BITS EMB

BITR IE4

FC0H–FFFH

1-bit indirect addressing using the

L register

BSC, I/O

BTST FC3H.@L

BAND C,P3.@L

3-4

S3C7565/P7565

ADDRESSING MODES

SELECT BANK REGISTER (SB)

The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register con-

sists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown

in Figure 3-2.

During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB

instruction. You later restore the value to the SB using the POP SB instruction.

SMB (F83H)

SMB 2 SMB 1

SRB (F82H)

SRB 1

SB

Register

SMB 3

SMB 0

0

SRB 0

Figure 3-2. SMB and SRB Values in the SB Register

SELECT REGISTER BANK (SRB) INSTRUCTION

The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The

SRB value is set by the “SRB n” instruction, where n = 0, 1, 2, 3.

One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set

using the “SRB n” instruction. The current SRB value is retained until another register is requested by program

software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts

and subroutine calls. RESET clears the 4-bit SRB value to logic zero.

SELECT MEMORY BANK (SMB) INSTRUCTION

To select one of the three available data memory banks, you must execute an SMB n instruction specifying the

number of the memory bank you want (0, 1, or 15). For example, the instruction “SMB 1” selects bank 1 and

“SMB 15” selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB

flag setting.

The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not

specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB

value to logic zero.

The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack

area during interrupts and subroutine calls.

BANK1 PAGE SELECTION REGISTER (PASR)

PASR is an 8-bit register for selecting a page in bank1, and is mapped to the RAM address, F8AH–F8BH.

It should be read or written by an 8-bit RAM control instruction only and the MSB 3 bits should be “0”. PASR

retains the existing value as long as any change is not required, and the RESET value is 0. Therefore, when it

returns to bank1 from other bank (bank0 or bank15) without changing the contents of PASR, the previously

specified page is selected. PASR must not be changed in the interrupt service routine because its value cannot

be recovered as the original value when the routine is finished.

3-5

ADDRESSING MODES

S3C7565/P7565

DIRECT AND INDIRECT ADDRESSING

1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or

bit address as the instruction operand.

Indirect addressing specifies a memory location that contains the required direct address. The S3C7 instruction

set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM

address must always be used as the instruction operand.

1-BIT ADDRESSING

Table 3-2. 1-Bit Direct and Indirect RAM Addressing

Operand

Notation

Addressing Mode

Description

EMB Flag Addressable

Memory

Bank

Hardware I/O

Mapping

Setting

Area

DA.b

Direct: bit is indicated by the

0

000H–07FH

F80H–FFFH

Bank 0

–

RAM address (DA), memory

bank selection, and specified

bit number (b).

Bank 15

All 1-bit

addressable

peripherals

(SMB = 15)

1

x

000H–FFFH SMB = 0, 1, 15

mema.b

Direct: bit is indicated by

addressable area (mema) and

bit number (b).

FB0H–FBFH

FF0H–FFFH

Bank 15

IS0, IS1,

EMB, ERB,

IEx, IRQx,

Pn.m

memb.@L

Indirect: lower two bits of

register L as indicated by the

upper 10 bits of RAM area

(memb) and the upper two

bits of register L.

x

FC0H–FFFH

000H–0FFH

Bank 15

BSCn.x

Pn.m

@H + DA.b

Indirect: bit indicated by the

lower four bits of the address

(DA), memory bank selection,

and the H register identifier.

0

1

Bank 0

–

000H–FFFH SMB = 0, 1, 15 All 1-bit

addressable

peripherals

(SMB = 15)

NOTE: “x” means don't care.

3-6

S3C7565/P7565

ADDRESSING MODES

+

PROGRAMMING TIP — 1-Bit Addressing Modes

1-Bit Direct Addressing

1. If EMB = "0":

AFLAG EQU

BFLAG EQU

CFLAG EQU

SMB

34H.3

85H.3

0BAH.0

0

BITS

BTST

BITS

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

; 34H.3 ¬

; F85H.3 ¬

; If FBAH.0 = 1, skip

; Else if, FBAH.0 = 0, F85H.3 (BMOD.3) ¬

; FF3H.0 (P3.0) ¬

1

BITS

1

2. If EMB = "1":

AFLAG EQU

BFLAG EQU

CFLAG EQU

SMB

34H.3

85H.3

0BAH.0

0

BITS

BTST

BITS

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

; 34H.3 ¬

; 85H.3 ¬

; If 0BAH.0 = 1, skip

; Else if 0BAH.0 = 0, 085H.3 ¬

; FF3H.0 (P3.0) ¬

1

BITS

1

3-7

ADDRESSING MODES

S3C7565/P7565

+

PROGRAMMING TIP — 1-Bit Addressing Modes (Continued)

1-Bit Indirect Addressing

1. If EMB = "0":

AFLAG EQU

BFLAG EQU

CFLAG EQU

SMB

34H.3

85H.3

0BAH.0

0

LD

BTSTZ

BITS

H,#0BH

@H+CFLAG

CFLAG

; H ¬ #0BH

; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

; Else if 0BAH.0 = 0, FBAH.0 ¬

1

2. If EMB = "1":

AFLAG EQU

BFLAG EQU

CFLAG EQU

SMB

34H.3

85H.3

0BAH.0

0

LD

BTSTZ

BITS

H,#0BH

@H+CFLAG

CFLAG

; H ¬ #0BH

; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

; Else if 0BAH.0 = 0, 0BAH.0 ¬

1

3-8

S3C7565/P7565

ADDRESSING MODES

4-BIT ADDRESSING

Table 3-3. 4-Bit Direct and Indirect RAM Addressing

Addressing Mode EMB Flag Addressable Memory

Operand

Notation

Hardware I/O

Mapping

Description

Setting

Area

Bank

Bank 0

Bank 15

0

DA

Direct: 4-bit address indicated

000H–07FH

F80H–FFFH

–

by the RAM address (DA) and

the memory bank selection

All 4-bit

addressable

peripherals

1

0

000H–FFFH

000H–0FFH

SMB = 0, 1,

15

(SMB = 15)

Bank 0

–

@HL

Indirect: 4-bit address indicated

by the memory bank selection

and register HL

1

000H–FFFH SMB = 0, 1,15

All 4-bit

addressable

peripherals

(SMB = 15)

x

000H–0FFH

Bank 0

–

@WX

@WL

Indirect: 4-bit address indicated

by register WX

Indirect: 4-bit address indicated

by register WL

NOTE: “x” means don't care.

+

PROGRAMMING TIP — 4-Bit Addressing Modes

4-Bit Direct Addressing

1. If EMB = "0":

ADATA EQU

46H

BDATA EQU

8EH

SMB

LD

SMB

LD

15

A,P3

0

ADATA,A

BDATA,A

; Non-essential instruction, since EMB = "0"

; A ¬ (P3)

; Non-essential instruction, since EMB = "0"

; (046H) ¬

A

LD

; (F8EH (LCON)) ¬

A

2. If EMB = "1":

ADATA EQU

46H

BDATA EQU

8EH

SMB

LD

SMB

LD

15

A,P3

0

ADATA,A

BDATA,A

; A ¬ (P3)

; (046H) ¬

; (08EH) ¬

A

LD

3-9

ADDRESSING MODES

S3C7565/P7565

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Continued)

4-Bit Indirect Addressing (Example 1)

1. If EMB = "0", compare bank 0 locations 040H–046H with bank 0 locations 060H–066H:

ADATA EQU

BDATA EQU

SMB

46H

66H

1

; Non-essential instruction, since EMB = "0"

LD

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

COMP LD

CPSE

; A ¬ bank 0 (040H–046H)

; If bank 0 (060H–066H) = A, skip

SRET

DECS

L

JR

COMP

RET

2. If EMB = "1", compare bank 0 locations 040H–046H to bank 1 locations 160H–166H:

ADATA EQU

BDATA EQU

SMB

46H

66H

1

LD

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

COMP LD

CPSE

; A ¬ bank 0 (040H–046H)

; If bank 1 (160H–166H) = A, skip

SRET

DECS

L

JR

COMP

RET

3-10

S3C7565/P7565

ADDRESSING MODES

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Concluded)

4-Bit Indirect Addressing (Example 2)

1. If EMB = "0", exchange bank 0 locations 040H–046H with bank 0 locations 060H–066H:

ADATA EQU

BDATA EQU

SMB

46H

66H

1

; Non-essential instruction, since EMB = "0"

LD

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

TRANS LD

XCHD

; A ¬ bank 0 (040H–046H)

; Bank 0 (060H–066H) «

A

JR

2. If EMB = "1", exchange bank 0 locations 040H–046H to bank 1 locations 160H–166H:

ADATA EQU

BDATA EQU

SMB

46H

66H

1

LD

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

TRANS LD

XCHD

; A ¬ bank 0 (040H–046H)

; Bank 1 (160H–166H) «

A

JR

3-11

ADDRESSING MODES

8-BIT ADDRESSING

S3C7565/P7565

Table 3-4. 8-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA

Direct: 8-bit address indicated

0

000H–07FH

F80H–FFFH

Bank 0

–

by the RAM address (DA =

even number) and memory

bank selection

Bank 15

All 8-bit

addressable

peripherals

1

0

000H–FFFH

000H–0FFH

SMB = 0,

1,15

(SMB = 15)

@HL

Indirect: the 8-bit address indi-

cated by the memory bank

selection and register HL; (the

4-bit L register value must be

an even number)

Bank 0

–

1

000H–FFFH

SMB = 0,

1,15

All 8-bit

addressable

peripherals

(SMB = 15)

+

PROGRAMMING TIP — 8-Bit Addressing Modes

8-Bit Direct Addressing

1. If EMB = "0":

ADATA EQU

46H

BDATA EQU

8EH

SMB

LD

SMB

LD

15

EA,P4

0

ADATA,EA

BDATA,EA

; Non-essential instruction, since EMB = "0"

; E ¬ (P5), A ¬ (P4)

; (046H) ¬ A, (047H) ¬

; (F8EH) ¬ A, (F8FH) ¬

E

LD

2. If EMB = "1":

ADATA EQU

46H

BDATA EQU

8EH

SMB

LD

SMB

LD

15

EA,P4

0

ADATA,EA

BDATA,EA

; E ¬ (P5), A ¬ (P4)

; (046H) ¬ A, (047H) ¬

; (08EH) ¬ A, (08FH) ¬

E

LD

3-12

S3C7565/P7565

ADDRESSING MODES

+

PROGRAMMING TIP — 8-Bit Addressing Modes (Continued)

8-Bit Indirect Addressing

1. If EMB = "0":

ADATA EQU

46H

SMB

LD

1

; Non-essential instruction, since EMB = "0"

; A ¬ (046H), E ¬ (047H)

HL,#ADATA

EA,@HL

2. If EMB = "1":

ADATA EQU

46H

SMB

LD

1

HL,#ADATA

EA,@HL

; A ¬ (146H), E ¬ (147H)

3-13

ADDRESSING MODES

S3C7565/P7565

NOTES

3-14

S3C7565/P7565

MEMORY MAP

4

MEMORY MAP

OVERVIEW

To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank

15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the

specific memory location.

Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank

flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the

current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless

of the current EMB value.

I/O MAP FOR HARDWARE REGISTERS

Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations

F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map

gives you the following information:

— Register address

— Register name (mnemonic for program addressing)

— Bit values (both addressable and non-manipulable)

— Read-only, write-only, or read and write addressability

— 1-bit, 4-bit, or 8-bit data manipulation characteristics

4-1

MEMORY MAP

S3C7565/P7565

Table 4-1. I/O Map for Memory Bank 15

Memory Bank 15

Register Bit 3

Addressing Mode

1-Bit 4-Bit 8-Bit

Address

F80H

Bit 2

Bit 1

Bit 0

R/W

SP

R/W

No

Yes

F81H

Locations F84H–F82H are not mapped

F85H

F86H

F87H

F88H

F89H

F8AH

F8BH

F8CH

F8DH

F8EH

F8FH

F90H

F91H

F92H

BMOD

BCNT

W

R

.3

Yes

No

Yes

.3 ⁽¹⁾

No

.3

WMOD

PASR

.3

.7

.2

“0”

.2

.1

.5

.0

W

R/W

W

No

Yes

No

Yes

No

Yes

No

.4

.3

.1

.0

“0”

.3

“0”

.2

“0”

.1

.4

LMOD

LCON

.0

.7

.6

.5

.4

.3

.2

.1

.0

.4

W

.7

“0”

.2

.5

TMOD0

.3

“0”

.5

“0”

W

“0”

TOE1

.6

.4

TOL2 ⁽²⁾

TOE0

“0”

R/W

R

Yes

No

.3

Location F93H is not mapped

F94H

F95H

F96H

F97H

F98H

F99H

F9AH

TCNT0

TREF0

Timer/Counter 0 Counter Register

Yes

No

Timer/Counter 0 Reference Register

Watchdog timer mode Register

W

WDMOD

W

WDFLAG ⁽³⁾

TMOD1A

TMOD1B

TCNT1A

WDTCF

“0”

W

Locations F9FH–F9BH are not mapped

FA0H

FA1H

FA2H

FA3H

FA4H

FA5H

FA6H

FA7H

.3

.7

.2

.6

.2

.6

“0”

.5

“0”

.4

W

.3

Yes

.3

“0”

.5

“0”

.4

W

.3

“0”

Timer/Counter 1A Counter Register

R

No

TCNT1B

Timer/Counter 1B Counter Register

4-2

S3C7565/P7565

MEMORY MAP

Table 4-1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Addressing Mode

1-Bit 4-Bit 8-Bit

Address

FA8H

Register

Bit 3

Bit 2

Bit 1

Bit 0

R/W

TREF1A

Timer/Counter 1 Reference Register A

W

No

Yes

FA9H

FAAH

FABH

FACH

FADH

TREF1B

DTMR

Timer/Counter 1 Reference Register B

“0”

.7

.2

.6

.1

.5

.0

.4

W

No

Yes

Locations FAFH–FAEH are not mapped

FB0H

FB1H

FB2H

FB3H

FB4H

FB5H

FB6H

FB7H

FB8H

PSW

IS1

IS0

SC2

.2

EMB

SC1

.1

ERB

SC0

.0

R/W

R

Yes

No

Yes

No

C ⁽⁴⁾

IME

IPR

W

IME

No

Yes

No

PCON

IMOD0

IMOD1

IMODK

SCMOD

Power Control Register

W

“0”

.3

“0”

.1

“0”

.1

.0

W

No

W

No

.2

.0

W

No

.2

“0”

IEB

.0

W

Yes

IE4

IRQ4

IRQB

R/W

Yes

Location FB9H is not mapped

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

FC0H

FC1H

FC2H

FC3H

“0”

IEK

IET2

“0”

IRQK

IRQT2

“0”

IEW

IET1

IET0

IES

IRQW

IRQT1

IRQT0

IRQS

IRQ0

R/W

Yes

No

IE1

“0”

IRQ1

“0”

IE0

IE2

IRQ2

BSC0

BSC1

BSC2

BSC3

R/W

Yes

Locations FCDH–FC4H are not mapped

FCEH

FD0H

P7MOD

CLMOD

.3

.2

Location FCFH is not mapped

“0” .1

Location FD1H is not mapped

.1

.0

W

No

Yes

No

.3

.0

4-3

MEMORY MAP

S3C7565/P7565

Table 4-1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Addressing Mode

1-Bit 4-Bit 8-Bit

Address

FD2H

Register

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

.0

R/W

CMOD

R/W

No

Yes

No

Yes

FD3H

.7

.6

.5

“0”

FD4H

CMPREG

PNE1

R

No

Location FD5H is not mapped

FD6H

FD7H

FD8H

FD9H

FDAH

.3

“0”

.3

.2

.6

.1

.5

.0

.4

W

Yes

PNE2

VLC1R

IMOD2

.2

.1

.0

W

R/W

W

No

Yes

No

Yes

No

“0”

VLC1F

.0

Location FDBH is not mapped

FDCH

FDDH

FDEH

PUMOD1

PUMOD2

SMOD

PUR3

PUR7

“0”

PUR2

PUR6

PUR1

PUR5

PUR9

PUR0

PUR4

PUR8

W

No

.3

No

Yes

No

Yes

No

PUR10

Location FDFH is not mapped

FE0H

FE1H

.3

.7

.2

.6

.1

.5

.0

Yes

“0”

Locations FE3H–FE2H are not mapped

FE4H

FE5H

FE6H

FE7H

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

FF0H

FF1H

FF2H

FF3H

SBUF

PMG1

PMG2

PMG3

PMG4

PMG5

R/W

W

No

Yes

No

Yes

No

PM0.3

“0”

PM0.2

PM2.2

PM3.2

PM0.1

PM2.1

PM3.1

PM0.0

PM2.0

PM3.0

PM3.3

W

PM10.3 PM10.2 PM10.1 PM10.0

PM4.3

PM5.3

PM6.3

PM7.3

PM8.3

PM9.3

.3

PM4.2

PM5.2

PM6.2

PM7.2

PM8.2

PM9.2

.2

PM4.1

PM5.1

PM6.1

PM7.1

PM8.1

PM9.1

.1

PM4.0

PM5.0

PM6.0

PM7.0

PM8.0

PM9.0

.0

W

P0

P1

P2

P3

RW

R

.3

.2

.1

.0

“0”

.2

.1

.0

R/W

.3

.2

.1

.0

4-4

S3C7565/P7565

MEMORY MAP

Table 4-1. I/O Map for Memory Bank 15 (Concluded)

Memory Bank 15

Addressing Mode

1-Bit 4-Bit 8-Bit

Address

FF4H

FF5H

FF6H

FF7H

FF8H

FF9H

FFAH

Register

P4

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

.0

R/W

Yes

No

P5

.3/.7

.3

.2/.6

.2

.1/.5

.1

.0/.4

.0

P6

R/W

P7

.3/.7

.3

.2/.6

.2

.1/.5

.1

.0/.4

.0

R/W ⁽⁵⁾

R/W

P8

P9

.3/.7

.3

.2/.6

.2

.1/.5

.1

.0/.4

.0

P10

Locations FFFH–FFBH are not mapped

NOTES:

1. Bit 3 in the WMOD register is read-only.

2. TOL2 flag is read-only.

3. F9AH.0,F9AH.1, and F9AH.2 are fixed to “0”.

4. The carry flag can be read or written by specific bit manipulation instructions only.

5. P8.0-P8.1 can not be used as push-pull output.

REGISTER DESCRIPTIONS

In this section, register descriptions are presented in a consistent format to familiarize you with the

memory-mapped I/O locations in bank 15 of the RAM. Figure 4-1 describes features of the register description

format. Register descriptions are arranged in alphabetical order. Programmers can use this section as a

quick-reference source when writing application programs.

Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are

not included in these descriptions. More detailed information about how these registers are used is included in

Part II of this manual, "Hardware Descriptions", in the context of the corresponding peripheral hardware module

descriptions.

4-5

MEMORY MAP

S3C7565/P7565

Register and bit IDs

used for bit addressing

Name of individual

bit or related bits

Associated

Register location

Register ID

Register name

hardware module

in RAM bank 15

CLMOD - Clock Output Mode Control Register

CPU

FD0H

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

CLMOD1.3

Enable/Disable Clock Output Control bit

Disable clock output (CLO1, CLO2)

Enable clock output (CLO1, CLO2)

0

CLMOD1.2

Bit 2

Always logic

0

CLMOD1.1-.0

Clock Source and Frequency Selection Control Bits

Select CPU clock souce

0

1

0

1

0

1

Select main system clock fx/8 (524 kHz at 4.19 MHz)

Select main system clock fx/16 (262 kHz at 4.19 MHz)

Select main system clock fx/64 (65.5 kHz at 4.19 MHz)

R = Read-only

W = Write-only

R/W = Read/write

Bit value immediately

following a RESET

Bit number in

MSB to LSB order

Type of addressing

that must be used to

address the bit

Description of the

effect of specific

bit settings

Bit identifier used

for bit addressing

(1-bit, 4-bit, or 8-bit)

Figure 4-1. Register Description Format

4-6

S3C7565/P7565

MEMORY MAP

BMOD— Basic Timer Mode Register

BT

F85H

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

1/4

Bit Addressing

BMOD.3

Basic Timer Restart Bit

Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero

1

BMOD.2–.0

Input Clock Frequency and Signal Stabilization Interval Control Bits

fxx/2¹²(1.02 kHz)

2²⁰/fxx (250 ms)

0

1

0

1

0

1

0

1

Input clock frequency:

Interrupt interval time:

fxx/2⁹(8.18 kHz)

2¹⁷/fxx (31.3 ms)

Input clock frequency:

Interrupt interval time:

fxx/2⁷(32.7 kHz)

2¹⁵/fxx (7.82 ms)

Input clock frequency:

Interrupt interval time:

fxx/2⁵(131 kHz)

2¹³/fxx (1.95 ms)

Input clock frequency:

Interrupt interval time:

NOTES:

1. Interrupt interval time is the time required to set the IRQB to "1" periodically.

2. When a RESET occurs, the oscillation stabilization time is 31.3 ms (217/fxx) at 4.19 MHz.

3. "fxx" is the system clock rate given a clock frequency of 4.19 MHz.

4-7

MEMORY MAP

S3C7565/P7565

CLMOD — Clock Output Mode 1 Register

CPU

FD0H

3

.3

0

2

"0"

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

CLMOD.3

Enable/Disable Clock Output Control Bit

0

1

Disable clock output

Enable clock output

CLMOD.2

Bit 2

0

Always logic zero

CLMOD.1–.0

Clock Source and Frequency Selection Control Bits

0

Select CPU clock source fxx/4, fxx/8, or fxx/64 (1.05 MHz, 524 kHz, or

65.5 kHz)

0

1

0

1

Select system clock fxx/8 (524 kHz)

Select system clock fxx/16 (262 kHz)

Select system clock fxx/64 (65.5 kHz)

NOTE: "fxx" is the system clock, given a clock frequency of 4.19 MHz.

4-8

S3C7565/P7565

MEMORY MAP

CMOD— Comparator Mode Register

COMPARATOR

FD3H,FD2H

7

.7

0

6

.6

0

5

.5

0

4

“0”

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

Bit Addressing

.7

.6

Comparator Enable/Disable Bit

0

1

Comparator operation disable

Comparator operation enable

Conversion Timer Control Bit

8 x 2⁷/fx, 244.4 ms at 4.19 MHz

8 x 2⁴/fx, 30.5 ms at 4.19 MHz

0

1

.5

External/Internal Reference Selection Bit

0

1

Internal reference, CIN0–3; analog input

External reference at CIN3, CIN0–2; analog input

.4

Bit 4

0

Always logic zero

.3–.0

Reference Voltage Selection Bits

(N+0.5)

Selected V_REF= V_DD

´

, N = 0 to 15

16

4-9

MEMORY MAP

S3C7565/P7565

DTMR — DTMF Mode Register

DTMF

FADH,FACH

7

.7

0

6

.6

0

5

.5

0

4

.4

0

3

2

.2

0

1

0

.0

0

Bit

Identifier

“0”

.1

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

DTMR.7–.4

DTMR Bit Values for Keyboard Inputs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Function key D

1

2

3

4

5

6

7

8

9

0

*

#

1

0

1

0

1

Function key A

Function key B

Function key C

DTMR.3

Bit 3

0

Always logic zero

DTMR.2–.1

Tone Selection Bits

0

1

0

1

0

1

Dual-tone enable

Dual-tone enable (alternate setting)

Single-column tone enable

Single-low tone enable

DTMR.0

DTMF Operation Enable/Disable Bit

0

1

Disable DTMF operation

Enable DTMF operation

4-10

S3C7565/P7565

MEMORY MAP

IE0, 1, IRQ0, 1— INT0, 1 Interrupt Enable/Request Flags

CPU

FBEH

3

IE1

0

2

IRQ1

0

1

IE0

0

IRQ0

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IE1

INT1 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT1 pin

Enable interrupt requests at the INT1 pin

IRQ1

IE0

INT1 Interrupt Request Flag

–

Generate INT1 interrupt (This bit is set and cleared by hardware when rising or

falling edge detected at INT1 pin.)

INT0 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT0 pin

Enable interrupt requests at the INT0 pin

IRQ0

INT0 Interrupt Request Flag

–

Generate INT0 interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at INT0 pin.)

4-11

MEMORY MAP

S3C7565/P7565

IE2, IRQ2— INT2 Interrupt Enable/Request Flags

CPU

FBFH

3

"0"

0

2

"0"

0

1

IE2

0

IRQ2

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3–.2

IE2

Bits 3–2

0

Always logic zero

INT2 Interrupt Enable Flag

0

1

Disable INT2 interrupt requests at the INT2 pin

Enable INT2 interrupt requests at the INT2 pin

IRQ2

INT2 Interrupt Request Flag

–

Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically

by hardware when a rising or falling edge is detected at INT2. Since INT2 is a

quasi-interrupt, IRQ2 flag must be cleared by software.)

4-12

S3C7565/P7565

MEMORY MAP

IE4, IRQ4— INT4 Interrupt Enable/Request Flags

IEB, IRQB— INTB Interrupt Enable/Request Flags

CPU

FB8H

3

IE4

0

2

IRQ4

0

1

IEB

0

IRQB

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IE4

INT4 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT4 pin

Enable interrupt requests at the INT4 pin

IRQ4

IEB

INT4 Interrupt Request Flag

–

Generate INT4 interrupt (This bit is set and cleared automatically by hardware

when rising and falling signal edge detected at INT4 pin.)

INTB Interrupt Enable Flag

0

1

Disable INTB interrupt requests

Enable INTB interrupt requests

IRQB

INTB Interrupt Request Flag

–

Generate INTB interrupt (This bit is set and cleared automatically by hardware

when reference interval signal received from basic timer.)

4-13

MEMORY MAP

S3C7565/P7565

IES, IRQS— INTS Interrupt Enable/Request Flags

CPU

FBDH

3

"0"

0

2

"0"

0

1

IES

0

IRQS

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3–.2

IES

Bits 3–2

0

Always logic zero

INTS Interrupt Enable Flag

0

1

Disable INTS interrupt requests

Enable INTS interrupt requests

IRQS

INTS Interrupt Request Flag

–

Generate INTS interrupt (This bit is set and cleared automatically by hardware

when serial data transfer completion signal received from serial I/O interface.)

4-14

S3C7565/P7565

MEMORY MAP

IET0, IRQT0— INTT0 Interrupt Enable/Request Flags

IET2, IRQT2 — INTT1B Interrupt Enable/Request Flags

CPU

FBCH

3

IET2

0

2

IRQT2

0

1

IET0

0

IRQT0

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IET2

INTT1B Interrupt Enable Flag

0

1

Disable INTT1B interrupt requests

Enable INTT1B interrupt requests

IRQT2

IET0

INTT1B Interrupt Request Flag

–

Generate INTT1B interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT1B and TREF1B registers match.)

INTT0 Interrupt Enable Flag

0

1

Disable INTT0 interrupt requests

Enable INTT0 interrupt requests

IRQT0

INTT0 Interrupt Request Flag

–

Generate INTT0 interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT0 and TREF0 registers match.)

4-15

MEMORY MAP

S3C7565/P7565

IET1, IRQT1— INTT1A Interrupt Enable/Request Flags

IEK, IRQK— INTK Interrupt Enable/Request Flags

CPU

FBBH

3

IEK

0

2

IRQK

0

1

IET1

0

IRQT1

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IEK

INTK Interrupt Enable Flag

0

1

Disable interrupt requests at the K0–K7 pins

Enable interrupt requests at the K0–K7 pins

IRQK

IET1

INTK Interrupt Request Flag

–

Generate INTK interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at K0–K7 pins.)

INTT1/INTT1A Interrupt Enable Flag

0

1

Disable INTT1/INTT1A interrupt requests

Enable INTT1/INTT1A interrupt requests

IRQT1

INTT1/INTT1A Interrupt Request Flag

–

Generate INTT1/INTT1A interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT1/TCNT1A and TREF1/TREF1A registers

match.)

4-16

S3C7565/P7565

MEMORY MAP

IEW, IRQW— INTW Interrupt Enable/Request Flags

CPU

FBAH

3

"0"

0

2

"0"

0

1

IEW

0

IRQW

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3–.2

IEW

Bits 3–2

0

Always logic zero

INTW Interrupt Enable Flag

0

1

Disable INTW interrupt requests

Enable INTW interrupt requests

IRQW

INTW Interrupt Request Flag

–

Generate INTW interrupt (This bit is set when the timer interval is set to 0.5 s

or 3.91 ms.)

NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.

4-17

MEMORY MAP

S3C7565/P7565

IMOD0— External Interrupt 0 (INT0) Mode Register

CPU

FB4H

3

"0"

0

2

"0"

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD0.3–.2

IMOD0.1–.0

Bits 3–2

0

Always logic zero

External Interrupt Mode Control Bits

0

1

0

1

0

1

Interrupt requests are triggered by a rising signal edge

Interrupt requests are triggered by a falling signal edge

Interrupt requests are triggered by both rising and falling signal edges

Interrupt request flag (IRQx) cannot be set to logic one

4-18

S3C7565/P7565

MEMORY MAP

IMOD1— External Interrupt 1 (INT1) Mode Register

CPU

FB5H

3

"0"

0

2

"0"

0

1

"0"

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD1.3–.1

IMOD1.0

Bits 3–1

0

Always logic zero

External Interrupt 1 Edge Detection Control Bit

0

1

Rising edge detection

Falling edge detection

4-19

MEMORY MAP

S3C7565/P7565

IMOD2— External Interrupt 2 (INT2) Mode Register

CPU

FDAH

3

"0"

0

2

"0"

0

1

"0"

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD2.3–.1

IMOD2.0

Bits 3–1

0

Always logic zero

External Interrupt 2 Edge Detection Selection Bit

0

1

Interrupt request at INT2 pin trigged by rising edge

Interrupt request at INT2 pin trigged by falling edge

4-20

S3C7565/P7565

MEMORY MAP

IMODK— External Key Interrupt Mode Register

CPU

FB6H

3

"0"

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMODK.3

IMODK.2

Bit 3

0

Always logic zero

External Key Interrupt Edge Detection Selection Bit

0

1

Falling edge detection

Rising edge detection

IMODK.1–.0

External Key Interrupt Mode Control Bits

0

1

0

1

0

1

Disable key interrupt

Enable edge detection at K0–K3 pins

Enable edge detection at K4–K7 pins

Enable edge detection at K0–K7 pins

NOTES:

1. To generate a key interrupt, the selected pins must be configured to input mode.

2. If any one of key interrupt pins selected by IMODK register is configured as output mode, only falling edge can be

detected.

3. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge

detection and pins by setting IMODK register.

4-21

MEMORY MAP

S3C7565/P7565

IPR— Interrupt Priority Register

CPU

FB2H

3

IME

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

1/4

Bit Addressing

IME

Interrupt Master Enable Bit

0

1

Disable all interrupt processing

Enable processing for all interrupt service requests

IPR.2–.0

Interrupt Priority Assignment Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Process all interrupt requests at low priority

Process INTB and INT4 interrupts only

Process INT0 interrupts only

Process INT1 interrupts only

Process INTS interrupts only

Process INTT0 and INTT1B interrupts only

Process INTT1 (INTT1A) interrupts only

Process INTK interrupts only

4-22

S3C7565/P7565

MEMORY MAP

LCON— LCD Output Control Register

LCD

F8FH,F8EH

7

.7

0

6

“0”

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

LCON.7

TR2 Control Bit

0

1

TR2 off

TR2 on

LCON.6

LCON.5

Bit 6

0

Always logic zero

LCDCK and LCDSY Disable/Enable

0

1

Disable LCDCK and LCDSY signal output

Enable LCDCK and LCDSY signal output

LCON.4

Watch Timer (fw) Clock Selection Bit

0

1

f_LCD= 4,096 Hz when fw = fx/128 (32.768 kHz @fx = 4.19 MHz)

f_LCD= 8,192 Hz when fw = fx/64 (65.563 kHz @fx = 4.19 MHz)

LCD Clock Frequency Selection Bits

LCON.3–.2

when 1/8 duty: fw / 2⁷(256 Hz); when 1/12 duty: fw / 2⁶(512 Hz);

0

1

0

1

0

1

when 1/16 duty: fw / 2⁶(512 Hz)

when 1/8 duty: fw / 2⁶(512 Hz); when 1/12 duty: fw / 2⁵(1024 Hz);

when 1/16 duty: fw / 2⁵(1024 Hz)

when 1/8 duty: fw / 2⁵(1024 Hz); when 1/12 duty: fw / 2⁴(2048 Hz);

when 1/16 duty: fw / 2⁴(2048 Hz)

when 1/8 duty: fw / 2⁴(2048 Hz); when 1/12 duty: fw / 2³(4096 Hz);

when 1/16 duty: fw / 2³(4096 Hz)

LCON.1

LCON.0

LCD Dividing Resistors Control Bit

0

1

Normal LCD dividing resistors

Diminish a LCD dividing resistor to strengthen LCD drive

TR1 Control Bit

0

1

TR1 off

TR1 on

4-23

MEMORY MAP

S3C7565/P7565

LMOD— LCD Mode Register

LCD

F8DH,F8CH

7

.7

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

LMOD.7–.5

LCD Output Segment and Pin Configuration Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

Segments 40–43, 44–47, 48–51, 52–55, and 56–59

Segments 40–43, 44–47, 48–51, and 52–55; normal I/O at port 6

Segments 40–43, 44–47, and 48–51; normal I/O at port 6 and port 7

Segments 40–43 and 44–47; normal I/O at port 6, 7, and 8

Segments 40–43; Normal I/O at ports 6, 7, 8, and 9

Normal I/O at ports 6, 7, 8, 9, and 10

Segments 40–43, 44–47, 48–51, and 56–59; normal I/O at port 7

NOTE: Segment pins that can be used for normal I/O should be configured to output mode

for the SEG function.

LMOD.4

LCD Bias Selection Bit

0

1

1/4 Bias

1/5 Bias

LMOD.3–.2

LCD Duty and Selection Bits

0

1

0

1

0

When 1/8 duty (COM0–COM7 select)

When 1/12 duty (COM0–COM11 select)

When 1/16 duty (COM0–COM15 select)

NOTE: When 1/16 duty is selected, ports 4 and 5 should be configured as output mode;

when 1/8 duty is selected, ports 4 and 5 can be used as normal I/O ports.

LMOD.1–.0

LCD Display Mode Selection Bits

0

1

0

1

All LCD dots off

All LCD dots on

Normal display

4-24

S3C7565/P7565

MEMORY MAP

P7MOD— Port 7 Mode Register

I/O

FCEH

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

P7MOD.3

P7MOD.2

P7MOD.1

P7MOD.0

P7.3 Analog/Digital Selection Bit

0

1

Configure P7.3 as an digital input pin

Configure P7.3 as an analog input pin

P7.2 Analog/Digital Selection Bit

0

1

Configure P7.2 as an digital input pin

Configure P7.2 as an analog input pin

P7.1 Analog/Digital Selection Bit

0

1

Configure P7.1 as an digital input pin

Configure P7.1 as an analog input pin

P7.0 Analog/Digital Selection Bit

0

1

Configure P7.0 as an digital input pin

Configure P7.0 as an analog input pin

4-25

MEMORY MAP

S3C7565/P7565

PASR — Page Selection Register

F8BH, F8AH

7

"0"

0

6

"0"

0

5

"0"

0

4

.4

0

3

.3

0

2

.2

0

1

0

.0

0

Bit

Identifier

.1

0

RESET Value

Read/Write

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

R/W

8

Bit Addressing

.7–.5

.4–.0

Bits 7–4

0

Always logic zero

Page Selection Register in the Bank1

0

1

00H page in the Bank1

01H page in the Bank1

¢¢

• • •

1

0

1

13H page for LCD display register in the Bank1

NOTE: The 00H–13H pages can be used in the S3C7565.

4-26

S3C7565/P7565

MEMORY MAP

PCON— Power Control Register

CPU

FB3H

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

PCON.3–.2

CPU Operating Mode Control Bits

0

1

0

1

0

Enable normal CPU operating mode

Initiate idle power-down mode

Initiate stop power-down mode

PCON.1–.0

CPU Clock Frequency Selection Bits

0

1

0

1

If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4

If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4

If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4

NOTE: “fx” is the main system clock; “fxt” is the subsystem clock.

4-27

MEMORY MAP

S3C7565/P7565

PMG1 — Port I/O Mode Flags (Group 1: Ports 0, 2)

I/O

FE7H, FE6H

7

“0”

0

6

PM2.2

0

5

PM2.1

0

4

PM2.0

0

3

PM0.3

0

2

1

0

Bit

Identifier

PM0.2

PM0.1

PM0.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7

Bit 7

0

Always logic zero

PM2.2

P2.2 I/O Mode Selection Flag

0

1

Set P2.2 to input mode

Set P2.2 to output mode

PM2.1

PM2.0

P2.1 I/O Mode Selection Flag

0

1

Set P2.1 to input mode

Set P2.1 to output mode

P2.0 I/O Mode Selection Flag

0

1

Set P2.0 to input mode

Set P2.0 to output mode

PM0.3

P0.3 I/O Mode Selection Flag

0

1

Set P0.3 to input mode

Set P0.3 to output mode

PM0.2

PM0.1

PM0.0

P0.2 I/O Mode Selection Flag

0

1

Set P0.2 to input mode

Set P0.2 to output mode

P0.1 I/O Mode Selection Flag

0

1

Set P0.1 to input mode

Set P0.1 to output mode

P0.0 I/O Mode Selection Flag

0

1

Set P0.0 to input mode

Set P0.0 to output mode

4-28

S3C7565/P7565

MEMORY MAP

PMG2 — Port I/O Mode Flags (Group 2: Ports 3, 10)

I/O

FE9H, FE8H

7

6

5

4

3

PM3.3

0

2

1

0

Bit

Identifier

PM10.3 PM10.2 PM10.1 PM10.0

PM3.2

PM3.1

PM3.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PM10.3

PM10.2

PM10.1

PM10.0

PM3.3

PM3.2

PM3.1

PM3.0

P10.3 I/O Mode Selection Flag

0

1

Set P10.3 to input mode

Set P10.3 to output mode

P10.2 I/O Mode Selection Flag

0

1

Set P10.2 to input mode

Set P10.2 to output mode

P10.1 I/O Mode Selection Flag

0

1

Set P10.1 to input mode

Set P10.1 to output mode

P10.0 I/O Mode Selection Flag

0

1

Set P10.0 to input mode

Set P10.0 to output mode

P3.3 I/O Mode Selection Flag

0

1

Set P3.3 to input mode

Set P3.3 to output mode

P3.2 I/O Mode Selection Flag

0

1

Set P3.2 to input mode

Set P3.2 to output mode

P3.1 I/O Mode Selection Flag

0

1

Set P3.1 to input mode

Set P3.1 to output mode

P3.0 I/O Mode Selection Flag

0

1

Set P3.0 to input mode

Set P3.0 to output mode

4-29

MEMORY MAP

S3C7565/P7565

PMG3 — Port I/O Mode Flags (Group 3: Ports 4, 5)

I/O

FEBH, FEAH

7

PM5.3

0

6

PM5.2

0

5

PM5.1

0

4

PM5.0

0

3

PM4.3

0

2

1

0

Bit

Identifier

PM4.2

PM4.1

PM4.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PM5.3

P5.3 I/O Mode Selection Flag

0

1

Set P5.3 to input mode

Set P5.3 to output mode

PM5.2

PM5.1

PM5.0

PM4.3

PM4.2

PM4.1

PM4.0

P5.2 I/O Mode Selection Flag

0

1

Set P5.2 to input mode

Set P5.2 to output mode

P5.1 I/O Mode Selection Flag

0

1

Set P5.1 to input mode

Set P5.1 to output mode

P5.0 I/O Mode Selection Flag

0

1

Set P5.0 to input mode

Set P5.0 to output mode

P4.3 I/O Mode Selection Flag

0

1

Set P4.3 to input mode

Set P4.3 to output mode

P4.2 I/O Mode Selection Flag

0

1

Set P4.2 to input mode

Set P4.2 to output mode

P4.1 I/O Mode Selection Flag

0

1

Set P4.1 to input mode

Set P4.1 to output mode

P4.0 I/O Mode Selection Flag

0

1

Set P4.0 to input mode

Set P4.0 to output mode

4-30

S3C7565/P7565

MEMORY MAP

PMG4 — Port I/O Mode Flags (Group 3: Ports 6, 7)

I/O

FEDH, FECH

7

PM7.3

0

6

PM7.2

0

5

PM7.1

0

4

PM6.0

0

3

PM6.3

0

2

1

0

Bit

Identifier

PM6.2

PM6.1

PM6.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PM7.3

PM7.2

PM7.1

PM7.0

P7.3 I/O Mode Selection Flag

0

1

Set P7.3 to input mode

Set P7.3 to output mode

P7.2 I/O Mode Selection Flag

0

1

Set P7.2 to input mode

Set P7.2 to output mode

P7.1 I/O Mode Selection Flag

0

1

Set P7.1 to input mode

Set P7.1 to output mode

P7.0 I/O Mode Selection Flag

0

1

Set P7.0 to input mode

Set P7.0 to output mode

PM6.3

PM6.2

PM6.1

P6.3 I/O Mode Selection Flag

0

1

Set P6.3 to input mode

Set P6.3 to output mode

P6.2 I/O Mode Selection Flag

0

1

Set P6.2 to input mode

Set P6.2 to output mode

P6.1 I/O Mode Selection Flag

0

1

Set P6.1 to input mode

Set P6.1 to output mode

PM6.0

P6.0 I/O Mode Selection Flag

0

1

Set P6.0 to input mode

Set P6.0 to output mode

4-31

MEMORY MAP

S3C7565/P7565

PMG5 — Port I/O Mode Flags (Group 3: Ports 8, 9)

I/O

FEFH, FEEH

7

PM9.3

0

6

PM9.2

0

5

PM9.1

0

4

PM9.0

0

3

PM8.3

0

2

1

0

Bit

Identifier

PM8.2

PM8.1

PM8.0

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PM9.3

PM9.2

PM9.1

PM9.0

P9.3 I/O Mode Selection Flag

0

1

Set P9.3 to input mode

Set P9.3 to output mode

P9.2 I/O Mode Selection Flag

0

1

Set P9.2 to input mode

Set P9.2 to output mode

P9.1 I/O Mode Selection Flag

0

1

Set P9.1 to input mode

Set P9.1 to output mode

P9.0 I/O Mode Selection Flag

0

1

Set P9.0 to input mode

Set P9.0 to output mode

PM8.3

PM8.2

PM8.1

P8.3 I/O Mode Selection Flag

0

1

Set P8.3 to input mode

Set P8.3 to output mode

P8.2 I/O Mode Selection Flag

0

1

Set P8.2 to input mode

Set P8.2 to output mode

P8.1 I/O Mode Selection Flag

0

1

Set P8.1 to input mode

Not available

PM8.0

P8.0 I/O Mode Selection Flag

0

1

Set P8.0 to input mode

Not available

4-32

S3C7565/P7565

MEMORY MAP

PNE1 — N-Channel Open-Drain Mode Register 1

I/O

FD7H, FD6H

7

“0”

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

1

.1

0

.0

0

Bit

Identifier

.2

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

.7

.6

Bit 7

0

Always logic 0

P2.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P2.2 as a push-pull

Configure P2.2 as a n-channel open-drain

.5

P2.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P2.1 as a push-pull

Configure P2.1 as a n-channel open-drain

.4

.3

.2

.1

.0

P2.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P2.0 as a push-pull

Configure P2.0 as a n-channel open-drain

P0.3 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.3 as a push-pull

Configure P0.3 as a n-channel open-drain

P0.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.2 as a push-pull

Configure P0.2 as a n-channel open-drain

P0.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.1 as a push-pull

Configure P0.1 as a n-channel open-drain

P0.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.0 as a push-pull

Configure P0.0 as a n-channel open-drain

4-33

MEMORY MAP

S3C7565/P7565

PNE2 — N-Channel Open-Drain Mode Register 2

I/O

FD8H

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

.3

.2

.1

.0

P3.3 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.3 as a push-pull

Configure P3.3 as a n-channel open-drain

P3.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.2 as a push-pull

Configure P3.2 as a n-channel open-drain

P3.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.1 as a push-pull

Configure P3.1 as a n-channel open-drain

P3.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.0 as a push-pull

Configure P3.0 as a n-channel open-drain

4-34

S3C7565/P7565

MEMORY MAP

PSW— Program Status Word

CPU

FB1H, FB0H

7

6

SC2

0

5

SC1

0

4

SC0

0

3

IS1

0

2

IS0

0

1

0

Bit

Identifier

C

EMB

ERB

(1)

0

RESET Value

Read/Write

R/W

R

8

R

8

R

8

R/W

(2)

1/4/8

Bit Addressing

C

Carry Flag

0

1

No overflow or borrow condition exists

An overflow or borrow condition does exist

SC2–SC0

IS1, IS0

Skip Condition Flags

0

1

No skip condition exists; no direct manipulation of these bits is allowed

A skip condition exists; no direct manipulation of these bits is allowed

Interrupt Status Flags

0

1

Service all interrupt requests

Service only the high-priority interrupt(s) as determined in the interrupt

priority register (IPR)

1

0

1

Do not service any more interrupt requests

Undefined

EMB

Enable Data Memory Bank Flag

0

Restrict program access to data memory to bank 15 (F80H–FFFH) and to

the locations 000H–07FH in the bank 0 only

1

Enable full access to data memory banks 0–14, and 15

ERB

Enable Register Bank Flag

0

1

Select register bank 0 as working register area

Select register banks 0, 1, 2, or 3 as working register area in accordance with

the select register bank (SRB) instruction operand

NOTES:

1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during

power-down mode (IDLE or STOP), the current value of the carry flag is retained.

2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for

detailed information.

4-35

MEMORY MAP

S3C7565/P7565

PUMOD1 — Pull-up Resistor Mode Register 1

I/O

FDDH, FDCH

7

PUR7

0

6

PUR6

0

5

PUR5

0

4

PUR4

0

3

PUR3

0

2

1

0

PUR0

0

Bit

Identifier

PUR2

PUR1

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

PUR7

PUR6

PUR5

PUR4

PUR3

PUR2

PUR1

PUR0

Connect/Disconnect Port 7 Pull-up Resistor Control Bit

0

1

Disconnect port 7 pull-up resistor

Connect port 7 pull-up resistor

Connect/Disconnect Port 6 Pull-up Resistor Control Bit

0

1

Disconnect port 6 pull-up resistor

Connect port 6 pull-up resistor

Connect/Disconnect Port 5 Pull-up Resistor Control Bit

0

1

Disconnect port 5 pull-up resistor

Connect port 5 pull-up resistor

Connect/Disconnect Port 4 Pull-up Resistor Control Bit

0

1

Disconnect port 4 pull-up resistor

Connect port 4 pull-up resistor

Connect/Disconnect Port 3 Pull-up Resistor Control Bit

0

1

Disconnect port 3 pull-up resistor

Connect port 3 pull-up resistor

Connect/Disconnect Port 2 Pull-up Resistor Control Bit

0

1

Disconnect port 2 pull-up resistor

Connect port 2 pull-up resistor

Connect/Disconnect Port 1 Pull-up Resistor Control Bit

0

1

Disconnect port 1 pull-up resistor

Connect port 1 pull-up resistor

Connect/Disconnect Port 0 Pull-up Resistor Control Bit

0

1

Disconnect port 0 pull-up resistor

Connect port 0 pull-up resistor

4-36

S3C7565/P7565

MEMORY MAP

PUMOD2 — Pull-up Resistor Mode Register 2

I/O

FDEH

3

“0”

0

2

PUR10

0

1

PUR9

0

PUR8

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

.3

Bit 3

0

Always cleared to logic zero

PUR10

Connect/Disconnect Port 10 Pull-up Resistor Control Bit

0

1

Disconnect port 10 pull-up resistor

Connect port 10 pull-up resistor

PUR9

PUR8

Connect/Disconnect Port 9 Pull-up Resistor Control Bit

0

1

Disconnect port 9 pull-up resistor

Connect port 9 pull-up resistor

Connect/Disconnect Port 8 Pull-up Resistor Control Bit

0

1

Disconnect port 8 pull-up resistor

Connect port 8 pull-up resistor

4-37

MEMORY MAP

S3C7565/P7565

SCMOD— System Clock Mode Control Register

CPU

FB7H

3

.3

0

2

.2

0

1

"0"

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

1

W

1

W

1

W

1

Bit Addressing

SCMOD.3

SCMOD.2

Bit 3

0

1

Enable main system clock

Disable main system clock

Bit 2

0

1

Enable sub system clock

Disable sub system clock

SCMOD.1

SCMOD.0

Bit 1

0

Always logic zero

Bit 0

0

1

Select main system clock

Select sub system clock

NOTES:

1. SCMOD bits 3 and 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by

separate 1-bit instructions.

2. Sub-oscillation goes into stop mode only by SCMOD.2. PCON which revokes stop mode cannot stop the

sub-oscillation. The stop of sub-oscillation is released only by reset regardless of the value of SCMOD.2.

3. You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed):

Main operation ® sub-operation ® sub-idle (LCD on, after a few minutes later without any external input) ®

sub-operation ® main operation ® SCMOD.2 = 1 ® main stop mode (LCD off).

4-38

S3C7565/P7565

MEMORY MAP

SMOD — Serial I/O Mode Register

SIO

FE1H, FE0H

7

.7

0

6

.6

0

5

.5

0

4

"0"

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Bit

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

1/8

Bit Addressing

SMOD.7–.5

Serial I/O Clock Selection and SBUF R/W Status Control Bits

0

1

0

1

x

Use an external clock at the SCK pin;

Enable SBUF when SIO operation is halted or when SCK goes high

Use the TOL0 clock from timer/counter 0;

Enable SBUF when SIO operation is halted or when SCK goes high

Use the selected CPU clock (fxx/4, 8, or 64; "fxx" is the system

clock) then, enable SBUF read/write operation. "x" means don't

care.

4.09 kHz clock (fxx/2¹⁰)

1

0

1

0

1

262 kHz clock (fxx/2⁴); Note: You cannot select a fxx/2⁴clock

frequency if you have selected a CPU clock of fxx/64

NOTE: All kHz frequency ratings assume a system clock of 4.19 MHz.

Bit 4

SMOD.4

SMOD.3

0

Always logic zero

Initiate Serial I/O Operation Bit

1

Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial

transmission. When SIO transmission starts, this bit is cleared by hardware to

logic zero

SMOD.2

Enable/Disable SIO Data Shifter and Clock Counter Bit

0

Disable the data shifter and clock counter; the contents of IRQS flag is

retained when serial transmission is completed

1

Enable the data shifter and clock counter; The IRQS flag is set to logic one

when serial transmission is completed

SMOD.1

SMOD.0

Serial I/O Transmission Mode Selection Bit

0

1

Receive-only mode

Transmit-and-receive mode

LSB/MSB Transmission Mode Selection Bit

0

1

Transmit the most significant bit (MSB) first

Transmit the least significant bit (LSB) first

4-39

MEMORY MAP

S3C7565/P7565

TMOD0— Timer/Counter 0 Mode Register

T/C0

F91H, F90H

7

"0"

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

"0"

0

"0"

0

Bit

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

1/8

Bit Addressing

TMOD0.7

Bit 7

0

Always logic zero

TMOD0.6–.4

Timer/Counter 0 Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

External clock input at TCL0 pin on rising edge

External clock input at TCL0 pin on falling edge

Internal system clock (fxx) of 4.19 MHz/2¹⁰(4.09 kHz)

Select clock: fxx/2⁶(65.5 kHz at 4.19 MHz)

Select clock: fxx/2⁴(262 kHz at 4.19 MHz)

Select clock: fxx (4.19 MHz)

TMOD0.3

TMOD0.2

Clear Counter and Resume Counting Control Bit

Clear TCNT0, IRQT0, and TOL0 and resume counting immediately

(This bit is cleared automatically when counting starts.)

1

Enable/Disable Timer/Counter 0 Bit

0

1

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Bit 1

0

Always logic zero

Bit 0

0

4-40

S3C7565/P7565

MEMORY MAP

TMOD1A— Timer/Counter 1/1A Mode Register

T/C

FA1H, FA0H

7

.7

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

"0"

0

"0"

0

Bit

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

1/8

Bit Addressing

TMOD1.7

One 16-bit Timer/Counter, Two 8-bit Timer/Counter 1A/1B Configuration

Control Bit

0

1

Two 8-bit timer/counter 1A/1B mode (Timer/counter 1A and 1B)

One 16-bit timer/counter mode (Timer/counter 1)

TMOD1.6–.4

Timer/Counter 1/1A Input Clock Selection Bit

0

1

0

1

0

1

0

1

0

1

External clock input (TCL1) on rising edge

External clock input (TCL1) on falling edge

fxx/2¹⁰= 4.09 kHz

fxx/2⁶= 65.5 kHz

fxx/2⁴= 262 kHz

fxx = 4.19 MHz

TMOD1.3

TMOD1.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT1A, IRQT1, and TOL1 and resume counting immediately when two

8-bit timer 1A/1B mode is configured (TMOD1.7 = 0). Clear TCNT1, IRQT1,

and TOL1 and resume counting immediately when one 16-bit timer mode is

configured (TMOD1.7 = 1)

Enable/Disable 16-bit Timer/Counter 1/1A Bit

0

Disable timer/counter 1/1A; retain TCNT1A contents (TMOD1.7 = 0) or TCNT1

(TMOD1.7 = 1)

1

Enable timer/counter 1/1A

Always logic zero

TMOD1.1

TMOD1.0

Bit 1

0

Bit 0

0

Always logic zero

4-41

MEMORY MAP

S3C7565/P7565

TMOD1B— Timer/Counter 1B Mode Register

T/C

FA3H, FA2H

7

"0"

0

6

.6

0

5

.5

0

4

.4

0

3

.3

0

2

.2

0

1

"0"

0

"0"

0

Bit

Identifier

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

1/8

Bit Addressing

TMOD1.7

Bit 7

0

Always logic zero

TMOD1.6–.4

Timer/Counter 1 Input Clock Selection Bit

0

1

0

1

0

1

Not available

fxx/2¹⁰= 4.09 kHz

6

fxx/2 = 65.5 kHz

4

1

0

1

fxx/2 = 262 kHz

fxx = 4.19 MHz

TMOD1.3

TMOD1.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT1B, IRQT2, and resume counting immediately

(This bit is cleared automatically when counting starts.)

Enable/Disable Timer/Counter 1 Bit

0

1

Disable timer/counter 1B; retain TCNT1B contents

Enable timer/counter 1B

TMOD1.1

TMOD1.0

Bit 1

0

Always logic zero

Bit 0

0

4-42

S3C7565/P7565

MEMORY MAP

TOE0, TOE1, TOL2— Timer Output Enable Flags

T/C

F92H

3

TOE1

0

2

TOE0

0

1

"0"

0

TOL2

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R

1/4

Bit Addressing

TOE1

TOE0

Timer/Counter 1/1A Output Enable Flag

0

1

Disable timer/counter 1 or 1A output at the TCLO1 pin

Enable timer/counter 1 or 1A output at the TCLO1 pin

Timer/Counter 0 Output Enable Flag

0

1

Disable timer/counter 0 output at the TCLO0 pin

Enable timer/counter 0 output at the TCLO0 pin

.1

Bit 1

0

Always logic zero

TOL2

Timer/Counter 1B Output Latch Read Bit

0

1

Timer/Counter 1B output clock is low, 1-bit read-only addressable

Timer/Counter 1B output clock is high, 1-bit read-only addressable

4-43

MEMORY MAP

S3C7565/P7565

VLC1R — VLC1 Register

FD9H

3

“0”

0

2

“0”

0

1

“0”

0

VLC1F

0

Bit

Identifier

RESET Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

VLC1R.3–.1

VLC1F.0

Bits 3–1

0

Always logic zero

P2.1 Digital Input or Analog Input Selection Bit

0

1

Configure P2.1 as an digital input pin

Configure P2.1 as an analog input pin for LCD bias

4-44

S3C7565/P7565

MEMORY MAP

WDFLAG — Watch-Dog Timer's Counter Clear Flag

WT

F9AH

3

WDTCF

0

2

"0"

0

1

"0"

0

"0"

0

Bit

Identifier

RESET Value

Read/Write

W

4

W

4

W

4

1/4

Bit Addressing

WDTCF

Watch-dog Timer's Counter Clear Bit

0

1

–

Clear the WDT's counter to zero and restart the WDT's counter

WDFLAG.2–.0

Bits 2–0

Always logic zero

0

4-45

MEMORY MAP

S3C7565/P7565

WDMOD — Watch-Dog Timer Mode Control Register

WT

F99H,F98H

7

.7

1

6

.6

0

5

.5

1

4

.4

0

3

2

.2

1

.1

0

.0

1

Bit

Identifier

.3

0

RESET Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

WMOD.7–.0

Watch-Dog Timer Enable/Disable Control

0

1

0

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Others

4-46

S3C7565/P7565

MEMORY MAP

WMOD — Watch Timer Mode Register

WT

F89H,F88H

7

.7

0

6

"0"

0

5

.5

0

4

.4

0

3

2

.2

0

1

.1

0

.0

0

Bit

Identifier

.3

(note)

RESET Value

Read/Write

W

8

W

8

W

8

W

8

R

1

W

8

W

8

W

8

Bit Addressing

WMOD.7

Enable/Disable Buzzer Output Bit

0

1

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

WMOD.6

Bit 6

0

Always logic zero

WMOD.5–.4

Output Buzzer Frequency Selection Bits

0

1

0

1

0

1

0.5 kHz buzzer (BUZ) signal output

1 kHz buzzer (BUZ) signal output

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

WMOD.3

XT_INInput Level Control Bit

0

1

Input level to XT_INpin is low; 1-bit read-only addressable for tests

Input level to XT_INpin is high; 1-bit read-only addressable for tests

WMOD.2

WMOD.1

Enable/Disable Watch Timer Bit

0

1

Disable watch timer and clear frequency dividing circuits

Enable watch timer

Watch Timer Speed Control Bit

0

1

Normal speed; set IRQW to 0.5 seconds

High-speed operation; set IRQW to 3.91 ms

WMOD.0

Watch Timer Clock Selection Bit

0

1

Select main system clock (fx)/128 as the watch timer clock

Select a subsystem clock as the watch timer clock

NOTES:

1. RESET sets WMOD.3 to the current input level of the subsystem clock, XT . If the input level is high, WMOD.3 is set to

IN

logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.

2. Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fx) is assumed to be 32.768 kHz

4-47

MEMORY MAP

S3C7565/P7565

NOTES

4-48

S3C7565/P7565

OSCILLATOR CIRCUITS

6

OSCILLATOR CIRCUITS

OVERVIEW

The S3C7565 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock

circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.

Specifically, a clock pulse is required by the following peripheral modules:

— LCD controller

— Basic timer

— Timer/counters 0 and 1

— Watch timer

— Serial I/O interface

— Clock output circuit

— DTMF generator

— Comparator

CPU Clock Notation

In this document, the following notation is used for descriptions of the CPU clock:

fx

Main system clock

Subsystem clock

fxt

fxx

Selected system clock

6-1

OSCILLATOR CIRCUITS

Clock Control Registers

S3C7565/P7565

The power control register, PCON, is used to select normal CPU operating mode or one of two power-down

modes — stop or idle. Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to

engage stop or idle power-down mode.

The system clock mode control register, SCMOD, lets you select the main system clock (fx) or a subsystem clock

(fxt) as the CPU clock and to start (or stop) main/sub system clock oscillation. The resulting clock source, either

main system clock or subsystem clock, is referred to as the selected system clock (fxx).

The main system clock is selected and oscillation started when all SCMOD bits are cleared to logic zero. By

setting SCMOD.3 and SCMOD.0 to different values, you can select a subsystem clock source and start or stop

main/sub system clock oscillation. Main system clock oscillation can be stopped by setting SCMOD.3 only when

the subsystem clock is operating. To stop main system clock oscillation (assuming the main system clock is

selected), you must use the STOP instruction instead of manipulating SCMOD.3.

The main system clock can be divided by 4, 8, or 64. By manipulating PCON bits 1 and 0, you select one of the

following frequencies as the selected system clock (fxx).

fx

4

fxt

4

fx

8

fx

64

,

When the SCMOD and PCON registers are both cleared to zero after RESET, the normal CPU operating mode

is enabled, a main system clock of fx/64 is selected, and main system clock oscillation is initiated.

Using a Subsystem Clock

If a subsystem clock is being used for an application, the idle power-down mode can be initiated by executing an

IDLE instruction. Since the subsystem clock source cannot be stopped internally, you cannot, however, use a

STOP instruction to enable the stop power-down mode.

The watch timer, buzzer and LCD display operate normally with a subsystem clock source, since they operate at

very slow speeds and with very low power consumption (as low as 122 µs at 32.768 kHz).

6-2

S3C7565/P7565

OSCILLATOR CIRCUITS

DTMF Generator

fx

Watch Timer

LCD Controller

fxt

Main-system

Sub-system

Oscillator

Circuit

Oscillator

Circuit

Oscillator

Stop

Selector

XIN

XOUT

XTIN

XTOUT

fxx

1/8-1/4096

Oscillator

Stop

Basic Timer

Frequency

Dividing

Circuit

Timer/Counter

Watch Timer

LCD Controller

Clock Output Circuit

Comparator

1/2

1/16

Serial I/O Interface

SCMOD.3

Selector

SCMOD.0

SCMOD.2

fx/1, 2, 16

fxt

Selector

1/4

CPU stop signal

(IDLE mode)

PCON.0

PCON.1

PCON.2

PCON.3

CPU Clock

Wait release signal

Oscillator

Control

Circuit

Idle

Internal RESET signal

Power down release signal

Stop

fx: Main-system clock

fxt: Sub-system clock

fxx: System clock

PCON.3, .2 clear

Figure 6-1. Clock Circuit Diagram

6-3

OSCILLATOR CIRCUITS

S3C7565/P7565

MAIN SYSTEM OSCILLATOR CIRCUITS

SUB SYSTEM OSCILLATOR CIRCUITS

XIN

XTIN

XOUT

XTOUT

32.768 kHz

Figure 6-2. Crystal/Ceramic Oscillator (fx)

Figure 6-5. Crystal/Ceramic Oscillator (fxt)

XIN

XTIN

External

Clock

XOUT

XTOUT

Figure 6-6. External Oscillator (fxt)

Figure 6-3. External Oscillator (fx)

XIN

R

XOUT

Figure 6-4. RC Oscillator (fx)

6-4

S3C7565/P7565

OSCILLATOR CIRCUITS

POWER CONTROL REGISTER (PCON)

The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control

CPU operating and power-down modes. PCON can be addressed directly by 4-bit write instructions or indirectly

by the instructions IDLE and STOP.

FB3H

PCON.3

PCON.2

PCON.1

PCON.0

PCON bits 3 and 2 are addressed by the STOP and IDLE instructions, respectively, to engage the idle and stop

power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the

enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. There

are two basic choices:

— Main system clock (fx) or subsystem clock (fxt);

— Divided fx/4, 8, 64 or fxt/4 clock frequency.

PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If

SCMOD.0 = "0" the main system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 =

"1" the subsystem clock is selected.

RESET sets PCON register values (and SCMOD) to logic zero: SCMOD.3 and SCMOD.0 select the main system

clock (fx) and start clock oscillation; PCON.1 and PCON.0 divide the selected fx frequency by 64, and PCON.3

and PCON.2 enable normal CPU operating mode.

Table 6-1. Power Control Register (PCON) Organization

PCON Bit Settings

Resulting CPU Operating Mode

PCON.3

PCON.2

0

1

0

1

0

Normal CPU operating mode

Idle power-down mode

Stop power-down mode

PCON Bit Settings

Resulting CPU Clock Frequency

PCON.1

PCON.0

If SCMOD.0 = "0"

If SCMOD.0 = "1"

0

1

0

1

fx/64

fx/8

fxt/4

fx/4

+

PROGRAMMING TIP — Setting the CPU Clock

To set the CPU clock to 0.95 µs at 4.19 MHz:

BITS

SMB

LD

EMB

15

A,#3H

PCON,A

LD

6-5

OSCILLATOR CIRCUITS

S3C7565/P7565

INSTRUCTION CYCLE TIMES

The unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a

subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6-2 shows

corresponding cycle times in microseconds.

Table 6-2. Instruction Cycle Times for CPU Clock Rates

Selected

CPU Clock

Resulting Frequency

Oscillation

Source

Cycle Time (µs)

fx/64

fx/8

65.5 kHz

524.0 kHz

1.05 MHz

8.19 kHz

fx = 4.19 MHz

15.3

1.91

fx/4

0.95

fxt/4

fxt = 32.768 kHz

122.0

6-6

S3C7565/P7565

OSCILLATOR CIRCUITS

SYSTEM CLOCK MODE REGISTER (SCMOD)

The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control

main and sub-system clock oscillation. RESET clears all SCMOD values to logic zero, selecting the main system

clock (fx) as the CPU clock and starting clock oscillation.

It's SCMOD.0, SCMOD.2, and SCMOD.3 bits can be manipulated by 1-bit write instructions (In other words,

SCMOD.0, SCMOD.2, and SCMOD.3 cannot be modified simultaneously by a 4-bit write). Bit 1 is always logic

zero.

FB7H

SCMOD.3 SCMOD.2

"0"

SCMOD.0

A subsystem clock (fxt) can be selected as the system clock by manipulating the SCMOD.3 and SCMOD.0 bit

settings. If SCMOD.3 = "0" and SCMOD.0 = "1", the subsystem clock is selected and main system clock

oscillation continues. If SCMOD.3 = "1" and SCMOD.0 = "1", fxt is selected, but main system clock oscillation

stops.

If you have selected fx as the CPU clock, setting SCMOD.3 to "1" will not stop main system clock oscillation.

This can only be done by a STOP instruction.

Table 6-3. System Clock Mode Register (SCMOD) Organization

SCMOD Register Bit Settings

Resulting Clock Selection

CPU Clock fx Oscillation

fx On

SCMOD.3

SCMOD.0

0

1

0

1

fxt

On

Off

SCMOD.2

Sub-oscillation on/off

0

1

Enable sub system clock

Disable sub system clock

NOTE: You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed):

Main operation ® sub-operation ® sub-idle (LCD on, after a few minutes later without any

external input) ® sub-operation ® main operation ® SCMOD.2 = 1 ® main stop mode (LCD off).

6-7

OSCILLATOR CIRCUITS

S3C7565/P7565

SWITCHING THE CPU CLOCK

Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD,

determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this

frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and

to modify operating frequencies.

SCMOD.3 and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main

system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the selected fx

clock by 4, 8, or 64,or fxt clock by 4.

NOTE

A clock switch operation does not go into effect immediately when you make the SCMOD and PCON

register modifications — the previously selected clock continues to run for a certain number of machine

cycles.

For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64)

and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you

first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation

to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After

this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1".

This same “stepped” approach must be taken to switch from a subsystem clock to the main system clock: first,

clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles

has elapsed, select the main system clock by clearing all SCMOD values to logic zero.

Following a RESET, CPU operation starts with the lowest main system clock frequency of 15.3 µs at 4.19 MHz

after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-4 details the number of

machine cycles that must elapse before a CPU clock switch modification goes into effect.

Table 6-4. Elapsed Machine Cycles During CPU Clock Switch

AFTER

SCMOD.0 = 0

PCON.1 = 1 PCON.0 = 0

SCMOD.0 = 1

BEFORE

PCON.1 = 0

PCON.0 = 0

PCON.1 = 1

PCON.0 = 1

PCON.1 = 0

PCON.0 = 0

PCON.1 = 1

PCON.0 = 0

PCON.1 = 1

PCON.0 = 1

N/A

1 Machine Cycle

N/A

SCMOD.0 = 0

8 Machine Cycles

16 Machine Cycles

N/A

1 Machine Cycles

N/A

2 Machine Cycles

N/A

fx/4fxt

(M/C)

SCMOD.0 = 1

fx/4fxt (M/C)

N/A

NOTES:

1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered.

2. Since the X input is connected internally to V to avoid current leakage due to the crystal oscillator in stop mode, do

IN

SS

not set SCMOD.3 to "1" when an external clock is used as the main system clock.

3. “N/A” means “not available”.

6-8

S3C7565/P7565

OSCILLATOR CIRCUITS

+

PROGRAMMING TIP — Switching Between Main System and Subsystem Clock

1. Switch from the main system clock to the subsystem clock:

MA2SUB

BITS

CALL

BITS

RET

LD

NOP

DECS

JR

SCMOD.0

DLY80

SCMOD.3

; Switches to subsystem clock

; Delay 80 machine cycles

; Stop the main system clock

DLY80

DEL1

A,#0FH

A

DEL1

RET

2. Switch from the subsystem clock to the main system clock:

SUB2MA

BITR

CALL

BITR

RET

SCMOD.3

DLY80

SCMOD.0

; Start main system clock oscillation

; Delay 80 machine cycles

; Switch to main system clock

6-9

OSCILLATOR CIRCUITS

S3C7565/P7565

CLOCK OUTPUT MODE REGISTER (CLMOD)

The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the

CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions

only.

FD0H

CLMOD.3

"0"

CLMOD.1

CLMOD.0

RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without

initiating clock oscillation), and disables clock output.

CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four

possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64.

Table 6-5. Clock Output Mode Register (CLMOD) Organization

CLMOD Bit Settings

Resulting Clock Output

CLMOD.1

CLMOD.0

Clock Source

Frequency

0

1

0

1

0

1

CPU clock (fx/4, fx/8, fx/64, fxt/4)

1.05 MHz, 524 kHz, 65.5 kHz, 8.2 kHz

fxx/8

524 kHz

262 kHz

65.5 kHz

fxx/16

fxx/64

CLMOD.3

Result of CLMOD.3 Setting

0

1

Clock output is disabled

Clock output is enabled

NOTE: Frequencies assume that fxx, fx = 4.19 MHz and fxt = 32.768 kHz.

6-10

S3C7565/P7565

OSCILLATOR CIRCUITS

CLOCK OUTPUT CIRCUIT

The clock output circuit, used to output clock pulses to the CLO pin, has the following components:

— 4-bit clock output mode register (CLMOD)

— Clock selector

— Output latch

— Port mode flag

— CLO output pin (P2.0)

CLMOD.3

CLO

CLMOD.2

4

CLMOD.1

Clock

Selector

P2.0 Output Latch

PM 2

CLMOD.0

Clocks

(fxx/8, fxx/16, fxx/64, CPU clock)

Figure 6-7. CLO Output Pin Circuit Diagram

CLOCK OUTPUT PROCEDURE

The procedure for outputting clock pulses to the CLO pin may be summarized as follows:

1. Disable clock output by clearing CLMOD.3 to logic zero.

2. Set the clock output frequency (CLMOD.1, CLMOD.0).

3. Load a "0" to the output latch of the CLO pin (P2.0).

4. Set the P2.0 mode flag (PM2.0) to output mode.

5. Enable clock output by setting CLMOD.3 to logic one.

+

PROGRAMMING TIP — CPU Clock Output to the CLO Pin

To output the CPU clock to the CLO pin:

BITS

SMB

LD

BITR

LD

EMB

15

EA,#10H

PMG1,EA

P2.0

A,#9H

CLMOD,A

; P2.0 ¬ Output mode

; Clear P2.0 output latch

LD

6-11

OSCILLATOR CIRCUITS

S3C7565/P7565

NOTES

6-12

S3C7565/P7565

INTERRUPTS

7

INTERRUPTS

OVERVIEW

The S3C7565 interrupt control circuit has five functional components:

— Interrupt enable flags (IEx)

— Interrupt request flags (IRQx)

— Interrupt master enable register (IME)

— Interrupt priority register (IPR)

— Power-down release signal circuit

Three kinds of interrupts are supported:

— Internal interrupts generated by on-chip processes

— External interrupts generated by external peripheral devices

— Quasi-interrupts used for edge detection and as clock sources

Table 7-1. Interrupt Types and Corresponding Port Pin(s)

Interrupt Name Corresponding Port Pins

P1.0, P1.1, P1.3, K0–K7

Interrupt Type

External interrupts

Internal interrupts

Quasi-interrupts

INT0, INT1, INT4, INTK

INTB, INTT0, INTT1 (INTT1A, INTT1B), INTS

Not applicable

P1.2

INT2

INTW

Not applicable

7-1

INTERRUPTS

S3C7565/P7565

Vectored Interrupts

Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program

software. A vectored interrupt is generated when the following flags and register settings, corresponding to the

specific interrupt (INTn) are set to logic one:

— Interrupt enable flag (IEx)

— Interrupt master enable flag (IME)

— Interrupt request flag (IRQx)

— Interrupt status flags (IS0, IS1)

— Interrupt priority register (IPR)

If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is

loaded into the program counter and the program starts executing the service routine from this address.

EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM

during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction.

The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the

main routine, as well as during service routines. Any changes that are made to enable flag values during a

service routine are not stored in the vector address.

When an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the program

status word (PSW), and the enable flag values for the interrupt is fetched from the respective vector address.

Then, if necessary, you can modify the enable flags during the interrupt service routine. When the interrupt

service routine is returned to the main routine by the IRET instruction, the original values saved in the stack are

restored and the main program continues program execution with these values.

Software-Generated Interrupts

To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the

interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met,

and the service routine can be initiated.

Multiple Interrupts

By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and

thereby process multiple interrupts simultaneously.

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

Power-Down Mode Release

An interrupt can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are

initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down

mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases,

the interrupt routine will not be executed since IME = "0".

7-2

S3C7565/P7565

INTERRUPTS

Interrupt is generated (INT xx)

Request flag (IRQx)

IEx = 1?

1

No

Retain value until IEx = 1

Generate corresponding vector interrupt

and release power-down mode

No

IME = 1?

Retain value until IME = 1

Yes

Retain value until interrupt

IS1, 0 = 0, 0?

service routine is completed

No

IS1, 0 = 0, 1?

Yes

No

High-priority interrupt

Yes

IS1, 0 = 1, 0

Store contents of PC and PSW in the stack area;

set PC contents to corresponding vector address

Yes

Are both interrupt sources

of shared vector address used?

IRQx flag value remains 1

No

Reset corresponding IRQx flag

Jump to interrupt start address

Verify interrupt source and clear

IRQx with a BTSTZ instruction

Figure 7-1. Interrupt Execution Flowchart

7-3

INTERRUPTS

S3C7565/P7565

IMOD1

IMOD0

IE2

IEW IEK IET1 IET2 IET0 IES

IE1

IE0

IE4

IEB

IRQB

IRQ4

INTB

INT4

INT0

INT1

@

IRQ0

@

IRQ1

IRQS

IRQT0

IRQT2

IRQT1

IRQK

IRQW

1RQ2

INTS

INTT0

INTT1B

INTT1(INTT1A)

@

K0-K7

INT2

IMODK

@

IMOD2

Power-Down

Mode

Release Signal

IME

IPR

Interrupt Control Unit

IS1 IS0

Vector Interrupt

Generator

@ = Edge Detection Circuit

Figure 7-2. Interrupt Control Circuit Diagram

7-4

S3C7565/P7565

INTERRUPTS

MULTIPLE INTERRUPTS

The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter-

rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service

routine for a lower-priority request is accepted during the execution of a higher priority routine.

Two-Level Interrupt Handling

Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits

of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all

interrupt requests are serviced (see Figure 7-3).

Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one ("0" ® "1" or "1" ® "0"), and the

values are stored in the stack along with the other PSW bits. After the interrupt routine has been serviced, the

modified IS1 and IS0 values are automatically restored from the stack by an IRET instruction.

IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable

memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable

interrupt processing with a DI instruction.

When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt

currently defined by the interrupt priority register (IPR).

Normal Program

Processing

High or Low Level

Interrupt Processing

(Status 1)

(Status 0)

High Level Interrupt

Processing

INT Disable

(Status 2)

Set IPR

INT Enable

Low or

High Level

Interrupt

High Level

Interrupt

Generated

Figure 7-3. Two-Level Interrupt Handling

7-5

INTERRUPTS

S3C7565/P7565

Multi-Level Interrupt Handling

With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt

is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7-2).

When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1"

and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority

request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority

level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7-4).

Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling

Process Status

Before INT

IS1 IS0

Effect of ISx Bit Setting

After INT ACK

IS1

0

IS0

1

0

1

0

All interrupt requests are serviced.

0

1

Only high-priority interrupts as determined by the

current settings in the IPR register are serviced.

1

0

2

–

1

0

1

No additional interrupt requests will be serviced.

Value undefined

–

Normal Program

Processing

Single

Interrupt

(Status 0)

2-Level

INT Disable

Interrupt

Set IPR

Status 1

INT Disable

3-Level

Interrupt

INT Enable

Modify Status

INT Enable

Status 0

Low or

High Level

Interrupt

High Level

Low or

High Level

Interrupt

Generated

Status 1

Status 2

Generated

Status 0

Figure 7-4. Multi-Level Interrupt Handling

7-6

S3C7565/P7565

INTERRUPTS

INTERRUPT PRIORITY REGISTER (IPR)

The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic

zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI

instruction.

FB2H

IME

IPR.2

IPR.1

IPR.0

By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or

you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by

a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by

any other interrupt source.

Table 7-3. Standard Interrupt Priorities

Interrupt

INTB, INT4

INT0

Default Priority

1

2

3

4

5

6

7

INT1

INTS

INTT0, INTT1B

INTT1 (INTT1A)

INTK

The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if

an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the

IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the

current enable memory bank (EMB) value.

Table 7-4. Interrupt Priority Register Settings

IPR.2

IPR.1

IPR.0

Result of IPR Bit Setting

Process all interrupt requests at low priority ^(note)

Process INTB and INT4 interrupts only

Process INT0 interrupts only

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Process INT1 interrupts only

Process INTS interrupts only

Process INTT0 and INTT1B interrupts only

Process INTT1 (INTT1A) interrupts only

Process INTK interrupts only

NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more

interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown in

Table 7-3. Using the IPR settings, you can select specific interrupts for high-priority processing in the event of

contention. When the high-priority (IPR) interrupt has been processed, waiting interrupts are handled according to

their default priorities.

7-7

INTERRUPTS

S3C7565/P7565

+

PROGRAMMING TIP — Setting the INT Interrupt Priority

The following instruction sequence sets the INT1 interrupt to high priority:

BITS

SMB

DI

LD

EMB

15

; IPR.3 (IME) ¬

0

1

A,#3H

IPR,A

EI

EXTERNAL INTERRUPT 0, 1 AND 2 MODE REGISTERS (IMOD0, IMOD1 AND IMOD2)

The following components are used to process external interrupts at the INT0, INT1 and INT2 pins:

— Edge detection circuit

— Three mode registers, IMOD0, IMOD1 and IMOD2

The mode registers are used to control the triggering edge of the input signal. IMOD0, IMOD1 and IMOD2

settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The

INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling

edges. Since INT2 is a qusi-interrupt, the interrupt request flag (IRQ2) must be cleared by software.

FB4H

FB5H

"0"

IMOD0.1

"0"

IMOD0.0

IMOD1.0

FDAH

"0"

IMOD2.0

IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic

zero, selecting rising edges as the trigger for incoming interrupt requests.

Table 7-5. IMOD0, 1 and 2 Register Organization

IMOD0

0

IMOD0.1

IMOD0.0

Effect of IMOD0 Settings

Rising edge detection

0

1

0

1

0

1

Falling edge detection

Both rising and falling edge detection

IRQ0 flag cannot be set to "1"

IMOD1

IMOD2

0

IMOD1.0

IMOD2.0

Effect of IMOD1 and IMOD2 Settings

0

1

Rising edge detection

Falling edge detection

7-8

S3C7565/P7565

INTERRUPTS

EXTERNAL INTERRUPT 0, 1 and 2 MODE REGISTERS (Continued)

IMOD0

2

EDGE Detection

IMOD2

IRQ0

IRQ1

IRQ2

INT0

INT1

INT2

IMOD1

P1.2 P1.1 P1.0

Figure 7-5. Circuit Diagram for INT0, INT1 and INT2 Pins

When modifying the IMOD registers, it is possible to accidentally set an interrupt request flag. To avoid unwanted

interrupts, take these precautions when writing your programs:

1. Disable all interrupts with a DI instruction.

2. Modify the IMOD register.

3. Clear all relevant interrupt request flags.

4. Enable the interrupt by setting the appropriate IEx flag.

5. Enable all interrupts with an EI instructions.

7-9

INTERRUPTS

S3C7565/P7565

EXTERNAL KEY INTERRUPT MODE REGISTER (IMODK)

The mode register for external key interrupts at the K0–K7 pins, IMODK, is addressable only by 4-bit write

instructions. RESET clears all IMODK bits to logic zero.

FB6H

"0"

IMODK.2

IMODK.1

IMODK.0

Rising or falling edge can be detected by bit IMODK.2 settings. If a rising or falling edge is detected at any one of

the selected K pin by the IMODK register, the IRQK flag is set to logic one and a release signal for power-down

mode is generated. If one or more of the pins which are configured as key interrupt (KS0-KS7) are in low input,

the key interrupt can not be occurred.

Table 7-6. IMODK Register Bit Settings

IMODK

0

IMODK.2

IMODK.1

IMODK.0

Effect of IMODK Settings

Disable key interrupt

0, 1

0

1

0

1

0

1

Enable edge detection at the K0–K3 pins

Enable edge detection at the K4–K7 pins

Enable edge detection at the K0–K7 pins

IMODK.2

NOTES:

0

1

Falling edge detection

Rising edge detection

1. To generate a key interrupt, the selected pins must be configured to input mode. If any one pin of the selected pins is

configured to output mode, only falling edge can be detected.

2. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select

edge detection and pins by setting IMODK register.

7-10

S3C7565/P7565

INTERRUPTS

P6.3/K7

P6.2/K6

P6.1/K5

P6.0/K4

P0.3/K3

P0.2/K2

P0.1/K1

P0.0/K0

Enable/

Disable

Rising/

Falling

Edge

IRQK

Selector

Enable/

Disable

IMODK

Figure 7-6. Circuit Diagram for INTK

7-11

INTERRUPTS

S3C7565/P7565

+

PROGRAMMING TIP — Using INTK as a Key Input Interrupt

When the key interrupt is used, the selected key interrupt source pin must be set to input:

1. When K0–K7 are selected (eight pins):

BITS

SMB

LD

EMB

15

A,#3H

LD

IMODK,A

EA,#00H

PMG1,EA

PMG4,EA

EA,#41H

PUMOD1,EA

; (IMODK) ¬ #3H, K0–K7 falling edge select

; P0 ¬ input mode

; P6 ¬ input mode

; Enable P0 and P6 pull-up resistors

2. When K0–K3 are selected (four pins):

BITS

SMB

LD

EMB

15

A,#1H

LD

IMODK,A

EA,#00H

PMG1,EA

EA,#1H

PUMOD1,EA

; (IMODK) ¬ #1H, K0–K3 falling edge select

; P0 ¬ input mode

LD

; Enable P0 pull-up resistors

7-12

S3C7565/P7565

INTERRUPTS

INTERRUPT FLAGS

There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each

interrupt, the interrupt master enable flag, which enables or disables all interrupt processing.

Interrupt Master Enable Flag (IME)

The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an

IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the

IME flag is set to logic one.

The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions,

regardless of the current value of the enable memory bank flag (EMB).

IME

0

IPR.2

IPR.1

IPR.0

Effect of Bit Settings

Inhibit all interrupts

Enable all interrupts

1

Interrupt Enable Flags (IEx)

IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request

flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.

Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed

directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag.

Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses

Address

FB8H

Bit 3

IE4

0

Bit 2

IRQ4

0

Bit 1

IEB

Bit 0

IRQB

IRQW

IRQT1

IRQT0

IRQS

IRQ0

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

IEW

IET1

IET0

IES

IEK

IET2

0

IRQK

IRQT2

0

IE1

0

IRQ1

0

IE0

IE2

IRQ2

NOTES:

1. IEx refers generically to all interrupt enable flags.

2. IRQx refers generically to all interrupt request flags.

3. IEx = 0 is interrupt disable mode.

4. IEx = 1 is interrupt enable mode.

7-13

INTERRUPTS

S3C7565/P7565

Interrupt Request Flags (IRQx)

Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions.IRQx flags can be addressed

directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.

When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then

automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt

request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt

service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary,

follow these guidelines for using IRQx flags:

1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.

2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the

exception of IRQW and IRQ2).

3. When IRQx is set to "1" by software, an interrupt is generated.

When two interrupts share the same service routine start address, interrupt processing may occur in one of two

ways:

— When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been

serviced.

— When two interrupts are enabled, the request flag is not automatically cleared so that the user has an

opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared

manually using a BTSTZ instruction.

Table 7-8. Interrupt Request Flag Conditions and Priorities

Interrupt

Source

Internal /

External

Pre-condition for IRQx Flag Setting

Interrupt

Priority

IRQ Flag

Name

INTB

I

Reference time interval signal from basic

timer

1

IRQB

INT4

INT0

INT1

INTS

E

I

Both rising and falling edges detected at INT4

Rising or falling edge detected at INT0 pin

Rising or falling edge detected at INT1 pin

1

2

3

4

IRQ4

IRQ0

IRQ1

IRQS

Completion signal for serial transmit-and-

receive or receive-only operation

INTT0

I

Signals for TCNT0 and TREF0 registers

match

5

6

7

IRQT0

IRQT2

IRQT1

IRQK

INTT1B

Signals for TCNT1B and TREF1B registers

match

INTT1

(INTT1A)

I

Signals for TCNT1(TCNT1A) and TREF1

(TREF1A) registers match

INTK

E

When a rising or falling edge detected at any

one of the K0–K7 pins

INT2

E

I

Rising or falling edge detected at INT2

Time interval of 0.5 s or 3.19 ms

–

IRQ2

INTW

IRQW

7-14

S3C7565/P7565

INTERRUPTS

+

PROGRAMMING TIP — Enabling the INTB and INT4 Interrupts

To simultaneously enable INTB and INT4 interrupts:

INTB

DI

BTSTZ

JR

IRQB

INT4

; IRQB = 1 ?

; If no, INT4 interrupt; if yes, INTB interrupt is processed

•

EI

IRET

;

INT4

BITR

IRQ4

; INT4 is processed

•

EI

IRET

To simultaneously enable INTT0 and INTT1B interrupts:

INTT0

DI

BTSTZ

JR

IRQT0

INTT1B

; IRQB = 1 ?

; If no, INTT1B interrupt; if yes, INTT0 interrupt is

; processed

•

EI

IRET

;

INTT1B

BITR

IRQT2

; INTT1B is processed

•

EI

IRET

7-15

INTERRUPTS

S3C7565/P7565

NOTES

7-16

S3C7565/P7565

POWER-DOWN

8

POWER-DOWN

OVERVIEW

The S3C7565 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle

mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must

always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals

and the oscillation source continue to operate normally.

When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and

the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has

elapsed, normal CPU operation resumes.

In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard-

ware components are powered-down. The effect of stop mode on specific peripheral hardware components —

CPU, basic timer, serial I/O, timer/counters 0 and 1, watch timer, and LCD controller — and on external interrupt

requests, is detailed in Table 8-1.

NOTE

Do not use stop mode if you are using an external clock source because X_INinput must be restricted

internally to V_SSto reduce current leakage.

Idle or stop modes are terminated either by a RESET, or by an interrupt which is enabled by the corresponding

interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset operation is

executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to “1”, power-down

mode is released immediately upon entering power-down mode.

When an interrupt is used to release power-down mode, the operation differs depending on the value of the

interrupt master enable flag (IME):

— If the IME flag = “0”, program execution starts immediately after the instruction which issues the request to

enter power-down mode is executed. The interrupt request flag remains set to logical one.

— If the IME flag = “1”, two instructions are executed after the power-down mode release and the vectored

interrupt is then initiated. However, when the release signal is caused by INT2 or INTW, the operation is

identical to the IME = “0” condition. Assuming that both interrupt enable flag and interrupt request flag are set

to “1”, the release signal is generated when power-down mode is entered.

8-1

POWER-DOWN

S3C7565/P7565

Table 8-1. Hardware Operation During Power-Down Modes

Idle Mode (IDLE)

Can be changed only if the main system Can be changed if the main system clock

Stop Mode (STOP) ^(note)

Operation

System clock status

Clock oscillator

Basic timer

clock is used

or subsystem clock is used

Main system clock oscillation stops

CPU clock oscillation stops (main and

subsystem clock oscillation continues)

Basic timer stops

Basic timer operates (with IRQB set at

each reference interval)

Serial I/O interface

Timer/counter 0

Operates only if external SCK input is

selected as the serial I/O clock

Operates if a clock other than the CPU

clock is selected as the serial I/O clock

Operates only if TCL0 is selected as the Timer/counter 0 operates

counter clock

Timer/counter 1

Operates only if TCL1 is selected as the Timer/counter 1 (Timer/counter 1A )

(Timer/counter 1A)

counter clock

operates

Timer/counter 1B

Operates only if TCL2 is selected as the Timer/counter 1B operates

counter clock

Comparator

Watch timer

Comparator operation is stopped

Comparator operates

Operates only if subsystem clock (fxt) is Watch timer operates

selected as the counter clock

LCD controller

Operates only if a subsystem clock is

selected as LCDCK

LCD controller operates

External interrupts

INT0, INT1, INT2, INT4, and INTK are

acknowledged

INT0, INT1, INT2, INT4, and INTK are

acknowledged

CPU

All CPU operations are disabled

Mode release signal

Interrupt request signals are enabled by

an interrupt enable flag or by RESET

input

NOTE: When the main clock is selected as the system clock (CPU clock).

8-2

S3C7565/P7565

POWER-DOWN

IDLE MODE TIMING DIAGRAMS

Oscillator

Stabilization

Idle

(31.3 ms/4.19 MHz)

Instruction

RESET

Normal Mode

Idle Mode

Normal Mode

Normal Oscillation

Clock

Signal

Figure 8-1. Timing When Idle Mode is Released by RESET

Idle

Instruction

Mode

Release

Signal

Interrupt Acknowledge (IME = 1)

Normal Mode

Idle Mode

Normal Mode

Normal Oscillation

Clock

Signal

Figure 8-2. Timing When Idle Mode is Released by an Interrupt

8-3

POWER-DOWN

S3C7565/P7565

STOP MODE TIMING DIAGRAMS

Oscillator

Stabilization

Stop

(31.3 ms/4.19 MHz)

Instruction

RESET

Normal Mode

Idle Mode

Normal Mode

Stop mode

Oscillation

Stops

Oscillation Resumes

Clock

Signal

Figure 8-3. Timing When Stop Mode is Released by RESET

Oscillator

Stabilization

(BMOD Setting)

Stop

Instruction

Mode

Release

signal

INT ACK(IME=1)

Normal Mode

Idle Mode

Stop mode

Oscillation

Stops

Oscillation Resumes

Clock

Signal

Figure 8-4. Timing When Stop Mode is Release by an Interrupt

8-4

S3C7565/P7565

POWER-DOWN

+

PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing

The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption.

In this example, the system clock source is switched from the main system clock to a subsystem clock and the

LCD display is turned on:

KEYCLK

DI

CALL

SMB

LD

MA2SUB

15

; Main system clock ® subsystem clock switch subroutine

EA,#00H

P4,EA

A,#3H

IMODK,A

0

IRQW

IRQK

IEW

IEK

WATDIS

IRQK

CIDLE

SUB2MA

; All key strobe outputs to low level

; Select K0–K7 enable

LD

SMB

BITR

BITS

CALL

BTSTZ

JR

CLKS1

CIDLE

; Execute clock and display changing subroutine

; Subsystem clock ® main system clock switch subroutine

; Engage idle mode

CALL

EI

RET

IDLE

NOP

JPS

CLKS1

8-5

POWER-DOWN

S3C7565/P7565

RECOMMENDED CONNECTIONS FOR UNUSED PINS

To reduce overall power consumption, please configure unused pins according to the guidelines described in

Table 8-2.

Table 8-2. Unused Pin Connections for Reduced Power Consumption

Pin/Share Pin Names

P0.0/SCK/K0

Recommended Connection

Input mode: Connect to V_DD

P0.1/SO/K1

P0.2/SI/K2

Output mode: No connection

P0.3/BUZ/K3

Connect to V_DD

P1.0/INT0–P1.2/INT2

P1.3/INT4

Input mode: Connect to V_DD

Output mode: No connection

P2.0/CLO

P2.1/VLC

P2.2

P3.0/TCLO0

P3.1/TCLO1

P3.2/TCL0

P3.3/TCL1

P4.0/COM8–P4.3/COM11

P5.0/COM12–P5.3/COM15

P6.0/ SEG59/K4–P6.3/SEG56/K7

P7.0/SEG55/CIN0–P7.3/SEG52/CIN3

P8.0/SEG51–P8.3/SEG48

P9.0/SEG47–P9.3/SEG44

P10.0/SEG43–P10.3/SEG40

SEG0–SEG39

COM0–COM7

No connection

(Note)

Connect XT_INto V_SS

XT_IN

XT_OUT

TEST

No connection

Connect to V_SS

NOTE: You can stop the sub-oscillator by setting the SCMOD.2 to one.

8-6

S3C7565/P7565

RESET

9

RESET

OVERVIEW

When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is

initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at

4.19 MHz has elapsed, normal system operation resumes.

Regardless of when the RESET occurs — during normal operating mode or during a power-down mode — most

hardware register values are set to the reset values described in Table 9-1 below. The current status of several

register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs

during normal operating mode, their values are undefined. Current values that are retained in this case are as

follows:

— Carry flag

— Data memory values

— General-purpose registers E, A, L, H, X, W, Z, and Y

— Serial I/O buffer register (SBUF)

Oscillator

Stabilization

(31.3 ms/4.19 MHz)

RESET

Input

Normal Mode or

Power-Down

Mode

Normal Mode

Idle Mode

RESET Operation

Figure 9-1. Timing for Oscillation Stabilization After RESET

HARDWARE RESET VALUES AFTER RESET

Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-

down mode or during normal operation.

9-1

RESET

S3C7565/P7565

Table 9-1. Hardware Register Values After RESET

Hardware Component

or Subcomponent

If RESET Occurs During

Normal Operation

Power-Down Mode

Program counter (PC)

Lower six bits of address 0000H Lower six bits of address 0000H

are transferred to PC13–, and are transferred to PC13–, and

the contents of 0001H to PC7–0. the contents of 0001H to PC7–0.

Program Status Word (PSW):

Carry flag (C)

Retained

Undefined

Skip flag (SC0–SC2)

0

Interrupt status flags (IS0, IS1)

Bank enable flags (EMB, ERB)

Bit 6 of address 0000H in

program memory is transferred

to the ERB flag, and bit 7 of the

address to the EMB flag.

program memory is transferred

to the ERB flag, and bit 7 of the

address to the EMB flag.

Stack pointer (SP)

Undefined

Data Memory (RAM):

General registers E, A, L, H, X, W, Z, Y

General-purpose registers

Values retained

Undefined

(note)

Undefined

Values retained

Bank selection registers (SMB, SRB)

BSC register (BSC0–BSC3)

0, 0

0

0, 0

0

Page selection register (PASR)

0

Clocks:

Power control register (PCON)

0

Clock output mode register (CLMOD)

System clock mode register (SCMOD)

Interrupts:

Interrupt request flags (IRQx)

Interrupt enable flags (Iex)

Interrupt priority flag (IPR)

0

Interrupt master enable flag (IME)

INT0 mode register (IMOD0)

INT1 mode register (IMOD1)

INT2 mode register (IMOD2)

INTK mode register (IMODK)

NOTE: The values of the 0F8H–0FDH are not retained when a RESET signal is input.

9-2

S3C7565/P7565

RESET

Table 9-1. Hardware Register Values After RESET (Continued)

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

Normal Operation

I/O Ports:

Output buffers

Off

0

Off

0

Output latches

Port mode flags (PM)

0

Pull-up resistor mode reg (PUMOD1/2)

Port 7 mode register (P7MOD)

0

Basic Timer:

Count register (BCNT)

Mode register (BMOD)

Mode register (WDMOD)

Counter clear flag (WDTCF)

Undefined

0

A5H

0

A5H

0

Timer/Counters 0 and 1:

Count registers

0

(TCNT0/TCNT1A/TCNT1B)

Reference registers

(TREF0/TREF1A/TREF1B)

FFH, FFFFH

0

FFH, FFFFH

0

Mode registers

(TMOD0/TMOD1A/TMOD1B)

Output enable flags (TOE0/1)

TOL2

0

Undefined

Watch Timer:

Watch timer mode register (WMOD)

0

9-3

RESET

S3C7565/P7565

Table 9-1. Hardware Register Values After RESET (Concluded)

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

Normal Operation

LCD Driver/Controller:

LCD mode register (LMOD)

LCD control register (LCON)

VLC1 register (VLC1R)

Display data memory

Output buffers

0

Values retained

Off

0

Undefined

Off

Serial I/O Interface:

SIO mode register (SMOD)

SIO interface buffer (SBUF)

0

Values retained

Undefined

N-Channel Open-Drain Mode Register

PNE1–PNE2

0

Comparator

Comparator mode register (CMOD)

Comparison result register (CMPREG)

0

Undefined

DTMF Generator

DTMF mode register (DTMR)

0

9-4

S3C7565/P7565

I/O PORTS

10 I/O PORTS

OVERVIEW

The S3C7565 has 11 ports. There are total of 6 input pins and 37 configurable I/O pins, for a maximum number

of 43 pins.

Pin addresses for all ports are mapped to bank 15 of the RAM. The contents of I/O port pin latches can be read,

written, or tested at the corresponding address using bit manipulation instructions.

Port Mode Flags

Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the

corresponding register bit.

Pull-up Resistor Mode Register (PUMOD)

The pull-up mode registers (PUMOD1, 2) are used to assign internal pull-up resistors by software to specific

ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically

disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

10-1

I/O PORTS

S3C7565/P7565

Table 10-1. I/O Port Overview

Port

I/O

Pins

Pin Names

P0.0–P0.3

Address

Function Description

4-bit I/O port.

0

I/O

4

FF0H

1-bit and 4-bit read/write and test is possible.

Individual pins are software configurable as

input or output.

Individual pins are software configurable as

open-drain or push-pull output.

4-bit pull-up resistors are software assignable;

pull-up resistors are automatically disabled for

output pins.

1

2

I

4

3

P1.0–P1.3

FF1H

4-bit input port.

1-bit and 4-bit read and test is possible.

4-bit pull-up resistors are assignable.

I/O

P2.0–P2.2

P3.0–P3.3

FF2H

FF3H

Same as port 0 except that port 2 is a 3-bit I/O

port.

3

I/O

4

8

Same as port 0.

4, 5

P4.0–P4.3

P5.0–P5.3

FF4H

FF5H

4-bit I/O ports.

1-, 4-bit or 8-bit read/write and test is possible.

Individual pins are software configurable as

input or output.

4-bit pull-up resistors are software assignable;

pull-up resistors are automatically disabled for

output pins.

6, 7

8,9

I/O

8

2

P6.0–P6.3

P7.0–P7.3

FF6H

FF7H

Same as P4 and P5.

P8.0–P8.1

FF8H

Input ports.

1-, 4-bit or 8-bit read and test is possible.

4-bit pull-up resistors are software assignable;

pull-up resistors are automatically disabled for

output pins.

6

4

P8.2–P8.3

P9.0–P9.3

FF8H

FF9H

Same as P4 and P5.

10

I/O

P10.0–P10.3

FFAH

Sample as P4 and P5

Table 10-2. Port Pin Status During Instruction Execution

Instruction Type

Example

Input Mode Status

Output Mode Status

1-bit test

BTST P0.1

Input or test data at each pin

Input or test data at output latch

1-bit input

4-bit input

8-bit input

LDB

LD

C,P1.3

A,P7

EA,P4

1-bit output

BITR P2.3

Output latch contents undefined

Output pin status is modified

4-bit output

8-bit output

LD

P2,A

P6,EA

Transfer accumulator data to the

output latch

Transfer accumulator data to the

output pin

10-2

S3C7565/P7565

I/O PORTS

PORT MODE FLAGS (PM FLAGS)

Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the

corresponding I/O buffer.

For convenient program reference, PM flags are organized into five groups — PMG1, PMG2, PMG3, PMG4, and

PMG5 as shown is Table 1-3. They are addressable by 8-bit write instructions only

When a PM flag is “0”, the port is set to input mode; when it is “1”, the port is enabled for output. RESET clears

all port mode flags t logical zero, automatically configuring the corresponding I/O ports to input mode.

Table 10-3. Port Mode Group Flags

PM Group ID

Address

FE6H

FE7H

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

Bit 3

PM0.3

"0"

Bit 2

PM0.2

PM2.2

PM3.2

PM10.2

PM4.2

PM5.2

PM6.2

PM7.2

PM8.2

PM9.2

Bit 1

PM0.1

PM2.1

PM3.1

PM10.1

PM4.1

PM5.1

PM6.1

PM7.1

PM8.1

PM9.1

Bit 0

PM0.0

PM2.0

PM3.0

PM10.0

PM4.0

PM5.0

PM6.0

PM7.0

PM8.0

PM9.0

PMG1

PMG2

PMG3

PMG4

PMG5

PM3.3

PM10.3

PM4.3

PM5.3

PM6.3

PM7.3

PM8.3

PM9.3

NOTES:

1. If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode: PM0.0 for

P0.0, PM0.1 for P0.1, etc,. All flags are cleared to "0" after a RESET.

2. When PM8.0 and PM8.1 are set to “1”, P8.0 and 8.1 can be used as SEG51/LCDCK, SEG50/LCDSY output

only; P8.0 and P8.1 can not be used as push-pull output.

+

PROGRAMMING TIP — Configuring I/O Ports to Input or Output

Configure ports 0 and 2 as an output port:

BITS

SMB

LD

EMB

15

EA,#7FH

PMG1,EA

LD

; P0 and P2 ¬ Output

10-3

I/O PORTS

S3C7565/P7565

PULL-UP RESISTOR MODE REGISTER (PUMOD)

The pull-up resistor mode registers (PUMOD1 and PUMOD2) are used to assign internal pull-up resistors to

specific ports by software. When a configurable I/O port pin is used as an output pin, the pull-up resistor assigned

to it is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

PUMOD1 is addressable by 8-bit write instructions only, and PUMOD2 by 4-bit write instructions only. A RESET

clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up

resistors.

Table 10-4. Pull-up Resistor Mode Register (PUMOD) Organization

PUMOD ID

Address

FDCH

Bit 3

PUR3

PUR7

"0"

Bit 2

PUR2

PUR6

PUR10

Bit 1

PUR1

PUR5

PUR9

Bit 0

PUR0

PUR4

PUR8

PUMOD1

FDDH

PUMOD2

FDEH

NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2,

and so on.

+

PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-up Resistors

P6 and P7 enable pull-up resistors.

BITS

SMB

LD

EMB

15

EA,#0C0H

PUMOD1,EA

LD

; P6 and P7 enable

N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE)

The n-channel, open-drain mode register (PNE) is used to configure ports 0, 2 and 3 as n-channel open-drain or

push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to

n-channel open-drain; when set to "0", the output pin is configured to push-pull. The PNE register consists of an

8-bit register and a 4-bit register; PNE1 can be addressed by 8-bit write instructions only and PNE2 by 4-bit write

instructions only.

FD6H

FD7H

PNE0.3

“0”

PNE0.2

PNE2.2

PNE0.1

PNE2.1

PNE0.0

PNE2.0

PNE1

FD8H

PNE3.3

PNE3.2

PNE3.1

PNE3.0

PNE2

10-4

S3C7565/P7565

I/O PORTS

VLC1 REGISTER (VLC1R)

VLC1R register settings determine whether P2.1 would be used for digital input or analog input. VLC1R register

can be read or written by using 1-/4-bit RAM control instructions. VLC1R is mapped to the address FD9H and

initialized to logic zero by a RESET, which configures P2.1 as a digital input port.

FD9H

“0”

VLC1F

When VLC1F, bit 3 of VLC1R, is set to “1”, P2.1 is configured as an analog input pin for VLC1. When set to “0”, it

is configured as a digital input pin. To use P2.1 as VLCD for external LCD power supply, VLC1F must be set

to “1”.

PORT 7 MODE REGISTER (P7MOD)

P7MOD register settings determine whether port 7 would be used for analog or digital input. P7MOD is a 4-bit

write only register. P7MOD is mapped to the address FCEH and initialized to logic zero by a RESET, which

configures port 7 as a digital input port.

FCEH

P7MOD.3

P7MOD.2

P7MOD.1

P7MOD.0

When the bit is set to “1”, the corresponding pin is configured as an analog input pin. When set to “0”, it is

configured as a digital input pin: P7MOD.0 for P7.0, P7MOD.1 for P7.1, P7MOD.2 for P7.2, and P7MOD.3 for

P7.3

10-5

I/O PORTS

S3C7565/P7565

PORT 0 CIRCUIT DIAGRAM

VDD

PNE0.3

PNE0.2

PNE0.1

PNE0.0

PUR0

PPUURO0

PM0.3

PM0.2

PM0.1

PM0.0

SCK

P0.0/SCK

SO

P0.1/SO

Output

Latch

1,4

P0.2/SI

BUZ

P0.3/BUZ

CMOS Push-Pull,

N-Channel

Open-Drain

M

U

X

PM0.0

PM0.1

PM0.2

PM0.3

1,4

SCK

SI

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the

port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (PUMOD).

`

Figure 10-1. Port 0 Circuit Diagram

10-6

S3C7565/P7565

I/O PORTS

PORT 1 CIRCUIT DIAGRAM

VDD

INT0 INT1 INT2 INT4

PUMOD.1

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

Figure 10-2. Port 1 Circuit Diagram

10-7

I/O PORTS

S3C7565/P7565

PORT 0, 2 CIRCUIT DIAGRAM

VDD

PNE2.2

PNE2.1

PNE2.0

PPUURO2

PM2.2

PM2.1

PM2.0

CLO

P2.0/CLO

P2.1/VLC1

Output

Latch

1,4

P2.2

CMOS Push-Pull,

N-Channel

Open-Drain

PM2.0

M

U

X

PM2.1

PM2.2

1,4

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the

port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (PUMOD).

Figure 10-3. Port 2 Circuit Diagram

10-8

S3C7565/P7565

I/O PORTS

PORT 3 CIRCUIT DIAGRAM

VDD

PNE3.3

PNE3.2

PNE3.1

PNE3.0

PUR3

PPUURRO3

PM3.3

PM3.2

PM3.1

PM3.0

TCLO0

P3.0/TCLO0

P3.1/TCLO1

TCLO1

Output

Latch

1,4

P3.2/TCL0

P3.3/TCL1

CMOS Push-Pull,

N-Channel

Open-Drain

M

U

X

PM3.0

PM3.1

PM3.2

PM3.3

1,4

TCL0

TCL1

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the

port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (PUMOD).

Figure 10-4. Port 3 Circuit Diagram

10-9

I/O PORTS

S3C7565/P7565

PORT 4, 5, 6, 7, 8, 9, 10 CIRCUIT DIAGRAM

VDD

PURx

PPUURROx

x = port number (4, 5, 6, 7, 8, 9, 10)

PMx.3

PMx.2

PMx.1

PMx.0

Px.0

Px.1

Output

Latch

1,4,8

Px.2

Px.3

PMx.0

PMx.1

PMx.2

PMx.3

M

U

X

1,4,8

NOTES:

1. When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-

up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Port 6 is a schmitt trigger input.

2. When PM8.0 and PM8.1 are set to "1", port 8.0 and 8.1 can be used as SEG51/LCDCK, SEG50/LCDSY

output only. These ports can not be used as push-pull output port.

Figure 10-5. Ports 4, 5, 6, 7, 8, 9, and 10 Circuit Diagram

10-10

S3C7565/P7565

TIMERS and TIMER/COUNTERS

11 TIMERS and TIMER/COUNTERS

OVERVIEW

The S3C7565 microcontroller has four timer and timer/counter modules:

— 8-bit basic timer (BT)

— 8-bit timer/counter (TC0)

— 16-bit timer/counter (TC1, configurable as two 8-bit timer 1A/1B)

— Watch timer (WT)

The 8-bit basic timer (BT) is the microcontroller's main interval timer and watch-dog timer. It generates an

interrupt request at a fixed time interval when the appropriate modification is made to its mode register. The

basic timer is also used to determine clock oscillation stabilization time when stop mode is released by an

interrupt and after a RESET.

The 8-bit timer/counter (TC0) and the 16-bit timer/counter (TC1) are programmable timer/counters that are used

primarily for event counting and for clock frequency modification and output. In addition, TC1 generates a clock

signal that can be used by the serial I/O interface.

The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency

divider circuit. Watch timer functions include real-time and watch-time measurement, main and subsystem clock

interval timing, buzzer output generation. It also generates a clock signal for the LCD controller.

11-1

TIMERS and TIMER/COUNTERS

S3C7565/P7565

BASIC TIMER (BT)

OVERVIEW

The 8-bit basic timer (BT) has six functional components:

— Clock selector logic

— 4-bit mode register (BMOD)

— 8-bit counter register (BCNT)

— 8-bit watchdog timer mode register (WDMOD)

— Watchdog timer counter clear flag (WDTCF)

— 3-bit watchdog timer counter register (WDCNT)

The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.

You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize

clock oscillation when stop mode is released by an interrupt and following RESET. Bit settings in the basic timer

mode register BMOD turns the BT module on and off, selects the input clock frequency, and controls interrupt or

stabilization intervals.

Interval Timer Function

The basic timer's primary function is to measure elapsed time intervals. The standard time interval is equal to

256 basic timer clock pulses.

To restart the basic timer, one bit setting is required: bit 3 of the mode register BMOD should be set to logic one.

The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit

values to BMOD.2–BMOD.0.

The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the

frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs

(³ 255). An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the

designated time interval has elapsed. An interrupt request is than generated, BCNT is cleared to logic zero, and

counting continues from 00H.

Watchdog Timer Function

The basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation

error. For this purpose, instruction that clear the watchdog timer (BITS WDTCF) should be executed at proper

points in a program within given period. If an instruction that clears the watchdog timer is not executed within the

given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset

status. An operation of watchdog timer is as follows:

— Write some values (except #5AH) to watchdog timer mode register, WDMOD

— If WDCNT overflows, system reset is generated.

11-2

S3C7565/P7565

TIMERS and TIMER/COUNTERS

Oscillation Stabilization Interval Control

Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also

determines the time interval (also referred to as “wait time”) required to stabilize clock signal oscillation when

stop mode is released by an interrupt. When a RESET signal is inputted, the standard stabilization interval for

system clock oscillation following the RESET is 31.3 ms at 4.19 MHz.

Table 11-1. Basic Timer Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

Controls the clock frequency

(mode) of the basic timer; also,

the oscillation stabilization

interval after stop mode release

or RESET

4-bit write-only;

BMOD.3: 1-bit

writeable

BMOD

Control

4-bit

F85H

“0”

U ^(note)

A5H

“0”

Counts clock pulses matching

the BMOD frequency setting

8-bit read-only

8-bit write-only

1-, 4-bit write

BCNT

WDMOD

WDTCF

Counter

Control

8-bit F86H–F87H

8-bit F98H–F99H

Controls watchdog timer

operation.

Clears the watchdog timer’s

counter.

1-bit

F9AH.3

NOTE: “U” means the value is undetermined after a RESET.

11-3

TIMERS and TIMER/COUNTERS

S3C7565/P7565

"Clear" Signal

Clear

BCNT

Clear

IRQB

BITS

Instruction

BMOD.3

BMOD.2

BMOD.1

BMOD.0

Interrupt

Request

Overflow

Clock

Selector

BCNT

IRQB

4

1-Bit R/W

CPU Clock

Start Signal

8

(Power-Down Release)

Clock Input

1 Pulse Period = BT Input Clock 2⁸(1/2 Duty)

3-Bit Counter

Overflow

WDCNT

Reset Signal

Generation

RESET

Clear

WDMOD

8

WDTCF

BITS

DELAY

(note)

Stop

Clear

WAIT

RESET

Instruction

NOTES:

1. WAIT means the stabilization time after RESET or stabilization time after stop mode release.

2. The RESET signal can be generated if the WDMOD is toggled eight times. "Toggle" means to

change the value of WDMOD from 5AH to another value, or vice versa.

Figure 11-1. Basic Timer Circuit Diagram

11-4

S3C7565/P7565

TIMERS and TIMER/COUNTERS

BASIC TIMER MODE REGISTER (BMOD)

The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also

1-bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation

is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following

effects:

— Restart the basic timer;

— Control the frequency of clock signal input to the basic timer;

— Determine time interval required for clock oscillation to stabilize following the release of stop mode by an

interrupt.

By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency

during program execution. Four BT frequencies, ranging from fxx/2¹²to fxx/2⁵, are selectable. Since BMOD's

reset value is logic zero, the default clock frequency setting is fxx/2¹².

The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set

to logic one by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt

request flag (IRQB) are both cleared to logic zero, and timer operation restarts.

The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determine

the clock input frequency and oscillation stabilization interval.

Table 11-2. Basic Timer Mode Register (BMOD) Organization

BMOD.3

Basic Timer Start Control Bit

Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"

1

BMOD.2

BMOD.1

BMOD.0

Basic Timer Input Clock

Interrupt Interval Time

(Wait time when STOP mode

is released)

12

20

0

1

0

1

0

1

0

1

fxx/2 (1.02 kHz)

2

/fxx (250 ms)

/fxx (31.3 ms)

/fxx (7.82 ms)

/fxx (1.95 ms)

9

17

fxx/2 (8.18 kHz)

2

7

15

13

fxx/2 (32.7 kHz)

5

fxx/2 (131 kHz)

NOTES:

1. Clock frequencies and oscillation stabilization assume a system oscillator clock frequency (fxx) of 4.19 MHz.

2. fxx = system clock frequency.

3. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.

11-5

TIMERS and TIMER/COUNTERS

S3C7565/P7565

BASIC TIMER COUNTER (BCNT)

BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. RESET leaves the

BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register

control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the

frequency determined by the current BMOD bit settings is detected.

When BCNT has incrementing to hexadecimal “FFH” (³ 255 clock pulses), it is cleared to “00H” and an overflow

is generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt

request is generated, BCNT immediately resumes counting incoming clock signals.

NOTE

Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data

while the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can

select the latter value as valid data. Until the results of the consecutive reads match, however, the

read operation must be repeated until the validation condition is met.

BASIC TIMER OPERATION SEQUENCE

The basic timer's sequence of operations may be summarized as follows:

1. Set BMOD.3 to logic one to restart the basic timer

2. BCNT is then incremented by one after each clock pulse corresponding to BMOD selection

3. BCNT overflows if BCNT = 255 (BCNT = FFH)

4. When an overflow occurs, the IRQB flag is set by hardware to logic one

5. The interrupt request is generated

6. BCNT is then cleared by hardware to logic zero

7. Basic timer resumes counting clock pulses

11-6

S3C7565/P7565

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Basic Timer

1. To read the basic timer count register (BCNT):

BITS

SMB

EMB

15

BCNTR LD

EA,BCNT

YZ,EA

EA,BCNT

EA,YZ

BCNTR

LD

CPSE

JR

2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:

BITS

SMB

LD

EMB

15

A,#0BH

BMOD,A

LD

; Wait time is 31.3 ms

STOP

NOP

; Set stop power-down mode

Normal Mode

Stop Mode

Idle Mode

(31.3 ms)

Normal Mode

CPU

Operation

STOP

Instruction

Stop Mode is

Released by

Interrupt

3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):

BITS

SMB

LD

EMB

15

A,#0FH

BMOD,A

LD

EI

BITS

IEB

; Basic timer interrupt enable flag is set to "1"

4. Clear BCNT and the IRQB flag and restart the basic timer:

BITS

SMB

BITS

EMB

15

BMOD.3

11-7

TIMERS and TIMER/COUNTERS

S3C7565/P7565

WATCHDOG TIMER MODE REGISTER (WDMOD)

The watchdog timer mode register, WDMOD, is a 8-bit write-only register. WDMOD register controls to enable or

disable the watchdog function. WDMOD values are set to logic “A5H” following RESET and this value enables the

watchdog timer. Watchdog timer is set to the longest interval because BT overflow signal is generated with the

longest interval.

WDMOD

Watchdog Timer Enable/Disable Control

Disable watchdog timer function

Enable watchdog timer function

5AH

Any other value

WATCHDOG TIMER COUNTER (WDCNT)

The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and

restarts whenever the WDTCF register control bit is set to “1”. RESET, stop, and wait signal clears the WDCNT to

logic zero also.

WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit

setting is generated. When WDCNT has incremented to hexadecimal “07H”, it is cleared to “00H” and an

overflow is generated. The overflow causes the system RESET. When the interrupt request is generated, BCNT

immediately resumes counting incoming clock signals.

WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF)

The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears

the WDCNT to zero and restarts the WDCNT. WDTCF register bits 2–0 are always logic zero.

Table 11-3. Watchdog Timer Interval Time

BMOD

x000b

x011b

x101b

x111b

BT Input Clock

fxx/2¹²

WDCNT Input Clock

fxx/(2¹²´ 2⁸)

fxx/(2⁹´ 2⁸)

WDT Interval Time

(7 or 8) ³´ (2¹²´ 2⁸)/fxx = 1.75–2 sec

(7 or 8) ³´ (2⁹´ 2⁸)/fxx = 218.7–250 ms

(7 or 8) ³´ (2⁷´ 2⁸)/fxx = 54.6–62.5 ms

(7 or 8)³´ (2⁵´ 2⁸)/fxx = 13.6–15.6 ms

fxx/2⁹

fxx/2⁷

fxx/(2⁷´ 2⁸)

fxx/2⁵

fxx/(2⁵´ 2⁸)

NOTES:

1. Clock frequencies assume a system oscillator clock frequency (fxx) of 4.19 MHz.

2. fxx = system clock frequency.

11-8

S3C7565/P7565

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Watchdog Timer

RESET

DI

LD

EA,#00H

SP,EA

·

LD

A,#0DH

; WDCNT input clock is 7.82 ms

LD

BMOD,A

·

MAIN

BITS

WDTCF

MAIN

; Main routine operation period must be shorter than

; watchdog-timer’s period

·

JP

11-9

TIMERS and TIMER/COUNTERS

S3C7565/P7565

8-BIT TIMER/COUNTER 0 (TC0)

OVERVIEW

Timer/counter 0 (TC0) is used to count system “events” by identifying the transition (high-to-low or low-to-high) of

incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has

elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter

value with the reference register value, TC0 can be used to measure specific time intervals.

TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write

the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by

counter logic.

An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to

be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into

the TMOD0 register during program execution.

TC0 FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock

frequency.

Counts various system "events" based on edge detection of external clock

signals at the TC0 input pin, TCL0. To start the event counting operation,

TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0".

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC0 output pin, TCLO0.

Divides the frequency of an incoming external clock signal according to a

modifiable reference value (TREF0), and outputs the modified frequency to the

TCLO0 pin.

11-10

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC0 COMPONENT SUMMARY

Mode register (TMOD0)

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCL0 pin.

Reference register (TREF0)

Counter register (TCNT0)

Clock selector circuit

8-bit comparator

Stores the reference value for the desired number of clock pulses between

interrupt requests.

Counts internal or external clock pulses based on the bit settings in TMOD0

and TREF0.

Together with the mode register (TMOD0), lets you select one of four internal

clock frequencies or an external clock.

Determines when to generate an interrupt by comparing the current value of

the counter register (TCNT0) with the reference value previously programmed

into the reference register (TREF0).

Output latch (TOL0)

Where a clock pulse is stored pending output to the TC0 output pin, TCLO0.

When the contents of the TCNT0 and TREF0 registers coincide, the

timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is

inverted, and an interrupt is generated.

Output enable flag (TOE0)

Must be set to logic one before the contents of the TOL0 latch can be output to

TCLO0.

Interrupt request flag (IRQT0) Cleared when TC0 operation starts and the TC0 interrupt service routine is

executed and set to 1 whenever the counter value and reference value

coincide.

Interrupt enable flag (IET0)

Must be set to logic one before the interrupt requests generated by

timer/counter 0 can be processed.

Table 11-4. TC0 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

TMOD0

Control

8-bit F90H–F91H

"0"

Controls TC0 enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and clock frequency

(bits 6–4)

8-bit write-only;

(TMOD0.3 is also

1-bit writeable)

TCNT0

TREF0

TOE0

Counter

Reference

Flag

8-bit F94H–F95H

8-bit F96H–F97H

"0"

FFH

"0"

Counts clock pulses matching

the TMOD0 frequency setting

8-bit read-only

8-bit write-only

Stores reference value for the

timer/counter 0 interval setting

1-bit

F92H.2

Controls timer/counter 0 output

to the TCLO0 pin

1/4-bit read or

write

11-11

TIMERS and TIMER/COUNTERS

S3C7565/P7565

Clocks

(fxx/2¹⁰, fxx/2⁶, fxx/2⁴, fxx)

TCL0

8

TMOD0.7

TMOD0.6

8-Bit

Comparator

TCNT0

TREF0

Clock

Selector

TMOD0.5

8

TMOD0.4

Clear

TMOD0.3

TMOD0.2

TMOD0.1

TMOD0.0

Inverted

TOL0

Clear

Set

IRQT0

Clear

TCLO0

PM3.0

P3.0 Latch

TOE0

Figure 11-2. TC0 Circuit Diagram

TC0 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 0

— Set TMOD0.2 to logic one

— Set the TC0 interrupt enable flag IET0 to logic one

— Set TMOD0.3 to logic one

TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 0

— Set TMOD0.2 to logic zero

Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read

if necessary.

11-12

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected

system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select

the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be

generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are

compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt

request is generated.

To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock

frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF0 register.

TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD0.4–TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag

(IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0

is then cleared to 00H and TC0 continues counting. The interrupt request mechanism for TC0 includes an

interrupt enable flag (IET0) and an interrupt request flag (IRQT0).

TC0 OPERATION SEQUENCE

The general sequence of operations for using TC0 can be summarized as follows:

1. Set TMOD0.2 to "1" to enable TC0.

2. Set TMOD0.6 to "1" to enable the system clock (fxx) input.

n

3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fxx/2 ).

4. Load a value to TREF0 to specify the interval between interrupt requests.

5. Set the TC0 interrupt enable flag (IET0) to "1".

6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting.

7. TCNT0 increments with each internal clock pulse.

8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1" and an interrupt request is

generated.

9. Output latch (TOL0) logic toggles high or low.

10. TCNT0 is cleared to 00H and counting resumes.

11. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".

11-13

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC0 EVENT COUNTER FUNCTION

Timer/counter 0 can monitor or detect system “events” by using the external clock input at the TCL0 pin as the

counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The

counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD0.4–TMOD0.6 settings, the operation sequence for TC0's event counter

function is identical to its programmable timer/counter function. To activate the TC0 event counter function,

— Set TMOD0.2 to "1" to enable TC0;

— Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin;

— Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5

and TMOD0.4.

— P3.2 must be set to input mode.

Table 11-5. TMOD0 Settings for TCL0 Edge Detection

TMOD0.5

TMOD0.4

TCL0 Edge Detection

Rising edges

Falling edges

0

1

11-14

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC0 CLOCK FREQUENCY OUTPUT

Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select

the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected

by loading the desired reference value into the reference register TREF0. To enable the output to the TCLO0 pin,

the following conditions must be met:

— TC0 output enable flag TOE0 must be set to "1"

— I/O mode flag for P3.0 (PM3.0) must be set to output mode ("1")

— Output latch value for P3.0 must be set to "0"

In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as

follows:

1. Load a reference value to TREF0.

2. Set the internal clock frequency in TMOD0.

3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1").

4. Set P3.0 mode flag (PM3.0) to "1".

5. Set P3.0 output latch to "0".

6. Set TOE0 flag to "1".

Each time the contents of TCNT0 and TREF0 coincide and an interrupt request is generated, the state of the

output latch TOL0 is inverted and the TC0-generated clock signal is output to the TCLO0 pin.

+

PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin

Output a 30 ms pulse width signal to the TCLO0 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

EA,#01H

PMG2,EA

P3.0

; P3.0 ¬ output mode

; P3.0 clear

TOE0

11-15

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC0 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you

can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the

TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows:

1. Load a signal divider value to the TREF0 register.

2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin.

3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection.

4. Set port 3.0 mode flag (PM3.0) to output ("1").

5. Set P3.0 output latch to "0".

6. Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin

+

PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin

Output external TCL0 clock pulse to the TCLO0 pin (divided by four):

External (TCL0)

Clock Pulse

TCLO0

Output Pulse

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF0,EA

EA,#0CH

TMOD0,EA

EA,#01H

PMG2,EA

P3.0

; P3.0 ¬ output mode

; P3.0 clear

TOE0

11-16

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC0 MODE REGISTER (TMOD0)

TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit,

TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations.

F90H

F91H

TMOD0.3

"0"

TMOD0.2

TMOD0.6

"0"

TMOD0.5

TMOD0.4

TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,

IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal

TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are

retained until TC0 is re-enabled.

The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL0 pin, and

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC0 operation.

Table 11-6. TC0 Mode Register (TMOD0) Organization

Bit Name

TMOD0.7

TMOD0.6

TMOD0.5

TMOD0.4

TMOD0.3

Setting

Resulting TC0 Function

Address

0

Always logic zero

0,1

F91H

Specify input clock edge and internal frequency

1

Clear TCNT0, IRQT0, and TOL0 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes.)

TMOD0.2

0

1

0

F90H

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Always logic zero

11-17

TIMERS and TIMER/COUNTERS

S3C7565/P7565

Table 11-7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings

TMOD0.6

TMOD0.5

TMOD0.4

Resulting Counter Source and Clock Frequency

0

1

0

1

0

1

0

1

0

1

External clock input (TCL0) on rising edges

External clock input (TCL0) on falling edges

fxx/2¹⁰(4.09 kHz)

fxx/2⁶(65.5 kHz)

fxx/2⁴(262 kHz)

fxx = 4.19 MHz

NOTE: “fxx” = selected system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC0 Counting Operation

1. Set TC0 timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD0,EA

LD

EI

BITS

IET0

2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:

BITS

SMB

BITS

EMB

15

TMOD0.3

11-18

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC0 COUNTER REGISTER (TCNT0)

The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control

instructions. RESET sets all TCNT0 register values to logic zero (00H).

Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. The TCNT0 register

value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency

setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4).

Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 reference

buffer, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag,

IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter

interval has elapsed.

Count

Clock

TREF0

TCNT0

Reference Value = n

n

0

1

2

n-1

0

1

2

n-1

0

1

2

3

Match

TOL0

Interval Time

Timer Start Instruction

(TMOD0.3 is set)

IRQT0 Set

Figure 11-3. TO0 Timing Diagram

11-19

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC0 REFERENCE REGISTER (TREF0)

The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control

instructions. RESET initializes the TREF0 value to “FFH”.

TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used

to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output

source.

During timer/counter operation, the value loaded into the reference register is compared to the TCNT0 value.

When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal

the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the

specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0

reference register:

1

TC0 timer interval = (TREF0 value + 1) ´

TMOD0 frequency setting

(TREF0 value ¹ 0)

TC0 OUTPUT ENABLE FLAG (TOE0)

The 8-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0

is addressable by 1/4-bit read or write instructions.

(MSB)

TOE1

(LSB)

TOL2

F92H

"0"

TOE0

When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET

occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled,

timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0.

TC0 OUTPUT LATCH (TOL0)

TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the

value of the counter register TCNT0 and the reference value stored in the TREF0 register, the TOL0 value is

inverted — the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal

is output. TC0 output may be directed to the TCLO0 pin, or it can be output directly to the serial I/O clock selector

circuit as the SCK signal.

Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero,

along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately.

When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if

necessary.

11-20

S3C7565/P7565

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Setting a TC0 Timer Interval

To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps.

1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter

10

clock = fxx/2 , and TREF0 is set to FFH):

2. Calculate the TREF0 value:

TREF0 value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF0 + 1 =

= 122.9 = 7AH

TREF0 value = 7AH – 1 = 79H

3. Load the value 79H to the TREF0 register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

LD

11-21

TIMERS and TIMER/COUNTERS

S3C7565/P7565

16-BIT TIMER/COUNTER 1

OVERVIEW

The 16-bit timer/counter functions as one 16-bit timer/counter or two 8-bit timer/counters. When the 16-bit

timer/counter functions as one 16-bit timer/counter, it is called timer/counter 1 (TC1), and when it functions as

two 8-bit timer/counters, it is called timer/counter 1A (TC1A), and timer/counter 1B (TC1B).

When the mode register bit, TMOD1A.7 is set to "1", the 16-bit timer/counter functions as one 16-bit

timer/counter, and when the mode register bit, TMOD1A.7 is set to "0", the 16-bit timer/counter functions as two

8-bit timer/counters.

The only functional differences between TC1 and TC1A are the sizes of the counter and reference value

registers (16-bit versus 8-bit).

The functional differences between TC1A and TC1B are the fact that only TC1A has the external event counter

and external signal divider function, and can generate a clock signal for the serial I/O interface.

The only functional difference between TC0 and TC1A is the fact that only TC1A can generate a clock signal, for

the serial I/O interface.

One 16-bit timer/counter mode (Timer/counter 1)

Two 8-bit timer/counters mode (Timer/counter 1A, 1B)

11-22

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TIMER/COUNTER 1 FUNCTION SUMMARY

16-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock

frequency.

Counts various system "events" based on edge detection of external clock

signals at the TC1 input pin, TCL1.

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC1 output pin, TCLO1.

Divides the frequency of an incoming external clock signal according to the

modifiable reference value (TREF1), and outputs the modified frequency to

the TCLO1 pin.

Serial I/O clock source

Outputs a modifiable clock signal for use as the SCK clock source.

11-23

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TIMER/COUNTER 1 COMPONENT SUMMARY

Mode register (TMOD1A)

Reference register (TREF1)

Counter register (TCNT1)

Clock selector circuit

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCL1 pin.

Stores the reference value for the desired number of clock pulses between

interrupt requests.

Counts internal clock pulses that are generated based on bit settings in the

mode register and reference register.

Together with the mode register (TMOD1A), lets you select one of four internal

clock frequencies, or the external system clock source.

16-bit comparator

Determines when to generate an interrupt by comparing the current value of

the counter (TCNT1) with the reference value previously programmed into the

reference register (TREF1).

Output latch (TOL1)

Where a TC1 clock pulse is stored pending output to the serial I/O circuit or to

the TC1 output pin, TCLO1. When the contents of the TCNT1 and TREF1

registers coincide, the timer/counter interrupt request flag (IRQT1) is set to "1",

the status of TOL1 is inverted, and an interrupt is generated.

Output enable flag (TOE1)

Must be set to logic one before the contents of the TOL1 latch can be output to

TCLO1.

Interrupt request flag (IRQT1) Cleared when TC1 operation starts and set to logic one whenever the counter

value and reference value match.

Interrupt enable flag (IET1)

Must be set to logic one before the interrupt requests generated by

timer/counter 1 can be processed.

Table 11-8. TC1 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

TMOD1A

Control

8-bit

FA0H–FA1H

"0"

Controls TC1 enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and the clock

frequency (bits 6–4)

8-bit write-only;

(TMOD1A.3 is

also 1-bit

writeable)

(TMOD1A.7 is

"1")

Select 16-bit TC1 or two 8-bit

TC1A and TC1B (bit 7)

TCNT1

TREF1

TOE1

Counter

Reference

Flag

16-bit FA4H–FA5H,

FA6H–FA7H

"0"

FFFFH

"0"

Counts clock pulses matching

the TMOD1A frequency setting

8-bit read-only

8-bit write-only

16-bit FA8H–FA9H,

FAAH–FABH

Stores reference value for TC1

interval setting

1-bit

F92H.3

Controls TC1 output to the

TCLO1 pin

1/4-bit read or

write

11-24

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TCL1

TMOD1B.7

TMOD1B.6

TMOD1B.5

TMOD1B.4

TMOD1B.3

TMOD1B.2

TMOD1B.1

TMOD1B.0

TMOD1A.7

TMOD1A.6

TMOD1A.5

TMOD1A.4

TMOD1A.3

TMOD1A.2

TMOD1A.1

TMOD1A.0

Clocks

(fx/2¹⁰, fx/2 ⁶, fx/2 ⁴, fxx)

DB

16

TCNT1

(16-Bit)

16-Bit

Comparator

TREF1

(16-Bit)

Clock

Selector

Clear

8

/

Clear

Set

Clear

TOL1

IRQT1

Serial I/O

TCLO1

PM3.1

P3.1 Latch

TOE1

NOTE:

TMOD1A.7 = 1, TMOD1A.0/TMOD1A.1 = 0

The content of TMOD1B register is "Don't care"

Figure 11-4. TC1 Circuit Diagram

11-25

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 1

— Set the TC1 interrupt enable flag IET1 to logic one

— Set TMOD1A.3 to logic one

TCNT1, IRQT1, and TOL1 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 1

— Set TMOD1A.2 to logic zero

Clock signal input to the counter register TCNT1 is halted. The current TCNT1 value is retained and can be read

if necessary.

TC1 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 1 can be programmed to generate interrupt requests at variable intervals, based on the system

clock frequency you select. The 8-bit TC1 mode register, TMOD1A, is used to activate the timer/counter and to

select the clock frequency; the 16-bit reference register, TREF1, is used to store the value for the desired

number of clock pulses between interrupt requests. The 16-bit counter register, TCNT1, counts the incoming

clock pulses, which are compared to the TREF1 value. When there is a match, an interrupt request is generated.

To program timer/counter 1 to generate interrupt requests at specific intervals, select one of the four internal

clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF1 register.

TCNT1 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD1A.4–TMOD1A.6 settings. To generate an interrupt request, the TC1 interrupt request flag

(IRQT1) is set to logic one, the status of TOL1 is inverted, and the interrupt is output. The content of TCNT1 is

then cleared to 0000H, and TC1 continues counting. The interrupt request mechanism for TC1 includes an

interrupt enable flag (IET1) and an interrupt request flag (IRQT1).

TC1 TIMER/COUNTER OPERATION SEQUENCE

The general sequence of operations for using TC1 can be summarized as follows:

1. Set TMOD1A.7 to "1" to be operated as timer/counter 1.

2. Set TMOD1A.2 to "1" to enable TC1.

3. Set TMOD1A.6 to "1" to enable the system clock (fxx) input.

4. Set TMOD1A.5 and TMOD1A.4 bits to desired internal frequency (fxx/2ⁿ).

5. Load a value to TREF1 to specify the interval between interrupt requests.

6. Set the TC1 interrupt enable flag (IET1) to "1".

7. Set TMOD1A.3 bit to "1" to clear TCNT1, IRQT1, and TOL1, and start counting.

8. TCNT1 increments with each internal clock pulse.

9. When the comparator shows TCNT1 = TREF1, the IRQT1 flag is set to "1" and an interrupt request is

generated.

10. Output latch (TOL1) logic toggles high or low.

11. TCNT1 is cleared to 0000H and counting resumes.

12. Programmable timer/counter operation continues until TMOD1A.2 is cleared to "0".

11-26

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1 EVENT COUNTER FUNCTION

Timer/counter 1 can monitor system "events" by using the external clock input at the TCL1 pin as the counter

source. The TC1 mode register selects rising or falling edge detection for incoming clock signals. The counter

register TCNT1 is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD1A.4–TMOD1A.6 settings, the operation sequence for TC1's event

counter function is identical to its programmable timer/counter function. To activate the TC1 event counter

function,

— Set TMOD1A.7 to "1" to be operated as timer/counter 1.

— Set TMOD1A.2 to "1" to enable TC1.

— Clear TMOD1A.6 to "0" to select the external clock source at the TCL1 pin.

— Select TCL1 edge detection for rising or falling signal edges by loading the appropriate values to TMOD1A.5

and TMOD1A.4.

— Pin P3.3 must be set to input mode.

Table 11-9. TMOD1A Settings for TCL1 Edge Detection

TMOD1A.5

TMOD1A.4

TCL1 Edge Detection

Rising edges

Falling edges

0

1

11-27

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1 CLOCK FREQUENCY OUTPUT

Using timer/counter 1, a modifiable clock frequency can be output to the TC1 clock output pin, TCLO1. To select

the clock frequency, load the appropriate values to the TC1 mode register, TMOD1A. The clock interval is

selected by loading the desired reference value into the 16-bit reference register TREF1. To enable the output to

the TCLO1 pin at I/O port 3.1, the following conditions must be met:

— TC1 output enable flag TOE1 must be set to "1".

— I/O mode flag for P3.1 (PM3.1) must be set to output mode ("1").

— P3.1 output latch must be cleared to "0".

In summary, the operational sequence required to output a TC1-generated clock signal to the TCLO1 pin is as

follows:

1. Load your reference value to TREF1.

2. Set the internal clock frequency in TMOD1A.

3. Initiate TC1 clock output to TCLO1 (TMOD1A.2 = "1").

4. Set port 3.1 mode flag (PM3.1) to "1".

5. Clear the P3.1 output latch.

6. Set TOE1 flag to "1".

Each time the contents of TCNT1 and TREF1 coincide and an interrupt request is generated, the state of the

output latch TOL1 is inverted and the TC1-generated clock signal is output to the TCLO1 pin.

+

PROGRAMMING TIP — TC1 Signal Output to the TCLO1 Pin

Output a 30 ms pulse width signal to the TCLO1 pin:

BITS

SMB

LD

EMB

15

EA,#79H

TREF1A,EA

EA,#00H

TREF1B,EA

EA,#0CCH

TMOD1A,EA

EA,#02H

PMG2,EA

P3.1

LD

BITR

BITS

; P3.1 ¬ output mode

; P3.1 clear

TOE1

11-28

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1 SERIAL I/O CLOCK GENERATION

Timer/counter 1 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter

and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register,

SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.

Use TMOD1A and TREF1A, TREF1B register settings to select the frequency and interval of the TC1 clock

signals to be used as SCK input to the serial interface. The generated clock signal is then sent directly to the

serial I/O clock selector circuit (the TOE1 flag may be disabled).

TC1 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC1 reference register, TREF1, you

can divide the incoming clock signal by the TREF1 value and then output this modified clock frequency to the

TCLO1 pin. The sequence of operations used to divide external clock input and output the signals to the TCLO1

pin can be summarized as follows:

1. Load a signal divider value to the TREF1 register.

2. Set TMOD1A.7 to "1" to be operated as timer/counter 1.

3. Clear TMOD1A.6 to "0" to enable external clock input at the TCLO1 pin.

4. Set TMOD1A.5 and TMOD1A.4 to desired TCL1 signal edge detection.

5. Set P3.1 mode flag (PM3.1) to output ("1").

6. Clear the P3.1 output latch.

7. Set TOE1 flag to "1" to enable output of the divided frequency.

+

PROGRAMMING TIP — External TCL1 Clock Output to the TCLO1 Pin

Output the external TCL1 clock source to the TCLO1 pin (divide by four):

External (TCL1)

Clock Pulse

TCLO1

Output Pulse

BITS

SMB

LD

EMB

15

EA,#01H

TREF1A,EA

EA,#00H

TREF1B,EA

EA,#8CH

TMOD1A,EA

EA,#02H

PMG2,EA

P3.1

LD

BITR

BITS

; P3.1 ¬ output mode

; P3.1 clear

TOE1

11-29

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1 MODE REGISTER (TMOD1A)

TMOD1A is the 8-bit mode register for timer/counter 1. It is addressable by 8-bit write instructions. The

TMOD1A.3 bit is also 1-bit write addressable. RESET clears all TMOD1A bits to logic zero. Following a RESET,

timer/counter 1 is disabled.

FA0H

FA1H

TMOD1A.3 TMOD1A.2

"0"

TMOD1A.7 TMOD1A.6 TMOD1A.5 TMOD1A.4

TMOD1A.7 is the mode selection bit for one 16-bit timer/counter or two 8-bit timer/counters. TMOD1A.2 is the

enable/disable bit for timer/counter 1. When TMOD1A.3 is set to "1", the contents of TCNT1, IRQT1, and TOL1

are cleared, counting starts from 0000H, and TMOD1A.3 is automatically reset to "0" for normal TC1 operation.

When TC1 operation stops (TMOD1A.2 = "0"), the contents of the TC1 counter register, TCNT1, are retained

until TC1 is re-enabled.

The TMOD1A.6, TMOD1A.5, and TMOD1A.4 bit settings are used together to select the TC1 clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL1 pin

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC1 operations.

Table 11-10. TC1 Mode Register (TMOD1A) Organization

Bit Name

Setting

Resulting TC1 Function

Address

TMOD1A.7

0,1

Configure as one 16-bit timer/counter 1 or two 8-bit

timer/counters 1A, 1B.

TMOD1A.6

TMOD1A.5

TMOD1A.4

TMOD1A.3

0,1

1

FA1H

Specify input clock edge and internal frequency

FA0H

Clear TCNT1, IRQT1, and TOL1 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes).

TMOD1A.2

0

1

0

Disable timer/counter 1; retain TCNT1 contents

Enable timer/counter 1

TMOD1A.1

TMOD1A.0

Always logic zero

11-30

S3C7565/P7565

TIMERS and TIMER/COUNTERS

Table 11-11. TMOD1A.6, TMOD1A.5, and TMOD1A.4 Bit Settings

TMOD1A.6

TMOD1A.5

TMOD1A.4

Resulting Counter Source and Clock Frequency

External clock input (TCL1) on rising edges

External clock input (TCL1) on falling edges

fxx/2¹⁰= 4.09 kHz

0

1

0

1

0

1

0

1

0

1

fxx/2⁶= 65.5 kHz

fxx/2⁴= 262 kHz

fxx = 4.19 MHz

NOTE: “fxx” = selected system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC1 Counting Operation

1. Set TC1 timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#0CCH

TMOD1A,EA

LD

EI

BITS

IET1

2. Clear TCNT1, IRQT1, and TOL1 and restart TC1 counting operation:

BITS

SMB

BITS

EMB

15

TMOD1A.3

11-31

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1 COUNTER REGISTER (TCNT1)

The 16-bit counter register for timer/counter 1, TCNT1, is mapped to RAM addresses FA5H–FA4H (TCNT1A)

and FA7H–FA6H (TCNT1B). The two 8-bit registers are read-only and can be addressed by 8-bit RAM control

instructions. RESET sets all TCNT1 register values to logic zero (00H).

Whenever TMOD1A.2 and TMOD1A.3 are enabled, TCNT1 is cleared to logic zero and counting begins. The

TCNT1 register value is incremented each time an incoming clock signal is detected that matches the signal

edge and frequency setting of the TMOD1A register (specifically, TMOD1A.6, TMOD1A.5, and TMOD1A.4).

Each time TCNT1 is incremented, the new value is compared to the reference value stored in the TC1 reference

register, TREF1. When TCNT1 = TREF1, an overflow occurs in the TCNT1 register, the interrupt request flag,

IRQT1, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter

interval has elapsed.

Count

Clock

TREF1

TCNT1

Reference Value = n

n

0

1

2

n-1

0

1

2

n-1

0

1

2

3

Match

TOL1

Interval Time

Timer Start Instruction

(TMOD1A.3 is set)

IRQT1 Set

Figure 11-5. TC1 Timing Diagram

11-32

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1 REFERENCE REGISTER (TREF1)

The TC1 reference register TREF1 is a 16-bit write-only register that is mapped to RAM locations FA9H–FA8H

(TREF1A) and FABH–FAAH (TREF1B). It is addressable by 8-bit RAM control instructions. RESET clears the

TREF1 value to "FFFFH".

TREF1 is used to store a reference value to be compared to the incrementing TCNT1 register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC1 is being used

to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output

source.

During timer/counter operation, the value loaded into the reference register compared to the TCNT1 value.

When TCNT1 = TREF1, the TC1 output latch (TOL1) is inverted and an interrupt request is generated to signal

the interval or event. The TREF1 value, together with the TMOD1A clock frequency selection, determines the

specific TC1 timer interval. Use the following formula to calculate the correct value to load to the TREF1

reference register:

1

TC1 timer interval = (TREF1 value + 1) ´

TMOD1A frequency setting

(TREF1 value ¹ 0)

TC1 OUTPUT ENABLE FLAG (TOE1)

The 16-bit timer/counter 1 output enable flag TOE1 flag controls output from timer/counter 1 to the TCLO1 pin.

TOE1 is addressable by 1/4-bit read or write instructions.

Bit 2

Bit 1

"0"

Bit 0

Bit 3

F92H

TOE0

TOL2

TOE1

When you set the TOE1 flag to "1", the contents of TOL1 can be output to the TCLO1 pin. Whenever a RESET

occurs, TOE1 is automatically set to logic zero, disabling all TC1 output.

TC1 OUTPUT LATCH (TOL1)

TOL1 is the output latch for timer/counter 1. When the 16-bit comparator detects a correspondence between the

value of the counter register TCNT1 and the reference value stored in the TREF1 register, the TOL1 logic

toggles high-to-low or low-to-high. Whenever the state of TOL1 is switched, the TC1 signal exits the latch for

output. TC1 output is directed (if TOE1 = "1") to the TCLO1 pin at I/O port 3.1.

When timer/counter 1 is started, (TMOD1A.3 = "1"), the contents of the output latch are cleared automatically.

However, when TC1 is disabled (TMOD1A.2 = "0"), the contents of the TOL1 latch are retained and can be read,

if necessary.

11-33

TIMERS and TIMER/COUNTERS

S3C7565/P7565

+

PROGRAMMING TIP — Setting a TC1 Timer Interval

To set a 30 ms timer interval for TC1, given fxx = 4.19 MHz, follow these steps:

1. Select the timer/counter 1 mode register with a maximum setup time of 16 seconds;

assume the TC1 counter clock = fxx/2¹⁰and TREF1 is set to FFFFH.

2. Calculate the TREF1 value:

TREF1 value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF1 + 1 =

= 122.9 = 7AH

TREF1 value = 7AH – 1 = 79H

3. Load the value 79H to the TREF1 register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF1A,EA

EA,#00H

TREF1B,EA

EA,#0CCH

TMOD1A,EA

11-34

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TIMER/COUNTER 1A FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock

frequency.

Counts various system "events" based on edge detection of external clock

signals at the TC1 input pin, TCL1.

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC1 output pin, TCLO1.

Divides the frequency of an incoming external clock signal according to the

modifiable reference value (TREF1A), and outputs the modified frequency

to the TCLO1 pin.

Serial I/O clock source

Outputs a modifiable clock signal for use as the SCK clock source.

11-35

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TIMER/COUNTER 1A COMPONENT SUMMARY

Mode register (TMOD1A)

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCL1 pin.

Reference register (TREF1A) Stores the reference value for the desired number of clock pulses between

interrupt requests.

Counter register (TCNT1A)

Clock selector circuit

8-bit comparator

Counts internal clock pulses that are generated based on bit settings in the

mode register and reference register.

Together with the mode register (TMOD1A), lets you select one of four internal

clock frequencies, or the external system clock source.

Determines when to generate an interrupt by comparing the current value of

the counter (TCNT1A) with the reference value previously programmed into

the reference register (TREF1A).

Output latch (TOL1)

Where a TC1A clock pulse is stored pending output to the serial I/O circuit or

to the TC1A output pin, TCLO1. When the contents of the TCNT1A and

TREF1A registers coincide, the timer/counter interrupt request flag (IRQT1) is

set to "1", the status of TOL1 is inverted, and an interrupt is generated.

Output enable flag (TOE1)

Must be set to logic one before the contents of the TOL1 latch can be output to

TCLO1.

Interrupt request flag (IRQT1) Cleared when TC1A operation starts and set to logic one whenever the counter

value and reference value match.

Interrupt enable flag (IET1)

Must be set to logic one before the interrupt requests generated by

timer/counter 1A can be processed.

Table 11-12. TC1A Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

TMOD1A

8-bit FA0H–FA1H

"0"

Control

Controls TC1A enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and the clock

frequency (bits 6–4)

8-bit write-only;

(TMOD1A.3 is

also 1-bit

writeable)

(TMOD1A.7 is

"0")

Select 16-bit TC1 or two 8-bit

TC1A and TC1B (bit 7)

TCNT1A

TREF1A

TOE1

8-bit FA4H–FA5H

8-bit FA8H–FA9H

"0"

FFH

"0"

Counter

Counts clock pulses matching

the TMOD1A frequency setting

8-bit read-only

8-bit write-only

Reference Stores reference value for

TC1A interval setting

1-bit

F92H.3

Flag

Controls TC1A output to the

TCLO1 pin

1/4-bit read or

write

11-36

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TCL1

TMOD1B.7

TMOD1B.6

TMOD1B.5

TMOD1B.4

TMOD1B.3

TMOD1B.2

TMOD1B.1

TMOD1B.0

TMOD1A.7

TMOD1A.6

TMOD1A.5

TMOD1A.4

TMOD1A.3

TMOD1A.2

TMOD1A.1

TMOD1A.0

Clocks

(fx/2¹⁰, fx/2 ⁶, fx/2 ⁴, fxx)

DB

8

8-Bit

TCNT1A

TREF1A

Comparator

Clock

Selector

Clear

8

/

Clear

Set

IRQT1

Clear

TOL1

Serial I/O

TCLO1

PM3.1

P3.1 Latch

TOE1

NOTE:

TMOD1A.7 = 1, TMOD1A.0/TMOD1A.1 = 0

Figure 11-6. TC1A Circuit Diagram

11-37

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1A ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 1A

— Set the TC1A interrupt enable flag IET1 to logic one

— Set TMOD1A.3 to logic one

TCNT1A, IRQT1, and TOL1 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 1A

— Set TMOD1A.2 to logic zero

Clock signal input to the counter register TCNT1A is halted. The current TCNT1A value is retained and can be

read if necessary.

TC1A PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 1A can be programmed to generate interrupt requests at variable intervals, based on the system

clock frequency you select. The 8-bit TC1A mode register, TMOD1A, is used to activate the timer/counter and to

select the clock frequency; the 8-bit reference register, TREF1A, is used to store the value for the desired

number of clock pulses between interrupt requests. The 8-bit counter register, TCNT1A, counts the incoming

clock pulses, which are compared to the TREF1A value. When there is a match, an interrupt request is

generated.

To program Timer/counter 1A to generate interrupt requests at specific intervals, select one of the four internal

clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF1A

register. TCNT1A is incremented each time an internal counter pulse is detected with the reference clock

frequency specified by TMOD1A.4–TMOD1A.6 settings. To generate an interrupt request, the TC1A interrupt

request flag (IRQT1) is set to logic one, the status of TOL1 is inverted, and the interrupt is output. The content of

TCNT1A is then cleared to 00H, and TC1A continues counting. The interrupt request mechanism for TC1A

includes an interrupt enable flag (IET1) and an interrupt request flag (IRQT1).

TC1A TIMER/COUNTER OPERATION SEQUENCE

The general sequence of operations for using TC1A can be summarized as follows:

1. Set TMOD1A.7 to "0" to be operated as timer/counter 1A, 1B.

2. Set TMOD1A.2 to "1" to enable TC1A.

3. Set TMOD1A.6 to "1" to enable the system clock (fxx) input.

n

4. Set TMOD1A.5 and TMOD1A.4 bits to desired internal frequency (fxx/2 ).

5. Load a value to TREF1A to specify the interval between interrupt requests.

6. Set the TC1A interrupt enable flag (IET1) to "1".

7. Set TMOD1A.3 bit to "1" to clear TCNT1A, IRQT1, and TOL1, and start counting.

8. TCNT1A increments with each internal clock pulse.

9. When the comparator shows TCNT1A = TREF1A, the IRQT1 flag is set to "1" and an interrupt request is

generated.

10. Output latch (TOL1) logic toggles high or low.

11. TCNT1A is cleared to 0000H and counting resumes.

12. Programmable timer/counter operation continues until TMOD1A.2 is cleared to "0".

11-38

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1A EVENT COUNTER FUNCTION

Timer/counter 1A can monitor system “events” by using the external clock input at the TCL1 pin as the counter

source. The TC1A mode register selects rising or falling edge detection for incoming clock signals. The counter

register TCNT1A is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD1A.4–TMOD1A.6 settings, the operation sequence for TC1A's event

counter function is identical to its programmable timer/counter function. To activate the TC1A event counter

function.

— Set TMOD1A.7 to "0" to be operated as timer/counter 1A.

— Set TMOD1A.2 to "1" to enable TC1A.

— Clear TMOD1A.6 to "0" to select the external clock source at the TCL1 pin.

— Select TCL1 edge detection for rising or falling signal edges by loading the appropriate values to TMOD1A.5

and TMOD1A.4.

— Pin P3.3 must be set to input mode.

Table 11-13. TMOD1A Settings for TCL1 Edge Detection

TMOD1A.5

TMOD1A.4

TCL1 Edge Detection

Rising edges

Falling edges

0

1

11-39

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1A CLOCK FREQUENCY OUTPUT

Using timer/counter 1A, a modifiable clock frequency can be output to the TC1A clock output pin, TCLO1. To

select the clock frequency, load the appropriate values to the TC1A mode register, TMOD1A. The clock interval

is selected by loading the desired reference value into the 8-bit reference register TREF1A. To enable the output

to the TCLO1 pin at I/O port 3.1, the following conditions must be met:

— TC1A output enable flag TOE1 must be set to "1".

— I/O mode flag for P3.1 (PM3.1) must be set to output mode ("1").

— P3.1 output latch must be cleared to "0".

In summary, the operational sequence required to output a TC1A-generated clock signal to the TCLO1 pin is as

follows:

1. Set the TMOD1A.7 to "0" to be operated as timer/counter 1A.

2. Load your reference value to TREF1A.

3. Set the internal clock frequency in TMOD1A.

4. Initiate TC1A clock output to TCLO1 (TMOD1A.2 = "1").

5. Set port 3.1 mode flag (PM3.1) to "1".

6. Clear the P3.1 output latch.

7. Set TOE1 flag to "1".

Each time the contents of TCNT1A and TREF1A coincide and an interrupt request is generated, the state of the

output latch TOL1 is inverted and the TC1A-generated clock signal is output to the TCLO1 pin.

+

PROGRAMMING TIP — TC1A Signal Output to the TCLO1 Pin

Output a 30 ms pulse width signal to the TCLO1 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#79H

TREF1A,EA

EA,#04CH

TMOD1A,EA

EA,#02H

PMG2,EA

P3.1

; P3.1 ¬ output mode

; P3.1 clear

TOE1

11-40

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1A SERIAL I/O CLOCK GENERATION

Timer/counter1A can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter

and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register,

SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.

Use TMOD1A and TREF1A register settings to select the frequency and interval of the TC1A clock signals to be

used as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock

selector circuit (the TOE1 flag may be disabled).

TC1A EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC1A reference register, TREF1A,

you can divide the incoming clock signal by the TREF1A value and then output this modified clock frequency to

the TCLO1 pin. The sequence of operations used to divide external clock input and output the signals to the

TCLO1 pin can be summarized as follows:

1. Set TMOD1A.7 to "0" be operated as timer/counter 1A.

2. Load a signal divider value to the TREF1A register.

3. Clear TMOD1A.6 to "0" to enable external clock input at the TCLO1 pin.

4. Set TMOD1A.5 and TMOD1A.4 to desired TCL1 signal edge detection.

5. Set P3.1 mode flag (PM3.1) to output ("1").

6. Clear the P3.1 output latch.

7. Set TOE1 flag to "1" to enable output of the divided frequency.

+

PROGRAMMING TIP — External TCL1 Clock Output to the TCLO1 Pin

Output the external TCL1 clock source to the TCLO1 pin (divide by four):

External (TCL1)

Clock Pulse

TCLO1

Output Pulse

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF1A,EA

EA,#0CH

TMOD1A,EA

EA,#02H

PMG2,EA

P3.1

; P3.1 ¬ output mode

; P3.1 clear

TOE1

11-41

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1A MODE REGISTER (TMOD1A)

TMOD1A is the 8-bit mode register for timer/counter 1A. It is addressable by 8-bit write instructions. The

TMOD1A.3 bit is also 1-bit write addressable. RESET clears all TMOD1A bits to logic zero. Following a RESET,

Timer/counter 1A is disabled.

FA0H

FA1H

TMOD1A.3 TMOD1A.2

"0"

TMOD1A.7 TMOD1A.6 TMOD1A.5 TMOD1A.4

TMOD1A.7 is the mode selection bit for one 16-bit timer/counter or two 8-bit timer/counters. TMOD1A.2 is the

enable/disable bit for timer/counter 1A. When TMOD1A.3 is set to "1", the contents of TCNT1A, IRQT1, and

TOL1 are cleared, counting starts from 00H, and TMOD1A.3 is automatically reset to "0" for normal TC1A

operation. When TC1A operation stops (TMOD1A.2 = "0"), the contents of the TC1A counter register, TCNT1A,

are retained until TC1A is re-enabled.

The TMOD1A.6, TMOD1A.5, and TMOD1A.4 bit settings are used together to select the TC1A clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL1 pin

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC1A operations.

Table 11-14. TC1A Mode Register (TMOD1A) Organization

Bit Name

Setting

Resulting TC1 Function

Address

TMOD1A.7

0,1

Configure as one 16-bit timer/counter 1 or two 8-bit

timer/counters 1A, 1B.

TMOD1A.6

TMOD1A.5

TMOD1A.4

TMOD1A.3

0,1

1

FA1H

Specify input clock edge and internal frequency

FA0H

Clear TCNT1A, IRQT1, and TOL1 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes).

TMOD1A.2

0

1

0

Disable timer/counter 1A; retain TCNT1A contents

Enable timer/counter 1A

TMOD1A.1

TMOD1A.0

Always logic zero

11-42

S3C7565/P7565

TIMERS and TIMER/COUNTERS

Table 11-15. TMOD1A.6, TMOD1A.5, and TMOD1A.4 Bit Settings

TMOD1A.6

TMOD1A.5

TMOD1A.4

Resulting Counter Source and Clock Frequency

External clock input (TCL1) on rising edges

External clock input (TCL1) on falling edges

fxx/2¹⁰= 4.09 kHz

0

1

0

1

0

1

0

1

0

1

fxx/2⁶= 65.5 kHz

fxx/2⁴= 262 kHz

fxx = 4.19 MHz

NOTE: “fxx” = selected system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC1A Counting Operation

1. Set TC1A timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD1A,EA

LD

EI

BITS

IET1

2. Clear TCNT1A, IRQT1, and TOL1 and restart TC1A counting operation:

BITS

SMB

BITS

EMB

15

TMOD1A.3

11-43

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1A COUNTER REGISTER (TCNT1A)

The 8-bit counter register for timer/counter 1A, TCNT1A, is mapped to RAM addresses FA5H–FA4H. The 8-bit

register is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT1A register

values to logic zero (00H).

Whenever TMOD1A.2 and TMOD1A.3 are enabled, TCNT1A is cleared to logic zero and counting begins. The

TCNT1A register value is incremented each time an incoming clock signal is detected that matches the signal

edge and frequency setting of the TMOD1A register (specifically, TMOD1A.6, TMOD1A.5, and TMOD1A.4).

Each time TCNT1A is incremented, the new value is compared to the reference value stored in the TC1A

reference register, TREF1A. When TCNT1A = TREF1A, an overflow occurs in the TCNT1A register, the interrupt

request flag, IRQT1, is set to logic one, and an interrupt request is generated to indicate that the specified

timer/counter interval has elapsed.

Count

Clock

TREF1A

TCNT1A

Reference Value = n

n

0

1

2

n-1

0

1

2

n-1

0

1

2

3

Match

TOL1

Interval Time

Timer Start Instruction

(TMOD1A.3 is set)

IRQT1 Set

Figure 11-7. TC1A Timing Diagram

11-44

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1A REFERENCE REGISTER (TREF1A)

The TC1A reference register TREF1A is a 8-bit write-only register that is mapped to RAM locations FA9H–FA8H.

It is addressable by 8-bit RAM control instructions. RESET clears the TREF1A value to “FFH”.

TREF1A is used to store a reference value to be compared to the incrementing TCNT1A register in order to

identify an elapsed time interval. Reference values will differ depending upon the specific function that TC1A is

being used to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary

frequency output source.

During timer/counter operation, the value loaded into the reference register compared to the TCNT1A value.

When TCNT1A = TREF1A, the TC1A output latch (TOL1) is inverted and an interrupt request is generated to

signal the interval or event. The TREF1A value, together with the TMOD1A clock frequency selection,

determines the specific TC1A timer interval. Use the following formula to calculate the correct value to load to

the TREF1A reference register:

1

TC1A timer interval = (TREF1A value + 1) ´

TMOD1A frequency setting

(TREF1A value ¹ 0)

TC1A OUTPUT ENABLE FLAG (TOE1)

The 8-bit timer/counter 1A output enable flag TOE1 flag controls output from timer/counter 1A to the TCLO1 pin.

TOE1 is addressable by 1/4-bit read or write instructions.

Bit 2

Bit 1

"0"

Bit 0

Bit 3

F92H

TOE0

TOL2

TOE1

When you set the TOE1 flag to "1", the contents of TOL1 can be output to the TCLO1 pin. Whenever a RESET

occurs, TOE1 is automatically set to logic zero, disabling all TC1A output.

TC1A OUTPUT LATCH (TOL1)

TOL1 is the output latch for timer/counter 1. When the 8-bit comparator detects a correspondence between the

value of the counter register TCNT1A and the reference value stored in the TREF1A register, the TOL1 logic

toggles high-to-low or low-to-high. Whenever the state of TOL1 is switched, the TC1A signal exits the latch for

output. TC1A output is directed (if TOE1 = "1") to the TCLO1 pin at I/O port 3.1.

When timer/counter 1 is started, (TMOD1A.3 = "1"), the contents of the output latch are cleared automatically.

However, when TC1A is disabled (TMOD1A.2 = "0"), the contents of the TOL1 latch are retained.

11-45

TIMERS and TIMER/COUNTERS

S3C7565/P7565

+

PROGRAMMING TIP — Setting a TC1A Timer Interval

To set a 30 ms timer interval for TC1A, given fxx = 4.19 MHz, follow these steps:

1. Select the timer/counter 1A mode register with a maximum setup time of 62.5 ms;

assume the TC1A counter clock = fxx/2¹⁰and TREF1A is set to FFH.

2. Calculate the TREF1A value:

TREF1A value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF1A + 1 =

= 122.9 = 7AH

TREF1A value = 7AH – 1 = 79H

3. Load the value 79H to the TREF1A register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF1A,EA

EA,#4CH

TMOD1A,EA

LD

11-46

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TIMER/COUNTER 1B FUNCTION SUMMARY

8-bit programmable timer

Generates interrupts at specific time intervals based on the selected clock

frequency.

TIMER/COUNTER 1B COMPONENT SUMMARY

Mode register (TMOD1B)

Activates the timer/counter and selects the internal clock frequency.

Reference register (TREF1B) Stores the reference value for the desired number of clock pulses between

interrupt requests.

Counter register (TCNT1B)

Clock selector circuit

8-bit comparator

Counts internal clock pulses that are generated based on bit settings in the

mode register and reference register.

Together with the mode register (TMOD1B), lets you select one of four internal

clock frequencies.

Determines when to generate an interrupt by comparing the current value of

the counter (TCNT1B) with the reference value previously programmed into

the reference register (TREF1B).

Output latch (TOL2)

When the contents of the TCNT1B and TREF1B registers coincide, the

timer/counter interrupt request flag (IRQT2) is set to "1", the status of TOL2 is

inverted, and an interrupt is generated.

Interrupt request flag (IRQT2) Cleared when TC1B operation starts and set to logic one whenever the counter

value and reference value match.

Interrupt enable flag (IET2)

Must be set to logic one before the interrupt requests generated by

timer/counter 1B can be processed.

Table 11-16. TC1 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

TMOD1B

Control

8-bit FA2H–FA3H

"0"

Controls TC1B enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and the clock

frequency (bits 6–4)

8-bit write-only;

(TMOD1B.3 is

also 1-bit

writeable)

TCNT1B

TREF1B

TOL2

Counter

Reference

Flag

8-bit FA6H–FA7H

8-bit FAAH–FABH

"0"

FFH

"0"

Counts clock pulses matching

the TMOD1B frequency setting

8-bit read-only

8-bit write-only

1/4-bit read-only

Stores reference value for

TC1B interval setting

1-bit

F92H.0

TC1B output latch

11-47

TIMERS and TIMER/COUNTERS

S3C7565/P7565

Clocks

(fx/2¹⁰, fx/2 ⁶, fx/2 ⁴, fxx)

TMOD1B.7

TMOD1B.6

TMOD1B.5

TMOD1B.4

TMOD1B.3

TMOD1B.2

TMOD1B.1

TMOD1B.0

TMOD1A.7

TMOD1A.6

TMOD1A.5

TMOD1A.4

TMOD1A.3

TMOD1A.2

TMOD1A.1

TMOD1A.0

8

/

DB

8

8-Bit

Comparator

TCNT1B

TREF1B

Clock

Selector

Clear

Set

IRQT2

Clear

1/4-Bit

Read

TOL2

NOTE: TMOD1A.7 = 0, TMOD1A.0/TMOD1A.1 = 0

Figure 11-8. TC1B Circuit Diagram

TC1B ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 1B

— Set the TC1B interrupt enable flag IET2 to logic one

— Set TMOD1B.3 to logic one

TCNT1B, IRQT2, and TOL2 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 1B

— Set TMOD1B.2 to logic zero

Clock signal input to the counter register TCNT1B is halted. The current TCNT1B value is retained and can be

read if necessary.

11-48

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1B PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 1B can be programmed to generate interrupt requests at variable intervals, based on the system

clock frequency you select. The 8-bit TC1B mode register, TMOD1B, is used to activate the timer/counter and to

select the clock frequency; the 8-bit reference register, TREF1B, is used to store the value for the desired

number of clock pulses between interrupt requests. The 8-bit counter register, TCNT1B, counts the incoming

clock pulses, which are compared to the TREF1B value. When there is a match, an interrupt request is

generated.

To program timer/counter 1B to generate interrupt requests at specific intervals, select one of the four internal

clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF1B

register. TCNT1B is incremented each time an internal counter pulse is detected with the reference clock

frequency specified by TMOD1B.4–TMOD1B.6 settings. To generate an interrupt request, the TC1B interrupt

request flag (IRQT2) is set to logic one, the status of TOL2 is inverted, and the interrupt is output. The content of

TCNT1B is then cleared to 00H, and TC1B continues counting. The interrupt request mechanism for TC1B

includes an interrupt enable flag (IET2) and an interrupt request flag (IRQT2).

TC1B TIMER/COUNTER OPERATION SEQUENCE

The general sequence of operations for using TC1B can be summarized as follows:

1. Set TMOD1A.7 to "0" to be operated as timer/counter 1A, 1B.

2. Set TMOD1B.2 to "1" to enable TC1B.

3. Set TMOD1B.6 to "1" to enable the system clock (fxx) input.

n

4. Set TMOD1B.5 and TMOD1B.4 bits to desired internal frequency (fxx/2 ).

5. Load a value to TREF1B to specify the interval between interrupt requests.

6. Set the TC1B interrupt enable flag (IET2) to "1".

7. Set TMOD1B.3 bit to "1" to clear TCNT1B, IRQT2, and TOL2, and start counting.

8. TCNT1B increments with each internal clock pulse.

9. When the comparator shows TCNT1B = TREF1B, the IRQT2 flag is set to "1" and an interrupt request is

generated.

10. Output latch (TOL2) logic toggles high or low.

11. TCNT1B is cleared to 00H and counting resumes.

12. Programmable timer/counter operation continues until TMOD1B.2 is cleared to "0".

11-49

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1B MODE REGISTER (TMOD1B)

TMOD1B is the 8-bit mode register for timer/counter 1B. It is addressable by 8-bit write instructions. The

TMOD1B.3 bit is also 1-bit write addressable. RESET clears all TMOD1B bits to logic zero. Following a RESET,

timer/counter 1B is disabled.

FA2H

FA3H

TMOD1B.3 TMOD1B.2

"0"

"0" TMOD1B.6 TMOD1B.5 TMOD1B.4

TMOD1B.2 is the enable/disable bit for timer/counter 1. When TMOD1B.3 is set to "1", the contents of TCNT1B,

IRQT2, and TOL2 are cleared, counting starts from 00H, and TMOD1B.3 is automatically reset to "0" for normal

TC1B operation. When TC1B operation stops (TMOD1B.2 = "0"), the contents of the TC1B counter register,

TCNT1B, are retained until TC1B is re-enabled.

The TMOD1B.6, TMOD1B.5, and TMOD1B.4 bit settings are used together to select the TC1B clock source. This

selection involves a variable:

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC1B operations.

Table 11-17. TC1B Mode Register (TMOD1B) Organization

Bit Name

TMOD1B.7

TMOD1B.6

TMOD1B.5

TMOD1B.4

TMOD1B.3

Setting

0

Resulting TC1B Function

Address

Always logic zero

0, 1

FA3H

Specify input clock edge and internal frequency

1

FA2H

Clear TCNT1B, IRQT2, and TOL2 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes).

TMOD1B.2

0

1

0

Disable timer/counter 1B; retain TCNT1B contents

Enable timer/counter 1B

TMOD1B.1

TMOD1B.0

Always logic zero

11-50

S3C7565/P7565

TIMERS and TIMER/COUNTERS

Table 11-18. TMOD1B.6, TMOD1B.5, and TMOD1B.4 Bit Settings

TMOD1B.6

TMOD1B.5

TMOD1B.4

Resulting Counter Source and Clock Frequency

Not available

0

1

0

1

0

1

0

1

0

1

Not available

fxx/2¹⁰= 4.09 kHz

fxx/2⁶= 65.5 kHz

fxx/2⁴= 262 kHz

fxx = 4.19 MHz

NOTE: “fxx” = selected system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC1B Counting Operation

1. Set TC1B timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD1B,EA

LD

EI

BITS

IET2

2. Clear TCNT1B, IRQT2, and TOL2 and restart TC1B counting operation:

BITS

SMB

BITS

EMB

15

TMOD1B.3

11-51

TIMERS and TIMER/COUNTERS

S3C7565/P7565

TC1B COUNTER REGISTER (TCNT1B)

The 8-bit counter register for timer/counter 1B, TCNT1B, is mapped to RAM addresses FA7H–FA6H. The 8-bit

register is read-only and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT1B register

values to logic zero (00H).

Whenever TMOD1B.2 and TMOD1B.3 are enabled, TCNT1B is cleared to logic zero and counting begins. The

TCNT1B register value is incremented each time an incoming clock signal is detected that matches the signal

edge and frequency setting of the TMOD1B register (specifically, TMOD1B.6, TMOD1B.5, and TMOD1B.4).

Each time TCNT1B is incremented, the new value is compared to the reference value stored in the TC1B

reference register, TREF1B. When TCNT1B = TREF1B, an overflow occurs in the TCNT1B register, the interrupt

request flag, IRQT2, is set to logic one, and an interrupt request is generated to indicate that the specified

timer/counter interval has elapsed.

Count

Clock

TREF1B

TCNT1B

Reference Value = n

n

0

1

2

n-1

0

1

2

n-1

0

1

2

3

Match

TOL2

Interval Time

Timer Start Instruction

(TMOD1B.3 is set)

IRQT2 Set

Figure 11-9. TC1B Timing Diagram

11-52

S3C7565/P7565

TIMERS and TIMER/COUNTERS

TC1B REFERENCE REGISTER (TREF1B)

The TC1B reference register TREF1B is a 8-bit write-only register that is mapped to RAM locations FABH–

FAAH. It is addressable by 8-bit RAM control instructions. RESET clears the TREF1B value to “FFH”.

TREF1B is used to store a reference value to be compared to the incrementing TCNT1B register in order to

identify an elapsed time interval. Reference values will differ depending upon the specific function that TC1B is

being used to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary

frequency output source.

During timer/counter operation, the value loaded into the reference register compared to the TCNT1B value.

When TCNT1B = TREF1B, the TC1B output latch (TOL2) is inverted and an interrupt request is generated to

signal the interval or event. The TREF1B value, together with the TMOD1B clock frequency selection,

determines the specific TC1B timer interval. Use the following formula to calculate the correct value to load to

the TREF1B reference register:

1

TC1B timer interval = (TREF1B value + 1) ´

TMOD1B frequency setting

(TREF1B value ¹ 0)

TC1B OUTPUT LATCH (TOL2)

Bit 3

Bit 2

Bit 1

"0"

Bit 0

F92H

TOE1

TOE0

TOL2

TOL2 is the output latch for timer/counter 1B. When the 8-bit comparator detects a correspondence between the

value of the counter register TCNT1B and the reference value stored in the TREF1B register, the TOL2 logic

toggles high-to-low or low-to-high. Whenever the state of TOL2 is switched, the TC1B signal exits the latch for

output.

When timer/counter 1B is started, (TMOD1B.3 = "1"), the contents of the output latch are cleared automatically.

However, when TC1B is disabled (TMOD1B.2 = "0"), the contents of the TOL2 latch are retained and can be

read, if necessary.

11-53

TIMERS and TIMER/COUNTERS

S3C7565/P7565

+

PROGRAMMING TIP — Setting a TC1B Timer Interval

To set a 30 ms timer interval for TC1B, given fxx = 4.19 MHz, follow these steps:

1. Select the timer/counter 1B mode register with a maximum setup time of 62.5 ms;

assume the TC1B counter clock = fxx/2¹⁰and TREF1B is set to FFH.

2. Calculate the TREF1B value:

TREF1B value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF1B + 1 =

= 122.9 = 7AH

TREF1B value = 7AH – 1 = 79H

3. Load the value 79H to the TREF1B register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF1B,EA

EA,#4CH

TMOD1B,EA

LD

11-54

S3C7565/P7565

TIMERS and TIMER/COUNTERS

WATCH TIMER

OVERVIEW

The watch timer is a multi-purpose timer which consists of three basic components:

— 8-bit watch timer mode register (WMOD)

— Clock selector

— Frequency divider circuit

Watch timer functions include real-time and watch-time measurement and interval timing for the main and

subsystem clock. It is also used as a clock source for the LCD controller and for generating buzzer (BUZ) output.

Real-Time and Watch-Time Measurement

To start watch timer operation, set bit 2 of the watch timer mode register (WMOD.2) to logic one. The watch

timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence

in

0.5 second intervals.

Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be

cleared to logic zero by program software as soon as a requested interrupt service routine has been executed.

Using a Main System or Subsystem Clock Source

The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock.

When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its

source; if WMOD.0 = "0", the main system clock (fx) is used as the signal source, according to the following

formula:

Main system clock (fx)

Watch timer clock (fw) =

= 32.768 kHz (fx = 4.19 MHz)

128

This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the

main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using the subsystem clock as

the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby

releasing stop mode.

Clock Source Generation for LCD Controller

The watch timer supplies the clock frequency for the LCD controller (f_LCD). Therefore, if the watch timer is

disabled, the LCD controller does not operate.

11-55

TIMERS and TIMER/COUNTERS

S3C7565/P7565

Buzzer Output Frequency Generator

The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to the BUZ pins. To select the

desired BUZ frequency , load the appropriate value to the WMOD register. This output can then be used to

actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met:

— The WMOD.7 register bit is set to "1"

— The output latch for I/O port 0.3 is cleared to "0"

— The port 0.3 output mode flag (PM0.3) set to "output" mode

Timing Tests in High-Speed Mode

By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91

ms. At its normal speed (WMOD.1 = "0"), the watch timer generates an interrupt request every 0.5 seconds.

High-speed mode is useful for timing events for program debugging sequences.

Check Subsystem Clock Level Feature

The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the

input level at the XT_INpin is high; if WMOD.3 is "0", the input level at the XT_INpin is low.

11-56

S3C7565/P7565

TIMERS and TIMER/COUNTERS

P0.3 Latch

PM0.3

WMOD.7

BUZ

WMOD.6

WMOD.5

WMOD.4

WMOD.3

WMOD.2

WMOD.1

WMOD.0

MUX

8

fw/64 (0.5 kHz)

fw/32 (1 kHz)

fw/16 (2 kHz)

fw/8 (4 kHz)

Enable/DISABLE

Selector

Circuit

IRQW

fw/2⁷

fw/2¹⁴(2Hz)

Frequency

Dividing

Circuit

fw

Clock

Selector

fw/2³

(32.768 kHz)

f

LCD

fx = Main-system Clock

fxt = Sub-system Clock

fw = Watch Timer Frequency

MUX

LCON.4

fxt

fx/128 fx/64

Figure 11-10. Watch Timer Circuit Diagram

11-57

TIMERS and TIMER/COUNTERS

S3C7565/P7565

WATCH TIMER MODE REGISTER (WMOD)

The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only

addressable. An exception is WMOD bit 3 (the XT_INinput level control bit) which is 1-bit read-only addressable.

A RESET automatically sets WMOD.3 to the current input level of the subsystem clock, XT_IN(high, if logic one;

low, if logic zero), and all other WMOD bits to logic zero.

F88H

F89H

WMOD.3

WMOD.7

WMOD.2

"0"

WMOD.1

WMOD.5

WMOD.0

WMOD.4

In summary, WMOD settings control the following watch timer functions:

— Watch timer clock selection

— Watch timer speed control

— Enable/disable watch timer

— XT_INinput level control

(WMOD.0)

(WMOD.1)

(WMOD.2)

(WMOD.3)

— Buzzer frequency selection

— Enable/disable buzzer output

(WMOD.4 and WMOD.5)

(WMOD.7)

Table 11-19. Watch Timer Mode Register (WMOD) Organization

Bit Name

Values

Function

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

Address

WMOD.7

0

1

F89H

WMOD.6

0

Always logic zero

WMOD.5–.4

0

1

0

1

0

1

0.5 kHz buzzer (BUZ) signal output

1 kHz buzzer (BUZ) signal output

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

Input level to XT_INpin is low

WMOD.3

0

1

F88H

Input level to XT_INpin is high

WMOD.2

WMOD.1

WMOD.0

0

1

0

1

0

1

Disable watch timer; clear frequency dividing circuits

Enable watch timer

Normal mode; sets IRQW to 0.5 seconds

High-speed mode; sets IRQW to 3.91 ms

Select (fx/128 ) as the watch timer clock (fw)

Select subsystem clock as watch timer clock (fw)

NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fxt) is assumed to be 32.768 kHz.

11-58

S3C7565/P7565

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Watch Timer

1. Select a subsystem clock as the LCD display clock, a 0.5 s interrupt, and 2 kHz buzzer enable:

BITS

SMB

LD

BITR

LD

EMB

15

EA,#8H

PMG1,EA

P0.3

EA,#85H

WMOD,EA

IEW

; P0.3 ¬ output mode

LD

BITS

2. Sample real-time clock processing method:

CLOCK

BTSTZ

IRQW

; 0.5 s check

RET

; No, return

•

; Yes, 0.5 s interrupt generation

; Increment HOUR, MINUTE, SECOND

11-59

TIMERS and TIMER/COUNTERS

S3C7565/P7565

NOTES

11-60

S3C7565/P7565

LCD CONTROLLER/DRIVER

12 LCD CONTROLLER/DRIVER

OVERVIEW

The S3C7565 microcontrollers can directly drive an up-to-960-dot (60 segments x 16 commons) LCD panel.

Data written to the LCD display RAM can be automatically transferred to the segment signal pins without

program control.

When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during Idle mode.

— LCD controller/driver

— Display RAM for storing display data

— 60 segment output pins (SEG0–SEG59)

— 16 common output pins (COM0–COM15)

— LCD operating power supply pins (V_LC1

)

— V_LC1pin for controlling the driver and bias voltage

The frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings

in the LCD mode register, LMOD.

The LCD control register, LCON, is used to turn the LCD display on and off, to switch current to the dividing

resistors for the LCD display. Data written to the LCD display RAM can be transferred to the segment signal pins

automatically without program control.

When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during main

clock stop and idle modes.

VLC1

/

1

8

COM0-COM7

LCD

Controller/

Driver

/

COM8-COM15/

P4.0-P5.3

/

8

SEG0-SEG39

40

20

SEG40-SEG59/

P10.3-P6.0

/

Figure 12-1. LCD Function Diagram

12-1

LCD CONTROLLER/DRIVER

S3C7565/P7565

Port

Latch

20

SEG59/P6.0

SEG58/P6.1

Display

RAM

(Bank 2)

MUX

Selector

224

60

56

SEG40/P10.3

SEG0

fLCD

Port

Latch

8

COM15/P5.3

COM14/P5.2

Timing

Controller

COM

Control

LMOD

COM0

LCD

Voltage

Control

LCON

VLC1

LCDSY

LCDCK

P8.0 Latch

P8.1 Latch

PM8.0

PM8.1

Figure 12-2. LCD Circuit Diagram

12-2

S3C7565/P7565

LCD CONTROLLER/DRIVER

LCD RAM ADDRESS AREA

The RAM area of bank 1 page 13H are used as LCD data memory. These locations can be addressed by

1-bit, 4-bit, 8-bit instructions. When the bit value of a display segment is “1” the LCD display is turned on; when

the bit value is “0”, the display is turned off.

Display RAM data are sent out through the segment pins, SEG0–SEG59, using the direct memory access (DMA)

method that is synchronized with the f

signal. The RAM addresses in this location that are not used for LCD

LCD

display can be allocated to general-purpose use.

S S S S

E E E E

G G G G

56 57 58 59

S S S S S S S S

E E E E E E E E

G G G G G G G G

0

1 2 3 4 5 6 7

b0 b1 b2 b3 b0 b1 b2 b3

b0 b1 b2 b3

10EH

100H

110H

120H

130H

101H

111H

121H

131H

COM0

COM1

COM2

COM3

11EH

12EH

13EH

1C0H

1D0H

1E0H

1C1H

1D1H

1E1H

1F1H

1CEH

1DEH

1EEH

1FEH

COM12

COM13

COM14

COM15

1F0H

Figure 12-3. LCD Display Data RAM Organization

Table 12-1. Common and Segment Pins per Duty Cycle

Duty

1/16

1/12

1/8

Common Pins

COM0–COM15

COM0–COM11

COM0–COM7

Segment Pins

Dot Number

960 dots

60 pins

720 dots

480 dots

12-3

LCD CONTROLLER/DRIVER

S3C7565/P7565

LCD CONTROL REGISTER (LCON)

The LCD control register (LCON) is used to turn the LCD display on and off, to select watch timer clock and LCD

clock, and to control the flow of current to dividing resistors in the LCD circuit. Following a RESET, all LCON

values are cleared to "0". This turns the LCD display off and stops the flow of current to the dividing resistors.

LCON

LCON.3

LCON.7

LCON.2

“0”

LCON.1

LCON.5

LCON.0

LCON.4

F8EH

F8FH

The effect of the LCON.0 setting is dependent upon the current setting of bits LMOD.0 and LMOD.1. Bit 1 in the

LCON is used for contrast control application.

Table 12-2. LCD Control Register (LCON) Bit 7, 6, 5

LCON Bit

Setting

Description

LCON.7

0

1

0

1

TR2 off

TR2 on

LCON.6

LCON.5

Always logic zero

Disable LCDCK and LCDSY signal outputs

Enable LCDCK and LCDSY signal outpus

Table 12-3. Watch Timer (fw) Clock Selection Bits

(When the main system clock is supplied to the watch timer source.)

LCON.4

Watch timer clock when the main system clock is selected as the watch timer clock

f_LCD= 4096 Hz when fw = fx / 128 (32.768 kHz @fx = 4.19 MHz)

0

1

f_LCD=8192 Hz when fw = fx / 64 (65.563 kHz @fx = 4.19 MHz)

Table 12-4. LCD Clock Selection Bits

LCON.3

LCON.2

LCD Clock (LCDCK)

1/8 duty (COM0–COM7) 1/12 duty (COM0–COM11) 1/16 duty (COM0–COM15)

7

6

0

1

0

1

0

1

fw / 2 (256 Hz)

fw / 2 (512 Hz)

6

5

fw / 2 (512 Hz)

fw / 2 (1024 Hz)

5

4

fw / 2 (1024 Hz)

fw / 2 (2048 Hz)

4

3

fw / 2 (2048 Hz)

fw / 2 (4096 Hz)

NOTES:

1. LCDCK is supplied only when the watch timer operates. To use the LCD controller , you must set bit 2 in the watch

mode register WMOD to “1”.

2. When fw = 32.768 kHz, f

= 4096 Hz

LCD

12-4

S3C7565/P7565

LCD CONTROLLER/DRIVER

Table 12-5. LCD Control Register (LCON) Bit 1, 0

LCON Bit

Setting

Description

LCON.1

0

1

0

1

Normal LCD dividing resisitors

Diminish a LCD dividing resistor to strengthen LCD drive

LCON.0

TR1 off

TR1 on

NOTE: When the LCON.1 is selected to “logic one”, the leakage current of LCD bias resistor will be increased.

12-5

LCD CONTROLLER/DRIVER

S3C7565/P7565

LCD MODE REGISTER (LMOD)

The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and

display on/off. LMOD can be manipulated using 8-bit write instructions.

F8CH

F8DH

LMOD.3

LMOD.7

LMOD.2

LMOD.6

LMOD.1

LMOD.5

LMOD.0

LMOD.4

The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This

is also referred to as the frame frequency. Since LCDCK is generated by dividing the watch timer clock (fw), the

watch timer must be enabled when the LCD display is turned on. RESET clears the LMOD register values to

logic zero.

The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch

timer source. The LCD mode register LMOD controls the output mode of the 20 pins used for normal outputs

(P10.3–P6.0). Bits LMOD.7–5 define the segment output and normal bit output configuration.

Table 12-6. LCD Clock Signal (LCDCK) Frame Frequency

LCDCK

256 Hz

512 Hz

1024 Hz

2048 Hz

4096 Hz

Display Duty Cycle

1/8

32

–

64

42.7

32

128

85.3

64

256

170.7

128

–

1/12

1/16

341.3

256

–

NOTE:

COM0

1 FRAME

12-6

S3C7565/P7565

LCD CONTROLLER/DRIVER

LCD Mode Register (LMOD) Organization

RESET clears the LMOD register values to logic zero.

Table 12-7. Segment/Port Output Selection Bits

LMOD.7 LMOD.6 LMOD.5

SEG40–43

SEG44–47

SEG48–51

SEG52–55

SEG56–59

Total

Segment

0

1

0

1

0

1

0

1

0

1

0

1

0

SEG port

60

56

52

48

44

40

56

Normal port

Normal port Normal port

Normal port Normal port Normal port

Normal port Normal port Normal port Normal port

Normal port Normal port Normal port Normal port Normal port

SEG port SEG port SEG port Normal port SEG port

NOTE: Segment pins that can also be used for normal I/O should be configured to output mode when the SEG function is

used.

Table 12-8. LCD Bias Selection Bit

LMOD.4

Bias Selection for LCD Display

0

1

1/4 bias

1/5 bias

Table 12-9. Duty Selection Bits

LMOD.3

LMOD.2

Duty

0

1

0

1

0

1/8 duty (COM0–COM7 select)

1/12 duty (COM0–COM11 select)

1/16 duty (COM0–COM15 select)

Table 12-10. Display Mode Selection Bits

LMOD.1 LMOD.0 COM0–COM15

SEG0–SEG59 SEG40/P10.3–SEG59/P6.0 Power Supply to the

COM8/P4.0–COM15/P5.3

Dividing Resistor

0

1

0

1

All of the LCD dots off

All of the LCD dots on

Normal I/O port function

On

Common and segment signal

output corresponds to display data

(normal display mode)

12-7

LCD CONTROLLER/DRIVER

V_LC1REGISTER (VLC1R)

S3C7565/P7565

VLC1R register settings determine whether P2.1 would be used for digital input or analog input. VLC1R register

can be read or writen by using 1-/4-bit RAM control instructions. VLC1R is mapped to the address FD9H and

initialized to logic zero by a RESET, which configures P2.1 as digital input port.

FD9H

“0”

VLC1F

When VLC1F, bit 0 of VLC1R, is set to “1”, P2.1 is configured as an analog input pin for V_LC1. To use P2.1 as

VLCD for external LCD power supply, VLC1F must be set to “1”. When set to”0”, it is configured as a digital

input pin.

LCD VOLTAGE DIVIDING RESISTORS

S3C7565

LCON.7

(ON)

LCON.7

(OFF)

VDD

LCON.0

(OFF)

LCON.0

(ON)

TR1

V_LC1F= "1"

V_1LCF = "0"

V

LC1

V_LC1

P2.1

TR2

P2.1

TR2

R

V_LC2

V_LC3

VLC2

Digital Port

VLC3

LMOD.4

VLC4

V_LC4

R

V_LC5

VLC5

R

VSS

V_SS

For External Bias Voltage

For Internal Bias Voltage

NOTE:

VLC1F must be set to "1" to use P2.1 as digital port.

Figure 12-4. Internal Voltage Dividing Resistor Connection

12-8

S3C7565/P7565

LCD CONTROLLER/DRIVER

COMMON (COM) SIGNALS

The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.

— In 1/8 duty mode, COM0–COM7 pins are selected.

— In 1/12 duty mode, COM0–COM11 pins are selected.

— In 1/16 duty mode, COM0–COM15 pins are selected.

When 1/8 duty is selected by clearing LMOD.2 and LMOD.3 to zero, COM8–COM15 (P4.0–P5.3) can be used for

normal I/O port.

SEGMENT (SEG) SIGNALS

The 60 LCD segment signal pins are connected to corresponding display RAM locations at bank 1. Bits of the

display RAM are synchronized with the common signal output pins.

When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.

When the display bit is "0", a “no-select” signal is sent to the corresponding segment pin.

12-9

LCD CONTROLLER/DRIVER

S3C7565/P7565

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

15

0 1 2 3

150 1 2 3

VDD

VSS

FR

1 Frame

VLC1

VLC2

VLC3

VLC4

VLC5

VSS

COM0

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

VLC1

VLC2

VLC3

VLC4

COM1

COM2

S S S S S

E E E E E

G G G G G

0 1 2 3 4

VLC5

VSS

VLC1

VLC2

VLC3

VLC4

VLC5

VSS

VLC1

VLC2

VLC3

VLC4

SEG0

VLC5

VSS

Figure 12-5. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)

12-10

S3C7565/P7565

LCD CONTROLLER/DRIVER

15

0 1 2 3

150 1 2 3

VDD

VSS

FR

1 Frame

VLC1

VLC2

VLC3

VLC4

VLC5

VSS

SEG1

VLC1

VLC2

VLC3

VLC4

VLC5

0V

SEG0-COM0

-VLC5

-VLC4

-VLC3

-VLC2

-VLC1

VLC1

VLC2

VLC3

VLC4

VLC5

0V

SEG1-COM0

-VLC5

-VLC4

-VLC3

-VLC2

-VLC1

Figure 12-5. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)

12-11

LCD CONTROLLER/DRIVER

S3C7565/P7565

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

VDD

VSS

FR

1 Frame

VLC1

VLC2 (VLC3)

VLC4

S S S S S

E E E E E

G G G G G

0 1 2 3 4

COM0

VLC5

VSS

VLC1

VLC2 (VLC3)

VLC4

COM1

COM2

VLC5

VSS

VLC1

VLC2 (VLC3)

VLC4

VLC5

VSS

VLC1

VLC2 (VLC3)

VLC4

VLC5

SEG0

VSS

VLC1

VLC2 (VLC3)

VLC4

VLC5

SEG0-COM0

0V

-VLC5

-VLC4

-VLC2(-VLC3)

-VLC1

Figure 12-6. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

12-12

S3C7565/P7565

LCD CONTROLLER/DRIVER

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

VDD

VSS

FR

1 Frame

VLC1

VLC2 (VLC3)

VLC4

SEG1

VLC5

VSS

VLC1

VLC2 (VLC3)

VLC4

VLC5

0V

SEG0-COM0

-VLC5

-VLC4

-VLC2 (VLC3)

-VLC1

Figure 12-6. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)

12-13

LCD CONTROLLER/DRIVER

S3C7565/P7565

NOTES

12-14

S3C7565/P7565

DTMF GENERATOR

13 DTMF GENERATOR

OVERVIEW

The dual-tone multi-frequency (DTMF) output circuit is used to generate 16 dual-tone multiple frequency signals

for tone dialing. This function is controlled by the DTMF mode register. By writing the contents of the output latch

for the DTMF circuit with output instructions, 16 dual or single tones can be output to the DTMF output pin. The

tone output frequency is selected by the DTMF mode register. A frequency of 3.579545 MHz is used for the

DTMF generator. Clock output is inhibited when DTMR.0 (DTMF Enable Bit) because low.

The decoder receives data from the data latch and outputs the result to the row and column tone counter. The

row and column tone counter are incremented until new data is latched. When DTMR.0 is logic one, data is

latched, and the tone output is changed.

Table 13-1. Keyboard Arrangement

1

2

3

A

ROW1

ROW2

ROW3

ROW4

4

5

6

B

7

8

0

9

#

C

D

*

Column 1

Column 2

Column 3

Column 4

Input

Specified Frequency (Hz)

Actual Frequency (Hz)

% Error

+ 0.31

- 0.49

- 0.54

+ 0.74

+ 0.57

- 0.32

- 0.35

+ 0.73

ROW 1

697

770

699.1

766.2

ROW 2

ROW 3

852

847.4

ROW 4

941

948.0

Column 1

Column 2

Column 3

Column 4

1209

1336

1477

1633

1215.7

1331.7

1471.7

1645.0

13-1

DTMF GENERATOR

S3C7565/P7565

DTMF MODE REGISTER

DTMF output is controlled by the DTMF mode register. The bit position DTMR.0 enables or disables the DTMF

operation. If DTMR.0 = 1, the DTMF operation is enabled.

Programmers should write zeros or ones to the bit positions DTMR.4–DTMR.7 according to the keyboard input

specification. Writing the data in a look-up table is useful for program efficiency. The DTMR register is a

write-only register, and is manipulated by 8-bit RAM control instructions.

Table 13-2. DTMF Mode Register (DTMR) Organization

Bit Name

Setting

Resulting DTMF Function

Specify according to keyboard

Address

DTMR.7–.4

0,1

FACH

DTMR.3

–

Don't care

FADH

DTMR.2–.1

0

1

0

1

0

1

Dual-tone enable

Single-column tone enable

Single-row tone enable

Disable DTMF operation

Enable DTMF operation

DTMR.0

0

1

13-2

S3C7565/P7565

DTMF GENERATOR

Table 13-3. DTMR.7–DTMR.4 key Input Control Settings

DTMR.7

DTMR.6

DTMR.5

DTMR.4

Keyboard

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D

1

2

3

4

5

6

7

8

9

0

*

#

A

B

C

DTMF WAVEFORM

DTMF is generated with DTMF offset voltage.

V

DD

V

SS

DTMF ON

DTMF OFF

Figure 13-1. DTMF Output Waveform

13-3

DTMF GENERATOR

S3C7565/P7565

NOTES

13-4

S3C7565/P7565

SERIAL I/O INTERFACE

14 SERIAL I/O INTERFACE

OVERVIEW

The serial I/O interface (SIO) has the following functional components:

— 8-bit mode register (SMOD)

— Clock selector circuit

— 8-bit buffer register (SBUF)

— 3-bit serial clock counter

Using the serial I/O interface, 8-bit data can be exchanged with an external device. The transmission frequency

is controlled by making the appropriate bit settings to the SMOD register.

The serial interface can run off an internal or an external clock source, or the TOL1 signal that is generated by

the 16-/8-bit timer/counter, TC1/TC1A. If the TOL1 clock signal is used, you can modify its frequency to adjust

the serial data transmission rate.

SERIAL I/O OPERATION SEQUENCE

The general operation sequence of the serial I/O interface can be summarized as follows:

1. Set SIO mode to transmit-and-receive or to receive-only.

2. Select MSB-first or LSB-first transmission mode.

3. Set the SCK clock signal in the mode register, SMOD.

4. Set SIO interrupt enable flag (IES) to "1".

5. Initiate SIO transmission by setting bit 3 of the SMOD to "1".

6. When the SIO operation is complete, IRQS flag is set and an interrupt is generated.

14-1

SERIAL I/O INTERFACE

S3C7565/P7565

Internal Bus

8

LSB/MSB

SO

SBUF (8-Bit)

SI

R

Overflow

IRQS

SCK

Q

D

CK

TOL1

Q0

Q1

Q2

3-Bit Counter

CPU CLK

fxx/2¹⁰

Clock

Selector

R

S

Q

Clear

fxx/2⁴

SMOD.7 SMOD.6 SMOD.5

-

SMOD.3 SMOD.2 SMOD.1 SMOD.0

(note)

Bits

8

Internal Bus

NOTE: Instruction Execution

Figure 14-1. Serial I/O Interface Circuit Diagram

14-2

S3C7565/P7565

SERIAL I/O INTERFACE

SERIAL I/O MODE REGISTER (SMOD)

The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface.

Its reset value is logical zero. SMOD is organized in two 4-bit registers, as follows:

FE0H

FE1H

SMOD.3

SMOD.7

SMOD.2

SMOD.6

SMOD.1

SMOD.5

SMOD.0

0

SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in

transmit-and-receive mode or receive-only mode. SMOD is a write-only register and can be addressed only by

8-bit RAM control instructions. One exception to this is SMOD.3, which can be written by a 1-bit RAM control

instruction. When SMOD.3 is set to 1, the contents of the serial interface interrupt request flag, IRQS, and the

3-bit serial clock counter are cleared, and SIO operations are initiated. When the SIO transmission starts,

SMOD.3 is cleared to logical zero.

Table 14-1. SIO Mode Register (SMOD) Organization

0

1

0

1

0

Most significant bit (MSB) is transmitted first

Least significant bit (LSB) is transmitted first

Receive-only mode

SMOD.0

SMOD.1

SMOD.2

Transmit-and-receive mode

Disable the data shifter and clock counter; retain contents of IRQS flag when serial

transmission is halted

1

0

Enable the data shifter and clock counter; set IRQS flag to "1" when serial

transmission is halted

Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset

this bit to logic zero

SMOD.3

SMOD.4

Bit not used; value is always "0"

SMOD.7

SMOD.6

SMOD.5

Clock Selection

R/W Status of SBUF

0

SBUF is enabled when SIO

External clock at SCK pin

operation is halted or when SCK

goes high.

0

1

0

1

0

1

x

0

Use TOL1 clock from TC1

CPU clock: fxx/4, fxx/8, fxx/64

Enable SBUF read/write

10

SBUF is enabled when SIO

4.09 kHz clock: fxx/2

operation is halted or when SCK

goes high.

4

1

262 kHz clock: fxx/2

NOTES:

1. “fxx” = system clock; “x” means “don't care”.

2. kHz frequency ratings assume a system clock (fxx) running at 4.19 MHz.

3. The SIO clock selector circuit cannot select a fxx/2⁴clock if the CPU clock is fxx/64.

4. When using the external clock as the SCK clock, the P0.0 must be set as an input pin. When using the

internal clock as the SCL clock, the P0.0 must be set as an output pin.

5. When using SI and SO as data input/output pins, they must each be set as input/output pins.

6. It must be selected MSB-first or LSB-first transmission mode before loading a data to SBUF.

14-3

SERIAL I/O INTERFACE

S3C7565/P7565

SERIAL I/O TIMING DIAGRAMS

SCK

SI

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SO

DO7

DO6

DO5

DO4

DO3

DO1

DO0

DO2

Transmit

Complete

IRQS

SET SMOD.3

Figure 14-2. SIO Timing in Transmit/Receive Mode

Figure 14-3. SIO Timing in Receive-Only Mode

14-4

S3C7565/P7565

SERIAL I/O INTERFACE

SERIAL I/O BUFFER REGISTER (SBUF)

The serial I/O buffer register ,SBUF, can be read or written using 8-bit RAM control instructions. Following a

RESET, the value of SBUF is undetermined.

When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer

register are output to the SO pin (P0.1) at the rate of one bit for each falling edge of the SIO clock. Receive data

are simultaneously input from the SI pin (P0.2) to SBUF at the rate of one bit for each rising edge of the SIO

clock. When receive-only mode is used, incoming data are input to the SIO buffer at the rate of one bit for each

rising edge of the SIO clock.

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O

1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fxx/2⁴and in

MSB-first mode:

BITS

SMB

LD

Bits

EMB

15

EA,#03H

PMG1,EA

EA,#0E6H

SMOD,EA

EA,#48H

SBUF,EA

SMOD.3

; P0.0 / SCK and P0.1 / SO ¬ Output

; SIO data transfer

/ P0.0

EXTERNAL

DEVICE

SCK

SO / P0.1

S3C7565

2. Use CPU clock to transfer and receive serial data at high speed:

BITR

LD

EMB

EA,#03H

LD

PMG1,EA

; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2 / SI ¬

; Input

LD

BITS

BITR

BTSTZ

JR

EA,#47H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

IES

; TDATA address = Bank0 (20H–7FH)

; SIO start

; SIO interrupt disable

STEST

IRQS

STEST

LD

EA,SBUF

RDATA,EA

; RDATA address = Bank0 (20H–7FH)

14-5

SERIAL I/O INTERFACE

S3C7565/P7565

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:

BITR

LD

BITS

EI

EMB

EA,#03H

PMG1,EA

EA,#87H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2/SI ¬ Input

; TDATA address = Bank0 (20H–7FH)

; SIO start

BITS

IES

; SIO interrupt enable

·

INTS

PUSH

BITR

LD

SB

EA

EMB

EA,TDATA

; Store SMB, SRB

; Store EA

; EA ¬ Transmit data

; TDATA address = Bank0 (20H–7FH)

; Transmit data « Receive data

; RDATA address = Bank0 (20H–7FH)

; SIO start

XCH

LD

BITS

POP

IRET

EA,SBUF

RDATA,EA

SMOD.3

EA

SB

/ P0.0

EXTERNAL

DEVICE

SCK

SO / P0.1

SI / P0.2

S3C7565

14-6

S3C7565/P7565

SERIAL I/O INTERFACE

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

4. Transmit and receive an external clock in LSB-first mode:

BITR

LD

BITS

EI

EMB

EA,#02H

PMG1,EA

EA,#07H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

; P0.1/SO ¬ Output, P0.0/SCK and P0.2/SI ¬ Input

; TDATA address = Bank0 (20H–7FH)

; SIO start

BITS

IES

; SIO interrupt enable

·

INTS

PUSH

BITR

LD

SB

EA

EMB

EA,TDATA

; Store SMB, SRB

; Store EA

; EA ¬ Transmit data

; TDATA address = Bank0 (20H–7FH)

; Transmit data « Receive data

; RDATA address = Bank0 (20H–7FH)

; SIO start

XCH

LD

BITS

POP

IRET

EA,SBUF

RDATA,EA

SMOD.3

EA

SB

/ P0.0

EXTERNAL

DEVICE

SCK

SO / P0.1

SI / P0.2

S3C7565

High Speed SIO Transmission

14-7

SERIAL I/O INTERFACE

S3C7565/P7565

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Concluded)

Use CPU clock to transfer and receive serial data at high speed:

BITS

SMB

LD

EMB

15

EA,#03H

LD

PMG1,EA

EA,#47H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

IES

; P0.0/SCK and P0.1/SO ¬ Output, P0.2/SI ¬ Input

LD

; SIO start

BITS

BITR

BTSTZ

JR

STEST

IRQS

STEST

LD

SMB

LD

EA,SBUF

0

RDATA,EA

14-8

S3C7565/P7565

COMPARATOR

15 COMPARATOR

OVERVIEW

Port 7 can be used as an analog input port for a comparator. The reference voltage for the 4-channel comparator

can be supplied either internally or externally at P7.3. When an internal reference voltage is used, four channels

(P7.0–P7.3) are used for analog inputs and the internal reference voltage varies within at 16 levels. If an external

reference voltage is input to P7.3, the remaining three pins (P7.0–P7.2) in port 7 are used for analog input.

Unused port 7 pins must be connected to V_DD.

When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial

values of the CMPREG are undefined and the comparator operation is disabled by a RESET. The comparator

module has the following components:

— Comparator

— Internal reference voltage generator (4-bit resolution)

— External reference voltage source at P7.3

— Comparator mode register (CMOD)

— Comparison result register (CMPREG)

15-1

COMPARATOR

S3C7565/P7565

P7.0/CIN0

M

U

X

P7.1/CIN1

P7.2/CIN2

P7.3/CIN3

Comparison

Result

Register

+

4

-

(CMPREG)

V

REF

(External)

M

U

X

V

DD

CMOD.7

CMOD.6

CMOD.5

0

1/2R

R

M

U

X

V

REF

(Internal)

8

CMOD.3

CMOD.2

CMOD.1

CMOD.0

1/2R

Figure 15-1. Comparator Circuit Diagram

15-2

S3C7565/P7565

COMPARATOR

COMPARATOR MODE REGISTER (CMOD)

The comparator mode register CMOD is an 8-bit register that is used to select the operation mode of the

comparator. It is mapped to addresses FD2H–FD3H and can be manipulated using 8-bit memory instructions.

Based on the CMOD.5 bit setting, an internal or an external reference voltage is input for the comparator, as

follows:

When CMOD.5 is set to logic zero:

— A reference voltage is selected by the CMOD.0 to CMOD.3 bit settings.

— P7.0–P7.3 are used as analog input pins.

— The internal digital to analog converter generates 16 reference voltages.

— The comparator can detect 150-mV differences between the reference voltage and the analog input

voltages.

— Comparator results are written into bits 0–3 of the comparison result register (CMPREG).

When CMOD.5 is set to logic one:

— An external reference voltage is supplied from P7.3/CIN3.

— P7.0 to P7.2 are used as the analog input pins.

— The comparator can detect 150-mV differences between the reference voltage and the analog input

voltages.

— Bits 0–2 in the CMPREG register contain the results.

Bit 6 in the CMOD register controls conversion time while bit 7 enables or disables comparator operation to

reduce power consumption. A RESET signal clears all bits to logic zero, causing the comparator to enter stop

mode.

CMOD.7 CMOD.6 CMOD.5

“ 0"

CMOD.3 CMOD.2 CMOD.1 CMOD.0

FD6H–FD7H

Reference Voltage (V

) Selection:

REF

V

x (n + 0.5)/16, n = 0 to 15

DD

1: CIN3; external reference, CIN0–2; analog input

0: Internal reference, CIN0–3; analog input

4

1: Conversion time (8 x 2 /fx, 30.5 µs @4.19 MHz)

7

0: Conversion time (8 x 2 /fx, 244.4 µs @4.19 MHz)

1: Comparator operation enable

0: Comparator operation disable

Figure 15-2. Comparator Mode Register (CMOD) Organization

15-3

COMPARATOR

S3C7565/P7565

PORT 7 MODE REGISTER (P7MOD)

P7MOD register settings determine whether port 7 would be used for analog or digital input. P7MOD is a 4-bit

write-only register. P7MOD is mapped to the address FCEH and initialized to logic zero by a RESET, which

configures port 7 as a digital input port.

FCEH

P7MOD.3 P7MOD.2 P7MOD.1 P7MOD.0

When the bit is set to “1”, the corresponding pin is configured as an analog input pin. When set to "0", it is

configured as a digital input pin: P7MOD.0 for P7.0, P7MOD.1 for P7.1, P7MOD.2 for P7.2, and P7MOD.3 for

P7.3.

COMPARATOR OPERATION00

The comparator compares analog voltage input at CIN0–CIN3 with an external or internal reference voltage

(V

) that is selected by the CMOD register. The result is written to the comparison result register CMPREG at

REF

address FD4H. The comparison result at internal reference is calculated as follows:

If "1" Analog input voltage ³ V_REF+ 150 mV

If "0" Analog input voltage £ V_REF– 150 mV

To obtain a comparison result, the data must be read out from the CMPREG register after V_REFis updated by

changing the CMOD value after a conversion time has elapsed.

Analog Input

Voltage CIN0-3)

Reference

Voltage (V

)

REF

Comparison Time

(CMPCLK x 8)

Comparator Clock

(CMPCLK, fx/32, fx/256)

Comparison

Start

Comparison

End

Comparison

Result (CMPREG)

Unknown

1

Unknown

0

Figure 15-3. Conversion Characteristics

15-4

S3C7565/P7565

COMPARATOR

+

PROGRAMMING TIP — Programming the Comparator

The following code converts the analog voltage input at the CIN0–CIN3 pins into 4-bit digital code.

BITR

LD

EMD

A,#0FH

P7MOD,A

EA,#0CxH

; Analog input selection (CIN0–CIN3)

; x = 0 – F, comparator enable

; Internal reference, conversion time

(30.5 µs at 4.19 MHz)

LD

INCS

JR

LD

INCS

JR

LD

CPSE

JR

LD

·

CMOD,EA

L,#0H

L

WAIT1

A,CMPREG

W,A

WAIT1

WAIT2

L

WAIT2

A,CMPREG

A,W

RECHECK

20H,A

; Store the result to general register 20H

·

RECHECK LD

JPS

W,A

WAIT2

15-5

COMPARATOR

S3C7565/P7565

NOTES

15-6

S3C7565/P7565

ELECTRICAL DATA

16 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7565 electrical characteristics is presented as tables and graphics. The

information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings

— D.C. electrical characteristics

— Main system clock oscillator characteristics

— Subsystem clock oscillator characteristics

— I/O capacitance

— A.C. electrical characteristics

— Operating voltage range

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode

— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

Miscellaneous Timing Waveforms

— A.C timing measurement point

— Clock timing measurement at X_IN

— Clock timing measurement at XT_IN

— TCL timing

— Input timing for RESET

— Input timing for external interrupts

— Serial data transfer timing

16-1

ELECTRICAL DATA

S3C7565/P7565

Table 16-1. Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Units

V

V_DD

V_I

Supply Voltage

Input Voltage

–

– 0.3 to + 6.5

– 0.3 to V_DD+ 0.3

Ports 0–10

V

V_O

I_OH

Output Voltage

Output Current High

–

V

One I/O pin active

– 15

mA

All I/O pins active

One I/O pin active

– 35

I_OL

Output Current Low

+ 30 (Peak value)

mA

+ 15 ^(note)

+ 100 (Peak value)

+ 60 ^(note)

Total for ports 0, 2–10

T_A

°

Operating Temperature

Storage Temperature

–

– 40 to + 85

C

T_STG

°

C

– 65 to + 150

NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .

OL

Table 16-2. D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

0.7 V_DD

V_DD

Input High

Voltage

All input pins except those

specified below for V_IH2–V_IH3

–

V

V_IH2

0.8 V_DD

V_DD

Ports 0, 1, 2, 6, P3.2, P3.3, and

RESET

V_IH3

V_IL1

X_IN, X_OUT, and XT_IN

V_DD– 0.1

–

0.3V_DD

Input Low

Voltage

All input pins except those

–

V

specified below for V _L2–V_IL3

I

V_IL2

0.2V_DD

Ports 0, 1, 2, 6, P3.2, P3.3, and

RESET

V_IL3

V_OH

X_IN, X_OUT, and XT_IN

0.1

–

V_DD= 4.5 V to 5.5 V

I_OH= – 1 mA

V_DD– 1.0

Output High

Voltage

–

V

Ports 0, 2–10

V_OL

V_DD= 4.5 V to 5.5 V

I_OL= 15 mA

Output Low

Voltage

–

2.0

Ports 0, 2–10

16-2

S3C7565/P7565

ELECTRICAL DATA

Table 16-2. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

I_LIH1

V_I= V_DD

Input High

Leakage

Current

–

3

µA

All input pins except those

specified below for I_LIH2

I_LIH2

V_I= V_DD

X_IN, XT_IN

20

I_LIL1

V = 0 V

I

Input Low

Leakage

Current

–

– 3

µA

All input pins except RESET,

X_IN, XT_IN

I_LIL2

I_LOH

V = 0 V

I

X_IN, XT_IN

– 20

3

V_O= V_DD

Output High

Leakage

Current

–

µA

kW

All output pins

I_LOL

V_O= 0 V

Output Low

Leakage

Current

– 3

All output pins

R_LI

V_I= 0 V; V_DD= 5 V, Port 0–10

V_DD= 3 V

Pull-Up

Resistor

25

47

100

50

95

200

400

R_L2

100

220

V_I= 0 V; V_DD= 5 V, RESET

V_DD= 3 V

200

40

450

55

800

70

R_LCD1

LCD Voltage

Dividing

–

kW

Resistor ^(Note)

V

R_LCD2

V_DC

20

–

28

–

35

V_DD= 2.7 V to 5.5 V

120

mV

|

_DD-COMi|

Voltage Drop

(i = 0–15)

– 15 µA per common pin

V

V_DS

V_DD= 2.7 V to 5.5 V

–

120

|

_DD-SEGx|

Voltage Drop

(x = 0–59)

– 15 µA per segment pin

V

V_LC1

V_DD= 2.7 V to 5.5 V

LCD clock = 0 Hz

V_DD–0.2

V_DD

V_DD+ 0.2

V

_LCXOutput

Voltage

V_LC2

V_LC3

V_LC4

V_LC5

0.8V_DD–0.2 0.8V_DD0.8V_DD+0.2

0.6V_DD–0.2 0.6V_DD0.6V_DD+0.2

0.4V_DD–0.2 0.4V_DD0.4V_DD+0.2

0.2V_DD–0.2 0.2V_DD0.2V_DD+0.2

NOTE: R

is the LCD Voltage dividing resistor when LCON.1 = “0”, and R

when LCON.1 = “1”.

LCD1

LCD2

16-3

ELECTRICAL DATA

S3C7565/P7565

Table 16-2. D.C. Electrical Characteristics (Concluded)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Supply

Symbol

Conditions

Min

Typ

Max

Units

I

–

3.9

7.0

mA

Run mode; V

= 5 V ± 10 %

DD1

DD

(1)

Current

3.58 MHz X-tal oscillator,

C1 = C2 = 22 pF

(DTMF on)

–

2.0

4.0

V

= 3 V ± 10 %

DD

Run mode;

= 5 V ± 10%

I

6.0 MHz

3.58 MHz

4.1

2.7

8.0

5.0

DD2

V

(DTMF off)

DD

Crystal oscillator

C1 = C2 = 22pF

6.0 MHz

3.58 MHz

1.9

1.2

4.0

2.3

V

= 3 V ± 10%

DD

I

Idle mode;

= 5 V ± 10 %

6.0 MHz

3.58 MHz

–

1.2

0.9

2.5

1.8

DD3

V

DD

Crystal oscillator

C1 = C2 = 22pF

6.0 MHz

3.58 MHz

0.5

0.4

1.5

1.0

V

= 3 V ± 10 %

DD

(2)

–

17.5

45

Run mode; V

= 3 V ± 10 %

mA

I

DD

DD4

32 kHz Crystal oscillator

Idle mode; V = 3 V ± 10 %

(2)

4.8

15

I

DD

DD5

32 kHz Crystal oscillator

I

Stop mode;

SCMOD = 0000

DD6

XT = 0 V

2.0

0.6

5

3

V

= 5 V ± 10 %

= 3 V ± 10 %

IN

DD

Stop mode;

SCMOD = 0100

0.2

0.1

3

2

V

= 5 V ± 10 %

DD

V

= 3 V ± 10 %

Row Tone level

V

= 2 to 5.5 V

– 16.0

1

– 14.0

2

– 11.0

3

dBV

%

ROW

DD

RL = 12 KW; Temp = – 30 to 60 °C

V = 2 to 5.5 V

DD

RL = 12 KW; Temp = – 30 to 60 °C

Ratio of

Column to Row

tone

dBCR

THD

Distortion

(Dual tone)

V

= 2 to 5.5 V

–

5

DD

1 MHz band

RL = 12 KW; Temp = – 30 to 60 °C

NOTES:

1. Data includes power consumption for subsystem clock oscillation.

2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the

subsystem clock is used.

3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and

output port drive currents.

16-4

S3C7565/P7565

ELECTRICAL DATA

Table 16-3. Main System Oscillator Characteristics

(T_A= – 40 °C + 85 C, V_DD= 1.8 V to 5.5 V)

°

Oscillator

Clock

Parameter

Test Condition

Min

Typ Max Units

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Ceramic

0.4

–

6.0

MHz

XIN

XOUT

Oscillator

C1

C2

V_DD= 1.8 V to 5.5 V

0.4

–

3

4

Stabilization time ⁽²⁾

Stabilization occurs

when V_DDis equal to

ms

the minimum

oscillator voltage

range; V_DD= 3.0 V

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Crystal

0.4

–

6.0

MHz

XIN

XOUT

Oscillator

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3 V

0.4

–

3

Stabilization time ⁽²⁾

10

30

6.0

ms

V_DD= 1.8 V to 5.5 V

V_DD= 2.7 V to 5.5 V

–

External

Clock

0.4

MHz

XIN

XOUT

X_INinput frequency ⁽¹⁾

V_DD= 1.8 V to 5.5 V

–

0.4

–

3

X_INinput high and low

level width (t_XH, t_XL)

83.3

1,250

ns

RC

Oscillator

Frequency

–

2

–

MHz

R = 25 kW, V_DD= 5 V

XIN

XOUT

R

1

R = 40 kW, V_DD= 3 V

NOTES:

1. Oscillation frequency and X_INinput frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

16-5

ELECTRICAL DATA

S3C7565/P7565

Table 16-4. Recommended Oscillator Constants

°

(T_A= – 40 C to + 85 C)

Manufacturer

Series

Number ⁽¹⁾

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

C1

33

(2)

C2

33

(2)

MIN

2.0

MAX

5.5

TDK

3.58 MHz–6.0 MHz

Leaded Type

FCR” ðÿM5

2.0

5.5

On-chip C

FCR” ðÿMC5

Leaded Type

(3)

3.58 MHz–6.0 MHz

2.0

5.5

On-chip C

SMD Type

CCR” ðÿMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

Table 16-5. Subsystem Clock Oscillator Characteristics

(T_A= – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

°

Oscillator

Clock

Parameter

Test Condition

Min

Typ

Max Units

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 1.8 V to 5.5 V

Crystal

Oscillator

32

32.768

35

kHz

XTIN XTOUT

C1

C2

Stabilization time ⁽²⁾

V_DD= 2.7 V to 5.5 V

V_DD= 1.8 V to 5.5 V

–

1.0

–

2

s

10

External

Clock

32

–

100

kHz

XTIN XTOUT

Open

XT input frequency ⁽¹⁾

IN

XT input high and low

IN

–

5

–

15

µs

level width (t_XTL, t_XTH

)

NOTES:

1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.

16-6

S3C7565/P7565

ELECTRICAL DATA

Table 16-6. Input/output Capacitance

°

(T_A= 25 C, V_DD= 0 V )

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

Units

C_IN

f = 1 MHz; Unmeasured pins

are returned to V_SS

–

15

pF

C_OUT

C_IO

Output

Capacitance

–

15

pF

I/O Capacitance

Table 16-7. Comparator Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 4.0 V to 5.5 V, V_SS= 0 V)

Parameter

Symbol

–

Condition

Min

Typ

Max

Units

V_DD

Input Voltage Range

–

0

–

V

V_REF

V_DD

± 150

3

Reference Voltage Range

Input Voltage Accuracy

Input Leakage Current

–

0

–

V

V_CIN

mV

mA

I_CIN, I_REF

– 3

16-7

ELECTRICAL DATA

S3C7565/P7565

Table 16-8. A.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

t_CY

V_DD= 2.7 V to 5.5 V

Instruction Cycle

Time ^(note)

0.67

–

64

µs

V_DD= 1.8 V to 5.5 V

V_DD= 2.7 V to 5.5 V

1.33

0

64

f_TI0, f_TI1

TCL0, TCL1 Input

Frequency

–

1.5

MHz

µs

V_DD= 1.8 V to 5.5 V

1

–

t_TIH0, t_TIL0V_DD= 2.7 V to 5.5 V

t_TIH1, t_TIL1

TCL0, TCL1 Input

High, Low Width

0.48

V_DD= 1.8 V to 5.5 V

1.8

t_KCY

V_DD= 2.7 V to 5.5 V

800

–

ns

SCK Cycle Time

External SCK source

650

Internal SCK source

V_DD= 1.8 V to 5.5 V

External SCK source

3200

3800

Internal SCK source; Output

16-8

S3C7565/P7565

ELECTRICAL DATA

Table 16-8. A.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

V_DD= 2.7 V to 5.5 V

External SCK source

Min

Typ

Max

Units

t_KH, t_KL

325

–

ns

SCK High, Low

Width

T_kCY

/

Internal SCK source

2–50

1600

V_DD= 1.8 V to 5.5 V

External SCK source

t_KCY

/

Internal SCK source

2–150

t_SIK

V_DD= 2.7 V to 5.5 V; Input

SI Setup Time to

100

–

ns

SCK High

V_DD= 2.7 V to 5.5 V; Output

V_DD= 1.8 V to 5.5 V; Input

V_DD= 1.8 V to 5.5 V; Output

V_DD= 2.7 V to 5.5 V; Input

150

500

400

t_KSI

SI Hold Time to

SCK High

V_DD= 2.7 V to 5.5 V; Output

V_DD= 1.8 V to 5.5 V; Input

V_DD= 1.8 V to 5.5 V; Output

V_DD= 2.7 V to 5.5 V; Input

400

600

500

–

t_KSO

Output Delay for

300

SCK to SO

V_DD= 2.7 V to 5.5 V; Output

V_DD= 1.8 V to 5.5 V; Input

V_DD= 2.7 V to 5.5 V; Output

INT0–INT2, INT4, KS0–KS7

250

1000

–

t_INTH, t_INTL

t_RSL

Interrupt Input

High, Low Width

10

–

µs

Input

–

RESET Input Low

Width

NOTE: Unless specified the otherwise, Instruction Cycle Time condition values assume a main system clock (fx) source.

16-9

ELECTRICAL DATA

S3C7565/P7565

Main Os. Freq. (Divided by 4)

6MHz

CPU Clock

1.5MHz

4.2MHz

3MHz

1.05MHz

0.75kHz

15.625kHz

1

2

3

4

5

6

7

1.8

2.7

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)

Figure 16-1. Standard Operating Voltage Range

Table 16-9. RAM Data Retention Supply Voltage in Stop Mode

°

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

1.8

–

Typ

–

Max

Unit

V

V_DDDR

Data retention supply voltage

Data retention supply current

–

5.5

10

I_DDDR

V_DDDR= 1.8 V

0.1

µA

t_SREL

t_WAIT

Release signal set time

–

0

–

µs

2¹⁷/ fx

Oscillator stabilization wait

time ⁽¹⁾

ms

Released by RESET

(2)

Released by interrupt

–

NOTES:

1. During the oscillator stabilization wait time, all the CPU operations must be stopped to avoid instability that can occur

during the oscillator start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay an execution of CPU instructions during the wait time.

16-10

S3C7565/P7565

ELECTRICAL DATA

TIMING WAVEFORMS

InternalReset

Operation

Idle Mode

Stop Mode

Operating

Mode

Data Retention Mode

VDD

VDDDR

Execution of

STOP Instruction

RESET

t

WAIT

t

SREL

Figure 16-2. Stop Mode Release Timing When Initiated by RESET

Idle Mode

Normal

Operating

Mode

Stop Mode

Data Retention Mode

VDD

VDDDR

tSREL

Execution of

STOP Instrction

tWAIT

Power-down Mode Terminating Signal

(Interrupt Request)

Figure 16-3. Stop Mode Release Timing When Initiated by Interrupt Request

16-11

ELECTRICAL DATA

S3C7565/P7565

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

Measurement

Points

Figure 16-4. A.C. Timing Measurement Points (Except for X_INand XT_IN)

1/fx

tXL

tXH

XIN

VDD - 0.1 V

0.1 V

Figure 16-5. Clock Timing Measurement at X

IN

1/fxt

tXTL

tXTH

XTIN

VDD - 0.1 V

0.1 V

Figure 16-6. Clock Timing Measurement at XT

IN

16-12

S3C7565/P7565

ELECTRICAL DATA

1/fTI

tTIL

tTIH

TCL0

0.8 VDD

0.2 VDD

Figure 16-7. TCL Timing

tRSL

RESET

0.2 VDD

Figure 16-8. Input Timing for RESET Signal

16-13

ELECTRICAL DATA

S3C7565/P7565

tINTL

tINTH

INT0, 1, 2, 4

K0 to K7

0.8 VDD

0.2 VDD

Figure 16-9. Input Timing for External Interrupts and Quasi-Interrupts

tKCY

tKL

tKH

SCK

0.8 VDD

0.2 VDD

tSIK

tKSI

0.8 VDD

0.2 VDD

SI

Input Data

tKSO

SO

Output Data

Figure 16-10. Serial Data Transfer Timing

16-14

S3C7565/P7565

MECHANICAL DATA

17 MECHANICAL DATA

This section contains the following information about the device package:

— Package dimensions in millimeters

— Pad diagram

— Pad/pin coordinate data table

23.90 ± 0.3

20.00 ± 0.2

0-8^O

+0.10

_0.05

0.15

0.10 MAX

100-QFP-1420C

#100

#1

0.65

(0.58)

0.30 ± 0.1

0.10 MAX

0.05 MIN

2.65 ± 0.10

3.00 MAX

0.80 ± 0.20

Figure 17-1. 100-QFP Package Dimensions

NOTE: Dimensions are in millimeters.

17-1

MECHANICAL DATA

S3C7565/P7565

NOTES

17-2

S3C7565/P7565

S3P7565 OTP

18 S3P7565 OTP

OVERVIEW

The S3P7565 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7565

microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data

format.

The S3P7565 is fully compatible with the S3C7565, both in function and in pin configuration. Because of its

simple programming requirements, the S3P7565 is ideal for use as an evaluation chip for the S3C7565.

18-1

S3P7565 OTP

S3C7565/P7565

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

P10.3/SEG40

P10.2/SEG41

P10.1/SEG42

P10.0/SEG43

P9.3/SEG44

P9.2/SEG45

P9.1/SEG46

P9.0/SEG47

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

1

2

3

4

5

6

7

8

9

DTMF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P0.0/SCK/K0

P0.1/SO/K1

SDAT/P0.2/SI/K2

SCLK/P0.3/BUZ/K3

VDD/VDD

VSS/VSS

XOUT

XIN

VPP/TEST

XTIN

P8.3/SEG48

P8.2/SEG49

XTOUT

P8.1/SEG50/LCDSY

P8.0/SEG51/LCDCK

P7.3/SEG52/CIN3

P7.2/SEG53/CIN2

P7.1/SEG54/CIN1

P7.0/SEG55/CIN0

P6.3/SEG56/K7

P6.2/SEG57/K6

P6.1/SEG58/K5

RESET/RESET

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

P2.0/CLO

P2.1/VLC1

P2.2

P3.0/TCLO0

Figure 18-1. S3P7565 Pin Assignments (100-QFP Package)

18-2

S3C7565/P7565

S3P7565 OTP

Table 18-1. Descriptions of Pins Used to Read/Write the EPROM

During Programming

Main Chip

Pin Name

P0.2

Pin Name

Pin No.

I/O

Function

SDAT

13

I/O

Serial data pin. Output port when reading and input

port when writing. Can be assigned as a Input/push-

pull output port.

P0.3

SCLK

14

19

I/O

I

Serial clock pin. Input only pin.

V_PP(TEST)

TEST

Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5

V is applied, OTP is in writing mode and when 5 V

is applied, OTP is in reading mode. When OTP is

operating, hold GND. (Option)

22

I

Chip initialization

RESET

V_DD/V_SS

Logic power supply pin. V_DDshould be tied to + 5 V

during programming.

15/16

Table 18-2. Comparison of S3P7565 and S3C7565 Features

S3P7565

Characteristic

S3C7565

Program Memory

16-Kbyte EPROM

1.8 V to 5.5 V

16-Kbyte mask ROM

Operating Voltage (V_DD

)

1.8 V to 5.5 V

V_DD= 5 V, V_PP(TEST) = 12.5V

OTP Programming Mode

Pin Configuration

100 QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V_PP(TEST) pin of the S3P7565, the EPROM programming mode is entered. The

operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 18-3 below.

Table 18-3. Operating Mode Selection Criteria

V_DD

V_PP

(TEST)

REG/MEM

Address

(A15–A0)

0000H

R/W

Mode

5 V

0

1

0

1

0

EPROM read

12.5 V

0000H

EPROM program

EPROM verify

0000H

0E3FH

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

18-3

S3P7565 OTP

S3C7565/P7565

Table 18-4. Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

– 0.3 to + 6.5

Units

V_DD

V_I

Supply Voltage

Input Voltage

–

V

– 0.3 to V_DD+ 0.3

– 15

Ports 0–10

V

V_O

I_OH

Output Voltage

Output Current High

–

One I/O pin active

mA

All I/O pins active

One I/O pin active

– 35

I_OL

Output Current Low

+ 30 (Peak value)

mA

+ 15 ^(note)

Total for ports 0, 2–10

+ 100 (Peak value)

+ 60 ^(note)

°

T_A

Operating Temperature

Storage Temperature

–

– 40 to + 85

C

°

C

T_STG

– 65 to + 150

NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .

OL

18-4

S3C7565/P7565

S3P7565 OTP

Table 18-5. D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

0.7 V_DD

V_DD

Input High

Voltage

All input pins except those

specified below for V_IH2–V_IH3

–

V

V_IH2

0.8 V_DD

V_DD

Ports 0, 1, 2, 6, P3.2, P3.3, and

RESET

V_IH3

V_IL1

X_IN, X_OUT, and XT_IN

V_DD– 0.1

–

V_DD

0.3 V_DD

Input Low

Voltage

All input pins except those

specified below for V_IL2–V_IL3

–

V

V_IL2

0.2 V_DD

Ports 0, 1, 2, 6, P3.2, P3.3,

and RESET

V_IL3

V_OH

X_IN, X_OUT, and XT_IN

0.1

–

V_DD= 4.5 V to 5.5 V

I_OH= – 1 mA

V_DD– 1.0

Output High

Voltage

–

V

Ports 0, 2–10

V_OL

V_DD= 4.5 V to 5.5 V

I_OL= 15 mA

Output Low

Voltage

–

2.0

3

Ports 0, 2–10

V_I= V_DD

I_LIH1

Input High

Leakage

Current

–

µA

All input pins except those

specified below for I_LIH2

I_LIH2

V_I= V_DD

X_IN, XT_IN

20

I_LIL1

V_I= 0 V

Input Low

Leakage

Current

– 3

All input pins except RESET,

X_IN, XT_IN

I_LIL2

V_I= 0 V

– 20

3

X_INXT

,

IN

I_LOH

V_O= V_DD

Output High

Leakage

Current

–

µA

All output pins

I_LOL

V_O= 0 V

Output Low

Leakage

Current

– 3

All output pins

18-5

S3P7565 OTP

S3C7565/P7565

Table 18-5. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

R_LI

V_I= 0 V; V_DD= 5 V,

Port 0–10

Pull-up Resistor

25

47

100

kW

V_DD= 3 V

50

95

200

400

R_L2

100

220

V_I= 0 V; V_DD= 5 V, RESET

V_DD= 3 V

200

40

450

55

800

70

R_LCD1

LCD Voltage

Dividing

–

kW

Resistor ^(note)

R_LCD2

V_DC

20

–

28

–

35

|V_DD–COMi|

V_DD= 2.7 V to 5.5 V

120

mV

Voltage Drop

(i = 0–15)

– 15 µA per common pin

|V_DD–SEGx|

V_DS

V_DD= 2.7 V to 5.5 V

–

120

Voltage Drop

(x = 0–59)

– 15 µA per segment pin

V_LCXOutput

Voltage

V_LC1

V_DD= 2.7 V to 5.5 V

LCD clock = 0 Hz

V_DD–0.2

V_DD

V_DD+0.2

V

V_LC2

V_LC3

V_LC4

V_LC5

0.8V_DD–0.2 0.8V_DD0.8V_DD+0.2

0.6V_DD–0.2 0.6V_DD0.6V_DD+0.2

0.4V_DD–0.2 0.4V_DD0.4V_DD+0.2

0.2V_DD–0.2 0.2V_DD0.2V_DD+0.2

NOTE: R

is the LCD Voltage dividing resistor when LCON.1 = “0”, and R

is the one when LCON.1 = “1”.

LCD1

LCD2

18-6

S3C7565/P7565

S3P7565 OTP

Table 18-5. D.C. Electrical Characteristics (Concluded)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

I_DD1

Conditions

Min

Typ

Max

Units

Supply Current ⁽¹⁾

–

3.9

7.0

mA

Run mode; V_DD= 5 V ± 10 %

3.58 MHz X-tal oscillator,

C1 = C2 = 22 pF

(DTMF on)

–

2.0

4.0

V_DD= 3 V ± 10%

I_DD2

Run mode;

V_DD= 5 V ± 10 %

6.0 MHz

3.58 MHz

4.1

2.7

8.0

5.0

(DTMF off)

Crystal oscillator

C1 = C2 = 22 pF

V

= 3 V ± 10 %

6.0 MHz

3.58 MHz

1.9

1.2

4.0

2.3

DD

I_DD3

Idle mode;

V_DD= 5 V ± 10 %

6.0 MHz

3.58 MHz

–

1.2

0.9

2.5

1.8

Crystal oscillator

C1 = C2 = 22 pF

6.0 MHz

3.58 MHz

0.5

0.4

1.5

1.0

V_DD= 3 V ± 10 %

(2)

–

17.5

45

Run mode; V_DD= 3 V ± 10 %

mA

I_DD4

32 kHz Crystal oscillator

(2)

y

15

Idle mode; V_DD= 3 V ± 10 %

I_DD5

32 kHz Crystal oscillator

I_DD6

Stop mode;

SCMOD = 0000

2.0

0.6

5

3

XT_IN= 0 V

V_DD= 5 V ± 10 %

V_DD= 3 V ± 10 %

Stop mode;

V_DD= 5 V ± 10 %

SCMOD = 0100

0.2

0.1

3

2

V_DD= 3 V ± 10 %

V_ROW

d_BCR

THD

V_DD= 2 to 5.5 V

Row Tone Level

– 16.0

– 14.0

– 11.0

dBV

%

RL = 12 KW; Temp = – 30 to 60 °C

V_DD= 2 to 5.5 V

Ratio of Column to

Row tone

1

–

2

–

3

5

RL = 12 KW; Temp = – 30 to 60 °C

V_DD= 2 to 5.5 V

Distortion

(Dual tone)

1 MHz band

RL = 12 KW; Temp = – 30 to 60 °C

NOTES:

1. Data includes power consumption for subsystem clock oscillation.

2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the

subsystem clock is used.

3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and

output port drive currents.

18-7

S3P7565 OTP

S3C7565/P7565

Table 18-6. Main System Oscillator Characteristics

(T_A= – 40 °C + 85 C, V_DD= 1.8 V to 5.5 V)

°

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max Unit

s

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

0.4

–

6.0

MHz

Ceramic

XIN

XOUT

Oscillator

C1

C2

V_DD= 1.8 V to 5.5 V

0.4

–

3.0

4

Stabilization time ⁽²⁾

ms

Stabilization occurs

when V_DDis equal to

the minimum

oscillator voltage

range; V_DD= 3.0 V

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

0.4

–

6.0

MHz

Crystal

XIN

XOUT

Oscillator

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3 V

0.4

–

3.0

10

Stabilization time ⁽²⁾

ms

V_DD= 1.8 V to 5.5 V

V_DD= 2.7 V to 5.5 V

–

30

X_INinput frequency ⁽¹⁾

0.4

6.0

MHz

External

Clock

XIN

XOUT

V_DD= 1.8 V to 5.5 V

–

0.4

–

3.0

X_INinput high and low

level width (t_XH, t_XL)

83.3

1,250

ns

–

2

–

MHz

RC

Oscillator

Frequency

XIN

XOUT

R = 25 kW, V_DD= 5 V

R

1

R = 40 kW, V_DD= 3 V

NOTES:

1. Oscillation frequency and X_INinput frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

18-8

S3C7565/P7565

S3P7565 OTP

Table 18-7. Subsystem Clock Oscillator Characteristics

°

(T_A= – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator

Clock

Parameter

Test Condition

Min

Typ

Max Units

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 1.8 V to 5.5 V

Crystal

Oscillator

32 32.768

35

kHz

XTIN XTOUT

C1

C2

Stabilization time ⁽²⁾

V_DD= 2.7 V to 5.5 V

V_DD= 1.8 V to 5.5 V

–

1.0

–

2

s

10

XT_INinput frequency ⁽¹⁾

External

Clock

32

–

100

kHz

XTIN XTOUT

Open

XT_INinput high and low

–

5

–

15

µs

level width (t_XTL, t_XTH

)

NOTES:

1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.

Table 18-8. Input/Output Capacitance

°

(T_A= 25 C, V_DD= 0 V )

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

Units

C_IN

f = 1 MHz; Unmeasured pins

are returned to V_SS

–

15

pF

C_OUT

C_IO

Output

Capacitance

–

15

pF

I/O Capacitance

18-9

S3P7565 OTP

S3C7565/P7565

Main Os. Freq. (Divided by 4)

6MHz

CPU Clock

1.5MHz

4.2MHz

3MHz

1.05MHz

0.75kHz

15.625kHz

1

2

3

4

5

6

7

1.8

2.7

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)

Figure 18-2. Standard Operating Voltage Range

18-10

S3C7565/P7565

DEVELOPMENT TOOLS

19 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development

support system is configured with a host system, debugging tools, and support software. For the host system, any

standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool

including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for

S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.

Samsung also offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked

help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be

sized, moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format. Assembled program code includes the object code that is used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and

an auxiliary definition (DEF) file with device specific information.

SASM57

The SASM57 is a relocatable assembler for Samsung's S3C7-series microcontrollers. The SASM57 takes a

source file containing assembly language statements and translates into a corresponding source code, object

code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating

system. It produces the relocatable object code only, so the user should link object file. Object files can be linked

with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value “FF” is filled into the unused ROM area upto the maximum ROM size of the target device

automatically.

TARGET BOARDS

Target boards are available for all S3C-series microcontrollers. All required target system cables and adapters

are included with the device-specific target board.

OTPs

One time programmable microcontroller (OTP) for the S3C7565 microcontroller and the OTP programmer

(Gang) are now available.

19-1

DEVELOPMENT TOOLS

S3C7565/P7565

IBM-PC AT or Compatible

RS-232C

SMDS2+

Target

Application

System

PROM/OTP Writer Unit

RAM Break/Display Unit

Trace/Timer Unit

Probe

Adapter

TB7565

Target

Board

POD

SAM4 Base Unit

Eva

Power Supply Unit

Chip

Figure 19-1. SMDS Product Configuration (SMDS2+)

19-2

S3C7565/P7565

DEVELOPMENT TOOLS

TB7565 TARGET BOARD

The TB7565 target board is used for the S3C7565 microcontroller. It is supported with the SMDS2+.

TB7565

To User_VCC

Off

On

RESET

Idle

Stop

J101

74HC11

25

J102

1

2

51

52

160 QFP

S3E7560

EVA Chip

1

XTAL

MDS

XTAL

XI

XTI

49

50 99

100

MDS

SM1259A

Figure 19-2. TB7565 Target Board Configuration

19-3

DEVELOPMENT TOOLS

S3C7565/P7565

Table 19-1. Power Selection Settings for TB7565

Operating Mode

“To User_Vcc” Settings

Comments

The SMDS2/SMDS2+

To User_VCC

supplies V_CCto the target

Target

System

Off

On

TB7565

VCC

VSS

board (evaluation chip) and

the target system.

VCC

SMDS2/SMDS2+

The SMDS2/SMDS2+

supplies V_CConly to the

To User_VCC

Off

External

VCC

On

Target

System

TB7565

target board (evaluation

chip). The target system

must have its own power

supply.

VSS

VCC

SMDS2+

Table 19-2. Main-Clock Selection Settings for TB7565

Operating Mode

Main Clock Settings

Comments

Set the X_INswitch to “MDS”

EVA Chip

S3E7560

when the target board is

connected to the

SMDS2/SMDS2+.

XOUT

XIN

No Connection

100 Pin Connector

SMDS2/SMDS2+

Set the X_INswitch to “XTAL”

EVA Chip

S3E7560

when the target board is used

as a standalone unit, and is

not connected to the

XTOUT

SMDS2/SMDS2+.

XTIN

No Connection

100 Pin Connector

SMDS2/SMDS2+

19-4

S3C7565/P7565

DEVELOPMENT TOOLS

Comments

Table 19-3. Sub-Clock Selection Settings for TB7565

Operating Mode

Sub Clock Settings

Set the XTI switch to “MDS”

when the target board is

connected to the

EVA Chip

S3E7560

SMDS2/SMDS2+.

XOUT

XIN

XTAL

Target Board

Set the XTI switch to “XTAL”

when the target board is used

as a standalone unit, and is

not connected to the

EVA Chip

S3E7560

SMDS2/SMDS2+.

XTOUT

XTIN

XTAL

Target Board

IDLE LED

This LED is ON when the evaluation chip (S3E7560) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (S3E7560) is in stop mode.

19-5

DEVELOPMENT TOOLS

S3C7565/P7565

J101

J102

SEG8

SEG6

SEG4

SEG2

SEG0

1

3

5

7

2

4

6

SEG7

SEG5

SEG3

SEG1

DTMF

P0.1/SO/K1

P0.3/BUZ/K3

P6.1/SEG58/K5

P6.3/SEG56/K7

P7.1/SEG54/CIN1

P7.3/SEG52/CIN3

P8.1/SEG50/LCDSY

P8.3/SEG48

P9.1/SEG46

P9.3/SEG44

P10.1/SEG42

P10.3/SEG40

SEG38

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

82

84

86

88

90

92

94

96

98

100

P6.2/SEG57/K6

P7.0/SEG55/CIN0

P7.2/SEG53/CIN2

P8.0/SEG51/LCDCK

P8.2/SEG49

P9.0/SEG47

P9.2/SEG45

P10.0/SEG43

P10.2/SEG41

SEG39

SEG37

SEG35

SEG33

SEG31

SEG29

SEG27

SEG25

SEG23

SEG21

SEG19

SEG17

SEG15

8

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

P0.0/SCK/K0

P0.2/SI/K2

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

VDD

VSS

XIN

XOUT

TEST

XT_OUT

P1.0/INT0

P1.2/INT2

P2.0/CLO

P2.2

P3.1/TCLO1

P3.3/TCL1

COM1

XT

IN

RESET

P1.1/INT1

P1.3/INT4

P2.1/V

P3.0/TCLO0

P3.2/TCL0

COM0

COM2

COM4

SEG36

SEG34

SEG32

SEG30

SEG28

SEG26

SEG24

SEG22

SEG20

SEG18

SEG16

SEG14

SEG12

SEG10

LC1

COM3

COM5

COM7

COM6

P4.0/COM8

P4.2/COM10

P5.0/COM12

P5.2/COM14

P4.1/COM9

P4.3/COM11

P5.1/COM13

P5.3/COM15

SEG13

SEG11

SEG9

P6.0/SEG59/K4

Figure 19-3. 50-Pin Connectors for TB7565

Target Board

Target System

J101

J102

J101

1

2

51 52

1

2

Target Cable for 50-Pin Connectors

Part Name: AS50D-A

Order Coder: SM6305

3

4

99 100

3

4

Figure 19-4. TB7565 Cables for 100 QFP Package (S3C7565)

19-6


型号：	S3P7565-QX
厂家：	SAMSUNG
描述：	Microcontroller, 4-Bit, OTPROM, SAM47 CPU, 6MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100 可编程只读存储器时钟微控制器外围集成电路
文件：	总274页 (文件大小：1625K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3P7565-QX [SAMSUNG]

相关型号：

S3P7574

S3P7588X

S3P7588XXX-TX

S3P8075

S3P8075XX-AT

S3P8075XX-QT

S3P8095

S3P8095-SO

S3P80A4

S3P80A5

S3P80A8

S3P80B4