S3P821AXX-QW_技术文档

S3C821A/P821A

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLES

Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range

of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupt

— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more

interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to

specific interrupt levels.

S3C821A/P821A MICROCONTROLLER

The S3C821A/P821A single-chip CMOS

microcontroller is fabricated using the highly

advanced CMOS process, based on Samsung’s

newest CPU architecture.

ports and one 7-bit port, for a total of 47 pins.

— Twelve bit-programmable pins for external

interrupts.

— One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset).

The S3C821A is a microcontroller with a 48-Kbyte

mask-programmable ROM embedded.

— One 8-bit timer/counter and one 16-bit

timer/counter with selectable operating modes.

The S3P821A is a microcontroller with a 48-Kbyte

one-time-programmable ROM embedded.

— Watch timer for real time.

— 4-input A/D converter

— Serial I/O interface

Using a proven modular design approach, Samsung

engineers have successfully developed the

S3C821A/P821A by integrating the following

peripheral modules with the powerful SAM8 core:

The S3C821A/P821A is versatile microcontroller for

cordless phone, pager, etc. They are currently

available in 80-pin TQFP and 80-pin QFP package.

— Six programmable I/O ports, including five 8-bit

OTP

The S3P821A is an OTP (One Time Programmable) version of the S3C821A microcontroller. The S3P821A

microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of a masked ROM. The

S3P821A is comparable to the S3C821A, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW

S3C821A/P821A

FEATURES

CPU

LCD Controller/Driver

•

SAM8 CPU core

•

Up to 32 segment pins

3, 4, and 8 common selectable

Choice of duty cycle

Memory

•

Data memory: 1040-byte of internal register file

(Excluding LCD RAM)

All dots can be switched on/off

Internal resistor circuit for LCD bias

Program memory: 48-Kbyte internal program

memory (ROM)

Serial Port

External Interface

64-Kbyte external data memory area

•

One synchronous SIO

•

A/D Converter

Instruction Execution Time

•

8-bit conversion resolution ´ 4 channel

34 ms conversion time (4 MHz CPU clock, fxx/4)

•

750 ns at 8 MHz (minimum, Main oscillator)

183 ms at 32,768 Hz (minimum, Sub oscillator)

Oscillation Sources

Interrupts

•

Crystal, ceramic, or RC for main system clock

Crystal or external oscillator for subsystem clock

Main system clock frequency: 8 MHz

•

7 interrupt levels and 19 interrupt sources

19 vectors

Fast interrupt processing feature (for one

selected interrupt level)

Subsystem clock frequency: 32.768 kHz

Power-down Modes

I/O Ports

Five 8-bit I/O ports (P0–P4) and one 7-bit I/O

port (P5) for a total of 47 bit-programmable pins

•

Main idle mode (only CPU clock stops)

Sub idle mode

•

Stop mode (main/sub system oscillation stops)

8-Bit Basic Timer

Operating Temperature Range

•

One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer

(software reset) function

°

•

– 40 C to + 85 C

Operating Voltage Range

Watch Timer

•

2.0 V to 5.5 V at 32 kHz (sub clock)-6 MHz

(main clock)

•

Time internal generation: 3.91 ms, 0.5 s at

32,768 Hz

2.2 V to 5.5 V at 8 MHz

•

Four frequency outputs to BUZ pin

Clock source generation for LCD

Package Type

80-pin TQFP, 80-pin QFP

•

Timers and Timer/Counters

•

One 8-bit timer/counter (Timer 0) with three

operating modes: Interval, Capture, and PWM

•

One 16-bit timer/counter (Timer 1) with two 8-bit

timer/counter modes

1-2

S3C821A/P821A

PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-P0.7

PORT 0

P1.0-P1.7

P2.0-P2.7

PORT 2

PORT 1

RESET

INTERNAL BUS

X

X_OUT

MAIN

OSC

IN

PORT 3

P3.0-P3.7

P4.0-P4.7

I/O PORT and INTERRUPT

CONTROL

SUB

OSC

X

X_OUT

IN

PORT 4

SAM8 CPU

T1CK

TA

TIMER 1

A and B

TB

T0CK

T0/T0CAP/

T0PWM

TIMER 0

PORT 5

P5.0-P5.6

1-KBYTE

48-KB ROM

REGISTER

FILE

COM0-COM3

SEG0-SEG3/

COM4-COM7

SEG4-SEG31

VLC1

SCK

LCD

DRIVER

SI

SIO

SO

V_DD1 (INTERNAL)

WATCH

TIMER

AV_SS

AV_REF

A/D

CONVERTER

V_SS1 (INTERNAL)

V_DD2 (EXTERNAL)

V_SS2 (EXTERNAL)

BUZ

ADC0-ADC3

Figure 1-1. S3C821A Simplified Block Diagram

1-3

PRODUCT OVERVIEW

S3C821A/P821A

PIN ASSIGNMENTS

1

2

3

4

5

6

7

8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG4

P1.1/SEG25/AD1

P1.2/SEG26/AD2

P1.3/SEG27/AD3

P1.4/SEG28/AD4

P1.5/SEG29/AD5

P1.6/SEG30/AD6

P1.7/SEG31/AD7

P2.0/AS

SEG3/COM7

SEG2/COM6

SEG1/COM5

SEG0/COM4

COM3

COM2

COM1

COM0

VDD2 (EXT)

VSS2

VLC1

P5.6

P5.5

P5.4

P5.3/BUZ

P5.2/SO

P5.1/SI

P5.0/SCK

P4.7/INT11

9

P2.1/DR

VDD1(INT)

VSS1

S3C821A

10

11

12

13

14

15

16

17

18

19

20

(80-TQFP)

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

Figure 1-2. S3C821A Pin Assignments (80-TQFP-1212)

1-4

S3C821A/P821A

PRODUCT OVERVIEW

1

2

3

4

5

6

7

8

P0.7/SEG23/A15

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG6

SEG5

SEG4

SEG3/COM7

SEG2/COM6

SEG1/COM5

SEG0/COM4

COM3

COM2

COM1

COM0

VDD2 (EXT)

VSS2

VLC1

P5.6

P5.5

P5.4

P5.3/BUZ

P5.2/SO

P5.1/SI

P5.0/SCK

P4.7/INT11

P4.6/INT10

P4.5/INT9

P1.0/SEG24/AD0

P1.1/SEG25/AD1

P1.2/SEG26/AD2

P1.3/SEG27/AD3

P1.4/SEG28/AD4

P1.5/SEG29/AD5

P1.6/SEG30/AD6

P1.7/SEG31/AD7

P2.0/AS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P2.1/DR

VDD1(INT)

S3C821A

VSS1

XOUT

XIN

TEST

(80-QFP)

XTIN

XTOUT

RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

P2.5/INT1/T1CK

P2.6/INT2/TA

Figure 1-3. S3C821A Pin Assignments (80-QFP-1420C)

1-5

PRODUCT OVERVIEW

S3C821A/P821A

PIN DESCRIPTIONS

Table 1-1. S3C821A Pin Descriptions

Names

Type

Description

Circuit

Type

Share

Pins

Numbers ^(note)

P0.0–P0.7

I/O

4-bit-programmable I/O port.

H-32

D-4

72–79

(74-80, 1)

SEG16/A8

–

SEG23/A15

Pull-up resistors and open-drain outputs

are software assignable. Pull-up resistors

are automatically disabled for output

pins. Configurable as LCD segments/

external interface address and data lines

P1.0–1.7

4-bit-programmable I/O port.

80, 1–7

(2-9)

SEG24/AD0

–

SEG31/AD7

Pull-up resistors and open-drain outputs

are software assignable. Pull-up resistors

are automatically disabled for output

pins. Configurable as LCD segments/

external interface address and data lines

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

1-bit-programmable I/O port.

8 (10)

9 (11)

AS

DR

DW

Pull-up resistors are software assignable,

and automatically disabled for output

pins. P2.0–P2.3 can alternately be used

as external interface lines. P2.4–P2.7 are

configurable as alternate functions or

external interrupts at falling edge with

noise filters.

18 (20)

19 (21)

20 (22)

21 (23)

22 (24)

23 (25)

DM

INT0/T0CK

INT1/T1CK

INT2/TA

INT3/TB

P3.0–P3.3

P3.4–P3.6

I/O

1-bit-programmable I/O port.

F-16

D-4

25–28

(27–30)

ADC0–ADC3

Pull-up resistors are software assignable,

and automatically disabled for output

pins. P3.0–P3.3 can alternately be used

as ADC. P3.7 is configurable as an

alternate function.

30–32

(32–34)

T0/T0PWM/

T0CAP

P3.7

D-4

E-4

33 (35)

P4.0–P4.7

1-bit-programmable I/O port.

34–41

(36–43)

INT4–INT11

Pull-up resistors and open-drain outputs

are software assignable. Pull-up resistors

are automatically disabled for output

pins. P4.0–P4.7 are configurable as

external interrupts at a selectable edge

with noise filters.

P5.0

P5.1

P5.2

1-bit-programmable I/O port.

D-4

42 (44)

43 (45)

44 (46)

45 (47)

46–48

SCK

SI

SO

Pull-up resistors are software assignable,

and automatically disabled for output

pins.

P5.0–P5.3 are configurable as alternate

functions. If SCK and SI are used as

input, these pins have noise filters.

P5.3

BUZ

P5.4–P5.6

(48–50)

NOTE: Parentheses indicate pin number for 80-QFP package.

1-6

S3C821A/P821A

PRODUCT OVERVIEW

Table 1-1. S3C821A Pin Descriptions (Continued)

Names

Type

Description

Circuit

Type

Share

Pins

Numbers ^(note)

V_SS1, V_DD1

–

Power input pins for internal power block

Main oscillator pins

–

10, 11 (12, 13)

12, 13 (14, 15)

14 (16)

–

X_OUT

X

IN

,

TEST

Chip test input pin

Hold GND when the device is operating

XT_IN, XT_OUT

–

I

Sub oscillator pins for sub-system clock

–

15, 16 (17,18)

17 (19)

–

B

RESET

RESET signal input pin. Schmitt trigger

input with internal pull-up resistor.

INT0–INT3

T0CK

I/O

External interrupts input with noise filter.

8Bit Timer 0 external clock input.

Timer 1/A external clock input.

Timer 1/A clock output

D-4

F-16

20–23 (22–25)

20 (22)

P2.4–P2.7

P2.4

T1CK

21 (23)

P2.5

TA

22 (24)

P2.6

TB

Timer B clock output

23 (25)

P2.7

T0

Timer 0 clock output

33 (35)

P3.7

T0PWM

T0CAP

ADC0–ADC3

Timer 0 PWM output

33 (35)

P3.7

Timer 0 capture input

33 (35)

P3.7

Analog input pins for A/D converts

module

25–28 (27–30)

P3.0–P3.3

AV_REF, AV_SS

–

A/D converter reference voltage and

ground

–

24, 29 (26, 31)

–

INT4–INT11

BUZ

I/O

External interrupts input with noise filter.

Buzzer signal output

E-4

D-4

34–41 (36–43)

45 (47)

P4.0–P4.7

P5.3

SCK, SI, SO

Serial clock, serial data input, serial data

output

42–44 (44–46)

P5.0–P5.2

V_LC1

–

LCD bias voltage input pins

–

49 (51)

–

V_SS2, V_DD2

COM0–COM3

Power input pins for external power block

50, 51 (52, 53)

O

LCD Common signal output

H-30

H-31

52–55 (54–57)

56–59 (58–61)

–

SEG0–SEG3

LCD Common or Segment signal output

(COM4–COM7)

SEG4–SEG15

O

LCD segment signal output

H-29

60–71 (62–73)

–

NOTE: Parentheses indicate pin number for 80-QFP package.

1-7

PRODUCT OVERVIEW

S3C821A/P821A

Table 1-1. S3C821A Pin Descriptions (Continued)

Names

Type

Description

Circuit

Type

Share

Pins

Numbers

SEG16–

SEG23

I/O

LCD segment signal output

H-32

72–79 (74–80, 1) P0.0–P0.7

80, 1–7 (2–9) P1.0–P1.7

72–79 (74–80, 1) P0.0–P0.7

SEG24–

SEG31

I/O

LCD segment signal output

H-32

A8–A15

I/O

External interface address lines

External interface address/data lines

Address strobe

H-32

D-4

AD0–AD7

80, 1–7 (2–9)

8 (10)

P1.0–P1.7

P2.0

AS

DR

DW

DM

I/O

Data read

D-4

9 (11)

18 (20)

19 (21)

P2.1

P2.2

P2.3

Data write

Data memory select

NOTE: Parentheses indicate pin number for 80-QFP package.

1-8

S3C821A/P821A

PRODUCT OVERVIEW

PIN CIRCUITS

V_DD

DATA

P-CHANNEL

OUTPUT

INPUT

-

N CHANNEL

OUTPUT

DISABLE

V_SS

Figure 1-6. Pin Circuit Type C

Figure 1-4. Pin Circuit Type A

V

DD

V_DD

PULL-UP

ENABLE

PULL-UP

RESISTOR

DATA

CIRCUIT

TYPE C

I/O

OUTPUT

DISABLE

Noise Filter

RESET

SCHMITT TRIGER

Figure 1-7. Pin Circuit Type D-4

Figure 1-5. Pin Circuit Type B

1-9

PRODUCT OVERVIEW

S3C821A/P821A

V_DD

PULL-UP

RESISTOR

PULL-UP

ENABLE

V_DD

OPEN-DRAIN EN

I/O

DATA

OUTPUT

DISABLE

V_SS

Figure 1-8. Pin Circuit Type E-4

V

DD

PULL-UP

ENABLE

DATA

CIRCUIT

TYPE C

I/O

OUTPUT

DISABLE

ADEN

ADSELECT

DATA

T0 ADC

Figure 1-9. Pin Circuit Type F-16

1-10

S3C821A/P821A

PRODUCT OVERVIEW

V

LC1

V

LC1

V

LC2

LC3

OUTPUT

V

LC4

LC5

V

LC4

V

SS

V

SS

Figure 1-12. Pin Circuit Type H-31

Figure 1-10. Pin Circuit Type H-29

V

LC1

LC2

OUTPUT

V

LC5

V

SS

Figure 1-11. Pin Circuit Type H-30

1-11

PRODUCT OVERVIEW

S3C821A/P821A

V

DD

PULL-UP

RESISTOR

V

DD

PULL-UP

ENABLE

OPEN-DRAIN EN

DATA

I/O

LCD OUT EN

SEG

V

SS

CIRCUIT

TYPE H-29

OUTPUT

DISABLE

Figure 1-13. Pin Circuit Type H-32

1-12

S3C821A/P821A

ADDRESS SPACES

2

ADDRESS SPACES

OVERVIEW

The S3C821A microcontroller has three types of address space:

— Internal program memory (ROM)

— Internal register file

— External data memory

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and

data between the CPU and the register file.

The S3C821A has an internal 48-Kbyte mask-programmable ROM. An external data memory interface is

implemented.

The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes.

A 32-byte LCD display register file is implemented.

There are 1,125 mapped registers in the internal register file. Of these, 1,040 are for general-purpose. (This

number includes a 16-byte working register common area used as a “scratch area” for data operations, four 192-

byte prime register areas, and four 64-byte areas (Set 2)). Nineteen 8-bit registers are used for the CPU and the

system control, and 34 registers are mapped for peripheral controls and data registers. Eleven register locations

are not mapped.

2-1

ADDRESS SPACES

S3C821A/P821A

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program codes or table data. The S3C821A has 48 K bytes of internal mask-

programmable program memory. The program memory address range is therefore 0H–BFFFH (see Figure 2-1).

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this

address range can be used as normal program memory. If you use the vector address area to store a program

code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which a program execution starts after a reset is 0100H.

(DECIMAL)

49,151

(HEX)

BFFFH

48-KBYTE

INTERNAL

PROGRAM

MEMORY

0FFH

0H

255

0

INTERRUPT

VECTOR AREA

Figure 2-1. Program Memory Address Space

2-2

S3C821A/P821A

ADDRESS SPACES

REGISTER ARCHITECTURE

In the S3C821A implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called

set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank

1), and the lower 32-byte area is a single 32-byte common area. In addition, set 2 is logically expanded four

separately addressable register pages, page 0–page 3.

The total number of addressable 8-bit registers is 1125. Of these 1125 registers, 19 bytes are for CPU and

system control registers, 32 bytes are for LCD data registers, 34 bytes are for peripheral control and data

registers, 16 bytes are used as a shared working registers, and 1024 registers are for general-purpose use.

You can always address set 1 register locations, regardless of which of the four register pages is currently

selected. Set 1 locations, however, can only be addressed using direct addressing modes.

The extension of register space into separately addressable areas (sets, banks, and pages) is supported by

various addressing mode restrictions, the select bank instructions (SB0 and SB1) and the register page pointer

(PP).

Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1.

Table 2-1. S3C821A Register Type Summary

Register Type

Number of Bytes

General-purpose registers (including the 16-byte

common working register area, four 192-byte prime

register area, and four 64-byte set 2 area)

LCD data registers

CPU and system control registers

Mapped clock, peripheral, I/O control, and data registers

1,040

32

19

34

Total Addressable Bytes

1,125

2-3

ADDRESS SPACES

S3C821A/P821A

FFH

PAGE 3

PAGE 2

PAGE 1

SET 1

BANK 1

FFH

32

BYTES

BANK 0

PAGE 0

SET 2

SYSTEM and

PERIPHERAL CONTROL

REGISTERS

GENERAL-PURPOSE

DATA REGISTERS

E0H

(Register Addressing Mode)

E0H

64

(Indirect Register,

Indexed Mode, and

Stack Operations)

BYTES DFH

SYSTEM REGISTERS

(Register Addressing

Mode)

256

BYTES

D0H

CFH

WORKING REGISTERS

(Working Register

C0H

BFH

Addressing Only)

C0H

PAGE 0

~

PAGE 4

~

PRIME

DATA REGISTERS

1FH

~

192

BYTES

~

LCD

(All Addressing

Modes)

DATA REGISTERS

32

BYTES

~

(All addressing modes)

LCD Display Register

00H

Figure 2-2. Internal Register File Organization

2-4

S3C821A/P821A

ADDRESS SPACES

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using

an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the

register page pointer (PP, DFH). In the S3C821A microcontroller, a paged register file expansion is implemented

for LCD data registers, and the register page pointer must be changed to address other pages.

After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always

"0000B", automatically selecting page 0 as the source and destination page for register addressing.

REGISTER PAGE POINTER (PP)

DFH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Destination register page selection bits:

0 0 0 0 Destination: page 0

Source register page selection bits:

0 0 0 0 Source: page 0

: In the S3C821A microcontroller, pages 0, 1, 2, 3, and 4 are implemented.

A hardware reset operation writes the 4-bit destination and source values shown

above to the register page pointer. These values should be modified to address

other pages.

NOTE

Figure 2-3. Register Page Pointer (PP)

+

PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1)

LD

SRP

LD

CLR

DJNZ

CLR

PP,#00H

#0C0H

R0,#0FFH

@R0

R0,RAMCL0

@R0

; Destination ¬ 0, Source ¬ 0

; Page0 RAM clear starts

RAMCL0

; R0 = 00H

LD

CLR

DJNZ

CLR

PP,#10H

R0,#0FFH

@R0

R0,RAMCL1

@R0

; Destination ¬ 1, Source ¬ 0

; Page1 RAM clear starts

RAMCL1

; R0 = 00H

NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

2-5

ADDRESS SPACES

S3C821A/P821A

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and

bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware

reset operation always selects bank 0 addressing.

The upper 32-byte area (bank 0 and bank 1, E0H–FFH) of set 1 contains 37 mapped system and peripheral

control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common

working register area (C0H–CFH). You can use the common working register area as a “scratch” area for data

operations being performed in other areas of the register file.

Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte

working register area can only be accessed using working register addressing (For more information about

working register addressing, please refer to Chapter 3, “Addressing Modes.”)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another

64 bytes of register space. This expanded area of the register file is called set 2. For the S3C821A, the set 2

address range (C0H–FFH) is accessible on pages 0-3.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only

Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register

Indirect addressing mode or Indexed addressing mode.

The set 2 register area on page 0 is commonly used for stack operations.

2-6

S3C821A/P821A

ADDRESS SPACES

PRIME REGISTER SPACE

The lower 192 bytes (00H–BFH) of the S3C821A's four 256-byte register pages is called prime register area.

Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.")

The prime register area on page 0 is immediately addressable following a reset. In order to address prime

registers on pages 0, 1, 2, or 3 you must set the register page pointer (PP) to the appropriate source and

destination values.

SET 1

FFH

PAGE 3

PAGE 2

PAGE 1

PAGE 0

BANK 0

BANK 1

FFH

FCH

E0H

SET 2

D0H

C0H

BFH

PAGE 0

CPU and system control

General-purpose

PAGE 4

PRIME

SPACE

1FH

00H

LCD Data

Register Area

Peripherals and I/O

LCD data register or

not mapped area

00H

Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

2-7

ADDRESS SPACES

S3C821A/P821A

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one

that consists of thirty-two 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to

form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block

anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected

working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant

address bits. This makes it possible for each register pointer to point to one of the 32 slices in the register file.

The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

FFH

F8H

SLICE 32

F7H

F0H

SLICE 31

1 1 1 1 1

X X X

SET 1

ONLY

RP1 (Registers R8–R15)

CFH

C0H

Each register pointer points to

one 8-byte slice of the register

space, selecting a total 16-byte

working register block.

~

10H

FH

8H

7H

0H

0 0 0 0 0

X X X

SLICE 2

SLICE 1

RP0 (Registers R0–R7)

Figure 2-5. 8-Byte Working Register Areas (Slices)

2-8

S3C821A/P821A

ADDRESS SPACES

USING THE REGISTER POINTERS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable

8-byte working register slices in the register file. After a reset, they point to the working register common area:

RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H-CFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see

Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently

pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in

set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed

addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general

programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice

(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-

contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can

flexibly define the working register area to support program requirements.

+

PROGRAMMING TIP — Setting the Register Pointers

SRP

SRP1

SRP0

CLR

LD

#70H

#48H

#0A0H

RP0

RP1,#0F8H

; RP0 ¬ 70H, RP1 ¬ 78H

; RP0 ¬ no change, RP1 ¬ 48H,

; RP0 ¬ A0H, RP1 ¬ no change

; RP0 ¬ 00H, RP1 ¬ no change

; RP0 ¬ no change, RP1 ¬ F8H

REGISTER FILE

CONTAINS 32

8-BYTE SLICES

0 0 0 0 1

x x x

FH (R15)

16-BYTE

RP1

0 0 0 0 0

RP0

8-BYTE SLICE

UPPER SLICE

•

CONTIGUOUS

WORKING

REGISTER

BLOCK

8H

7H

x x x

8-BYTE SLICE

0H (R0)

Figure 2-6. Contiguous 16-Byte Working Register Block

2-9

ADDRESS SPACES

S3C821A/P821A

F7H (R7)

|

8-BYTE SLICE

F0H (R0)

16-BYTE NON-

REGISTER FILE

CONTAINS 32

8-BYTE SLICES

CONTIGUOUS

WORKING

REGISTER

BLOCK

1 1 1 1 0

RP0

0 0 0 0 0

RP1

x x x

7H (R15)

|

0H (R8)

8-BYTE SLICE

Figure 2-7. Non-Contiguous 16-Byte Working Register Block

+

Programming Tip — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H-85H using the register pointer. The register addresses from 80H through 85H

contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

SRP0

ADD

ADC

#80H

; RP0 ¬ 80H

; R0 ¬ R0 + R1

; R0 ¬ R0 + R2 + C

; R0 ¬ R0 + R3 + C

; R0 ¬ R0 + R4 + C

; R0 ¬ R0 + R5 + C

R0,R1

R0,R2

R0,R3

R0,R4

R0,R5

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this

example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used

to calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

ADC

80H,81H

80H,82H

80H,83H

80H,84H

80H,85H

; 80H ¬ (80H) + (81H)

; 80H ¬ (80H) + (82H) + C

; 80H ¬ (80H) + (83H) + C

; 80H ¬ (80H) + (84H) + C

; 80H ¬ (80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of

instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-10

S3C821A/P821A

ADDRESS SPACES

REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register

pair, you can access any location in the register file except for set 2. With working register addressing, you use a

register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that

space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register

pair, the address of the first 8-bit register is always an even number and the address of the next register is always

an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and

the least significant byte is always stored in the next (+ 1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific

8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

n = EVEN ADDRESS

Rn + 1

Figure 2-8. 16-Bit Register Pair

2-11

ADDRESS SPACES

S3C821A/P821A

LCD Data Registers

or Genernal Purpose

Registers

Special-Purpose Registers

BANK 1 BANK 0

General-Purpose Registers

FFH

CONTROL

REGISTERS

SET 2

E0H

D0H

SYSTEM

REGISTERS

CFH

C0H

BFH

D7H

D6H

RP1

RP0

REGISTER

POINTERS

Each register pointer (RP) can independently point

to one of the 256-byte "slices" of the register file

(other than set 2). After a reset, RP0 points to

locations C0H-C7H and RP1 to locations C8H-

CFH (that is, to the common working register

area).

PRIME

REGISTERS

1FH

LCD DATA

REGISTERS

In the S3C821A microcontroller,

pages 0-4 are implemented. Pages 0-4

contain all of the addressable registers

in the internal register file.

:

NOTE

00H

PAGE 0-3

PAGE 4

Register Addressing Only

All

Indirect Register,

Indexed

All

Addressing

Modes

Addressing

Modes

Addressing

Modes

Can Be Pointed To By Register Pointer

Can Be Pointed To

By Register Pointer

Figure 2-9. Register File Addressing

2-12

S3C821A/P821A

ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations

C0H-CFH, as the active 16-byte working register block:

RP0 ® C0H-C7H

RP1 ® C8H-CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working

registers by operations that address any location on any page in the register file. Typically, these working

registers serve as temporary buffers for data operations between different pages.

FFH

PAGE 3

PAGE 2

PAGE 1

SET 1

PAGE 0

FFH

FCH

SET 2

E0H

DFH

C0H

BFH

CFH

C0H

~

PAGE 4

~

1FH

00H

Following a hardware reset, register

pointers RP0 and RP1 point to the

common working register area,

locations C0H–CFH.

~

PRIME

AREA

~

LCD DATA

REGISTERS

RP0 = 1 1 0 0 0 0 0 0

RP1 = 1 1 0 0 1 0 0 0

00H

Figure 2-10. Common Working Register Area

2-13

ADDRESS SPACES

S3C821A/P821A

+

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,

using working register addressing mode only.

Examples

1.

LD

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

SRP

LD

#0C0H

R2,40H

; R2 (C2H) ¬ the value in location 40H

2.

ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

SRP

ADD

#0C0H

R3,#45H

; R3 (C3H) ¬ R3 + 45H

4-BIT WORKING REGISTER ADD MRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in

a register pointer serves as an addressing "window" that makes it possible for instructions to access working

registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected

working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).

— The five high-order bits in the register pointer select an 8-byte slice of the register space.

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are

concatenated with the three low-order bits from the instruction address to form the complete address. As long as

the address stored in the register pointer remains unchanged, the three bits from the address will always point to

an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction

"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the

three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-14

S3C821A/P821A

ADDRESS SPACES

RP0

RP1

SELECTS

RP0 OR RP1

ADDRESS

OPCODE

4-BIT ADDRESS

PROVIDES THREE

LOW-ORDER BITS

REGISTER POINTER

PROVIDES FIVE

HIGH-ORDER BITS

TOGETHER THEY CREATE AN

8-BIT REGISTER ADDRESS

Figure 2-11. 4-Bit Working Register Addressing

RP0

0 1 1 1 0

RP1

0 0 0

0 1 1 1 1

0 0 0

SELECTS RP0

R6

OPCODE

1 1 1 0

REGISTER

ADDRESS

(76H)

INSTRUCTION:

'INC R6'

0 1 1 0

0 1 1 1 0

1 1 0

q

Figure 2-12. 4-Bit Working Register Addressing Example

2-15

ADDRESS SPACES

S3C821A/P821A

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To

initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working

register addressing.

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit

addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the

three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction

address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register

address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from

RP1 and the three address bits from the instruction are concatenated to form the complete register address,

0ABH (10101011B).

RP0

RP1

SELECTS

RP0 OR RP1

ADDRESS

THESE ADDRESS

BITS INDICATE

8-BIT WORKING

REGISTER

8-BIT LOGICAL

ADDRESS

1

0

ADDRESSING

THREE LOW-

ORDER BITS

REGISTER POINTER

PROVIDES FIVE

HIGH-ORDER BITS

8-BIT PHYSICAL ADDRESS

Figure 2-13. 8-Bit Working Register Addressing

2-16

S3C821A/P821A

ADDRESS SPACES

RP0

0 1 1 0 0

RP1

1 0 1 0 1

0 0 0

SELECTS RP1

R11

0 1 1

1 1 0 0

1

8-BIT ADDRESS

FROM INSTRUCTION

'LD R11, R2'

SPECIFIES WORKING

REGISTER ADDRESSING

REGISTER ADDRESS (0ABH)

1 0 1 0 1

0 1 1

Figure 2-14. 8-Bit Working Register Addressing Example

2-17

ADDRESS SPACES

S3C821A/P821A

SYSTEM AND USER STACKS

The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH

and POP instructions are used to control system stack operations. The S3C821A architecture supports stack

operations in the internal register file.

Stack Operations

Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents

of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to

their original locations. The stack address value is always decreased by one before a push operation and

increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top

of the stack, as shown in Figure 2-15.

HIGH ADDRESS

PCL

PCH

TOP OF

STACK

TOP OF

STACK

PCH

FLAGS

STACK CONTENTS

AFTER A CALL

INSTRUCTION

STACK CONTENTS

AFTER AN

INTERRUPT

LOW ADDRESS

Figure 2-15. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL, SPH)

Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.

The most significant byte of the SP address, SP15-SP8, is stored in the SPH register (D8H), and the least

significant byte, SP7-SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.

If only internal memory space is implemented in the S3C821A, the SPL must be initialized to an 8-bit value in

the range 00H-FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary.

If external memory is implemented, both SPL and SPH must be initialized with a full 16-bit address.

When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the

register file), you can use the SPH register as a general-purpose data register. However, if an overflow or

underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register

during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,

overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can

initialize the SPL value to "FFH" instead of "00H".

2-18

S3C821A/P821A

ADDRESS SPACES

+

Programming Tip — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD

SPL,#0FFH

; SPL ¬ FFH

; (Normally, the SPL is set to 0FFH by the initialization

; routine)

•

PUSH

•

PP

; Stack address 0FEH ¬ PP

; Stack address 0FDH ¬ RP0

; Stack address 0FCH ¬ RP1

; Stack address 0FBH ¬ R3

RP0

RP1

R3

•

POP

R3

; R3 ¬ Stack address 0FBH

; RP1 ¬ Stack address 0FCH

; RP0 ¬ Stack address 0FDH

; PP ¬ Stack address 0FEH

RP1

RP0

PP

2-19

S3C821A/P821A

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The program counter is used to fetch instructions that are stored in program memory for execution. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to

determine the location of the data operand. The operands specified in instructions may be condition codes,

immediate data, or a location in the register file, program memory, or data memory.

The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are

available for each instruction:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

— Immediate (IM)

3-1

ADDRESSING MODES

S3C821A/P821A

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).

Working register addressing differs from Register addressing as it uses a register pointer to specify an 8-byte

working register space in the register file and an 8-bit register within that space (see Figure 3-2).

PROGRAM MEMORY

REGISTER

FILE

8-BIT REGISTER

FILE ADDRESS

dst

OPERAND

POINTS TO ONE

REGISTER IN REGISTER

FILE

OPCODE

ONE-OPERAND

INSTRUCTION

(EXAMPLE)

VALUE USED IN

INSTRUCTION EXECUTION

SAMPLE INSTRUCTION:

DEC CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

REGISTER

FILE

MSB POINTS TO

RP0 or RP1

SELECTED

RP POINTS

TO START

OF WORKING

REGISTER

BLOCK

PROGRAM MEMORY

4-BIT

WORKING

REGISTER

3 LSBs

dst

src

OPERAND

POINTS TO THE

WORKING REGISTER

(1 of 8)

TWO-

OPERAND

INSTRUCTION

(EXAMPLE)

OPCODE

SAMPLE INSTRUCTION:

ADD R1,R2

;

Where R1 and R2 are registers in the currently selected

working register area

Figure 3-2. Working Register Addressing

3-2

S3C821A/P821A

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of

the operand. Depending on the instruction used, the actual address may point to a register in the register file, to

program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to

indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be

accessed using Indirect Register addressing mode.

PROGRAM MEMORY

REGISTER FILE

ADDRESS

8-BIT REGISTER

FILE ADDRESS

dst

POINTS TO ONE

REGISTER IN

OPCODE

ONE-OPERAND

INSTRUCTION

(EXAMPLE)

REGISTER FILE

ADDRESS OF OPERAND

USED BY INSTRUCTION

VALUE USED IN

INSTRUCTION

EXECUTION

OPERAND

SAMPLE INSTRUCTION:

RL @SHIFT Where SHIFT is the label of an 8-bit register address.

;

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

S3C821A/P821A

INDIRECT REGISTER ADDRESSING MODE (Continued)

REGISTER

FILE

PROGRAM MEMORY

REGISTER

PAIR

EXAMPLE

INSTRUCTION

REFERENCES

PROGRAM

dst

POINTS TO

REGISTER

PAIR

OPCODE

16-BIT

ADDRESS

POINTS TO

PROGRAM

MEMORY

PROGRAM MEMORY

OPERAND

SAMPLE INSTRUCTIONS:

CALL @RR2

VALUE USED IN

INSTRUCTION

JP

@RR2

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

S3C821A/P821A

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

REGISTER FILE

RP0 or RP1

MSB POINTS TO

RP0 or RP1

SELECTED

RP POINTS

TO START OF

WORKING

REGISTER

BLOCK

~

PROGRAM MEMORY

4-BIT

3 LSBs

WORKING

REGISTER

ADDRESS

dst

src

OPCODE

ADDRESS

POINTS TO THE

WORKING

REGISTER (1 of 8)

SAMPLE INSTRUCTION:

OR R3,@R6

VALUE USED IN

INSTRUCTION

OPERAND

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

S3C821A/P821A

INDIRECT REGISTER ADDRESSING MODE (Continued)

REGISTER FILE

RP0 or RP1

MSB POINTS TO

RP0 or RP1

SELECTED RP

POINTS TO

START OF

WORKING

REGISTER

BLOCK

PROGRAM MEMORY

4-BIT

WORKING

REGISTER

ADDRESS

dst

src

OPCODE

REGISTER

PAIR

NEXT 2 BITS POINT

TO WORKING

REGISTER PAIR

(1 of 4)

EXAMPLE

INSTRUCTION

REFERENCES

EITHER

PROGRAM

MEMORY OR

DATA MEMORY

16-BIT

ADDRESS

POINTS TO

PROGRAM

MEMORY OR

DATA

PROGRAM MEMORY

or

LSB SELECTS

DATA MEMORY

MEMORY

VALUE USED

IN

OPERAND

INSTRUCTION

SAMPLE INSTRUCTIONS:

LDC

LDE

R5,@RR6

R3,@RR14

@RR4,R8

;

Program memory access

External data memory access

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

S3C821A/P821A

ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to

calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access

locations in the internal register file or in external memory (if implemented). You cannot, however, access

locations C0H-FFH in set 1 using Indexed addressing.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range -128 to

+127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained

in a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and LDE instructions support Indexed addressing mode for internal program and for external data

memory (if implemented).

REGISTER FILE

MSB POINTS TO

RP0 or RP1

~

SELECTED RP

POINTS TO

START OF

WORKING

REGISTER

BLOCK

VALUE USED IN

INSTRUCTION

OPERAND

+

PROGRAM MEMORY

BASE ADDRESS

3 LSBs

dst / src

OPCODE

x

TWO-

OPERAND

INDEX

POINTS TO ONE

OF THE

INSTRUCTION

EXAMPLE

WORKING

REGISTERS

(1 of 8)

SAMPLE INSTRUCTION:

LD R0,#BASE[R1]

;

Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

S3C821A/P821A

INDEXED ADDRESSING MODE (Continued)

REGISTER

FILE

MSB POINTS TO

RP0 or RP1

SELECTED

RP POINTS

TO START OF

WORKING

REGISTER

BLOCK

~

PROGRAM MEMORY

OFFSET

dst / src

OPCODE

4-BIT

WORKING

REGISTER

ADDRESS

REGISTER

PAIR

NEXT 2 BITS

POINT TO

WORKING

REGISTER

PAIR (1 of 4)

x

16-BIT

ADDRESS

ADDED TO

OFFSET

PROGRAM MEMORY

or

LSB SELECTS

DATA MEMORY

+

8 BITS

16 BITS

VALUE USED IN

INSTRUCTION

OPERAND

16 BITS

SAMPLE INSTRUCTIONS:

LDC

LDE

R4,#04H[RR2]

;

The values in the program address (RR2 + 04H) are

loaded into register R4.

Identical operation to LDC example, except that

external data memory is accessed.

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

S3C821A/P821A

ADDRESSING MODES

INDEXED ADDRESSING MODE (Continued)

REGISTER

FILE

MSB POINTS TO

RP0 OR RP1

RP0 OR

RP1

SELECTED

RP POINTS

TO START OF

WORKING

REGISTER

BLOCK

~

PROGRAM MEMORY

OFFSET

4-BIT

WORKING

REGISTER

ADDRESS

OFFSET

dst / src

OPCODE

REGISTER

PAIR

NEXT 2 BITS

POINT TO

WORKING

REGISTER

PAIR

x

16-BIT

ADDRESS

ADDED TO

OFFSET

PROGRAM MEMORY

or

LSB SELECTS

DATA MEMORY

+

16 BITS

VALUE USED IN

INSTRUCTION

OPERAND

SAMPLE INSTRUCTIONS:

LDC R4,#1000H[RR2]

;

The values in the program address (RR2 + 1000H) are

loaded into register R4.

LDE R4,#1000H[RR2]

Identical operation to LDC example, except that

and external data memory is accessed.

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES

S3C821A/P821A

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for

Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

PROGRAM or

DATA MEMORY

MEMORY

ADDRESS

USED

PROGRAM MEMORY

UPPER ADDR BYTE

LOWER ADDR BYTE

LSB SELECTS PROGRAM

dst / src

"0" or "1"

MEMORY OR DATA MEMORY:

"0" = PROGRAM MEMORY

"1" = DATA MEMORY

OPCODE

SAMPLE INSTRUCTIONS:

LDC

LDE

R5,1234H

;

The values in the program address (1234H) are

loaded into register R5.

Identical operation to LDC example, except that external

data memory is accessed.

Figure 3-10. Direct Addressing for Load Instructions

3-10

S3C821A/P821A

ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

PROGRAM MEMORY

NEXT OPCODE

PROGRAM

MEMORY

ADDRESS

USED

LOWER ADDR BYTE

UPPER ADDR BYTE

OPCODE

SAMPLE INSTRUCTIONS:

JP

CALL

C,JOB1

DISPLAY

; Where JOB1 is a 16-bit immediate address

; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES

S3C821A/P821A

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program

memory. The selected pair of memory locations contains the actual address of the next instruction to be

executed. Only the CALL instruction can use the Indirect Address mode.

Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program

memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are

assumed to be all zeros.

PROGRAM

MEMORY

NEXT INSTRUCTION

LSB MUST BE ZERO

dst

CURRENT

INSTRUCTION

OPCODE

LOWER ADDR BYTE

UPPER ADDR BYTE

PROGRAM MEMORY

LOCATIONS 0–255

SAMPLE INSTRUCTION:

CALL #40H

;

The 16-bit value in program memory addresses

40H and 41H is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

S3C821A/P821A

ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between -128 and + 127 is specified

in the instruction. The displacement value is then added to the current PC value. The result is the address of the

next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction

immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The

instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

PROGRAM MEMORY

NEXT OPCODE

PROGRAM MEMORY

ADDRESS USED

CURRENT

PC VALUE

DISPLACEMENT

OPCODE

+

CURRENT

INSTRUCTION

SIGNED

DISPLACEMENT

VALUE

SAMPLE INSTRUCTION:

JR ULT,$+OFFSET

;

Where OFFSET is a value in the range

+127 to –128

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES

S3C821A/P821A

IMMEDIATE MODE (IM)

In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.

The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing

mode is useful for loading constant values into registers.

PROGRAM MEMORY

OPERAND

OPCODE

(The operand value is in the instruction.)

SAMPLE INSTRUCTION:

LD

R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

S3C821A/P821A

CONTROL REGISTERS

4

CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the S3C821A control registers are presented in an easy-to-read format.

You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates

the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed

information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual.

Data and counter registers are not described in detail in this reference chapter. More information about all of the

registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this

manual.

The locations and read/write characteristics of all mapped registers in the S3C821A register file are listed in

Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and Power-

Down."

4-1

CONTROL REGISTERS

S3C821A/P821A

Table 4-1. Set 1 Registers

Register Name

Mnemonic

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

Decimal

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

R/W

R ^(note)

R/W

R ^(note)

R/W

Timer 0 counter

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

Register pointer 1

RP1

Stack pointer (high byte)

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Register page pointer

SPH

SPL

IPH

IPL

IRQ

IMR

SYM

PP

NOTE: You cannot use a read-only register as a destination for the instruction OR, AND, LD, or LDB.

4-2

S3C821A/P821A

CONTROL REGISTERS

Table 4-2. Set 1, Bank 0 Registers

Register Name

Mnemonic

P0

Decimal

Hex

R/W

Port 0 data register

224

225

226

227

228

229

230

231

232

233

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

Port 1 data register

P1

Port 2 data register

P2

Port 3 data register

P3

Port 4 data register

P4

Port 5 data register

P5

Port 2 interrupt control register

Port 4 interrupt control register

Port 4 interrupt pending register

Port 4 interrupt edge select register

P2INT

P4INT

P4PND

P4EDGE

Locations EAH–EDH are not mapped.

R ⁽²⁾

Timer B counter

TBCNT

TACNT

238

239

240

241

242

243

244

245

246

247

248

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

Timer A counter

Timer B data register

Timer A data register

Timer B control register

Timer 1/A control register

SIO data register

TBDATA

R/W

R/W ⁽¹⁾

R ⁽²⁾

TADATA

TBCON

TACON

SIO

SIO control register

SIO prescaler register

ADC control register

ADC data register

SIOCON

SIOPS

ADCON

ADDATA

Location F9H is not mapped.

LCON

LCD control register

250

251

FAH

FBH

R/W

Watch timer control register

WTCON

Location FCH is not mapped.

R ⁽²⁾

R/W

Basic timer counter

BTCNT

EMT

253

FDH

FEH

FFH

External memory timing register

Interrupt priority register

254

255

IPR

NOTES:

1. ADCON.3 is a read-only bit.

2. You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.

4-3

CONTROL REGISTERS

S3C821A/P821A

Table 4-3. Set 1, Bank 1 Registers

Register Name

Mnemonic

P0CON

Decimal

Hex

R/W

Port 0 control register

224

E0H

R/W

Location E1H is not mapped.

P1CON

Port 1 control register

226

E2H

R/W

Location E3H is not mapped.

P2CONH

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 3 control register (high byte)

Port 3 control register (low byte)

Port 4 control register (high byte)

Port 4 control register (low byte)

Port 5 control register (high byte)

Port 5 control register (low byte)

228

229

230

231

232

233

234

235

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

R/W

P2CONL

P3CONH

P3CONL

P4CONH

P4CONL

P5CONH

P5CONL

Locations ECH–FEH are not mapped.

SCLKCON 255

Sub-clock control register

FFH

R/W

4-4

S3C821A/P821A

CONTROL REGISTERS

Bit number(s) that is/are appended to

the register name for bit addressing

Name of individual

bit or bit function

Register location

Register

mnemonic

Register address in the internal

(hexadecimal)

register file

Full register name

FLAGS — System Flags Register

D5H

Set 1

.0

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

x

0

Value

RESET

R/W

Read/Write

Addressing Mode

Register addressing mode only

Carry Flag (C)

.7

Operation does not generate a carry or borrow condition

Operation generates carry-out or borrow in high-order bit 7

0

1

Zero Flag (Z)

.6

.5

Operation result is a non-zero value

Operation result is zero

0

1

Sign Flag (S)

0

1

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

Description of the

effect of specific

Bit number:

MSB = Bit 7

LSB = Bit 0

bit settings

'–' = Not used

value notation:

RESET

'–' = Not used

Addressing mode or

modes you can use to

modify register values

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

Figure 4-1. Register Description Format

4-5

CONTROL REGISTERS

S3C821A/P821A

ADCON — A/D Converter Control Register

F7H

Set 1, Bank 0

Bit Identifier

.7

–

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

–

R/W

R

R/W

Addressing Mode

Register addressing mode only

.7

Not used for the S3C821A

.6–.4

A/D Input Pin Selection Bits

0

1

0

1

0

1

ADC0

ADC1

ADC2

ADC3

.3

End-of-Conversion Bit (Read-only)

0

1

Conversion not complete

Conversion complete

.2 and .1

Clock Source Selection Bits

0

1

0

1

0

1

fxx/16

fxx/8

fxx/4

fxx

.0

Start or Enable Bit

0

1

No effect (when write)

Start operation and auto cleared (when write)

4-6

S3C821A/P821A

CONTROL REGISTERS

BTCON — Basic Timer Control Register

D3H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Watchdog Timer Function Disable Code (for System Reset)

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Others

.3 and .2

Basic Timer Input Clock Selection Bits

fxx/4096 ⁽³⁾

fxx/1024

fxx/128

0

1

0

1

0

1

fxx/16

Basic Timer Counter Clear Bit ⁽¹⁾

.1

0

1

No effect

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 ⁽²⁾

.0

0

1

No effect

Clear both clock frequency dividers

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write

operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the

write operation, the BTCON.0 value is automatically cleared to "0".

3. The fxx is selected clock for peripheral hardware (main system clock or sub system clock).

4-7

CONTROL REGISTERS

S3C821A/P821A

CLKCON— System Clock Control Register

D4H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

Oscillator IRQ Wake-up Enable Bit

0

1

Enable IRQ for main system oscillator wake-up in power-down mode

Disable IRQ for main system oscillator wake-up in power-down mode

Main Oscillator Stop Control Bits ⁽³⁾

.6 and .5

0

1

0

1

0

1

No effect

STOP main oscillator (fx)

No effect

CPU Clock Selection Bits ⁽¹⁾

.4 and .3

0

1

0

1

0

1

fx/16 or fxt

fx/8 or fxt

fx/2 or fxt

fx (non-divided) or fxt

Subsystem Clock Selection Bits ⁽²⁾

.2–.0

1

0

1

Select sub system clock (fxt)

Select main system clock (fx)

Others

NOTES:

1. After a reset, the slowest clock (divided by 16) is selected as the CPU clock. To select faster clock speeds, load

the appropriate values to CLKCON.3 and CLKCON.4.

2. Although sub clock (fxt) is selected as CPU clock (fcpu), the selected clock (fxx) for basic timer, timer counter 0/1,

watch timer, and A/D converter is main clock if the value of CLKCON.6-.5 are not "10B (value to stop main clock)."

3. Although the value of CLKCON. 6-.5 are “10B (value to stop main clock)”, main clock is not stopped if main system

clock (fx) is selected as CPU clock (fcpu).

4-8

S3C821A/P821A

CONTROL REGISTERS

EMT — External Memory Timing Register ^(note)

FEH

Set 1, Bank 0

Bit Identifier

.7

–

.6

–

.5

–

.4

–

.3

–

.2

–

.1

0

.0

–

RESET Value

Read/Write

–

R/W

–

Addressing Mode

Register addressing mode only

Not used for the S3C821A

Stack Area Selection Bit

.7–.2

.1

0

1

Select internal register file area

Select external data memory area

.0

Not used for the S3C821A

NOTE: The EMT register is not used except EMT.1 register bit. The program initialization routine should clear the EMT

register except the bit 1 to "00H" following a reset. Modification of EMT values during normal operation may cause a

system malfunction.

4-9

CONTROL REGISTERS

S3C821A/P821A

FLAGS— System Flags Register

D5H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

.0

0

RESET Value

Read/Write

R/W

R

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

Carry Flag (C)

0

1

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

0

1

Operation result is £ +127 or ³ –128

Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0

1

Add operation completed

Subtraction operation completed

Half-Carry Flag (H)

0

1

No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

0

1

Interrupt return (IRET) in progress (when read)

Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0

1

Bank 0 is selected

Bank 1 is selected

4-10

S3C821A/P821A

CONTROL REGISTERS

IMR— Interrupt Mask Register

DDH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

–

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P4.3–P4.0

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P4.7–P4.4

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.7–P2.4

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer Overflow

0

1

Disable (mask)

Enable (un-mask)

.3

.2

Not used for the S3C821A

Interrupt Level 2 (IRQ2) Enable Bit; SIO Interrupt

0

1

Disable (mask)

Enable (un-mask)

.1

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match (Timer A and B)

0

1

Disable (mask)

Enable (un-mask)

.0

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow

0

1

Disable (mask)

Enable (un-mask)

NOTES:

1. When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

2. Interrupt levels IRQ3 is not used in the S3C821A interrupt structure.

4-11

CONTROL REGISTERS

S3C821A/P821A

IPH— Instruction Pointer (High Byte)

DAH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction

pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL

register (DBH).

IPL— Instruction Pointer (Low Byte)

DBH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

pointer address (IP7IP0). The upper byte of the IP address is located in the IPH

register (DAH).

4-12

S3C821A/P821A

CONTROL REGISTERS

IPR— Interrupt Priority Register

FFH

Set 1, Bank 0

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Group priority undefined

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

Group priority undefined

.6

.5

.3

.2

.0

Interrupt Subgroup C Priority Control Bit

0

1

IRQ6 > IRQ7

IRQ7 > IRQ6

Interrupt Group C Priority Control Bit

0

1

IRQ5 > (IRQ6, IRQ7)

(IRQ6, IRQ7) > IRQ5

Interrupt Subgroup B Priority Control Bit ^(note)

0

1

IRQ4

Interrupt Group B Priority Control Bit ^(note)

0

1

IRQ2 > IRQ4

IRQ4 > IRQ2

Interrupt Group A Priority Control Bit

0

1

IRQ0 > IRQ1

IRQ1 > IRQ0

NOTE: The S3C821A interrupt structure uses only the seven levels: IRQ0–IRQ2, and IRQ4–IRQ7. Because IRQ3 is not

recognized, the interrupt B subgroup settings (IPR.2 and IPR.3) are not evaluated.

4-13

CONTROL REGISTERS

S3C821A/P821A

IRQ— Interrupt Request Register

DCH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

R

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

Level 7 (IRQ7) Request Pending Bit; External Interrupts P4.3–P4.0

0

1

Not pending

Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P4.7–P4.4

0

1

Not pending

Pending

Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4

0

1

Not pending

Pending

Level 4 (IRQ4) Request Pending Bit; Watch Timer Overflow

0

1

Not pending

Pending

.3

.2

Not used for the S3C821A

Level 2 (IRQ2) Request Pending Bit; SIO Interrupt

0

1

Not pending

Pending

.1

.0

Level 1 (IRQ1) Request Pending Bit; Timer 1 Match (Timer A and B)

0

1

Not pending

Pending

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow

0

1

Not pending

Pending

NOTE: Interrupt level IRQ3 is not used in the S3C821A interrupt structure.

4-14

S3C821A/P821A

CONTROL REGISTERS

LCON — LCD Control Register

FAH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

–

.4

–

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Register addressing mode only

.7 and .6

LCD Duty and Bias Selection Bits

0

1

Display off, P-Tr off

Normal display (using V_LC1with external voltage), P-Tr off

1

0

1

All dots off, P-Tr on

Normal display (using V_LC1with internal voltage), P-Tr on

.5 and .4

.3 and .2

Not used for the S3C821A.

LCD Duty and Bias Selection Bits

0

1

0

1

0

1

1/3 duty, 1/3 bias; COM0–COM2/SEG0–SEG31

1/4 duty, 1/3 bias; COM0–COM3/SEG0–SEG31

1/8 duty, 1/4 bias; COM0–COM7/SEG4–SEG31

1/8 duty, 1/5 bias; COM0–COM7/SEG4–SEG31

.1 and .0

LCD Clock Selection Bits

fw/2⁶(512 Hz when fw is 32.768 kHz)

fw/2⁵(1,024 Hz when fw is 32.768 kHz)

fw/2⁴(2,048 Hz when fw is 32.768 kHz)

fw/2³(4,096 Hz when fw is 32.768 kHz)

0

1

0

1

0

1

4-15

CONTROL REGISTERS

S3C821A/P821A

P0CON— Port 0 Control Register

E0H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Upper Nibble Port Configuration (P0.7/A15–P0.4/A12)

0

1

0

1

0

1

x

0

1

x

0

1

x

Input mode

Pull-up input mode

Push-pull output mode

Open-drain output mode

LCD segment (SEG23–SEG20)

External interface (A15–A12)

.3–.0

Lower Nibble Port Configuration (P0.3/A11–P0.0/A8)

0

1

0

1

0

1

x

0

1

x

0

1

x

Input mode

Pull-up input mode

Push-pull output mode

Open-drain output mode

LCD segment (SEG19–SEG16)

External interface (A11–A8)

NOTE: "x" means don't care.

4-16

S3C821A/P821A

CONTROL REGISTERS

P1CON— Port 1 Control Register

E2H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Upper Nibble Port Configuration (P1.7/AD7–P1.4/AD4)

0

1

0

1

0

1

x

0

1

x

0

1

x

Input mode

Pull-up input mode

Push-pull output mode

Open-drain output mode

LCD segment (SEG31–SEG28)

External interface (AD7–AD4)

.3–.0

Lower Nibble Port Configuration (P1.3/AD3–P1.0/AD0)

0

1

0

1

0

1

x

0

1

x

0

1

x

Input mode

Pull-up input mode

Push-pull output mode

Open-drain output mode

LCD segment (SEG27–SEG24)

External interface (AD3–AD0)

NOTE: "x" means don't care.

4-17

CONTROL REGISTERS

S3C821A/P821A

P2CONH— Port 2 Control Register (High Byte)

E4H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P2.7/TB Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Select alternate function for P2.7 (TB clock)

P2.6/TA Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Select alternate function for P2.6 (TA clock)

P2.5/T1CK Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode (T1CK)

Schmitt trigger input, pull-up mode (T1CK)

Push-pull output mode

P2.5 remains "0" state

P2.4/T0CK Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode (T0CK)

Schmitt trigger input, pull-up mode (T0CK)

Push-pull output mode

P2.4 remains "0" state

NOTE: Pins configured as input can be used as interrupt input with noise filter.

4-18

S3C821A/P821A

CONTROL REGISTERS

P2CONL— Port 2 Control Register (Low Byte)

E5H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P2.3/DM Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

External memory interface line (DM)

P2.2/DW Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

External memory interface line (DW)

P2.1/DR Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

External memory interface line (DR)

P2.0/AS Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

External memory interface line (AS)

4-19

CONTROL REGISTERS

S3C821A/P821A

P2INT— Port 2 Interrupt Control Register

E6H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

Port 2 Interrupt Request Pending Bit (P2.7/INT3)

0

1

No interrupt request pending

Clear pending bit (when write)

Interrupt request is pending

.6

.5

Interrupt Control Settings (P2.7/INT3)

0

1

Disable interrupt on P2.7

Enable interrupt at falling edge on P2.7

Port 2 Interrupt Request Pending Bit (P2.6/INT2)

0

1

No interrupt request pending

Clear pending bit (when write)

Interrupt request is pending

.4

.3

Interrupt Control Settings (P2.6/INT2)

0

1

Disable interrupt on P2.6

Enable interrupt at falling edge on P2.6

Port 2 Interrupt Request Pending Bit (P2.5/INT1)

0

1

No interrupt request pending

Clear pending bit (when write)

Interrupt request is pending

.2

.1

Interrupt Control Settings (P2.5/INT1)

0

1

Disable interrupt on P2.5

Enable interrupt at falling edge on P2.5

Port 2 Interrupt Request Pending Bit (P2.4/INT0)

0

1

No interrupt request pending

Clear pending bit (when write)

Interrupt request is pending

.0

Interrupt Control Settings (P2.4/INT0)

0

1

Disable interrupt on P2.4

Enable interrupt at falling edge on P2.4

4-20

S3C821A/P821A

CONTROL REGISTERS

P3CONH— Port 3 Control Register (High Byte)

E6H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P3.7/T0/T0PWM/T0CAP Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode (T0CAP input)

Schmitt trigger input, pull-up mode (T0CAP input)

Push-pull output mode

Select alternate function (T0PWM/T0)

P3.6 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Output, high-impedance

P3.5 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Output, high-impedance

P3.4 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Output, high-impedance

4-21

CONTROL REGISTERS

S3C821A/P821A

P3CONL— Port 3 Control Register (Low Byte)

E7H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P3.3/ADC3 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

A/D converter input mode; schmitt trigger input off

P3.2/ADC2 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

A/D converter input mode; schmitt trigger input off

P3.1/ADC1 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

A/D converter input mode; schmitt trigger input off

P3.0/ADC0 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

A/D converter input mode; schmitt trigger input off

4-22

S3C821A/P821A

CONTROL REGISTERS

P4CONH— Port 4 Control Register (High Byte)

E8H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P4.7/INT11 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

P4.6/INT10 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

P4.5/INT9 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

P4.4/INT8 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

NOTE: Pins configured as input can be used as interrupt input with noise filter.

4-23

CONTROL REGISTERS

S3C821A/P821A

P4CONL— Port 4 Control Register (Low Byte)

E9H

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P4.3/INT7 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

P4.2/INT6 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

P4.1/INT5 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

P4.0/INT4 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

NOTE: Pins configured as input can be used as interrupt input with noise filter.

4-24

S3C821A/P821A

CONTROL REGISTERS

P4INT— Port 4 Interrupt Control Register

E7H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P4.7 External Interrupt (INT11) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.6 External Interrupt (INT10) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.5 External Interrupt (INT9) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.4 External Interrupt (INT8) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.3 External Interrupt (INT7) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.2 External Interrupt (INT6) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.1 External Interrupt (INT5) Enable Bit

0

1

Disable interrupt

Enable interrupt

P4.0 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

4-25

CONTROL REGISTERS

S3C821A/P821A

P4PND— Port 4 Interrupt Pending Register

E8H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P4.7 External Interrupt (INT11) Pending Flag

0

1

Clear pending bit (when write)

P4.7 interrupt request is pending (when read)

P4.6 External Interrupt (INT10) Pending Flag

0

1

Clear pending bit (when write)

P4.6 interrupt request is pending (when read)

P4.5 External Interrupt (INT9) Pending Flag

0

1

Clear pending bit (when write)

P4.5 interrupt request is pending (when read)

P4.4 External Interrupt (INT8) Pending Flag

0

1

Clear pending bit (when write)

P4.4 interrupt request is pending (when read)

P4.3 External Interrupt (INT7) Pending Flag

0

1

Clear pending bit (when write)

P4.3 interrupt request is pending (when read)

P4.2 External Interrupt (INT6) Pending Flag

0

1

Clear pending bit (when write)

P4.2 interrupt request is pending (when read)

P4.1 External Interrupt (INT5) Pending Flag

0

1

Clear pending bit (when write)

P4.1 interrupt request is pending (when read)

P4.0 External Interrupt (INT4) Pending Flag

0

1

Clear pending bit (when write)

P4.0 interrupt request is pending (when read)

NOTE: Writing a “1” to an interrupt pending flag (P4PND.0–.7) has no effect.

4-26

S3C821A/P821A

CONTROL REGISTERS

P4EDGE— Port 4 Interrupt Edge Selection Register

E9H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P4.7 External Interrupt (INT11) State Bit

0

1

Falling edge detection

Rising edge detection

P4.6 External Interrupt (INT10) State Bit

0

1

Falling edge detection

Rising edge detection

P4.5 External Interrupt (INT9) State Bit

0

1

Falling edge detection

Rising edge detection

P4.4 External Interrupt (INT8) State Bit

0

1

Falling edge detection

Rising edge detection

P4.3 External Interrupt (INT7) State Bit

0

1

Falling edge detection

Rising edge detection

P4.2 External Interrupt (INT6) State Bit

0

1

Falling edge detection

Rising edge detection

P4.1 External Interrupt (INT5) State Bit

0

1

Falling edge detection

Rising edge detection

P4.0 External Interrupt (INT4) State Bit

0

1

Falling edge detection

Rising edge detection

4-27

CONTROL REGISTERS

S3C821A/P821A

P5CONH— Port 5 Control Register (High Byte)

EAH

Set 1, Bank 1

Bit Identifier

.7

–

.6

–

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

–

R/W

Addressing Mode

Register addressing mode only

Not used for the S3C821A

P5.6 Mode Selection Bits

.7 and .6

.5 and .4

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Output, high-impedance

.3 and .2

P5.5 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Output, high-impedance

.1 and .0

P5.4 Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Output, high-impedance

4-28

S3C821A/P821A

CONTROL REGISTERS

P5CONL— Port 5 Control Register (Low Byte)

EBH

Set 1, Bank 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P5.3/BUZ Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Select alternate function (BUZ signal)

P5.2/SO Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Select alternate function (SO)

P5.1/SI Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode (SI input)

Schmitt trigger input, pull-up mode

Push-pull output mode

Output high-impedance

P5.0/SCK Mode Selection Bits

0

1

0

1

0

1

Schmitt trigger input mode (SCK input)

Schmitt trigger input, pull-up mode

Push-pull output mode

Select alternate function (SCK output)

NOTE: SI and SCK inputs have noise filter.

4-29

CONTROL REGISTERS

S3C821A/P821A

PP— Register Page Pointer

DFH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Destination Register Page Selection Bits

0

1

0

1

0

1

0

1

0

Destination: page 0

Destination: page 1

Destination: page 2

Destination: page 3

Destination: page 4

.3–.0

Source Register Page Selection Bits

0

1

0

1

0

1

0

1

0

Source: page 0

Source: page 1

Source: page 2

Source: page 3

Source: page 4

NOTES:

1. In the S3C821A microcontroller, the internal register file is configured as five pages (Pages 0–4). The pages 0–3 are

used for general purpose register file, and page 4 is used for LCD data register or general purpose registers.

2. You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

4-30

S3C821A/P821A

CONTROL REGISTERS

RP0— Register Pointer 0

D6H

Set 1

Bit Identifier

.7

1

.6

1

.5

0

.4

0

.3

0

.2

–

.1

–

.0

–

RESET Value

Read/Write

R/W

–

Addressing Mode

Register addressing only

.7–.3

.2–.0

Register Pointer 0 Address Value

Register pointer 0 can independently point to one of the 256-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to address C0H in register set 1, selecting the 8-byte working register

slice C0H–C7H.

Not used for the S3C821A

RP1— Register Pointer 1

D7H

Set 1

Bit Identifier

.7

1

.6

1

.5

0

.4

0

.3

1

.2

–

.1

–

.0

–

RESET Value

Read/Write

R/W

–

Addressing Mode

Register addressing only

.7–.3

.2–.0

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 256-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to address C8H in register set 1, selecting the 8-byte working register

slice C8H–CFH.

Not used for the S3C821A

4-31

CONTROL REGISTERS

S3C821A/P821A

SCLKCON— Sub-System Clock Control Register

FFH

Set 1, Bank 1

Bit Identifier

.7

–

.6

–

.5

–

.4

–

.3

–

.2

–

.1

–

.0

0

RESET Value

Read/Write

–

R/W

Addressing Mode

Register addressing only

.7–.1

.0

Not used for the S3C821A

Sub-System Clock Stop Enable Bit

0

1

Enable sub-system clock

Disable sub-system clock

NOTES:

1. The sub oscillator can be halted only by SCLKCON.0. In sub-oscillation mode, sub-oscillation stop can be released

only by a reset operation.

2. When sub and main oscillator are halted in main operating mode, stop mode can be released by an external interrupt or

a reset operation.

4-32

S3C821A/P821A

CONTROL REGISTERS

SIOCON— SIO Control Register

F5H

Set 1, Bank 0

Bit Identifier

.7

1

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

SIO Shift Clock Selection Bit

0

1

External clock

CPU clock

SIO Interrupt Pending Bit

0

1

No interrupt pending

Clear pending condition (when write)

Interrupt is pending

.5

.4

.3

.2

.1

.0

SIO Interrupt Enable Bit

0

1

Disable SIO interrupt

Enable SIO interrupt

SIO Start Edge Selection Bit

0

1

Falling edge start

Rising edge start

SIO Counter Clear and Shifter Start Bit

0

1

No action (when write)

Clear 3-bit counter and start shifting

SIO Shift Operation Enable Bit

0

1

Disable shifter and counter, retain IRQ status

Enable shifter and clock counter, set IRQ flag to "1"

SIO Mode Selection Bit

0

1

Receive only mode

Transmit/receive mode

Data Direction Control Bit

0

1

MSB first mode

LSB first mode

4-33

CONTROL REGISTERS

S3C821A/P821A

SPH— Stack Pointer (High Byte)

D8H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Stack Pointer Address (High Byte)

The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer

address (SP15–SP8). The lower byte of the stack pointer value is located in register

SPL (D9H). The SP value is undefined following a reset.

SPL— Stack Pointer (Low Byte)

D9H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Stack Pointer Address (Low Byte)

The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer

address (SP7–SP0). The upper byte of the stack pointer value is located in register

SPH (D8H). The SP value is undefined following a reset.

4-34

S3C821A/P821A

CONTROL REGISTERS

SYM — System Mode Register

DEH

Set 1

Bit Identifier

.7

0

.6

–

.5

–

.4

x

.3

x

.2

x

.1

0

.0

0

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Register addressing mode only

.7

Tri-State External Interface Enable Bit

0

1

Normal operation (disable tri-state operation)

Set external interface lines to high impedance (enable tri-state operation)

.6 and .5

.4–.2

Not used for the S3C821A

Fast Interrupt Level Selection Bits ⁽¹⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IRQ0

IRQ1

IRQ2

Not used for the S3C821A

IRQ4

IRQ5

IRQ6

IRQ7

Fast Interrupt Enable Bit ⁽²⁾

.1

0

1

Disable fast interrupt processing

Enable fast interrupt processing

Global Interrupt Enable Bit ⁽³⁾

.0

0

1

Disable all interrupt processing

Enable all interrupt processing

NOTES:

1. You can select only one interrupt level at a time for fast interrupt processing.

2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2-SYM.4.

3. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"

to SYM.0).

4-35

CONTROL REGISTERS

S3C821A/P821A

T0CON— Timer 0 Control Register

D2H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

Timer 0 Input Clock Selection Bits

0

1

0

1

0

1

fxx/4,096

fxx/256

fxx/8

External clock input (T0CK)

.5 and .4

Timer 0 Operating Mode Selection Bits

0

1

0

1

0

1

Interval timer mode

Capture mode (rising edges, counter running, OVF interrupt can occur)

Capture mode (falling edges, counter running, OVF interrupt can occur)

PWM mode (OVF interrupt can occur)

.3

.2

.1

.0

Timer 0 Counter Clear Bit

0

1

No effect

Clear T0 counter (when write)

Timer 0 Overflow Interrupt Enable Bit ^(note)

0

1

Disable T0 overflow interrupt

Enable T0 overflow interrupt

Timer 0 Interrupt Enable Bit

0

1

Disable T0 interrupt

Enable T0 interrupt

Timer 0 Interrupt Pending Bit

0

1

No T0 interrupt pending (when read)

Clear T0 interrupt pending condition (when write)

T0 interrupt is pending

NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0 match/

capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.

4-36

S3C821A/P821A

CONTROL REGISTERS

TACON— Timer Counter 1/A Control Register

F3H

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

Timer 1 Operating Mode Selection Bit

0

1

Two 8-bit timers mode (Timer A/B)

One 16-bit timer mode (Timer 1)

.6–.4

Timer 1/A Clock Selection Bits

0

1

0

1

x

0

1

0

1

x

fxx/1,024

fxx/512

fxx/8

fxx

T1CK (External clock at P2.5)

.3

.2

.1

.0

Timer 1/A Counter Clear Bit

0

1

No effect

Clear the timer A counter (when write)

Timer 1/A Counter Run Enable Bit

0

1

Disable Counter Running

Enable Counter Running

Timer 1/A Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Timer 1/A Interrupt Pending Bit

0

1

No interrupt pending (when read)

Clear pending bit (when write)

Interrupt is pending (when read)

No effect (when write)

NOTES:

1. "x" means don't care.

2. fxx is a selected clock for peripheral hardware.

4-37

CONTROL REGISTERS

S3C821A/P821A

TBCON— Timer B Control Register

F2H

Set 1, Bank 0

Bit Identifier

.7

–

.6

–

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

–

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

Not used for the S3C821A

Timer B Clock Selection Bits

0

1

0

1

0

1

fxx/1,024

fxx/512

fxx/8

fxx

.3

.2

.1

.0

Timer B Counter Clear Bit

0

1

No effect

Clear the timer B counter (when write)

Timer B Counter Run Enable Bit

0

1

Disable Counter Running

Enable Counter Running

Timer B Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Timer B Interrupt Pending Bit

0

1

No interrupt pending (when read)

Clear pending bit (when write)

Interrupt is pending (when read)

No effect (when write)

NOTE: fxx is a selected clock for peripheral hardware.

4-38

S3C821A/P821A

CONTROL REGISTERS

WTCON— Watch Timer Control Register

FBH

Set 1, Bank 0

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

Buzzer Signal Enable Bit

0

1

Disable buzzer signal output

Enable buzzer signal output

.6

Watch Timer Enable Bit

0

1

Disable watch timer; clear frequency dividing circuit

Enable watch timer

.5 and .4

Buzzer Signal Selection Bits

0

1

0

1

0

1

0.5 kHz buzzer (BUZ) signal output

1 kHz buzzer (BUZ) signal output

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

.3

.2

.1

Watch Timer Speed Selection Bit

fw/2¹⁴(0.5 sec) interval

fw/2⁷(3.91 ms) interval

0

1

Watch Timer Clock Selection Bit

Main system clock divided by 2⁷(fx/128)

Sub system clock (fxt)

0

1

Watch Timer Interrupt Pending Bit

0

1

No interrupt pending

Clear pending bit (when write)

Interrupt is pending

.0

Watch Timer Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

4-39

S3C821A/P821A

INTERRUPT STRUCTURE

5

INTERRUPT STRUCTURE

OVERVIEW

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU

recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level

has more than one vector address, the vector priorities are established in hardware. A vector address can be

assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks

can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight

possible interrupt levels: IRQ0–IRQ7, also called level 0-level 7. Each interrupt level directly corresponds to an

interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from

device to device. The S3C821A interrupt structure recognizes seven interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just

identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels

is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by

IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.

The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors

used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the

vector priorities are set in hardware. S3C821A uses nineteen vectors.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.

Each vector can have several interrupt sources. In the S3C821A interrupt structure, there are nineteen possible

interrupt sources.

When a service routine starts, the respective pending bit should be either cleared automatically by hardware or

cleared "manually" by program software. The characteristics of the source's pending mechanism determine which

method would be used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE

INTERRUPT TYPES

S3C821A/P821A

The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are

combined to determine the interrupt structure of an individual device and to make full use of its available

interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,

2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1:

Type 2:

Type 3:

One level (IRQn) + one vector (V₁) + one source (S₁)

One level (IRQn) + one vector (V₁) + multiple sources (S₁– S_n)

One level (IRQn) + multiple vectors (V₁– V_n) + multiple sources (S₁– S_n, S_n+1– S_n+m

)

In the S3C821A microcontroller, two interrupt types are implemented.

LEVELS

VECTORS

SOURCES

V

1

S

1

IRQn

TYPE 1:

TYPE 2:

S

1

V

1

S

2

S

3

S

n

IRQn

V

1

S

1

V

2

V

3

V

n

S

IRQn

2

3

TYPE 3:

S

n

n + 1

:

NOTES

1. The number of S and V values is expandable.

2. In the S3C821A implementation, interrupt

types 1 and 3 are used.

n

S

n + 2

S

n + m

Figure 5-1. S3C8-Series Interrupt Types

5-2

S3C821A/P821A

INTERRUPT STRUCTURE

S3C821A INTERRUPT STRUCTURE

The S3C821A microcontroller supports nineteen interrupt sources. All nineteen of the interrupt sources have a

corresponding interrupt vector address. Seven interrupt levels are recognized by the CPU in this device-specific

interrupt structure, as shown in Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which

contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt

with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a

single level are fixed in hardware).

When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the

program counter value and status flags are pushed to stack. The starting address of the service routine is fetched

from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the

service routine is executed.

5-3

INTERRUPT STRUCTURE

S3C821A/P821A

LEVEL

VECTOR

100H

SOURCE

RESET/CLEAR

Basic timer overflow

Timer 0 match/capture

H/W

S/W

RESET

1

0

1

0

FCH

IRQ0

IRQ1

FAH

F6H

F4H

Timer 0 overflow

Timer 1/A match

H/W

S/W

Timer B match

S/W

IRQ2

IRQ4

F0H

SIO interrupt

S/W

F2H

DEH

DCH

Watch timer overflow

3

2

1

0

P2.7 external interrupt

P2.6 external interrupt

S/W

IRQ5

IRQ6

IRQ7

DAH

D8H

P2.5 external interrupt

P2.4 external interrupt

S/W

3

2

1

0

D6H

D4H

P4.7 external interrupt

P4.6 external interrupt

S/W

D2H

D0H

P4.5 external interrupt

P4.4 external interrupt

S/W

3

2

1

0

C6H

C4H

P4.3 external interrupt

P4.2 external interrupt

S/W

C2H

C0H

P4.1 external interrupt

P4.0 external interrupt

S/W

:

For interrupt levels with two or more vectors, the lowest vector address usually has

the highest priority. For example, FAH has higher priority (0) than FCH (1) within

the level IRQ0. These priorities are fixed in hardware.

NOTE

Figure 5-2. S3C821A Interrupt Structure

5-4

S3C821A/P821A

INTERRUPT STRUCTURE

INTERRUPT VECTOR ADDRESSES

All interrupt vector addresses for the S3C821A interrupt structure are stored in the vector address area of the

internal 48-K byte ROM, 0H–BFFFH (see Figure 5-3).

You can allocate unused locations in the vector address area as normal program memory. If you do so, please be

careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).

The program reset address in the ROM is 0100H.

(DECIMAL)

49,151

(HEX)

BFFFH

48-KBYTE INTERNAL

PROGRAM MEMORY

(ROM) AREA

~

RESET

ADDRESS

100H

FFH

255

0

INTERRUPT

VECTOR ADDRESS

AREA

00H

Figure 5-3. ROM Vector Address Area

5-5

INTERRUPT STRUCTURE

Vector Address

S3C821A/P821A

Reset/Clear

Table 5-1. S3C821A Interrupt Vectors

Interrupt Source

Request

Interrupt

Decimal

Value

Hex

Value

Priority in H/W

S/W

Level

256

100H

Basic timer overflow

–

Ö

RESET

252

250

246

244

240

242

222

220

218

216

214

212

210

208

198

196

194

192

FCH

FAH

F6H

F4H

F0H

F2H

DEH

DCH

DAH

D8H

D6H

D4H

D2H

D0H

C6H

C4H

C2H

C0H

Timer 0 (match/capture)

Timer 0 overflow

IRQ0

1

0

1

0

–

3

2

1

0

3

2

1

0

3

2

1

0

Ö

Timer 1/A match

IRQ1

Ö

Timer B match

SIO interrupt

IRQ2

IRQ4

IRQ5

Watch timer overflow

P2.7 external interrupt

P2.6 external interrupt

P2.5 external interrupt

P2.4 external interrupt

P4.7 external interrupt

P4.6 external interrupt

P4.5 external interrupt

P4.4 external interrupt

P4.3 external interrupt

P4.2 external interrupt

P4.1 external interrupt

P4.0 external interrupt

IRQ6

IRQ7

NOTES:

1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.

2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority

over one with a higher vector address. The priorities within a given level are fixed in hardware.

5-6

S3C821A/P821A

INTERRUPT STRUCTURE

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then

serviced as they occur according to the established priorities.

NOTE

The system initialization routine executed after a reset must always contain an EI instruction to globally

enable the interrupt structure.

During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable

interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt

processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to

each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable

fast interrupts and control the activity of external interface, if implemented).

Table 5-2. Interrupt Control Register Overview

Control Register

ID

R/W

Function Description

Bit settings in the IMR register enable or disable interrupt

processing for each of the seven interrupt levels: IRQ0–IRQ2,

and IRQ4–IRQ7.

Interrupt mask register

IMR

R/W

Controls the relative processing priorities of the interrupt

levels. The seven levels of S3C821A are organized into three

groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is

IRQ2 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

Interrupt priority register

IPR

R/W

This register contains a request pending bit for each interrupt

level.

Interrupt request register

System mode register

IRQ

R

This register enables/disables fast interrupt processing,

dynamic global interrupt processing, and external interface

control (An external memory interface is implemented in the

S3C821A microcontroller).

SYM

R/W

5-7

INTERRUPT STRUCTURE

S3C821A/P821A

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.

The system-level control points in the interrupt structure are:

— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing an application program that handles interrupt processing, be sure to include the necessary

register file address (register pointer) information.

Q

INTERRUPT REQUEST

REGISTER (Read-only)

POLLING

CYCLE

EI

S

R

RESET

IRQ0-IRQ2,

and IRQ4-IRQ7

INTERRUPTS

INTERRUPT PRIORITY

REGISTER

VECTOR

INTERRUPT

CYCLE

INTERRUPT MASK

REGISTER

GLOBAL INTERRUPT

CONTROL (EI, DI, or

SYM.0 manipulation)

Figure 5-4. Interrupt Function Diagram

5-8

S3C821A/P821A

INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the

interrupt generated by the related peripheral (see Table 5-3).

Table 5-3. Interrupt Source Control and Data Registers

Interrupt Source

Interrupt Level

Register(s)

Location(s) in Set 1

T0CON ^(note)

T0DATA

Timer 0 match/capture

Timer 0 overflow

IRQ0

D2H

D1H

Timer 1/Timer A match

Timer B match

IRQ1

IRQ2

TACON, TBCON

TADATA, TBDATA

F3H, F2H, bank 0

F1H, F0H, bank 0

SIO interrupt

SIOPS, SIOCON

SIO

F6H, F5H, bank 0

F4H, bank 0

Watch timer overflow

IRQ4

IRQ5

WTCON

FBH, bank 0

P2.7 external interrupt

P2.6 external interrupt

P2.5 external interrupt

P2.4 external interrupt

P2CONH

P2INT

E4H, bank 1

E6H, bank 0

P4.7 external interrupt

P4.6 external interrupt

P4.5 external interrupt

P4.4 external interrupt

IRQ6

IRQ7

P4CONH

P4INT

P4PND

P4EDGE

E8H, bank 1

E7H, bank 0

E8H, bank 0

E9H, bank 0

P4.3 external interrupt

P4.2 external interrupt

P4.1 external interrupt

P4.0 external interrupt

P4CONL

P4INT

P4PND

P4EDGE

E9H, bank 1

E7H, bank 0

E8H, bank 0

E9H, bank 0

NOTE: Because the timer 0 overflow interrupt is cleared by hardware, the T0CON register controls only the enable/disable

functions. The T0CON register contains enable/disable and pending bits for the timer 0 match/capture interrupt.

5-9

INTERRUPT STRUCTURE

S3C821A/P821A

SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to

control fast interrupt processing (see Figure 5-5).

A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4-SYM.2,

is undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0

value of the SYM register. In order to enable interrupt processing, an Enable Interrupt (EI) instruction must be

included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly

to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions

for this purpose.

SYSTEM MODE REGISTER (SYM)

DEH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Global interrupt enable bit:

0 = Disable all interrupts processing

1 = Enable all interrupts processing

External interface tri-state enable bit:

0= Normal operation (Tri-state disabled)

1= Set external interface lines to high

impedance (Tri-state enabled)

Fast interrupt enable bit:

0 = Disable fast interrupts processing

1 = Enable fast interrupts processing

Not used for the S3C821A

Fast interrupt level selection bits:

IRQ0

IRQ1

IRQ2

Not used

IRQ4

IRQ5

IRQ6

IRQ7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Figure 5-5. System Mode Register (SYM)

5-10

S3C821A/P821A

INTERRUPT STRUCTURE

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual

interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required

settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit

of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a

level's IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions

using the Register addressing mode.

INTERRUPT MASK REGISTER (IMR)

DDH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

IRQ0

IRQ1

IRQ2

Not used

IRQ4

IRQ5

Interrupt level enable bits (7–4, 2–0):

0 = Disable (mask) interrupt level

1 = Enable (un-mask) interrupt level

IRQ6

IRQ7

Figure 5-6. Interrupt Mask Register (IMR)

5-11

INTERRUPT STRUCTURE

S3C821A/P821A

INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels

in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore

be written to their required settings by the initialization routine.

When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two

sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This

priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by

the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register

priority definitions (see Figure 5-7):

Group A

Group B

Group C

IRQ0, IRQ1

IRQ2, IRQ4

IRQ5, IRQ6, IRQ7

IPR

GROUP A

GROUP B

GROUP C

A1

A2

B1

B2

C1

C2

C3

IRQ0

IRQ1

IRQ2

IRQ4

IRQ5

IRQ6

IRQ7

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.

For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B"

would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of group C interrupts.

— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,

6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C. In the S3C821A

implementation, the interrupt level 3 is not used. Therefore, IPR.3 setting is not evaluated.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-12

S3C821A/P821A

INTERRUPT STRUCTURE

INTERRUPT PRIORITY REGISTER (IPR)

FFH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

GROUP PRIORITY:

D7 D4 D1

GROUP A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

=

UNDEFINED

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

UNDEFINED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GROUP B

0 = IRQ2 > IRQ4

1 = IRQ4 > IRQ2

(note)

SUBGROUP B

0 = IRQ4

1 = IRQ4

GROUP C

0 = IRQ5 > (IRQ6, IRQ7)

1 = (IRQ6, IRQ7) > IRQ5

SUBGROUP C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

:

In the S3C821A interrupt structure, only the levels IRQ0-IRQ2, and IRQ4-IRQ7 are

used. The setting for subgroup B, which controls relative priorities for the level IRQ3

is therefore not evaluated.

NOTE

Figure 5-8. Interrupt Priority Register (IPR)

5-13

INTERRUPT STRUCTURE

S3C821A/P821A

INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for

all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same

number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued

for that level. A "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of

the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of

specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing

is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,

however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events

occurred while the interrupt structure was globally disabled.

INTERRUPT REQUEST REGISTER (IRQ)

DCH, Set 1, Read-only

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

IRQ0

IRQ1

IRQ2

Not used

IRQ4

IRQ5

Interrupt level request pending bits:

IRQ6

0 = Interrupt level is not pending

1 = Interrupt level is pending

IRQ7

Figure 5-9. Interrupt Request Register (IRQ)

5-14

S3C821A/P821A

INTERRUPT STRUCTURE

INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the

interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service

routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding

pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is

waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service

routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or

written by application software.

In the S3C821A interrupt structure, the timer 0 overflow interrupt (IRQ0) belongs to this category of interrupts in

which pending condition is cleared automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit is the one that should be cleared by program software. The service routine must

clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must

be written to the corresponding pending bit location in the source’s mode or control register.

In the S3C821A interrupt structure, pending conditions for all interrupt sources, except the timer 0 overflow

interrupt, must be cleared in the interrupt service routine.

5-15

INTERRUPT STRUCTURE

S3C821A/P821A

INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the source's interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request is serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one levels are currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.

The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores

the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.

5-16

S3C821A/P821A

INTERRUPT STRUCTURE

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that

correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,

you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it

occurs).

4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the

previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the procedure above to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed

interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP

registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing allows an interrupt within a given level to be completed in

approximately six clock cycles rather than the usual 22 clock cycles. To select a specific interrupt level for fast

interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt

processing for the selected level, you set SYM.1 to “1”.

5-17

INTERRUPT STRUCTURE

S3C821A/P821A

FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the

program counter values), and

— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated

register called FLAGS' (“FLAGS prime”).

NOTE

For the S3C821A microcontroller, the service routine for any one of the seven interrupt levels: IRQ0–

IRQ2, or IRQ4–IRQ7, can be selected for fast interrupt processing.

Procedure for Initiating Fast Interrupts

To initiate fast interrupt processing, follow these steps:

1. Load the start address of the service routine into the instruction pointer (IP).

2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)

3. Write a "1" to the fast interrupt enable bit in the SYM register.

Fast Interrupt Service Routine

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

1. The contents of the instruction pointer and the PC are swapped.

2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.

3. The fast interrupt status bit in the FLAGS register is set.

4. The interrupt is serviced.

5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction

pointer and PC values are swapped back.

6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.

7. The fast interrupt status bit in FLAGS is cleared automatically.

Relationship to Interrupt Pending Bit Types

As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by

hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the

application program's interrupt service routine. You can select fast interrupt processing for interrupts with either

type of pending condition clear function — by hardware or by software.

Programming Guidelines

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the

SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,

including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast

interrupt service routine ends.

5-18

S3C821A/P821A

CLOCK CIRCUITS

7

CLOCK CIRCUITS

OVERVIEW

The S3C821A microcontroller has two oscillator circuits: a main system clock, and a subsystem clock circuit. The

CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The

maximum CPU clock frequency is determined by CLKCON register settings.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal, ceramic resonator, an external clock, or RC oscillation source

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (fx divided by 1, 2, 8, or 16 or fxt)

— Clock circuit control register, CLKCON

System Clock Notation

In this document, the following notation is used for descriptions of the system clock:

fx main system clock

fxt subsystem clock

fxx selected system clock for peripheral hardware

fcpu CPU clock

7-1

CLOCK CIRCUITS

S3C821A/P821A

MAIN SYSTEM OSCILLATOR CIRCUITS

SUBSYSTEM OSCILLATOR CIRCUITS

Xin

XTin

Xout

XTout

32.768 kHz

Figure 7-1. Crystal/Ceramic Oscillator

Figure 7-4. Crystal/Ceramic Oscillator

Xin

XTin

External

Clock

Xout

XTout

Figure 7-2. External Oscillator

Figure 7-5. External Oscillator

Xin

R

Xout

Figure 7-3. RC Oscillator

7-2

S3C821A/P821A

CLOCK CIRCUITS

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset

operation, by a watch timer overflow interrupt (when the watch timer clock source is subsystem clock) or by

an external interrupt (When the fx is selected as CPU clock).

— In Idle mode, the internal clock signal is gated away from the CPU, but it continues to be supplied to the

interrupt structure, basic timer, timer 0, timer 1, A/D converter, and watch timer. Idle mode is released by a

reset or by an interrupt (externally generated or internally generated).

Stop

CLKCON.5,.6

Instruction

CLKCON.3,.4

CLKCON.5,.6⁽⁴⁾

Basic Timer

Timer Counter0, 1

Watch Timer

M

U

X

Oscillator

Stop

fxx

A/D Converter

fx

MAIN

OSC

M

U

X

fcpu

CPU CLOCK

SIO

1/2

1/8

M

U

X

Oscillator

Wake-up

NOISE

FILTER

fxt

SUB

OSC

1/16

CLKCON.0-.2

3-Bit Signature Code ⁽²⁾

CLKCON.7

SCLKCON.0

INT Pin ⁽¹⁾

NOTES:

1. An external interrupt can be used to release Stop mode and "wake up" the main oscillator.

2. The sub oscillator can be halted only by SCLKCON.0. Sub oscillation stop can be released only by a

reset operation.

3. When sub and main oscillator are halted in main operation mode, stop mode can be released by an

external interrupt, or a reset operation.

4. Although sub clock (fxt) is selected as CPU clock (fcpu), the selected clock (fxx) for basic timer, timer

counter 0/1, watch timer, and A/D converter is main clock if the value of CLKCON.6-.5 are

not "10B (value to stop main clock)".

Figure 7-6. System Clock Circuit Diagram

7-3

CLOCK CIRCUITS

S3C821A/P821A

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and

has the following functions:

— Oscillator IRQ wake-up function enable/disable

— Oscillator frequency divide-by value

— System clock signal selection

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release

(This is called the "IRQ wake-up" function). The IRQ “wake-up” enable bit is CLKCON.7.

After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the

fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can raise the CPU clock speed to

fx, fx/2, fx/8, or fxt (subsystem clock).

For the S3C821A microcontroller, the CLKCON.2-CLKCON.0 system clock signature code can be any value

(The "101B" setting selects subsystem clock as CPU clock). The reset value for the clock signature code is

"000B".

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

D4H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

subsystem clock selection bits:

101 B = select subsystem clock

Other value = select main system clock

Oscillator IRQ wake-up enable bit:

0 = Enable IRQ for main system

oscillator wake-up function

Divide-by selection bits for

CPU clock frequency:

00 = fx/16 or fxt

1 = Disable IRQ for main system

oscillator wake-up function

01 = f x/8 or fxt

10 = fx /2 or fxt

11 = fx or fxt (non-divided)

(note)

Main oscillator stop control bits:

00 = No effect

01 = No effect

10 = Stop main oscillator

11 = No effect

Although the value of CLKCON.6-.5 are “10B (value to stop main clock)”,

main clock is not stopped if main system clock (fx) is selected

as CPU clock (fcpu).

NOTE:

Figure 7-7. System Clock Control Register (CLKCON)

7-4

S3C821A/P821A

CLOCK CIRCUITS

SWITCHING THE CPU CLOCK

Data loadings in the system clock control register, CLKCON, determine whether a main or a sub clock is selected

as the CPU clock, the system clock for peripheral hardware, and also how this frequency is to be divided. This

makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies.

CLKCON.2–.0 select the main clock (fx) or a sub clock (fxt). CLKCON.6–.5 start or stop main clock oscillation.

CLKCON.4–.3 control the frequency divider circuit, and divide the selected fx clock by 1, 2, 8, or 16, or fxt clock

by 1.

Let's say that, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you

want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set

CLKCON.2–.0 to "101B" and CLKCON.6–.5 to "10B" simultaneously. This switches the clock from fx to fxt and

stops main clock oscillation.

The following steps must be taken to switch from a sub clock to the main clock: first, set CLKCON.6–.5 to any

value except "10B" to enable main system clock oscillation. Then, after a certain number of machine cycles has

elapsed, select the main clock by setting CLKCON.2–.0 to any value except "101B". You must remember that

the selected clock (fxx) for the basic timer, timer counter 0/1, watch timer, and A/D converter is the main clock

during the interval time. Refer to "Figure 7-6. System Clock Circuit Diagram."

+

PROGRAMMING TIP — Switching the CPU Clock

1. This example shows how to change from the main clock to the sub clock:

MA2SUB

LD

CLKCON,#5DH

; Switches to the sub clock

; Stop the main clock oscillation

RET

2. This example shows how to change from the sub clock to the main clock:

SUB2MA

AND

CALL

AND

RET

SRP

LD

NOP

DJNZ

RET

CLKCON,#9FH

DLY20

CLKCON,#98H

; Start the main clock oscillation

; Delay 20 ms

; Switch to the main clock

DLY20

DEL

#0C0H

R0,#1BH

R0,DEL

7-5

CLOCK CIRCUITS

S3C821A/P821A

SUB-SYSTEM CLOCK CONTROL REGISTER (SCLKCON)

The sub-system clock control register, SCLKCON, is located in set 1, bank 1, address FFH. It is read/write

addressable and has sub-system clock stop function. SCLKCON register setting controls whether sub-system

clock is halted or not. After a reset, all CLKCON register and SCLKCON register values are cleared to logic zero,

both main-system clock and sub-system clock oscillation start, but main-system clock oscillation is selected as

the CPU clock.

Main-system clock oscillation or sub-system clock oscillation can be halted by manipulating CLKCON.6–.5 or

SCLKCON.0 respectively. At that time, oscillation stop can't be restarted by any interrupt but manipulating

CLKCON or SCLKCON.

SUB-SYSTEM CLOCK CONTROL REGISTER (SCLKCON)

FFH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Sub-system clock stop enable bit:

0 = Enable sub-system clock

1 = Disable sub-system clock

Not used for the

:

NOTES

1. The sub oscillator can be halted only by SCLKCON.0. Sub oscillation stop

can be released only by a reset operation.

2. When sub and main oscillator are halted in main opearating mode, stop mode

can be released by an external interrupt or a reset operation.

Figure 7-8. Sub-System Clock Control Register (SCLKCON)

7-6

S3C821A/P821A

RESET and POWER-DOWN

8

RESET and POWER-DOWN

SYSTEM RESET

OVERVIEW

During a power-on reset, the voltage at V_DDgoes to High level and the RESET pin is forced to Low level. The

RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This

procedure brings the S3C821A into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a

minimum time interval after the power supply comes within tolerance. The minimum required time of a reset

operation for oscillation stabilization is 1 millisecond.

Whenever a reset occurs during normal operation (that is, when both V_DDand RESET are High level), the

RESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then

reset to their default hardware values (see Table 8-1).

In summary, the following sequence of events occurs during a reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0, 1, 2, 3, 4, and 5 are set to input mode and all pull-up resistors are disabled for the I/O port pin

circuits.

— Peripheral control and data register settings are disabled and reset to their default hardware values (see

Table 8-1).

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM

location 0100H (and 0101H) is fetched and executed.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the

basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic

timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can

disable it by writing "1010B" to the upper nibble of BTCON.

8-1

RESET and POWER-DOWN

S3C821A/P821A

HARDWARE RESET VALUES

Table 8-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data

registers following a reset operation. The following notation is used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An "x" means that the bit value is undefined after a reset.

— A dash ("–") means that the bit is either not used or not mapped (but a “0” is read from the bit position).

Table 8-1. Set 1 Register Values After Reset

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

7

0

1

0

x

1

x

0

x

0

6

0

1

0

x

1

x

0

x

–

0

5

0

1

0

x

0

x

0

x

–

0

4

0

1

0

x

0

x

0

x

0

3

0

1

0

x

0

1

x

0

–

x

0

2

0

1

0

x

–

x

0

x

0

1

0

1

0

–

x

0

x

0

1

0

–

x

0

x

0

Timer 0 counter

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

Register pointer 1

RP1

Stack pointer (high byte)

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Register page pointer

SPH

SPL

IPH

IPL

IRQ

IMR

SYM

PP

8-2

S3C821A/P821A

RESET and POWER-DOWN

Table 8-2. Set 1, Bank 0 Register Values After Reset

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

7

0

–

0

6

0

5

0

4

0

3

0

2

0

1

0

Port 0 data register

P0

P1

224

225

226

227

228

229

230

231

232

233

Port 1 data register

Port 2 data register

P2

Port 3 data register

P3

Port 4 data register

P4

Port 5 data register

P5

Port 2 interrupt control register

Port 4 interrupt control register

Port 4 interrupt pending register

Port 4 interrupt edge select register

P2INT

P4INT

P4PND

P4EDGE

Locations EAH–EDH are not mapped.

Timer B counter

TBCNT

TACNT

TBDATA

TADATA

TBCON

TACON

SIO

238

239

240

241

242

243

244

245

246

247

248

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

0

1

–

0

1

0

–

x

0

1

–

0

x

0

1

0

x

0

1

0

x

0

1

0

x

0

1

0

x

0

1

0

x

0

1

0

x

Timer A counter

Timer B data register

Timer A data register

Timer B control register

Timer A control register

SIO data register

SIO control register

SIO prescaler register

ADC control register

ADC data register

SIOCON

SIOPS

ADCON

ADDATA

Location F9H is not mapped.

LCD control register

LCON

250

251

FAH

FBH

0

–

0

–

0

Watch timer mode register

WTCON

Location FCH is not mapped.

Basic timer counter

BTCNT

EMT

253

254

255

FDH

FEH

FFH

x

–

x

–

x

–

x

–

x

–

x

–

x

0

x

–

x

External memory timing register

Interrupt priority register

IPR

NOTES:

1. Except for T0CNT, IRQ, TACNT, TBCNT, ADCON.3, ADDATA, BTCNT, and FIS flag which are read-only, all registers in

set 1 are read/write addressable.

2. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.

8-3

RESET and POWER-DOWN

S3C821A/P821A

Table 8-3. Set 1, Bank 1 Register Values After Reset

Register Name

Port 0 control register

Port 1 control register

Mnemonic

Address

Bit Values After Reset

Dec

224

Hex

7

6

5

4

3

2

1

0

P0CON

E0H

0

Location E1H is not mapped.

P1CON 226 E2H

Location E3H is not mapped.

0

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 3 control register (high byte)

Port 3 control register (low byte)

Port 4 control register (high byte)

Port 4 control register (low byte)

Port 5 control register (high byte)

Port 5 control register (low byte)

P2CONH

P2CONL

P3CONH

P3CONL

P4CONH

P4CONL

P5CONH

P5CONL

228

229

230

231

232

233

234

235

E4H

E5H

E6H

E7H

E8H

E9H

EAH

EBH

0

–

0

–

0

Locations ECH–FEH are not mapped.

SCLKCON 255 FFH

Sub-clock control register

–

0

NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.

8-4

S3C821A/P821A

RESET and POWER-DOWN

POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is

halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator

stops. That is, the watch timer and LCD controller will not halted in stop mode if the subsystem clock is selected

as watch timer clock source. The data stored in the internal register file are retained in stop mode. Stop mode

can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when subsystem

clock is selected as clock source of watch timer), or by an external interrupt.

Example:

STOP

NOP

Using RESET to Release Stop Mode

Stop mode is released when the RESET signal goes active (Low level): all system and peripheral control

registers are reset to their default hardware values and the contents of all data registers are retained. When the

programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by

fetching the program instruction stored in ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts can be used to release stop mode. For the S3C821A microcontroller, we recommend using

the INT0–INT11 interrupt though P2.4–P2.7, P4.0–P4.7.

Using an Internal Interrupt to Release Stop Mode

An internal interrupt, watch timer, can be used to release stop mode because, the watch timer operates in stop

mode if the clock source of watch timer is subsystem clock. If system clock is subsystem clock, you can't use any

interrupts to release stop mode. That is, you had batter use the idle instruction instead of stop one when

subsystem clock is selected as the system clock.

Please note the following conditions for Stop mode release:

— If you release stop mode using an internal or external interrupt, the current values in system and peripheral

control registers are unchanged.

— If you use an internal or external interrupt for stop mode release, you can also program the duration of the

oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before

entering stop mode.

— If you use an interrupt to release stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains

unchanged and the currently selected clock value is used.

The internal or external interrupt is serviced when the stop mode release occurs. Following the IRET from the

service routine, the instruction immediately following the one that initiated stop mode is executed.

NOTE

Do not use stop mode if you are using an external clock source because X_INinput must be cleared

internally to V_SSto reduce current leakage, and do not configure any pins to floating node in stop mode

to reduce power consumption.

8-5

RESET and POWER-DOWN

S3C821A/P821A

IDLE MODE

Idle mode is invoked by the instruction IDLE. In Idle mode, CPU operations are halted while some peripherals

remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but the

following peripherals, which remain active:

— Interrupt logic

— Basic timer

— Timer 0

— Timer 1 (Timer A and B)

— Watch timer

— LCD controller

— A/D converter

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered. External interface pins

are halted by high or low level, in the idle mode.

Idle Mode Release

You can release Idle mode in one of two ways:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents

of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the

hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a

reset is the only way you can release Idle mode.

2. Activate any enabled interrupt — internal or external. When you use an interrupt to release Idle mode, the

2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The

interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction

immediately following the one which initiated Idle mode is executed.

8-6

S3C821A/P821A

I/O PORTS

9

I/O PORTS

OVERVIEW

The S3C821A microcontroller has two nibble-programmable and four bit-programmable I/O ports, P0-P5. The

ports from P0 to P4 are 8-bit ports and port 5 is a 7-bit port. This gives a total of 47 I/O pins. Each port can be

flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or

reading port registers. No special I/O instructions are required.

Table 9-1 gives you a general overview of the S3C821A I/O port functions.

Table 9-1. S3C821A Port Configuration Overview

Port

Configuration Options

0

4-bit-programmable I/O port.

Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are

automatically disabled for output pins. Configurable as LCD segments/external interface

address lines.

1

2

4-bit-programmable I/O port.

Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are

automatically disabled for output pins. Configurable as LCD segment/external interface

address and data lines.

1-bit-programmable I/O port.

Pull-up resistors are software assignable, and automatically disabled for output pins. P2.0–

P2.3 can alternately be used as external interface lines. P2.4–P2.7 are configurable as

alternate functions or external interrupts at falling edge with noise filters.

3

4

1-bit-programmable I/O port.

Pull-up resistors are software assignable, and automatically disabled for output pins. P3.0–P3.3

can alternately be used as ADC. P3.7 is configurable as an alternate function.

1-bit-programmable I/O port.

Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are

automatically disabled for output pins. P4.0–P4.7 are configurable as external interrupts at a

selectable edge with noise filters.

1-bit-programmable I/O port.

5

Pull-up resistors are software assignable, and automatically disabled for output pins.

P5.0–P5.3 are configurable as alternate functions. When SCK and SI are used as input, these

pins have noise filters.

9-1

I/O PORTS

S3C821A/P821A

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all four S3C821A I/O port data registers. Data

registers for ports 0, 1, 2, 3, 4, and 5 have the general format shown in Figure 9-1.

Table 9-2. Port Data Register Summary

Register Name

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Mnemonic

Decimal

224

Hex

E0H

E1H

E2H

E3H

E4H

E5H

Location

R/W

P0

P1

P2

P3

P4

P5

Set 1, Bank 0

225

226

227

228

229

I/O Port Data Register Format (n = 0-5)

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pn.7

When n=5, P5.7 does not exist.

NOTE:

Figure 9-1. S3C821A I/O Port Data Register Format

9-2

S3C821A/P821A

PORT 0

I/O PORTS

Port 0 pins P0.0–P0.7 can be configured on a nibble basis for general data input or output. When configured as

outputs, the pins in each nibble may optionally be set to open-drain. You can alternately configure port 0 as

additional address lines (A8–A15) for the external peripheral interface. It is possible to configure the lower nibble

as external interface address lines A8–A11, and to use the upper nibble pins for general I/O.

To access port 0, you should write or read the port 0 data register, P0 (R224, E0H, Bank 0) in set 1. The port 0

data register can't be written, however, when port 0 bits are configured as address lines for the external interface:

writing has no effect and reading only loads P0 data register with the state of the pin.

PORT 0 CONTROL REGISTER

The port 0 control register, P0CON (R224, E0H, set 1, Bank 1), controls the direction of the I/O lines and allows

an optional selection of pull-up resistor in input mode, and that of open-drain, or push-pull in output modes. The

P0CON setting "1xxxB" for each nibble configures the pins as external interface lines. The bits 4-7 control the

upper nibble pins, P0.4–P0.7, and the bits 0-3 control the lower nibble pins, P0.0–P0.3.

In normal operating mode, a reset operation clears all P0CON register values to "0". If you want to configure an

external memory area, you can use a routine to set the P0CON value to "1xxx1xxxB". This setting correctly

configures the address lines A8–A11 (lower nibble) and A12–A15 (upper nibble).

I/O PORT 0 CONTROL REGISTER (P0CON)

R224, E0H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Upper nibble port configuration

7 (3) 6 (2) 5 (1) 4 (0)

Lower nibble port configuration

Port Mode Selection

0

1

0

1

0

1

x

0

1

x

0

1

x

Input mode

Input, pull-up mode

Output, push-pull mode

Output, open-drain mode

LCD segment (SEG23-SEG16)

External interface (A15-A8)

(‘x’ means don’t care.)

Figure 9-2. Port 0 Control Register (P0CON)

9-3

I/O PORTS

PORT 1

S3C821A/P821A

Port 1 is basically identical to port 0, except for its alternate use as multiplexed address/data lines for the external

interface. (Port 0 can alternately be configured as additional address lines A8–A15.)

Port 1 pins, P1.0–P1.7, can be configured on a nibble basis for general data input or output. When configured as

outputs, the pins in each nibble may optionally be set to open-drain. You can alternately configure port 0 as

additional address/data lines (AD0–AD7) for external peripheral interface.

To access port 1, you should write or read the port 1 data register, P1 (R225, E1H, Bank 0) in set 1. The port 1

data register cannot be written, however, when the port 1 bits are configured as address lines for external

interface: writing has no effect and reading only loads P1 data register with the state of the pin.

PORT 1 CONTROL REGISTER

The port 1 control register, P1CON (R226, E2H, set 1, Bank 1), controls the direction of the I/O lines and allows

an optional selection of pull-up resistor in input mode, and that of open-drain, or push-pull in output mode. The

P1CON setting "1xxxB" for each nibble configures the pins as external interface lines. The bits 4–7 control the

upper nibble pins, P1.4–P1.7, and the bits 0–3 control the lower nibble pins, P1.0–P1.3.

In normal operating mode a reset operation clears all P1CON register values to "0". If you want to configure an

external memory area, you can use a routine to set the P1CON value to "1xxx1xxxB". This setting correctly

configures the address/data lines AD0–AD7.

I/O PORT 1 CONTROL REGISTER (P1CON)

R226, E2H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Upper nibble port configuration

7 (3) 6 (2) 5 (1) 4 (0)

Lower nibble port configuration

Port Mode Selection

0

1

0

1

0

1

x

0

1

x

0

1

x

Input mode

Input, pull-up mode

Output, push-pull mode

Output, open-drain mode

LCD segment (SEG31 -SEG24)

External interface (AD7-AD0)

(“x” means don’t care.)

Figure 9-3. Port 1 Control Register (P1CON)

9-4

S3C821A/P821A

PORT 2

I/O PORTS

Port 2 is an 8-bit I/O port with individually configurable pins. It is accessed directly by writing or reading the port 2

data register, P2 (R226, E2H, Bank 0) in set 1. You can use port 2 for general I/O, or for the following alternative

functions:

— P2.0–P2.3 can be configured as multiplexed external interface bus control lines for AS (address strobe)

signals, DR (data read), DW (data write), and DM (data memory).

— P2.4–P2.7 can be configured, respectively, as T0CK (T0 clock input), T1CK (T1 clock input), TA, and TB

output.

The special functions that you can program using the port 2 high byte control register must also be enabled in the

associated peripheral. Also, when using port 2 pins for functions other than general I/O, you must still set the

corresponding port 2 control register value to configure each bit to input or output mode.

PORT 2 CONTROL REGISTERS

Two 8-bit control registers are used to configure port 2 pins: P2CONH (E4H, set 1, Bank 1) for pins P2.4–P2.7

and P2CONL (E5H, set 1, Bank 1) for pins P2.0–P2.3. Each byte contains four bit-pairs and each bit-pair

configures one port 2 pin. The P2CONH and the P2CONL registers also control the alternative functions

described above.

Port 2 High-Byte Control Register (P2CONH)

Four bit-pairs in the port 2 control register (P2CONH) configure the port 2 pins, P2.4–P2.7, to schmitt trigger

input, schmitt trigger input with pull-up resistor, or push-pull output mode.

Table 9-3. Port 2 Data Register Summary (High Nibbles)

P2CONH Bit-Pair

Bits 0 and 1

Corresponding Port 2 Pin

Alternate Pin Function

P2.4

P2.5

P2.6

P2.7

T0 output or capture input (T0CK)

T0 clock input (T1CK)

Clock output (TA)

Bits 2 and 3

Bits 4 and 5

Bits 6 and 7

Clock output (TB)

9-5

I/O PORTS

S3C821A/P821A

PORT 2 CONTROL REGISTER, HITGH BYTE (P2CONH)

R228, E4H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.4/T0CK

P2.5/T1CK

P2.6/TA

P2.7/TB

P2CONH Bit-Pair Pin Configuration Settings:

00

01

10

11

Schmitt trigger input mode (or T0CK/T1CK input for P2.4/P2.5)

Schmitt trigger input, pull-up mode (or T0CK/T1CK input for P2.4/P2.5)

Output, push-pull mode

Select alternative function for P2.6 and P2.7

P2.4 and P2.5 remain “0” state

Figure 9-4. Port 2 High-Byte Control Register (P2CONH)

Port 2 Low-Byte Control Register (P2CONL)

The low-byte port 2 pins, P2.0–P2.3, can be configured individually as schmitt trigger inputs, schmitt trigger input

with pull-up resistor, or as push-pull outputs. You can alternately configure these pins as multiplexed bus control

signal lines for external interface. To select the bus signal function, you must set the related bit-pairs to "11B".

Table 9-4. Port 2 Data Register Summary (Low Nibbles)

P2CONL Bit-Pair

Corresponding Port 2 Pin

Alternate Pin Function

Address strobe (AS)

Bits 0 and 1

P2.0

Bits 2 and 3

Bits 4 and 5

Bits 6 and 7

P2.1

P2.2

P2.3

Data read (DR)

Data write (DW)

Data memory (DM)

9-6

S3C821A/P821A

I/O PORTS

PORT 2 CONTROL REGISTER, LOW BYTE (P2CONL)

R229, E5H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/

AS

P2.1/

DR

P2.2/

DW

P2.3/

DM

P2CONL Bit-Pair Pin Configuration Settings:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Output, push-pull mode

External memory interface line

Figure 9-5. Port 2 Low-Byte Control Register (P2CONL)

PORT 2 INTERRUPT REGISTER (P2INT)

R230, E6H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.4/INT0

P2.5/INT1

P2.6/INT2

P2.7/INT3

P2INT Bit-Pair Pin Configuration Settings:

Bits 0, 2, 4, 6

Interrupt control settings (n = 4, 5, 6, 7)

0 = Disable interrupt on P2.n

1 = Enable interrupt at falling edge on P2.n

Bits 1, 3, 5, 7

Interrupt request pending bits

0 = No interrupt request pending

0 = Clear pending bit (when write)

1 = Interrupt request is pending

Figure 9-6. Port 2 Interrupt Register (P2INT)

9-7

I/O PORTS

PORT 3

S3C821A/P821A

Port 3 can serve as a general-purpose 8-bit I/O port, or support alternative functions (T0CAP input or T0PWM/T0

output for P3.7 and A/D converter inputs for P3.0–P3.3). Port 3 is accessed directly by writing or reading the Port

3 data register, P3 (R227, E3H, Bank 0) in set 1.

— P3.0–P3.3 can be configured, respectively, as ADC0–ADC3 input.

— P3.7 can be configured as T0CAP input, T0PWM, or T0 output.

PORT 3 CONTROL REGISTERS

The direction of each port pin is configured by bit-pair settings in two control registers: P3CONH (high byte, E6H,

set 1, Bank 1) and P3CONL (low byte, E7H, set 1, Bank 1). P3CONH controls the pins, P3.4–P3.7, and P3CONL

controls the pins, P3.0–P3.3. Both registers are read-write addressable using 1-bit or 8-bit instructions.

There are two input modes: schmitt trigger input or schmitt trigger input with pull-up resistor.

A reset clears all P3CONH and P3CONL bits to logic zero. This configures Port 3 pins to schmitt trigger input.

PORT 3 CONTROL REGISTER, HITGH BYTE (P3CONH)

R230, E6H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 3.4

Pin 3.5

Pin 3.6

Pin 3.7/T0/

T0PWM/T0CAP

P3CONH Bit-Pair Pin Configuration Settings for Pins 3.4-P3.6:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Output, push-pull mode

Output, high-impedance

P3CONH Bit-Pair Pin Configuration Settings for Pin 3.7:

00

01

10

11

Schmitt trigger input mode (or T0CAP input for P3.7)

Schmitt trigger input, pull-up mode (or T0CAP input for P3.7)

Output, push-pull mode

Select alternate function (T0PWM/T0)

Figure 9-7. Port 3 High-Byte Control Register (P3CONH)

9-8

S3C821A/P821A

I/O PORTS

PORT 3 CONTROL REGISTER, LOW BYTE (P3CONL)

R231, E7H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 3.0/ADC0

Pin 3.1/ADC1

Pin 3.2/ADC2

Pin 3.3/ADC3

P3CONL Bit-Pair Pin Configuration Settings:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger iput, pull-up mode

Output, push-pull mode

A/D converter input mode (schmitt trigger input off)

Figure 9-8. Port 3 Low-Byte Control Register (P3CONL)

9-9

I/O PORTS

PORT 4

S3C821A/P821A

Port 4 pins P4.0–P4.7 can be configured on a bit-pair setting basis for general data input or output. When

configured as outputs, the pins may optionally be set to open-drain. All inputs are schmitt triggered. Port 4 is

accessed directly by writing or reading the Port 4 data register, P4 (R228, E4H, Bank 0) in set 1.

PORT 4 CONTROL REGISTERS

The direction of each port pin is configured by bit-pair settings in two control registers: P4CONH (high byte, E8H,

set 1, Bank 1) and P4CONL (low byte, E9H, set 1, Bank 1). P4CONH controls the pins, P4.4–P4.7, and P4CONL

controls the pins, P4.0–P4.3. Both registers are read-write addressable using 1-bit or 8-bit instructions.

There are two input modes: schmitt trigger input or schmitt trigger input with pull-up resistor.

A reset clears all P4CONH and P4CONL bits to logic zero. This configures Port 4 pins to schmitt trigger input.

PORT 4 CONTROL REGISTER, HITGH BYTE (P4CONH)

R232, E8H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 4.4/INT8

Pin 4.5/INT9

Pin 4.6/INT10

Pin 4.7/INT11

P4CONH Bit-Pair Pin Configuration Settings:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

Figure 9-9. Port 4 High-Byte Control Register (P4CONH)

9-10

S3C821A/P821A

I/O PORTS

PORT 4 CONTROL REGISTER, LOW BYTE (P4CONL)

R233, E9H, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 4.0/INT4

Pin 4.1/INT5

Pin 4.2/INT6

Pin 4.3/INT7

P4CONL Bit-Pair Pin Configuration Settings:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Push-pull output mode

Open-drain output mode

Figure 9-10. Port 4 Low-Byte Control Register (P4CONL)

Port 4 Interrupt Enable and Pending Registers (P4INT, P4PND)

To process external interrupts, two additional control registers are provided: the Port 4 interrupt enable register,

P4INT (R231, E7H, set 1, Bank 0) and the Port 4 interrupt pending register, P4PND (R232, E8H, set 1, Bank 0).

By setting bits in the Port 4 interrupt enable register P4INT to "1", you can use specific Port 4 pins to generate

interrupt requests when specific signal edges are detected. The interrupt names INT4–INT11 correspond to the

pins, P4.0–P4.7. After a reset, P4INT bits are cleared to "00H", disabling all external interrupts.

The Port 4 interrupt pending register P4PND lets you check for interrupt pending conditions and clear the pending

condition when the interrupt request has been serviced. Incoming interrupt requests are detected by polling the

P4PND bit values.

When the interrupt enable bit of any Port 4 pin is set to "1", a rising or falling signal edge at that pin generates an

interrupt request. (Remember that the Port 4 interrupt pins must first be configured by setting them to input mode

in the corresponding P4CONH or P4CONL register.)

The corresponding P4PND bit is then set to "1" and the IRQ pulse goes high to signal the CPU that an interrupt

request is waiting.

When a Port 4 interrupt request has been serviced, the application program must clear the related interrupt

pending register bit by writing a "0" to the pending bit in the P4PND register. Please note that writing a "1" value

has no effect.

Port 4 Interrupt Edge Selection Register (P4EDGE)

P4 interrupt can be generated in falling edge or rising edge, depending on the value of the P4 interrupt edge

selection register (R233, E9H, set 1, Bank 0), P4EDGE. If the value is set to "1", P4 interrupt is generated in

rising edge. If the value is set to "0", P4 interrupt is generated in falling edge.

9-11

I/O PORTS

S3C821A/P821A

PORT 4 INTERRUPT CONTROL REGISTER (P4INT)

R231, E7H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 4.0/INT4

Pin 4.1/INT5

Pin 4.2/INT6

Pin 4.3/INT7

Pin 4.4/INT8

Pin 4.5/INT9

Pin 4.6/INT10

Pin 4.7/INT11

Interrupt Control Settings:

0 = Disable interrupt

1 = Enable interrupt

Figure 9-11. Port 4 Interrupt Control Register (P4INT)

PORT 4 INTERRUPT PENDING REGISTER (P4PND)

R232, E8H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 4.0/INT4

Pin 4.1/INT5

Pin 4.2/INT6

Pin 4.3/INT7

Pin 4.4/INT8

Pin 4.5/INT9

Pin 4.6/INT10

Pin 4.7/INT11

Interrupt Request Pending Bits:

0 = No interrupt request pending

0 = Clear pending bit (when write)

1 = Interrupt request pending

Figure 9-12. Port 4 Interrupt Pending Register (P4PND)

9-12

S3C821A/P821A

I/O PORTS

PORT 4 INTERRUPT EDGE SELECTION REGISTER (P4EDGE)

R233, E9H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 4.0/INT4

Pin 4.1/INT5

Pin 4.2/INT6

Pin 4.3/INT7

Pin 4.4/INT8

Pin 4.5/INT9

Pin 4.6/INT10

Pin 4.7/INT11

Interrupt Control Settings:

0 = Falling edge interrupt

1 = Rising edge interrupt

Figure 9-13. Port 4 Edge Selection Register (P4EDGE)

9-13

I/O PORTS

PORT 5

S3C821A/P821A

Port 5 is a 7-bit I/O port with individually configurable pins. It is accessed directly by writing or reading the port 5

data register, P5 (R229, E5H, Bank 0) in set 1. You can use port 5 for general I/O, or for the following alternative

functions:

— P5.0–P5.3 can be configured, respectively, as SCK, output high impedance, SO, and BUZ output.

The special functions that you can program using the port 5 control register must also be enabled in the

associated peripheral. Also, when using port 5 pins for functions other than general I/O, you must still set the

corresponding port 5 control register value to configure each bit to input or output mode.

PORT 5 CONTROL REGISTERS

Two 8-bit control registers are used to configure port 5 pins: P5CONH (high byte, EAH, Set 1, Bank 1) for the

pins P5.4–P5.6 and P5CONL (EBH, set 1, Bank 1) for the pins P5.0–P5.3. Each byte contains four or three bit-

pairs and each bit-pair configures one of port 5 pins. The P5CONL register also controls the alternative functions

described below.

Port 5 High-Byte Control Register (P5CONH)

Three bit-pairs in the port 5 control register (P5CONH) configure the port 5 pins, P5.4–P5.6 to schmitt trigger

input, schmitt trigger input with pull-up resistor, or push-pull output mode.

Port 5 Low-Byte Control Register (P5CONL)

The low-byte port 5 pins, P5.0–P5.3, can be configured individually as schmitt trigger inputs, schmitt trigger input

with pull-up resistor, or as push-pull outputs. You can alternately configure these pins. To select the alternative

functions, you must set the related bit-pairs — SCK output, output high impedance, SO, and BUZ output — to

"11B".

Table 9-5. Port 5 Data Register Summary (Low Nibbles)

P5CONL Bit-Pair

Bits 0 and 1

Bits 2 and 3

Bits 4 and 5

Bits 6 and 7

Corresponding Port 5 Pin

Alternate Pin Function

P5.0

P5.1

P5.2

P5.3

SCK output

High impedance

SO

BUZ

9-14

S3C821A/P821A

I/O PORTS

PORT 5 CONTROL REGISTER, HITGH BYTE (P5CONH)

R234, EAH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 5.4

Pin 5.5

Pin 5.6

Not used for the S3C821A

P5CONH Bit-Pair Pin Configuration Settings:

00

01

10

11

Schmitt trigger input mode

Schmitt trigger input, pull-up mode

Output, push-pull mode

Output, high impedance

Figure 9-14. Port 5 High-Byte Control Register (P5CONH)

PORT 5 CONTROL REGISTER, LOW BYTE (P5CONL)

R235, EBH, Set 1, Bank 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pin 5.0/SCK

Pin 5.1/SI

Pin 5.2/SO

Pin 5.3/BUZ

P5CONL Bit-Pair Pin Configuration Settings:

00

Schmitt trigger input mode

(SI, SCK inputs for P5.1 and P5.0, respectively)

Schmitt trigger input, pull-up mode

Output, push-pull mode

Select alternative function (SCK output, output high-

impedance, SO, BUZ for P5.0-P5.3)

01

10

11

Figure 9-15. Port 5 Low-Byte Control Register (P5CONL)

9-15

S3C821A/P821A

BASIC TIMER and TIMER 0

10 BASIC TIMER and TIMER 0

OVERVIEW

S3C821A has two default timers: an 8-bit basic timer and an 8-bit general-purpose timer/counter. The 8-bit

timer/counter is called timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or

— To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer

— 8-bit basic timer counter, BTCNT (set 1, Bank 0, FDH, read-only)

— Basic timer control register, BTCON (set 1, D3H, read/write)

Timer 0

Timer 0 offers three operating modes, which you can select by setting T0CON appropriately:

— Interval timer mode

— Capture input mode with a rising or falling edge trigger at the P3.7 pin

— PWM mode

Timer 0 has the following functional components:

— Clock frequency divider (fxx divided by 4096, 256, or 8 ) with multiplexer

— External clock input pin (P2.4, T0CK)

— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)

— I/O pins for capture input (P3.7) or match output

— Timer 0 overflow interrupt (IRQ0, vector FAH) and match/capture interrupt (IRQ0, vector FCH) generation

— Timer 0 control register, T0CON (set 1, D2H, read/write)

10-1

BASIC TIMER and TIMER 0

S3C821A/P821A

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer

counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,

address D3H, and is read/write addressable using Register addressing mode.

A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of

fx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register

control bits BTCON.7–BTCON.4.

The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during the normal

operation by writing a "1" to BTCON.1. To clear the frequency dividers for both the basic timer input clock and

the timer 0 clock (unless timer 0 uses an external clock source), you should write a "1" to BTCON.0.

BASIC TIMER CONTROL REGISTER (BTCON)

D3H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Divider clear bit for basic

timer and timer 0:

0 = No effect

Watchdog function enable bits:

1010B = Disable watchdog timer

Others = Enable watchdog timer

1 = Clear both dividers

Basic timer counter clear bit:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00 = fxx/4096

01 = fxx/1024

10 = fxx/128

11 = fxx/16

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

S3C821A/P821A

BASIC TIMER and TIMER 0

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to

any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to

"00H", automatically enabling the watchdog timer function. A reset also selects fx/4096 as the BT clock.

Reset occurs whenever a basic timer counter overflows. During the normal operation, the application program

must prevent the overflow, which causes a reset operation, from occurring. To do this, the BTCNT value must be

cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation

will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal

operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always

broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop

mode has been released by an external interrupt.

In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT

value then starts increasing at the rate of fx/4096 (for reset), or at the rate of the preset clock source (for an

internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the

stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume the normal

operation.

In summary, the following events occur when stop mode is released:

1. During the stop mode, a power-on reset, or an external interrupt occurs to trigger the stop mode release and

oscillation starts.

2. If a power-on reset occurred, the basic timer counter would increase at the rate of fx/4096. If an internal or an

external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock

source.

3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.

4. When a BTCNT.3 overflow occurs, the normal CPU operation resumes.

TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt

— Clear timer 0 match/capture interrupt pending conditions

10-3

BASIC TIMER and TIMER 0

S3C821A/P821A

T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.

A reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency

of fx/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during the normal

operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) has interrupt level IRQ0 and the vector address FAH. When a timer 0

overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer 0 match/capture interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a

match/capture interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a

timer 0 match or capture interrupt is pending. After the interrupt request is serviced, the pending condition must

be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.

TIMER 0 CONTROL REGISTER (T0CON)

D2H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

00 = fxx/4096

Timer 0 match/capture

interrupt pending bit:

01 = fxx/256

10 = fxx/8

11 = External clock (P2.4/T0CK)

0 = No interrupt pending

0 = Clear pending bit (write)

1 = Interrupt is pending

Timer 0 match/capture interrupt

enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 0 operating mode selection bits:

00 = Interval mode

01 = Capture mode (capture on rising edge,

counter running, OVF can occur)

10 = Capture mode (capture on falling

edge, counter running, OVF can occur)

11 = PWM mode (OVF interrupt can occur)

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Figure 10-2. Timer 0 Control Register (T0CON)

10-4

S3C821A/P821A

BASIC TIMER and TIMER 0

TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)

The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/

capture interrupt (T0INT). T0OVF is assigned the interrupt level IRQ0, vector FAH. T0INT also belongs to the

interrupt level IRQ0, but is assigned a separate vector address, FCH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware after it is serviced. The T0INT

pending condition must, however, be cleared by the application’s interrupt service routine by writing a "0" to the

T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)

and clears the counter.

If, for example, you write the value "10H" to T0DATA and "0AH" to T0CON, the counter will increment until it

reaches "10H". At this point, the T0 interrupt request is generated, the counter value is reset, and counting

resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).

IRQ0 (T0INT)

PENDING

(T0CON.0)

INTERRUPT

ENABLE/DISABLE

(T0CON.1)

R (Clear)

CLK

COUNTER

Match

COMPARATOR

CTL

P3.7/T0

BUFFER REGISTER

T0CON.5

T0CON.4

Match Signal

T0CON.3

DATA REGISTER

Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode

10-5

BASIC TIMER and TIMER 0

S3C821A/P821A

Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the

value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.

Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data

value is less than or equal to ( £ ) the counter value and then the pulse is held to High level for as long as the

data value is greater than ( > ) the counter value. The time period is equal to t_CLK´ 256 (see Figure 10-4).

IRQ0

(T0INT)

PND

T0CON.0

INTERRUPT

ENABLE/DISABLE

(T0CON.1)

CLK

COUNTER

IRQ0 (T0OVF)

High level when

data > counter;

Low level when

P3.7/

T0PWM

COMPARATOR

CTL

Match

data

counter

£

T0CON.5

T0CON.4

BUFFER REGISTER

DATA REGISTER

T0CON.3

T0OVF

Interrupts are usually not used when timer 0 is configured to operate in PWM mode.

NOTE:

Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode

10-6

S3C821A/P821A

Capture Mode

BASIC TIMER and TIMER 0

In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter

value into the T0 data register. You can select rising or falling edge to trigger this operation.

Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by

setting the values of the timer 0 capture input selection bits in the port 3 control register, P3CONH.7–6, (set 1,

bank 1, E6H). When P3CONH.7–.6 is “00” or "01", the T0CAP input is selected.

Both kinds of timer 0 interrupts can be used in capture mode. The timer 0 overflow interrupt is generated

whenever a counter overflow occurs. The timer 0 match/capture interrupt is generated whenever the counter

value is loaded into the T0 data register.

By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,

you can calculate the pulse width (duration) of the signal being input from the T0CAP pin (see Figure 10-5).

T0CON.2

CLK

COUNTER

IRQ0 (T0OVF)

IRQ0 (T0INT)

PENDING

(T0CON.0)

P3.7/T0CAP

INTERRUPT ENABLE /

DISABLE (T0CON.1)

T0CON.5

T0CON.4

DATA REGISTER

Figure 10-5. Simplified Timer 0 Function Diagram: Capture Mode

10-7

BASIC TIMER and TIMER 0

S3C821A/P821A

(1)

or

Bit 1

RESET

STOP

Bits 3, 2

Basic Timer Control Register

(Write '1010xxxxB' to disable.)

Data Bus

Clear

1/4096

1/1024

(X or XT

fxx

)

in

8-Bit Basic Counter

(Read-Only)

RESET

DIV

R

MUX

Bits 7, 6

MUX

OVF

1/128

1/16

Bit 2

T0OVF

OVF

Bit 0

Data Bus

Bit 3

1/4096

R

Clear

1/256

1/8

DIV

8-Bit Up-Counter

(Read-Only)

R

(2)

Match

T0CK

P2.4

Bit 1

T0CON.0

Bit 0

8-Bit Comparator

T0INT

T0CAP

P3.7

T0PWM

P3.7

(2)

Bits 5, 4

Match Signal

Timer 0 Buffer Reg

T0CLR

T0OVF

Bits 5, 4

Timer 0 Data Register

(Read/Write)

Basic Timer Control Register

Timer 0 Control Register

Data Bus

NOTES:

1. In a power-on reset operation, the CPU is idle during the required oscillation

stabilization interval (until bit 4 of the basic timer counter overflows).

2. It is available only in interval mode.

Figure 10-6. Basic Timer and Timer 0 Block Diagram

10-8

S3C821A/P821A

BASIC TIMER and TIMER 0

+

PROGRAMMING TIP — Configuring the Basic Timer

This example shows how to configure the basic timer to sample specifications:

ORG

0100H

RESET

DI

LD

CLR

; Disable all interrupts

; Disable the watchdog timer

; Non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte ¬ "0"

; Stack area starts at 0FFH

BTCON,#0ABH

CLKCON,#18H

SYM

SPL

•

SRP

#0C0H

; Set register pointer ¬ 0C0H

EI

•

; Enable interrupts

•

MAIN

LD

BTCON,#53H

; Enable the watchdog timer

; Basic timer clock: fxx/4096

; Clear basic timer counter

NOP

•

JP

T,MAIN

•

10-9

BASIC TIMER and TIMER 0

S3C821A/P821A

+

PROGRAMMING TIP — Programming Timer 0

This sample program sets timer 0 to interval timer mode and the frequency of the oscillator clock, determining

the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:

— Timer 0 is used in interval mode. The timer interval is set to 4 milliseconds

— Oscillation frequency is 6 MHz

— General register 64H (page 0) ¬ 60H (page 0) + 62H (page 0) + 63H (page 0) + 64H (page 0) is executed

after a timer 0 interrupt

ORG

0FAH

; Timer 0 overflow interrupt

VECTOR

ORG

T0OVER

0FCH

; Timer 0 match/capture interrupt

VECTOR

ORG

T0INT

0100H

RESET

DI

; Disable all interrupts

LD

CLR

BTCON,#0ABH

CLKCON,#18H

SYM

; Disable the watchdog timer

; Select non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte ¬ "0"

; Stack area starts at 0FFH

SPL

•

LD

T0CON,#4AH

T0DATA,#5DH

; Write "01001010B"

; Input clock is fxx/256

; Interval timer mode

; Enable the timer 0 interrupt

; Disable the timer 0 overflow interrupt

; Set timer interval to 4 milliseconds

; Clear pending bit

LD

; (6 MHz/256) + (93 + 1) = 0.25 kHz (4 ms)

; RP ¬ 60H

; Destination ¬ 0, Source ¬ 0

; Register 60H (page 0) = 00H

; Bit reset (61.2H)

SRP

CLR

BITR

#60H

PP

R0

R1.2

SRP

#0C0H

; Set register pointer ¬ 0C0H

EI

•

; Enable interrupts

•

(Continued on next page)

10-10

S3C821A/P821A

BASIC TIMER and TIMER 0

+

PROGRAMMING TIP — Programming Timer 0 (Continued)

T0INT

PUSH

SRP0

LD

RP0

PP

#60H

PP,#00H

R0

; Save RP0 to stack

; Save PP to stack

; RP0 ¬ 60H

; Destination ¬ 0, Source ¬

; R0 ¬ R0 + 1

0

INC

ADD

ADC

R2,R0

R3,R2

R4,R3

; R2 ¬ R2 + R0

; R3 ¬ R3 + R2 + Carry

; R4 ¬ R4 + R3 + Carry

CP

R0,#32H

JR

BITS

; 50 ´ 4 = 200 ms

ULT,NO_200MS_SET

R1.2

; Bit setting (61.2H)

NO_200MS_SET:

LD

T0CON,#4AH

; Clear pending bit

POP

PP

RP0

; Restore page pointer value

; Restore register pointer 0 value

T0OVER

IRET

; Return from interrupt service routine

10-11

S3C821A/P821A

TIMER 1

11 TIMER 1

ONE 16-BIT TIMER MODE (TIMER 1)

The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. When TACON.7 is set to "1", it is in one

16-bit timer mode. When TACON.7 is set to "0", the timer 1 is used as two 8-bit timers.

— One 16-bit timer mode (Timer 1)

— Two 8-bit timers mode (Timer A and B)

OVERVIEW

The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 includes interval timer mode using appropriate

TACON setting.

Timer 1 has the following functional components:

— Clock frequency divider (fxx divided by 1024, 512, 8, or 1 and T1CK: External clock) with multiplexer

— 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)

— Timer 1 match interrupt (IRQ1, vector F6H) generation

— Timer 1 control register, TACON (set 1, bank 0,F3H, read/write)

FUNCTION DESCRIPTION

Interval Timer Function

The timer 1 module can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to the interrupt

level IRQ1, and is assigned a separate vector address, F6H.

The T1INT pending condition should be cleared by software after IRQ1 is serviced. The T1INT pending bit must

be cleared by the application sub-routine by writing a "0" to the TACON.0 pending bit.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to the

T1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt

(T1INT, vector F6H) and clears the counter.

If, for example, you write the value 10H and 32H to TADATA and TBDATA, respectively, and 8EH to TACON,

the counter will increment until it reaches 3210H. At this point, the T1 interrupt request is generated, the counter

value is reset, and counting resumes.

11-1

TIMER 1

S3C821A/P821A

Timer 1 Control Register (TACON)

You use the timer 1 control register, TACON, to

— Enable the timer 1 operating (interval timer)

— Select the timer 1 input clock frequency

— Clear the timer 1 counter, TACNT and TBCNT

— Enable the timer 1 interrupt

— Clear timer 1 interrupt pending conditions

TACON is located in set 1, bank 0, at address F3H, and is read/write addressable using register addressing

mode.

A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency

of fxx/1024, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during the normal

operation by writing a "1" to TACON.3.

To enable the timer 1 interrupt (IRQ1, vector F6H), you must write TACON.7, TACON.2, and TACON.1 to "1". To

generate the exact time interval, you should set TACON.3 and TACON.0 to “10B”, which clear counter and

interrupt pending bit. When the T1INT sub-routine is serviced, the pending condition must be cleared by software

by writing a "0" to the timer 1 interrupt pending bit, TACON.0.

TIMER 1 CONTROL REGISTER (TACON)

F3H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 1 interrupt pending bit:

0 = No interrupt pending

0 = Clear pending bit (when write)

1 = Interrupt is pending (when read)

1 = No effect (when write)

Timer 1 operating mode selection bit :

0 = Two 8-bit timers mode (Timer A/B)

1 = One 16-bit timer mode (Timer 1)

Timer 1 clock selection bits:

000 = fxx/1024

001 = fxx/512

Timer 1 interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

010 = fxx/8

011 = fxx

1xx = T1CK (external clock)

(“x” means don’t care.)

Timer 1 counter run enable bit:

0 = Disable counter running

1 = Enable counter running

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer A counter (when write)

Figure 11-1. Timer 1 Control Register (TACON)

11-2

S3C821A/P821A

TIMER 1

BLOCK DIAGRAM

TACON.6-.4

TACON.3

Clear

1/1024

1/512

1/8

TBCNT

TACNT

TA

Match

MUX

Comparator

P2.6

1/1

T1CK

P2.5

T1INT

TBDATA

TADATA

TACON.1

When TACON.7 is “1”, one 16-bit timer 1.

NOTE:

Figure 11-2. Timer 1 Functional Block Diagram

11-3

TIMER 1

S3C821A/P821A

TWO 8-BIT TIMERS MODE (TIMER A and B)

OVERVIEW

The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B support interval timer mode using

appropriate TACON and TBCON setting, respectively.

Timer A and B have the following functional components:

— Clock frequency divider with multiplexer

– fxx divided by 1024, 512, 8, or 1 and T1CK (External clock) for timer A

– fxx divided by 1024, 512, 8, or 1 for timer B

— 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA)

— Timer A match interrupt (IRQ1, vector F6H) generation

— Timer A control register, TACON (set 1, bank 0, F3H, read/write)

— Timer B match interrupt (IRQ1, vector F4H) generation

— Timer B control register, TBCON (set 1, bank 0, F2H, read/write)

FUNCTION DESCRIPTION

Interval Timer Function

The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match

interrupt (TBINT). TAINT belongs to the interrupt level IRQ1, and is assigned a separate vector address, F6H.

TBINT belongs to the interrupt level IRQ1 and is assigned a separate vector address, F4H.

The TAINT and TBINT pending condition should be cleared by software after they are serviced.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to

the TA or TB reference data registers, TADATA or TBDATA. The match signal generates corresponding match

interrupt (TAINT, vector F6H; TBINT, vector F4H) and clears the counter.

If, for example, you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will

increment until it reaches 10H. At this point, the TB interrupt request is generated, the counter value is reset, and

counting resumes.

Timer A and B Control Register (TACON, TBCON)

You use the timer A and B control register, TACON and TBCON, to

— Enable the timer A and B operating (interval timer)

— Select the timer A and B input clock frequency

— Clear the timer A and B counter, TACNT and TBCNT

— Enable the timer A and B interrupt

— Clear timer A and B interrupt pending conditions

11-4

S3C821A/P821A

TIMER 1

TACON and TBCON are located in set 1, bank 0, at address F3H and F2H, and is read/write addressable using

register addressing mode.

A reset clears TACON and TBCON to "00H". This sets timer A and B to disable interval timer mode, selects an

input clock frequency of fxx/1024, and disables timer A and B interrupt. You can clear the timer A and B counter

at any time during normal operation by writing a "1" to TACON.3 and TBCON.3.

To enable the timer A and B interrupt (IRQ1, vector F6H, F4H), you must write TACON.7 to "0", TACON.2

(TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should set TACON.3

(TBCON.3) and TACON.0 (TBCON.0) to “10B”, which clear counter and interrupt pending bit, respectively. When

the TAINT or TBINT sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to

the timer A or B interrupt pending bits, TACON.0 or TBCON.0.

TIMER A CONTROL REGISTER (TACON)

F3H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer A interrupt pending bit:

0 = No interrupt pending

0 = Clear pending bit (when write)

1 = Interrupt is pending (when read)

1 = No effect (when write)

Timer 1 operating mode selection bit :

0 = Two 8-bit timers mode (Timer A/B)

1 = One 16-bit timer mode (Timer 1)

Timer A clock selection bits:

000 = fxx/1024

001 = fxx/512

Timer A interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

010 = fxx/8

011 = fxx

1xx = T1CK (external clock)

(“x” means don’t care.)

Timer A counter run enable bit:

0 = Disable counter running

1 = Enable counter running

Timer A counter clear bit:

0 = No effect

1 = Clear the timer A counter (when write)

Figure 11-3. Timer A Control Register (TACON)

11-5

TIMER 1

S3C821A/P821A

TIMER B CONTROL REGISTER (TBCON)

F2H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer B interrupt pending bit:

0 = No interrupt pending

Not used for the S3C821A.

0 = Clear pending bit (when write)

1 = Interrupt is pending (when read)

1 = No effect (when write)

Timer B clock selection

bits:

00 = fxx/1024

01 = fxx/512

10 = fxx/8

Timer B interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

11 = fxx

Timer B counter run enable bit:

0 = Disable counter running

1 = Enable counter running

Timer B counter clear bit:

0 = No effect

1 = Clear the timer A counter (when write)

Figure 11-4. Timer B Control Register (TBCON)

11-6

S3C821A/P821A

TIMER 1

TACON.6-.4

TACON.3

Clear

1/1024

TACNT

Comparator

TADATA

R

1/512

1/8

Match

TA

MUX

P2.6

1/1

T1CK

P2.5

TACON.1

IRQ1

TBCON.1

1/1024

1/512

1/8

TBDATA

Comparator

TBCNT

TB

MUX

Match

P2.7

1/1

R

Clear

TBCON.3

TBCON.5-.4

When TACON.7 is “0”, two 8-bit timer A/B.

NOTE:

Figure 11-5. Timer A and B Function Block Diagram

11-7

S3C821A/P821A

WATCH TIMER

12 WATCH TIMER

OVERVIEW

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock.

After the watch timer starts and elapses a time, the watch timer interrupt is automatically set to "1", and interrupt

requests commence in 3.91 ms or 0.5 second.

The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to the BUZ output. By setting

WTCON.3 and WTCON.0 to "11b", the watch timer will function in high-speed mode, generating an interrupt

every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. The watch timer

supplies the clock frequency for the LCD controller (f_LCD). Therefore, if the watch timer is disabled, the LCD

controller does not operate.

— Real-time and Watch-time measurement

— Using a main system or subsystem clock source

— Clock source generation for LCD controller

— Buzzer output frequency generator

— Timing tests in high-speed mode

12-1

WATCH TIMER

S3C821A/P821A

WATCH TIMER CONTROL REGISTER (WTCON: R/W)

FBH

WTCON.7 WTCON.6 WTCON.5 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0

RESET

"0"

Table 12-1. Watch Timer Control Register (WTCON): 8-bit R/W

Bit Name

Values

Function

Disable buzzer (BUZ) signal output

Address

FBH,

WTCON.7

0

1

0

1

Enable buzzer (BUZ) signal output

Disable watch timer (clear frequency dividing circuits)

Enable watch timer

Bank 0

WTCON.6

WTCON.5–.4

0

1

0

1

0

1

0.5 kHz buzzer (BUZ) signal output

1 kHz buzzer (BUZ) signal output

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

fw/2¹⁴(0.5 sec) interval

WTCON.3

WTCON.2

WTCON.1

0

1

0

1

0

1

0

1

fw/2⁷(3.91 ms) interval

Main system clock divided by 2⁷(fx/128)

Sub system clock (fxt)

No interrupt pending

Clear pending bit (when write)

Interrupt is pending

WTCON.0

Disable interrupt

Enable interrupt

12-2

S3C821A/P821A

WATCH TIMER

WATCH TIMER CIRCUIT DIAGRAM

WTCON.5-.4

WTCON.7

BUZ

P5.3

MUX

WTCON.2

0.5 kHz

1 kHz

2 kHz

4 kHz

7

fxt

M

fw/2

Frequency

Dividing

Circuit

M

U

X

fw

IRQ4

U

14

fx/128

32.768 kHz

(note)

X

fx : Main system clock

fxt: Sub system clock

fw: Watch timer clock

WTCON.6

WTCON.3

f

: LCD clock

LCD

fxx: Selected clock for peripheral hardware

When the fxt (subsystem clock) is selected as watch timer clock.

NOTE:

Figure 12-1. Watch Timer Circuit Diagram

12-3

S3C821A/P821A

LCD CONTROLLER/DRIVER

13 LCD CONTROLLER/DRIVER

OVERVIEW

The S3C821A microcontroller can directly drive an up-to-224-dot (28 segments x 8 commons) LCD panel. Its

LCD block has the following components:

— LCD controller/driver

— Display RAM for storing display data

— 4 common/segment output pins (COM4/SEG0–COM7/SEG3)

— 28 segment output pins (SEG4–SEG31)

— 4 common output pins (COM0–COM3)

— Internal resistor circuit for LCD bias

— V_LC1pin for controlling the driver and bias voltage

The LCD control register, LCON, is used to turn the LCD display on and off, switch the current to the dividing

resistors for the LCD display, and frame frequency. Data written to the LCD display RAM can be automatically

transferred to the segment signal pins without any program control.

When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even in the main clock

stop or idle mode.

VLC1

1

COM0–COM3

LCD

CONTROLLER /

DRIVER

4

COM4–COM7/

SEG0–SEG3

8

4

SEG4–SEG31

28

Figure 13-1. LCD Function Diagram

13-1

LCD CONTROLLER/DRIVER

LCD CIRCUIT DIAGRAM

S3C821A/P821A

SEG31

SEG4

DISPLAY

RAM

(Page 4)

SELECTOR

32

fLCD

COM7/SEG3

COM6/SEG2

COM5/SEG1

COM4/SEG0

COM

CONTROL

or

TIMING

CONTROLLER

SELECTOR

COM3

COM2

COM1

COM0

COM

CONTROL

LCD

VOLTAGE

CONTROL

VCL1

LCON

Figure 13-2. LCD Circuit Diagram

13-2

S3C821A/P821A

LCD CONTROLLER/DRIVER

LCD RAM ADDRESS AREA

RAM addresses of page 4 are used as LCD data memory. These locations can be addressed by 1-bit or 8-bit

instructions. If the bit value of a display segment is "1", the LCD display is turned on. If the bit value is "0", the

display is turned off.

Display RAM data are sent out through the segment pins, SEG0–SEG31, using the direct memory access (DMA)

method that is synchronized with the f_LCDsignal. RAM addresses in this location that are not used for LCD

display can be allocated to general-purpose use.

.......

COM

Bit

SEG0

00H

SEG1

01H

SEG2

02H

SEG3

03H

SEG4

04H

SEG30

SEG31

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

.0

.1

.2

.3

.4

.5

.6

.7

.......

30H

31H

Figure 13-3. LCD Display Data RAM Organization

13-3

LCD CONTROLLER/DRIVER

S3C821A/P821A

LCD CONTROL REGISTER (LCON)

The LCD control register (LCON) is used to turn the LCD display on and off, LCD frame frequency, and control

the flow of the current to the dividing resistors in the LCD circuit. After a RESET, all LCON values are cleared to

"0". This turns the LCD display off and stops the flow of the current to the dividing resistors.

LCD CONTROL REGISTER (LCON)

FAH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

LCD clock select bits:

Not used for the S3C821A.

6

00 = fw/2

01 = fw/2

10 = fw/2

5

4

3

11 = fw/2

LCD duty and bias selection bits:

00 = Display off, P-Tr off

01 = Normal display (Using VLC1 with

external voltage), P-Tr off

LCD duty and bias selection bits:

00 = 1/3 duty, 1/3 bias; COM0-2/SEG0-31

01 = 1/4 duty, 1/3 bias; COM0-3/SEG0-31

10 = 1/8 duty, 1/4 bias; COM0-7/SEG4-31

11 = 1/8 duty, 1/5 bias; COM0-7/SEG4-31

10 = All dots off, P-Tr on

11 = Normal display, P-Tr on

(P-Tr is transistor between VDD and VLC1)

Figure 13-4. LCD Control Register (LCON)

13-4

S3C821A/P821A

LCD CONTROLLER/DRIVER

LCD VOLTAGE DIVIDING RESISTORS

On-chip voltage dividing resistors for the LCD drive power supply are fixed to the V_LC1–V_LC5pins. Figure 13-5

shows the bias connections for the S3C821A LCD drive power supply. To cut off the flow of current through the

dividing resistor, manipulate bits 7 and 6 of the LCON register.

1/5 Bias

1/4 Bias

1/3 Bias

S3C821A

V_DD

LCON.7

V_LC1

R

V_LC2

V_LC3

V_LC4

V_LC5

V_LC2

V_LC3

V_LC4

V_LC5

V_LC2

V_LC3

V_LC4

V_LC5

V_SS

Figure 13-5. LCD Bias Circuit Connection

13-5

LCD CONTROLLER/DRIVER

S3C821A/P821A

DD

In Case of Internal V

S3C821A

V_DD

LCON.7

V_LC1

ON

R

V_LC2

V_LC3

V_LC4

V_LC5

For LCD-off, LCON.7, .6 must be set to 00B or 10B.

For power-saving, LCD.7, .6 must be set to 00B when LCD is off.

For a normal display, LCON.7, .6 must be set to 11B.

NOTE:

Figure 13-6. Example 1 for the Usage of LCON.7, LCON.6

13-6

S3C821A/P821A

LCD CONTROLLER/DRIVER

In Case of External V

for Contrast

DD

S3C821A

V_DD

LCON.7

V_LC1

V_LC2

OFF

V_LC1

R

V_LC3

V_LC4

V_LC5

For LCD-off, LCON.7, .6 must be set to 00B.

NOTE:

For a normal display, LCON.7, .6 must be set to 01B.

Figure 13-7. Example 2 for the Usage of LCON.7, LCON.6

13-7

LCD CONTROLLER/DRIVER

S3C821A/P821A

In Case of Using a Port for Contrast

S3C821A

V

P

a.b

DD

LCON.7

V_LC1

OFF

V_LC1

R

V_LC2

V_LC3

V_LC4

V_LC5

For LCD-off, LCON.7, .6 must be set to 00B.

For power-saving, Pa.b must be in low level when LCS is off.

For a normal disaplay, Pa.b must be in high level and LCON.7, .6

must be set to 01B.

NOTE:

Figure 13-8. Example 3 for the Usage of LCON.7, LCON.6

13-8

S3C821A/P821A

LCD CONTROLLER/DRIVER

SEG2 SEG1 SEG0

0

1

2

0

1

2

V

LC1

SS

FR

COM0

1 FRAME

V

LC1

COM1

COM2

V

)

(

LC2 LC3

COM0

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

COM1

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

COM2

SEG0

SEG1

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

V

)

(

LC4 LC5

SS

+ V

LC1

+ 1/3 V

0 V

LC1

SEG0 COM0

-

1/3 V

-

V

-

LC1

Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)

13-9

LCD CONTROLLER/DRIVER

S3C821A/P821A

SEG1 SEG0

0

1

2

3

0

1

2

3

V

LC1

SS

V

FR

COM0

COM1

COM2

COM3

1 FRAME

V

LC1

V

)

(

LC2 LC3

COM0

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

COM1

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

COM2

COM3

SEG0

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

V

)

(

LC4 LC5

V

LC1

V

)

(

LC2 LC3

V

)

(

LC4 LC5

SS

V

LC1

V

)

(

LC2 LC3

SEG1

V

)

(

LC4 LC5

SS

+ V

LC1

+ 1/3 V

0 V

LC1

SEG0 COM0

-

1/3 V

-

V

-

LC1

Figure 13-10. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)

13-10

S3C821A/P821A

LCD CONTROLLER/DRIVER

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

0

1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

V

LC1

SS

FR

1 FRAME

V

LC1

LC2

V

(

)

LC3 LC4

S S S S S

COM0

E E E E E

G G G G G

5 6 7 8 9

LC5

SS

V

LC1

LC2

V

(

)

LC3 LC4

COM1

COM2

SEG5

LC5

SS

V

LC1

LC2

V

(

)

LC3 LC4

LC5

SS

V

LC1

LC2

V

(

)

LC3 LC4

LC5

SS

V

LC1

LC2

V

(

)

LC3 LC4

LC5

0V

SEG5 COM0

-

V

-

LC5

V

(

)

-

LC3

LC4

LC2

LC1

Figure 13-11. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

13-11

LCD CONTROLLER/DRIVER

S3C821A/P821A

0

1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

V

LC1

SS

FR

1 FRAME

V

LC1

LC2

V

(

)

LC3 LC4

SEG6

LC5

SS

V

LC1

LC2

V

(

)

LC3 LC4

LC5

SEG6 COM0

-

0V

V

-

LC5

V

(

)

-

LC3

LC2

LC1

LC4

Figure 13-11. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)

13-12

S3C821A/P821A

LCD CONTROLLER/DRIVER

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

0 1 2 3

7 0 1 2 3

7

V

LC1

SS

FR

1 FRAME

V

LC1

LC2

S S S S S

LC3

LC4

LC5

COM0

E E E E E

G G G G G

5 6 7 8 9

Vss

V

LC1

LC2

LC3

LC4

COM1

COM2

SEG5

LC5

SS

V

LC1

LC2

LC3

LC4

LC5

SS

V

LC1

LC2

LC3

LC4

LC5

SS

Figure 13-12. LCD Signal Waveforms (1/8 Duty, 1/5 Bias)

13-13

LCD CONTROLLER/DRIVER

S3C821A/P821A

0 1 2 3

7 0 1 2 3

7

V

LC1

SS

FR

1 FRAME

V

LC1

LC2

LC3

LC4

SEG6

LC5

SS

V

LC1

LC2

LC3

LC4

LC5

SEG5 COM0

-

0V

V

-

LC5

LC4

LC3

LC2

LC1

V

LC1

LC2

LC3

LC4

LC5

SEG6 COM0

-

0V

V

-

LC5

LC4

LC3

V

-

LC2

-

LC1

Figure 13-12. LCD Signal Waveforms (1/8 Duty, 1/5 Bias) (Continued)

13-14

S3C821A/P821A

A/D CONVERTER

14 ANALOG-TO-DIGITAL CONVERTER

OVERVIEW

The 8-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at

one of the four input channels to equivalent 8-bit digital values. The analog input level must lie between the

AV_REFand AV_SSvalues. The A/D converter has the following components:

— Analog comparator with successive approximation logic

— D/A converter logic (resistor string type)

— ADC control register (ADCON)

— Four multiplexed analog data input pins (ADC0–ADC3)

— 8-bit A/D conversion data output register (ADDATA)

— AV_REFand AV_SSinput pins

To initiate an analog-to-digital conversion procedure, you should load a value in analog input pin selection bits in

the A/D converter control register ADCON to select one of the four analog input pins (ADCn, n = 0–3) and set the

conversion start or enable bit, ADCON.0. The read-write ADCON register is located in set 1, bank 0, at address

F7H.

During a normal conversion, ADC block initially sets the successive approximation register to 80H (the

approximate half-way point of an 8-bit register). This register is then updated automatically during each

conversion step. The successive approximation block performs 8-bit conversions for one input channel at a time.

You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6–

ADCON.4) in the ADCON register.

To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed,

ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATA

register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of

ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next

conversion result.

NOTE

As the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog

level at the ADC0–ADC3 input pins during a conversion procedure be kept to an absolute minimum. Any

change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or

IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP

or IDLE mode after ADC operation is finished.

14-1

A/D CONVERTER

S3C821A/P821A

CONVERSION TIMING

The A/D conversion process requires 4 clocks to convert each bit. Therefore, a total of 34 clocks are required to

complete an 8-bit conversion (17 µs–170 µs). With an 4 MHz fxx clock frequency and fxx/4 clock source

selected, one clock cycle is 1 µs. If each bit conversion requires 4 clocks, the conversion rate is calculated as

follows:

(start 1 clock + (4 clock/bit ´ 8 bits) + EOC clock) = 34 clocks, 1 µs ´ 34 = 34 µs at 4 MHz (fxx/4)

ADCON.2 .1

-

ADCON.6 .4

(Input pin select)

-

fxx/n

(n = 1, 4, 8, 16)

CLOCK SELECT

To ADCON.3

(EOC Flag)

ADCON.0

(ADC Enable)

ANALOG

COMPARATOR

SUCCESSIVE

APPROXIMATION

LOGIC and REGISTER

Input pins

ADC3 ADC0

+

MUX

-

ADCON.0

(ADC Enable)

CONVERSION

RESULT (ADDATA

F8H, Set1, Bank0)

AV

8-BIT D/A

CONVERTER

REF

SS

To DATA BUS

Figure 14-1. A/D Converter Functional Block Diagram

14-2

S3C821A/P821A

A/D CONVERTER

A/D CONVERTER CONTROL REGISTER (ADCON)

The A/D converter control register, ADCON, is located at address F7H in set 1, bank 0. It has four functions:

— Analog input pin selection (bits 4, 5, and 6)

— End-of-conversion status detection (bit 3)

— Clock source selection (bits 2 and 1)

— A/D operation start or enable (bit 0)

After a reset, the ADC0 pin is automatically selected as the analog data input pin, and the start bit is turned off.

You can select only one analog input channel at a time. Other analog input pins (ADC0–ADC3) can be selected

dynamically by manipulating the ADCON.4–.6 bits.

A/D CONVERTER CONTROL REGISTER (ADCON)

F7H, Set 1, Bank 0, R/W (EOC bit is read-only)

.7

MSB

.6

.5

.4

.3

.2

.1

.0

LSB

Start or enable bit:

0 = Disable operation

1 = Start operation

Not used for the S3C821A

A/D input pin selection bits:

000 = ADC0

001 = ADC1

Clock source select bits:

00 = fxx/16

01 = fxx/8

010 = ADC2

10 = fxx/4

011 = ADC3

11 = fxx

End-of-conversion bit (read-only):

0 = Conversion not complete

1 = Conversion complete

Figure 14-2. A/D Converter Control Register (ADCON)

INTERNAL REFERENCE VOLTAGE LEVELS

In the ADC function block, the analog input voltage level is logically compared to a reference voltage. For the

S3C821A, the analog input level must be within the range of AV_SSto AV_REF, where AV_REF= V_DD. Different

reference voltage levels are generated internally along the resistor tree during the analog conversion process for

each conversion step. The reference voltage level for the first bit conversion is always 1/2 AV_REF

.

14-3

S3C821A/P821A

SERIAL I/O INTERFACE

15 SERIAL I/O INTERFACE

OVERVIEW

Serial I/O module, SIO can interface with various types of external device that require serial data transfer. The

components of each SIO function block are:

— 8-bit control register (SIOCON)

— Clock selector logic

— 8-bit data buffer (SIODATA)

— 8-bit prescaler (SIOPS)

— 3-bit serial clock counter

— Serial data I/O pins (SI, SO)

— External clock input/output pins (SCK)

The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control

register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.

PROGRAMMING PROCEDURE

To program the SIO modules, follow these basic steps:

1. Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P5CONL register if

necessary.

2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this

operation, SIOCON.2 must be set to "1" to enable the data shifter.

3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.5) to "1".

4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift

operation starts.

5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.6) is set to "1" and

an SIO interrupt request is generated.

15-1

SERIAL I/O INTERFACE

S3C821A/P821A

SIO CONTROL REGISTER (SIOCON)

The control register for serial I/O interface module, SIOCON, is located at F5H in set 1, bank 0. It has the control

settings for SIO module.

— Clock source selection (internal or external) for shift clock

— Interrupt enable

— Edge selection for shift operation

— Clear 3-bit counter and start shift operation

— Shift operation (transmit) enable

— Mode selection (transmit/receive or receive-only)

— Data direction selection (MSB first or LSB first)

A reset sets the SIOCON value to "80H". This configures the corresponding module with a CPU clock source at

the SCK, selects receive-only operating mode, and falling edge start. The data shift operation and the interrupt

are disabled. The selected data direction is MSB-first.

SIO CONTROL REGISTER (SIOCON)

F5H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

SIO shift clock selection:

0 = External clock

1 = CPU clock

Data direction control bit:

0 = MSB-first mode

1 = LSB-first mode

SIO interrupt pending bit:

0 = No interrupt pending

0 = Clear pending condition

(when write)

SIO mode selection bit:

0 = Receive-only mode

1 = Transmit/receive mode

1 = Interrupt is pending

SIO shift operation enable bit:

0 = Disable shifter and counter, retain IRQ status

1 = Enable shifter and clock counter,

set IRQ flag to “1”

SIO interrupt enable bit:

0 = Disable interrupt

1 = Enable interrupt

SIO start edge selection bit:

0 = Falling edge start

1 = Rising edge start

SIO counter clear and shifter start bit:

0 = No action (when write)

1 = Clear 3-bit counter and start shifting

Figure 15-1. Serial I/O Port Control Register (SIOCON)

15-2

S3C821A/P821A

SERIAL I/O INTERFACE

SIO PRE-SCALER REGISTER (SIOPS)

SIO prescaler register, SIOPS, is located at F6H in set 1, bank 0. The value stored in the SIO prescaler

registers, SIOPS, lets you determine the SIO clock rate (baud rate) as follows:

Baud rate = Input clock (CPU clock) / 2 ´ (Prescaler value + 1), or SCK input clock

SIO PRESCALER REGISTER (SIOPS)

F6H, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Baud rate = (CPU clock) / 2 x (SIOPS + 1)

Figure 15-2. SIO Prescaler Register (SIOPS)

BLOCK DIAGRAM

SIOINT

(IRQ2)

3-BIT COUNTER

SIOCON.6

Pending

CLK

CLEAR

SIOCON.5

(Interrupt Enable)

SIOCON.7

(Shift Clock

SIOCON.3

Source Select)

SIOCON.4

SIOCON.2

SIOCON.1

(Edge Select)

(Shift Enable)

(Mode Select)

SCK/P5.0

M

U

X

SIOPS

(F6H, set 1, bank 0)

CLK

8-BIT SIO SHIFT BUFFER

(SIODATA)

SO/P5.2

CPU clock

SI/P5.1

8-BIT P.S.

Prescaled value =

1 / 2(SIOPS + 1)

SIOCON.0

(LSB/MSB First

Mode Select)

8

DATA BUS

Figure 15-3. SIO Functional Block Diagram

15-3

SERIAL I/O INTERFACE

S3C821A/P821A

SERIAL I/O TIMING DIAGRAMS

Shift

Clock

Data

Input

D7

D6

D5

D4

D3

D2

D1

D0

Data

Output

D7

Transmit

Complete

IRQ2 Start

Figure 15-4. SIO Timing in Transmit/Receive Mode (Falling Edge Start)

Shift

Clock

Data

Input

D7

D6

D5

D4

D3

D2

D1

D0

High Impedance

Data

Output

Transmit

Complete

IRQ2 Start

Figure 15-5. SIO Timing in Receive-Only Mode (Falling Edge Start)

15-4

S3C821A/P821A

SERIAL I/O INTERFACE

SERIAL I/O TIMING DIAGRAMS (Continued)

Shift

Clock

Data

Input

D7

D6

D5

D4

D3

D2

D1

D0

Data

Output

D0

Transmit

Complete

IRQ2 Start

Figure 15-6. Timing in Transmit/Receive Mode (Rising Edge Start)

Shift

Clock

Data

Input

D7

D6

D5

D4

D3

D2

D1

D0

High Impedance

Data

Output

Transmit

Complete

IRQ2 Start

Figure 15-7. Timing in Receive-Only Mode (Rising Edge Start)

15-5

S3C821A/P821A

EXTERNAL INTERFACE

16 EXTERNAL INTERFACE

OVERVIEW

The SAM8 architecture supports an external memory interface. Data memory areas in external devices can be

accessed over the 16-bit multiplexed address/data bus.

The S3C821A microcontroller has a total of 80 pins, 47of which are for programmable I/O. Of these 47 I/O pins,

up to 20 can be configured as an external interface that supports access to external memory and other peripheral

devices.

Since memory addresses that are carried over the address/data bus are 16 bits long, up to 64 K bytes of memory

space can be addressed.

16-1

EXTERNAL INTERFACE

S3C821A/P821A

EXTERNAL INTERFACE CONTROL REGISTERS

This subsection presents an overview of the S3C821A system registers which are used to configure and control

the external peripheral interface:

— System mode register (SYM, R222, DEH, set 1)

— Port 0 control register (P0CON, R224, E0H, set 1, bank 1)

— Port 1 control register (P1CON, R226, E2H, set 1, bank 1)

— Port 2 low-byte control register (P2CONL, R229, E5H, set 1, bank 1)

Detailed descriptions of each of these registers can be found in Part I, Chapter 4, "Control Registers."

PORT 0 CONTROL REGISTER (P0CON)

The port 0 control register P0CON (E0H, set 1, bank 1) controls the upper and lower nibble configuration for port

0 pins. When P0CON bit 7 = "1", the upper nibble pins P0.7–P0.4 are configured as lines for the external

memory interface. When P0CON bit 3 = "1", the lower nibble pins P0.3–P0.0 are configured for external memory.

After a reset, P0CON is cleared to 00H. Bits 7 and/or 3 must then be set to "1" by program software to enable the

external memory interface function for port 0.

PORT 1 CONTROL REGISTER (P1CON)

The port 1 control register P1CON (E2H, set 1, bank 1) functions identically to the P0CON register, except that it

controls the upper and lower nibble configuration for port 1 pins: P1.7–P1.4 and P1.3–P1.0, respectively. P1CON

is also cleared to 00H by a reset.

PORT 2 CONTROL REGISTER (P2CONL)

The pins of I/O port 2, P2.3–P2.0, can alternately be used as lines for the signal outputs that are required to

control the activity of the multiplexed external memory interface bus. You manipulate the bit-pairs in the control

register, P2CONL (E5H, set 1, bank 1) to configure the pins individually for general-purpose use or as external

memory bus control lines. If the external memory interface is implemented, you must configure all four pins as

memory lines. When bit pairs 7/6, 5/4, 3/2, and 1/0 are set to "11B", the corresponding memory signal outputs

are activated:

Bit-pair

Symbol

DM

Function

Data memory pin

7/6

P2.3

5/4

3/2

1/0

P2.2

P2.1

P2.0

Data write pin

DW

Data read pin

DR

Address strobe pin

AS

In normal operating mode, a reset operation clears P2CONL to 00H, configuring P2.3–P2.0 as normal input pins.

16-2

S3C821A/P821A

EXTERNAL INTERFACE

HOW TO CONFIGURE THE EXTERNAL INTERFACE

The 3-state external memory interface is enabled or disabled by manipulating bit 7 of the system mode register

SYM (R222, DEH). A reset clears SYM.7 to logic zero, disabling the high impedance levels of the interface bus

lines and enabling the external interface.

To access the external memory, its port must be selected to external interface lines.

Table 16-1. Control Register Overview for the External Memory Interface

Register

SYM

Location

DEH

Bit (s)

Description

7

3

External 3-state interface enable bit

P0CON

E0H, Bank 1

If "1", enable port 0 pins P0.0–P0.3 for external memory

interface

7

3

7

If "1", enable port 0 pins P0.4–P0.7 for external memory

interface

P1CON

E2H, Bank 1

E5H, Bank 1

If "1", enable port 1 low nibble pins (P1.0–P1.3) for external

memory interface

If "1", external memory interface enable for port 1 high nibble

pins (P1.4–P1.7)

P2CONL

1, 0

3, 2

5, 4

7, 6

If both "1", address strobe (AS) enabled at P2.0

If both "1", data read signal (DR) enabled at P2.1

If both "1", data write signal (DW) enabled at P2.2

If both "1", data memory signal (DM) enabled at P2.3

Table 16-2. External Interface Control Register Values After a RESET (Normal Mode)

Register Name

Mnemonic

Address

Hex

Bit Values After RESET

Dec

R222

R224

R226

R229

7

0

6

–

0

5

–

0

4

x

0

3

x

0

2

x

0

1

0

System Mode Register

SYM

DEH

Port 0 Control Register

P0CON

P1CON

P2CONL

E0H, Bank 1

E2H, Bank 1

E5H, Bank 1

Port 1 Control Register

Port 2 Control Register (Low Byte)

NOTE: A dash (–) indicates that the bit is not mapped. An "x" means that the value is undefined after a RESET.

16-3

EXTERNAL INTERFACE

S3C821A/P821A

USING AN EXTERNAL SYSTEM STACK

SAM8 microcontrollers use the system stack to implement subroutine calls and returns for interrupt processing

and for dynamic data storage. Stack operations are supported in either the internal register file or in externally

configured data memory.

The PUSH and POP instructions support external system stack operations. The instructions PUSHUI, PUSHUD,

POPUI, and POPUD support user-defined stack operations in the register file only.

After a reset, the stack pointer value is undetermined. For external stack operations, a 16-bit stack pointer value

(in other words, both SPL and SPH) must be used.

An external stack holds return addresses for procedure calls and interrupts, as well as dynamically-generated

data. The contents of the PC are saved on the external stack during a CALL instruction and restored during a

RET instruction. During interrupts, the contents of the PC and the FLAGS register are saved on the external

stack and then restored by the IRET instruction.

To select the external stack area option, bit 1 in the external memory timing register (EMT, FEH, set 1, bank 0)

must be set to logic one. The instruction used to change the stack selection bit in the EMT register should not be

immediately followed by an instruction that uses the stack, since this will cause indeterminate program flow. Also,

interrupts should be disabled with a DI instruction before changing the stack selection bit.

16-4

S3C821A/P821A

EXTERNAL INTERFACE

MACHINE CYCLE (Mn)

T2

T1

T3

CLOCK

PORT A

A8–A15

PORT AD

A0–A7

D0–D7 OUTPUT

AS

DW

DR

DM

WRITE CYCLE

Figure 16-1. S3C821A External Bus Write Cycle Timing Diagram

16-5

EXTERNAL INTERFACE

S3C821A/P821A

MACHINE CYCLE (Mn)

T2

T1

T3

CLOCK

PORT A

A8–A15

PORT AD

A0–A7

D0–D7 INPUT

AS

DW

DR

DM

READ CYCLE

Figure 16-2. S3C821A External Bus Read Cycle Timing Diagram

16-6

S3C821A/P821A

EXTERNAL INTERFACE

8

D0-D7

A0-A7

A8-A15

74HCT374

74HCT574

8

AD0-AD7

Port AD

CLK

AS

A8-A15

Port A

SRAM

(64 KB)

S3C821A

DM

DR

CS

OE

DW

WE

Figure 16-3. External Interface Function Diagram (S3C821A, SRAM, EPROM, EEPROM)

16-7

S3C821A/P821A

ELECTRICAL DATA

17 ELECTRICAL DATA

OVERVIEW

In this section, S3C821A electrical characteristics are presented in tables and graphs. The information is

arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in Stop mode

— Stop mode release timing when initiated by an external interrupt

— Stop mode release timing when initiated by a Reset

— I/O capacitance

— A.C. electrical characteristics

— A/D converter electrical characteristics

— Input timing for external interrupts (P4, P2.4–P2.7)

— Input timing for RESET

— Serial data transfer timing

— Oscillation characteristics

— Oscillation stabilization time

— Operating voltage range

17-1

ELECTRICAL DATA

S3C821A/P821A

Table 17-1. Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Unit

V_DD

Supply voltage

–

– 0.3 to + 6.5

V

V_IN

V_O

– 0.3 to V_DD+ 0.3

– 18

Input voltage

All I/O ports

V

Output voltage

Output current High

–

I_OH

One I/O port active

mA

All I/O ports active

One I/O port active

– 60

I_OL

Output current Low

+ 30 (peak value)

mA

+ 15 ^(note)

+ 100 (peak value)

+ 60 ^(note)

Ports 0, 1, 2, and 3

Ports 4 and 5

+ 100 (peak value)

+ 60 ^(note)

T_A

°

Operating

temperature

–

– 40 to + 85

C

T_STG

°

C

Storage temperature

– 65 to + 150

NOTE: The values for Output Current Low (I_OL) are calculated as Peak Value ´ Duty .

17-2

S3C821A/P821A

ELECTRICAL DATA

Table 17-2. D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

f_OSC= 8 MHz

Min

Typ

Max

Unit

V_DD

Operating Voltage

2.2

–

5.5

V

(Instruction clock = 1.33 MHz)

f_OSC= 6 MHz

2.0

(Instruction clock = 1 MHz)

V_IH1

0.7 V_DD

V_DD

Input High

voltage

P0 and P1

–

V

V_IH2

V_IH3

V_IL1

V_IL2

V_IL3

V_OH

0.8 V_DD

V_DD– 0.1

0

V_DD

RESET, P2, P3, P4, and P5

X_INXT

,

IN

0.3 V_DD

0.2 V_DD

0.1

Input Low voltage

P0 and P1

RESET, P2, P3, P4, and P5

X_INXT

,

IN

V_DD– 1.0

Output High

voltage

–

0.4

–

V_DD= 3 V; I_OH= – 200 mA

All output pins

V_OL

V_DD= 3 V; I_OL= 1 mA

All output pins

Output Low

voltage

–

1.0

1

I_LIH1

V_IN= V_DD

Input High

µA

leakage current

All input pins except those specified

below for I_LIH2

I_LIH2

V_IN= V_DD

20

X_IN

X XT and XT

, ,

OUT IN OUT

,

I_LIL1

V_IN= 0 V

Input Low

–

– 1

leakage current

All input pins except those specified

below for I_LIL2and RESET

I_LIL2

V_IN= 0 V

– 20

X_IN

X XT and XT

, ,

OUT IN OUT

,

I_LOH

I_LOL

V_DC

V_OUT= V_DD

Output High

leakage current

–

1

All output pins

V_OUT= 0 V

Output Low

leakage current

– 1

120

All output pins

V_DD= 2.7 V to 5.5 V

mV

|V_DDCOMi|

–

– 15 mA per common pin

voltage drop

(i = 0–7)

V_DS

V_LCD= 2.7 V to 5.5 V

–

120

|V_DD–SEGx|

– 15 mA per segment pin

voltage drop

(x = 0–31)

17-3

ELECTRICAL DATA

S3C821A/P821A

Table 17-2. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Unit

Parameter

Symbol

Conditions

V_DD= 2.7 V to 5.5 V

Min

0.8 V_DD0.8 V_DD0.8 V_DD

– 0.15 + 0.15

0.6 V_DD0.6 V_DD0.6 V_DD

– 0.15 + 0.15

0.4 V_DD0.4 V_DD0.4 V_DD

– 0.15 + 0.15

0.2 V_DD0.2 V_DD0.2 V_DD

Typ

Max

V_LC2output

voltage

V

V_LC2

LCD clock = 0 Hz

V_LC1= V_DD

V_LC3output

voltage

V_LC3

V_LC4

V_LC5

R_L1

V_LC4output

voltage

V_LC5output

voltage

– 0.15

30

+ 0.15

200

Pull-up resistors

80

V_IN= 0 V; T_A= 25 °C

kW

V_DD= 3.0 ± 10 %; Ports 0–5

200

450

800

80

R_L2

V_IN= 0 V; T_A= 25 °C

V_DD= 3.0 ± 10 %

RESET only

R_LCD

V_LCD= 2.7 V to 5.5 V

T_A= 25 °C

LCD voltage

45

–

65

kW

dividing resistor

I_DD1

6.0 MHz

6.0

4.5

12

mA

Run mode; V_DD=5.0V±10%

Supply current

(note)

4.19 MHz

Crystal oscillator

C1 = C2 = 22 pF

9.0

6.0 MHz

2.9

5.8

V_DD= 3.0 V ± 10 %

4.19 MHz

2.0

1.3

4.0

2.6

I_DD2

6.0 MHz

Idle mode; V_DD=5.0 V± 0 %

4.19 MHz

Crystal oscillator

C1 = C2 = 22 pF

1.2

2.4

6.0 MHz

0.6

1.2

V_DD= 3.0 V ± 10 %

4.19 MHz

0.4

20

0.8

40

I_DD3

I_DD4

I_DD5

µA

Run mode; V_DD= 3.0 V ± 10 %

32 kHz crystal oscillator

7

14

Idle mode; V_DD= 3.0 V ± 10 %

32 kHz crystal oscillator

0.5

0.3

3

2

Stop mode; V_DD= 5.0 V ± 10 %

Stop mode; V_DD= 3.0 V ± 10 %

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and

ADC.

2. I

3. I

4. I

and I

include power consumption for subsystem clock oscillation.

DD1

DD3

DD5

DD2

DD4

are current when main system clock oscillation stops and the subsystem clock is used.

is current when main system clock and subsystem clock oscillation stops.

17-4

S3C821A/P821A

ELECTRICAL DATA

Table 17-3. Data Retention Supply Voltage in Stop Mode

°

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply

voltage

–

2.2

–

3.4

V

I_DDDR

t_WAIT

V_DDDR= 1.0 V

Data retention supply

current

–

1

µA

ms

Stop mode

2¹⁶/fx ⁽¹⁾

Oscillator stabilization

wait time

–

Released by RESET

(2)

Released by interrupt

NOTES:

1. fx is the main oscillator frequency.

2. The duration of the oscillation stabilization time (t_WAIT) when it is released by an interrupt is determined by

the setting in the basic timer control register, BTCON.

IDLE MODE

(Basic Timer active)

STOP MODE

NORMAL

OPERATING

MODE

DATA RETENTION MODE

V_DD

V_DDDR

EXECUTION OF

STOP INSTRUCTION

0.8 V_DD

Interrupt Request

t_WAIT

Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt

17-5

ELECTRICAL DATA

S3C821A/P821A

OSCILLATION

STABILIZATION

TIME

RESET

OCCURS

STOP MODE

NORMAL

OPERATING

MODE

DATA RETENTION MODE

V

DD

V

DDDR

EXECUTION OF

STOP INSTRUCTION

RESET

0.8 V

DD

0.2 V

DD

t

WAIT

Figure 17-2. Stop Mode Release Timing When Initiated by a RESET

17-6

S3C821A/P821A

ELECTRICAL DATA

Table 17-4. Input/output Capacitance

°

(T_A= – 25 C, V_DD= 0 V)

Parameter

Input

capacitance

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

f = 1 MHz; unmeasured pins

are connected to V_SS

–

10

pF

C_OUT

C_IO

Output

capacitance

I/O capacitance

Table 17-5. A.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

t_KCY

SCK cycle time

External SCK source

1,000

–

ns

Internal SCK source

External SCK source

1,000

500

t_{KH, KL}

t

SCK high, low

width

t_KCY/2–50

Internal SCK source

External SCK source

t_SIK

250

SI setup time to

SCK high

Internal SCK source

External SCK source

250

400

t_KSI

SI hold time to

SCK high

Internal SCK source

External SCK source

400

–

t_KSO

–

300

ns

Output delay for

SCK to SO

Internal SCK source

250

–

t_INTH

t

INTL

Interrupt input,

high, low width

All interrupt

V_DD= 3 V

500

700

–

,

t_RSL

Input

V_DD= 3 V

2,000

–

RESET input low

width

17-7

ELECTRICAL DATA

S3C821A/P821A

Table 17-6. A/D Converter Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.7 V to 5.5 V, V_SS= 0 V)

Parameter

Resolution

Symbol

Conditions

Min

–

Typ

8

Max

Unit

bit

–

V_DD= 5.12 V

Total accuracy

–

LSB

± 2

AV_REF= 5.12 V

AV_SS= 0 V

Conversion time ⁽¹⁾

t_CON

8 bit conversion

17

–

170

ms

34 x n/fxx ^{(2) n=1,4,8,16}

,

V_IAN

R_AN

AV_SS

2

AV_REF

–

Analog input voltage

Analog input impedance

Analog reference voltage

Analog ground

–

V

MW

V

–

1,000

AV_REF

AV_SS

I_ADIN

V_DD

–

2.5

V_SS

–

V_SS+ 0.3

10

–

V

AV_REF= V_DD= 5V

Analog input current

mA

NOTES:

1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.

2. fxx is a selected system clock for peripheral hardware.

17-8

S3C821A/P821A

ELECTRICAL DATA

t

INTL

INTH

0.8 V_DD

0.2 V_DD

:

The unit t

means one CPU clock period.

CPU

NOTE

Figure 17-3. Input Timing for External Interrupts

t

RSL

RESET

0.2 V

DD

Figure 17-4. Input Timing for RESET

t

KCY

t

KH

KL

0.8 V

0.2 V

SCK

DD

t

KSI

SIK

0.8 V

0.2 V

DD

INPUT DATA

SI

t

KSO

SO

OUTPUT DATA

Figure 17-5. Serial Data Transfer Timing

17-9

ELECTRICAL DATA

S3C821A/P821A

Table 17-7. Main System Oscillation Characteristics

°

(T_A= – 40 C + 85 C)

Condition (V_DD

)

Oscillator

Crystal

Clock Circuit

Parameter

Min

Typ

Max

Unit

C1

Main oscillation

frequency

2.2 V–5.5 V

0.4

–

8

MHz

X

IN

X

OUT

C2

C1

2.0 V–5.5 V

2.2 V–5.5 V

0.4

–

6

8

Ceramic

Main oscillation

frequency

X

IN

X

OUT

C2

2.0 V–5.5 V

2.2 V–5.5 V

0.4

–

6

8

X_INinput

External clock

X

IN

frequency

X

OUT

2.0 V–5.5 V

3.0 V

0.4

–

6

2

RC

Frequency

X

IN

R

X

OUT

Table 17-8. Subsystem Oscillation Characteristics

°

(T_A= – 40 C + 85 C)

Condition (V_DD

)

Oscillator

Crystal

Clock Circuit

Parameter

Min

Typ

Max

Unit

C1

Sub oscillation

frequency

2.0 V–5.5 V

32

32.768

35

kHz

XT

IN

XT

OUT

C2

XT_INinput

frequency

External clock

2.0 V–5.5 V

32

–

500

kHz

XT

IN

XT

OUT

17-10

S3C821A/P821A

ELECTRICAL DATA

Table 17-9. Main Oscillation Stabilization Time

°

(T_A= – 40 C + 85 C, V_DD= 2.0 V to 5.5 V)

Oscillator

Crystal

Test Condition

Min

–

Typ

–

Max

Unit

ms

fx > 400 kHz

20

10

Oscillation stabilization occurs when V_DDis equal

to the minimum oscillator voltage range.

X_INinput High and Low width (t_XH, t_XL)

Ceramic

–

ms

External clock

25

–

500

ns

1 / f

x

t

XH

XL

X

IN

V

– 0.1 V

DD

0.1 V

Figure 17-6. Clock Timing Measurement at X_IN

Table 17-10. Sub Oscillation Stabilization Time

°

(T_A= – 40 C + 85 C, V_DD= 2.0 V to 5.5 V)

Oscillator

Crystal

External clock

Test Condition

Min

–

Typ

–

Max

Unit

s

–

10

18

XT_INinput High and Low width (t_XH, t_XL)

1

–

ms

1 / f

xt

t

XTH

XTL

XT

IN

V

– 0.1 V

DD

0.1 V

Figure 17-7. Clock Timing Measurement at XT_IN

17-11

ELECTRICAL DATA

S3C821A/P821A

INSTRUCTION

f

x

(Main oscillation

CLOCK

frequency)

1.33 MHz

8 MHz

6 MHz

1.00 MHz

400 kHz

8.33 kHz

1

2

3

4

5

6

7

2.2

5.5

SUPPLY VOLTAGE (V)

INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

Figure 17-8. Operating Voltage Range

17-12

S3C821A/P821A

MECHANICAL DATA

18 MECHANICAL DATA

OVERVIEW

The S3C821A microcontroller is currently available in 80-pin QFP and TQFP package.

23.90

20.00

± 0.3

± 0.2

-

0 8°

+0.10

- 0.05

0.15

0.10 MAX

80-QFP-1420C

#80

0.05 MIN

#1

2.65

± 0.10

0.80

(0.80)

0.35

± 0.1

3.00 MAX

±

0.15 MAX

0.80

± 0.20

NOTE: Dimensions are in millimeters.

Figure 18-1. 80-Pin QFP Package Demensions

18-1

MECHANICAL DATA

S3C821A/P821A

14.00BSC

12.00BSC

-

0

7°

-

0.09 0.20

80-TQFP-1212

0.05-0.15

#80

1.00 ± 0.05

1.20 MAX

#1

0.50

(1.25)

-

0.17 0.27

±

0.08 MAX M

NOTE: Dimensions are in millimeters.

Figure 18-2. 80-Pin TQFP Package Demensions

18-2

S3C821A/P821A

CUSTOMER NOTICE

19 CUSTOMER NOTICE

DNJZ INSTRUCTION

When DJNZ instruction is used in a program, the working register being used as a counter should be set at the

one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

+

PROGRAMMING TIP — Using DJNZ instruction to transport RAM data from page 0 to page 1

LD

SRP

LD

DJNZ

LD

PP,#10H

#0C0H

; Destination ¬ 1, Source ¬ 0

R0,#0FFH

R1,@R0

@R0,R1

R0,RAMTRN

R1,@R0

@R0,R1

; Transportation starts

RAMTRN

; R0 = 00H

19-1

S3C821A/P821A

S3P821A OTP

20 S3P821A OTP

OVERVIEW

The S3P821A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C821A

microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data

format.

The S3P821A is fully compatible with the S3C821A, both in function and in pin configuration. Because of its

simple programming requirements, the S3P821A is ideal as an evaluation chip for the S3C821A.

20-1

S3P821A OTP

S3C821A/P821A

1

2

3

4

5

6

7

8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG4

P1.1/SEG25/AD1

SEG3/COM7

SEG2/COM6

SEG1/COM5

SEG0/COM4

COM3

COM2

COM1

COM0

VDD2 (EXT)

VSS2

VLC1

P5.6

P5.5

P5.4

P5.3/BUZ

P5.2/SO

P5.1/SI

P5.0/SCK

P4.7/INT11

P1.2/SEG26/AD2

P1.3/SEG27/AD3

P1.4/SEG28/AD4

P1.5/SEG29/AD5

P1.6/SEG30/AD6

P1.7/SEG31/AD7

SDAT/P2.0/AS

SCLK/P2.1/DR

VDD1/VDD1

9

S3P821A

10

11

12

13

14

15

16

17

18

19

20

VSS1/VSS1

(80-TQFP)

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESET/RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

Figure 20-1. S3P821A Pin Assignments (80-TQFP-1212 Package)

20-2

S3C821A/P821A

S3P821A OTP

1

2

3

4

5

6

7

8

P0.7/SEG23/A15

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG6

SEG5

SEG4

SEG3/COM7

SEG2/COM6

SEG1/COM5

SEG0/COM4

COM3

COM2

COM1

COM0

VDD2 (EXT)

VSS2

VLC1

P5.6

P5.5

P5.4

P5.3/BUZ

P5.2/SO

P5.1/SI

P5.0/SCK

P4.7/INT11

P4.6/INT10

P4.5/INT9

P1.0/SEG24/AD0

P1.1/SEG25/AD1

P1.2/SEG26/AD2

P1.3/SEG27/AD3

P1.4/SEG28/AD4

P1.5/SEG29/AD5

P1.6/SEG30/AD6

P1.7/SEG31/AD7

SDAT/P2.0/AS

SCLK/P2.1/DR

VDD1/VDD1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

S3P821A

VSS1/VSS1

(80-QFP)

XOUT

XIN

VPP/TEST

XTIN

XTOUT

RESET/RESET

P2.2/DW

P2.3/DM

P2.4/INT0/T0CK

P2.5/INT1/T1CK

P2.6/INT2/TA

Figure 20-2. S3P821A Pin Assignments (80-QFP-1420C Package)

20-3

S3P821A OTP

S3C821A/P821A

Table 20-1. Descriptions of Pins Used to Read/Write the EPROM

During Programming

Main Chip

Pin Name

P2.0

Pin Name

Pin No.

I/O

Function

SDAT

8 (10)

I/O

Serial data pin. Output port when reading and

input port when writing. Can be assigned as a

Input/push-pull output port.

P2.1

V_PP

SCLK

TEST

9 (11)

I/O

I

Serial clock pin. Input only pin.

14 (16)

Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing mode).

When 12.5 V is applied, OTP is in writing mode

and when 5 V is applied, OTP is in reading

mode. (Option)

17 (19)

I

Chip Initialization

RESET

V_DD1/V_SS1

10 (12)/11 (13)

–

Logic power supply pin. V_DDshould be tied to + 5

V during programming.

NOTE: ( ) means 80 QFP package.

Table 20-2. Comparison of S3P821A and S3C821A Features

S3P821A

Characteristic

Program Memory

Operating Voltage (V_DD

S3C821A

48-K byte EPROM

2.0 V to 5.5 V

48-K byte mask ROM

2.0 V to 5.5 V

)

OTP Programming Mode

V_DD= 5 V, V_PP(TEST) = 12.5 V

Pin Configuration

80 QFP/80 TQFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V_PP(TEST) pin of the S3P821A, the EPROM programming mode is entered. The

operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 20-3 below.

Table 20-3. Operating Mode Selection Criteria

V

ADDRESS

(A15–A0)

V_DD

REG/

R/W

MODE

PP

(TEST)

MEM

5 V

0

1

0000H

0E3FH

1

0

1

0

EPROM read

12.5 V

EPROM program

EPROM verify

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

20-4

S3C821A/P821A

S3P821A OTP

Table 20-4. D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

f_OSC= 8 MHz

Min

Typ

Max

Unit

Operating Voltage

V_DD

2.2

–

5.5

V

(Instruction clock = 1.33 MHz)

f_OSC= 6 MHz

2.0

(Instruction clock = 1 MHz)

P0 and P1

Input High

voltage

V_IH1

0.7 V_DD

–

V_DD

V

V_IH2

V_IH3

V_IL1

V_IL2

V_IL3

V_OH

0.8 V_DD

V_DD– 0.1

0

V_DD

RESET, P2, P3, P4, and P5

X_INXT

,

IN

Input Low voltage

P0 and P1

0.3 V_DD

0.2 V_DD

0.1

RESET, P2, P3, P4, and P5

X_INXT

,

IN

Output High

voltage

V_DD– 1.0

–

0.4

–

V_DD= 3 V; I_OH= – 200 mA

All output pins

Output Low

voltage

V_OL

V_DD= 3 V; I_OL= 1 mA

All output pins

–

1.0

1

Input High

I_LIH1

V_IN= V_DD

µA

leakage current

All input pins except those specified

below for I_LIH2

I_LIH2

I_LIL1

V_IN= V_DD

20

X_IN

X XT and XT

, ,

OUT IN OUT

,

Input Low

leakage current

V_IN= 0 V

–

– 1

All input pins except those specified

below for I_LIL2and RESET

I_LIL2

V_IN= 0 V

– 20

X_IN

X XT and XT

, ,

OUT IN OUT

,

Output High

leakage current

I_LOH

I_LOL

V_DC

V_OUT= V_DD

All output pins

V_OUT= 0 V

–

1

Output Low

leakage current

– 1

120

All output pins

V_DD= 2.7 V to 5.5 V

mV

|V_{DD COMi}

|

–

voltage drop

(i = 0-7)

– 15 mA per common pin

V_DS

V_LCD= 2.7 V to 5.5 V

–

120

|V_{DD SEGx}|

–

voltage drop

(x = 0-31)

– 15 mA per segment pin

20-5

S3P821A OTP

S3C821A/P821A

Table 20-4. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Unit

Parameter

Symbol

Conditions

V_DD= 2.7 V to 5.5 V

LCD clock = 0 Hz

V_LC1= V_DD

Min

0.8 V_DD0.8 V_DD0.8 V_DD

– 0.15 + 0.15

0.6 V_DD0.6 V_DD0.6 V_DD

– 0.15 + 0.15

0.4 V_DD0.4 V_DD0.4 V_DD

– 0.15 + 0.15

0.2 V_DD0.2 V_DD0.2 V_DD

Typ

Max

V_LC2output

voltage

V_LC2

V

V_LC3output

voltage

V_LC3

V_LC4

V_LC5

R_L1

V_LC4output

voltage

V_LC5output

voltage

– 0.15

30

+ 0.15

200

Pull-up resistors

80

V_IN= 0 V; T_A= 25°C

kW

V_DD= 3.0 ± 10%; Ports 0–5

R_L2

300

500

800

80

V_IN= 0 V; T_A= 25 °C

V_DD= 3.0 ± 10 %

RESET only

LCD voltage

R_LCD

V_LCD= 2.7 V to 5.5 V

T_A= 25 °C

45

–

65

kW

dividing resistor

I_DD1

6.0 MHz

6.0

4.5

12

mA

Run mode; V_DD=5.0V±10%

Supply current

(note)

Crystal oscillator

C1 = C2 = 22 pF

4.19 MHz

9.0

6.0 MHz

2.9

5.8

V_DD= 3.0 V ± 10 %

4.19 MHz

6.0 MHz

2.0

1.3

4.0

2.6

I_DD2

Idle mode; V_DD=5.0 V± 0%

Crystal oscillator

C1 = C2 = 22 pF

4.19 MHz

1.2

0.6

2.4

1.2

6.0 MHz

V_DD= 3.0 V ± 10 %

4.19 MHz

0.4

20

0.8

40

I_DD3

I_DD4

I_DD5

µA

Run mode; V_DD= 3.0 V ± 10 %

32 kHz crystal oscillator

7

14

Idle mode; V_DD= 3.0 V ± 10 %

32 kHz crystal oscillator

0.5

0.3

3

2

Stop mode; V_DD= 5.0 V ± 10 %

Stop mode; V_DD= 3.0 V ± 10 %

NOTES:

1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and

ADC.

2.

3.

4.

I

and I

include power consumption for subsystem clock oscillation.

DD1

DD3

DD5

DD2

and I

are current when main system clock oscillation stops and the subsystem clock is used.

DD4

is current when main system clock and subsystem clock oscillation stops.

20-6

S3C821A/P821A

S3P821A OTP

INSTRUCTION

f

x

(Main oscillation

CLOCK

frequency)

1.33 MHz

8 MHz

6 MHz

1.00 MHz

400 kHz

8.33 kHz

1

2

3

4

5

6

7

2.2

5.5

SUPPLY VOLTAGE (V)

INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

Figure 20-3. Operating Voltage Range

20-7

S3C821A/P821A

DEVELOPMENT TOOLS

21 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development

support system is configured with a host system, debugging tools, and support software. For the host system, any

standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool

including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for

S3C7, S3C6, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.

Samsung also offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked

help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be

sized, moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format. Assembled program code includes the object code that is used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and

an auxiliary definition (DEF) file with device specific information.

SASM88

The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a

source file containing assembly language statements and translates into a corresponding source code, object

code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating

system. It produces the relocatable object code only, so the user should link object file. Object files can be linked

with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device

automatically.

TARGET BOARDS

Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters

are included with the device-specific target board.

21-1

DEVELOPMENT TOOLS

S3C821A/P821A

IBM-PC AT or Compatible

RS-232C

SMDS2+

TARGET

APPLICATION

SYSTEM

PROM/OTP WRITER UNIT

RAM BREAK/ DISPLAY UNIT

TRACE/TIMER UNIT

PROBE

ADAPTER

BUS

TB821A

TARGET

BOARD

POD

SAM8 BASE UNIT

EVA

CHIP

POWER SUPPLY UNIT

Figure 21-1. SMDS Product Configuration (SMDS2+)

21-2

S3C821A/P821A

DEVELOPMENT TOOLS

TB821A TARGET BOARD

The TB821A target board is used for the S3C821A microcontroller. It is supported with the SMDS2+.

TB821A

To User_Vcc

OFF

ON

IDLE

STOP

RESE

7411

J10

25

1

2

41

42

144 QFP

S3E8210

EVA CHIP

1

XI

MDS

39

40 79

80

XTAL

SM1317A

Figure 21-2. TB821A Target Board Configuration

21-3

DEVELOPMENT TOOLS

S3C821A/P821A

Table 21-1. Power Selection Settings for TB821A

Operating Mode

"To User_Vcc"

Settings

Comments

The SMDS2/SMDS2+

supplies V_CCto the target

To User_Vcc

TARGET

TB821A

OFF

ON

board (evaluation chip) and

the target system.

V

CC

SYSTEM

V

SS

V

CC

SMDS2/SMDS2+

The SMDS2/SMDS2+

supplies V_CConly to the target

To User_Vcc

OFF ON

External

TARGET

SYSTEM

TB821A

board (evaluation chip). The

target system must have its

own power supply.

V

CC

V

SS

V

CC

SMDS2/SMDS2+

NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:

a

Table 21-2. Main-clock Selection Settings for TB821A

Sub Clock Settings

Operating Mode

Comments

Set the XI switch to “MDS”

when the target board is

connected to the

XIN

EVA CHIP

S3E8210

XTAL

MDS

SMDS2/SMDS2+.

X_OUT

X

IN

No connection

100 pin connector

SMDS2/SMDS2+

Set the XI switch to “XTAL”

when the target board is used

as a standalone unit, and is

not connected to the

XIN

EVA CHIP

S3E8210

XTAL

MDS

SMDS2/SMDS2+.

X_OUT

X

IN

XTAL

TARGET BOARD

21-4

S3C821A/P821A

DEVELOPMENT TOOLS

SMDS2+ Selection (SAM8)

In order to write data into program memory that is available in SMDS2+, the target board should be selected to

be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.

Table 21-3. The SMDS2+ Tool Selection Setting

"SW1" Setting

Operating Mode

R/W*

SMDS2+

TARGET

BOARD

SMDS

SMDS2+

IDLE LED

The Yellow LED is ON when the evaluation chip (S3E8210) is in idle mode.

STOP LED

The Red LED is ON when the evaluation chip (S3E8210) is in stop mode.

21-5

DEVELOPMENT TOOLS

S3C821A/P821A

J101

1

3

5

7

2

4

6

P0.7/SEG23/A15

P1.1/SEG25/AD1

P1.3/SEG27/AD3

P1.5/SEG29/AD5

P1.7/SEG31/AD7

P1.0/SEG24/AD0

P1.2/SEG26/AD2

P1.4/SEG28/AD4

P1.6/SEG30/AD6

8

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

P2.0/

AS

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

P2.1/

V

DR

V

X

(INT)

DD1

OUT

SS1

X

TEST

IN

XT

IN

OUT

RESET

P2.2/

DW

P2.3/

DM

P2.5/INT1/T1CK

P2.7/INT3/TB

P3.0/ADC0

P2.4/INT0/T0CK

P2.6/INT2/TA

AV

REF

P3.1/ADC1

P3.3/ADC3

P3.4

P3.2/ADC2

AV

SS

P3.5

P3.7/T0/T0PWM/T0CAP

P4.1/INT5

P3.6

P4.0/INT4

P4.2/INT6

P4.4/INT8

P4.3/INT7

J102

P4.5/INT9

P4.7/INT11

P5.1/SI

P5.3/BUZ

P5.5

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

42

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

78

80

P4.6/INT10

P5.0/SCK

P5.2/SO

P5.4

P5.6

VLC1

V

SS2

V

(EXT)

COM0

COM2

SEG0/COM4

SEG2/COM6

SEG4

SEG6

SEG8

SEG10

SEG12

DD2

COM1

COM3

SEG1/COM5

SEG3/COM7

SEG5

SEG7

SEG9

SEG11

SEG13

SEG14

SEG15

P0.0/SEG16/A8

P0.2/SEG18/A10

P0.4/SEG20/A12

P0.6/SEG22/A14

P0.1/SEG17/A9

P0.3/SEG19/A11

P0.5/SEG21/A13

Figure 21-3. 40-Pin Connectors (J101, J102) for TB821A

21-6

S3C821A/P821A

DEVELOPMENT TOOLS

TARGET BOARD

TARGET SYSTEM

J101

J102

J101

1

2

41 42

1

2

Target Cable for 40 Pin Connector

Part Name: AS40D-A

Order Code: SM6306

39 40 79 80

79 80 39 40

Figure 21-4. S3C821A Cables for 80-QFP Package

21-7


型号：	S3P821AXX-QW
厂家：	SAMSUNG
描述：	Microcontroller, 8-Bit, OTPROM, 8MHz, CMOS, PQFP80, 14 X 20 MM, QFP-80 可编程只读存储器时钟微控制器外围集成电路
文件：	总208页 (文件大小：1310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3P821AXX-QW [SAMSUNG]

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