S3P863A-QZ [SAMSUNG]

Microcontroller, 8-Bit, OTPROM, SAM8 CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44;


型号：	S3P863A-QZ
厂家：	SAMSUNG
描述：	Microcontroller, 8-Bit, OTPROM, SAM8 CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44 微控制器
文件：	总23页 (文件大小：166K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3C8639/C863A/P863A

PRODUCT OVERVIEW

SAM8 PRODUCT FAMILY

Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide

range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupt

— Built-in basic timer with watchdog function

The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more

interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned

to specific interrupt levels.

S3C8639/C863A/P863A MICROCONTROLLERS

S3C8639/C863A/P863A single-chip 8-bit

microcontrollers are based on the powerful SAM8

CPU architecture. The internal register file is logically

expanded to increase the on-chip register space.

S3C8639/C863A/P863A contain 32/48 Kbytes of on-

chip program ROM.

— One 12-bit counter with selectable clock sources,

including Hsync or Csync input

— PWM block with seven 8-bit PWM circuits

— Sync processor block (for Vsync and Hsync I/O,

Csync input, and Clamp signal output)

— DDC Multi-master and slave-only IIC-Bus

— 4-channel A/D converter (8-bit resolution)

In line with Samsung's modular design approach, the

following peripherals are integrated with the SAM8

core:

S3C8639/C863A/P863A are a versatile

— Four programmable I/O ports (total 27 pins)

microcontrollers which are ideal for use in multi-sync

monitors or in general-purpose applications that

require sophisticated timer/counter, PWM, sync

signal processing, A/D converter, and multi-master

IIC-bus support with DDC. They are available in a

42-pin SDIP or a 44-pin QFP package.

— One 8-bit basic timer for oscillation stabilization

and watchdog functions

— One 8-bit general-purpose timer/counter with

selectable clock sources

— One interval timer

OTP

S3C8639/C863A microcontrollers are also available in OTP (One Time Programmable) version named,

S3P863A. S3P863A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of

masked ROM. S3P863A is comparable to S3C8639/C863A, both in function and pin configuration except its

ROM size.

1-1

PRODUCT OVERVIEW

S3C8639/C863A/P863A

FEATURES

CPU

Low Voltage Reset (LVR)

LVR level is 2.4 V ± 200 mV

•

SAM88RC CPU core

•

Memory

Pulse Width Modulator (PWM)

8-bit PWM: 7-CH

(6-bit basic frame with 2-bit extension)

•

S3C8639: 32-Kbyte internal program memory

•

(ROM)

S3C863A: 48-Kbyte internal program memory

(ROM)

Sync-Processor Block

•

Vsync-I, Hsync-I, Csync-I input and Vsync-O,

Hsync-O, Clamp-O output pins

S3C8639: 784-byte general-purpose

S3C863A: 1040-byte general-purpose

•

Programmable Pseudo sync signal generation

Auto SOG detection

Instruction Set

Auto H-/V-sync polarity detection

Composite sync detection

•

78 instructions

IDLE and STOP instructions added for

power-down modes

DDC Multi-Master IIC-Bus 1-Ch

•

Serial Peripheral Interface

Instruction Execution Time

Minimum 333 ns (with 12 MHz CPU clock)

Support for Display Data Channel

(DDC1/DDC2B/DDC2Bi/DDC2B+)

•

Interrupts

Slave Only IIC-Bus 1-Ch

Serial Peripheral Interface

•

Ten interrupt sources/vectors

•

Eight interrupt level

Fast interrupt feature

A/D Converter

•

4-channel; 8-bit resolution

General I/O

Oscillator Frequency

•

Four I/O Ports (total 27pins)

•

8 MHz to 12 MHz crystal operation

Internal Max. 12 MHz CPU clock

8-Bit Basic Timer

•

Programmable timer for oscillation stabilization

interval control or watchdog timer function

Operating Temperature Range

– 40 °C to + 85 °C

•

Three selective internal clock frequencies

Operating Voltage Range

3.0 V to 5.5 V

Timer/Counters

•

One 8-bit Timer/Counter with several clock

sources (Capture mode)

Package Types

42-pin SDIP, 44-pin QFP

One 12-bit Counter with H-/C-sync and several

clock sources

•

One Interval Timer

1-2

S3C8639/C863A/P863A

PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-P0.7/INT0-INT2

Port 0

P2.0-P2.7

Port 2

TEST

DD1, VDD2

SS1, VSS2

RESET

INT0-INT2

Main

Osc

OUT

Port 1

P1.0-P1.2

I/O Port and Interrupt

PWM0

Control

8-Bit

PWM

(7-Ch)

Port 3

ADC

PWM6

P3.0-P3.7

AD0-AD3

Vsync-I

Hsync-I

Csync-I

Vsync-O

Hsync-O

Clamp-O

SAM8 CPU

Sync-

Processor

32/48-

Kbyte

ROM

784/1040-

Byte

SCL1

SDA1

8-Bit

Counter

(Timer M0)

Slave

Only

IIC-Bus

TM0CAP

* S3C8639

- 32 Kbyte ROM

- 784 Byte RAM

* S3C863A

- 48 Kbyte ROM

- 1040 Byte RAM

12-Bit

Counter

(Timer M1)

Interval

Timer

(Timer M2)

Multi-master IIC-Bus

and DDC1/2B/2Bi/2B+

SCL0

SDA0

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW

S3C8639/C863A/P863A

PIN ASSIGNMENTS

P3.7

P3.6

P3.5

P3.4

P3.3/AD3

P3.2/AD2

P3.1/AD1

P3.0/AD0

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3

P0.4/TM0CAP

P0.5

P0.6

P0.7

P1.0/SDA1

P1.1/SCL1

DD2

S3C8639

/C863A

(42-SDIP)

SS2

P2.7/Csync-I (SOG)

Hsync-I

Vsync-I

Vsync-O

Hsync-O

DD1

SS1

OUT

TEST (GND)

SDA0

Clamp-O

P2.6/PWM6

P2.5/PWM5

P2.4/PWM4

P2.3/PWM3

P2.2/PWM2

SCL0

RESET

P1.2

P2.0/PWM0

P2.1/PWM1

NOTE: The TEST pin must connect to V SS (GND) in the normal operation mode.

Figure 1-2. S3C8639/C863A 42-SDIP Pin Assignment

1-4

S3C8639/C863A/P863A

PRODUCT OVERVIEW

P0.5

P0.6

P0.7

P3.2/AD2

P3.1/AD1

P3.0/AD0

DD2

P1.0/SDA1

P1.1/SCL1

S3C8639

/C863A

44-QFP

VSS2

DD1

P2.7/Csync-I (SOG)

Hsync-I

Vsync-I

Vsync-O

Hsync-O

VSS1

OUT

(Top View)

TEST (GND)

SDA0

Clamp-O

NOTE: The TEST pin must connect to V

(GND) in the normal operation mode.

Figure 1-3. S3C8639/C863A 44-QFP Pin Assignment

1-5

PRODUCT OVERVIEW

S3C8639/C863A/P863A

PIN DESCRIPTIONS

Table 1-1. S3C8639/C863A Pin Descriptions

Circuit

SDIP Pin

Shared

Names

Type

Description

Type

Numbers Functions

P0.0

I/O

General-purpose, 8-bit I/O port. Shared

functions include three external interrupt inputs

and I/O for timer M0. Selective configuration of

port 0 pins to input or output mode is

supported.

D-1

INT0

INT1

INT2

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

TM0CAP

P1.0

P1.1

P1.2

I/O

General-purpose, 8-bit I/O port. Selective

configuration is available for port 1 pins to

input, push-pull output, n-channel open-drain

mode, or IIC-bus clock and data I/O.

E-1

SDA1

SCL1

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

General-purpose, 8-bit I/O port Selective

configuration of port 2 pins to input or output

mode is supported. The port 2 pin circuits are

designed to push-pull PWM output and Csync

(SOG) signal input.

D-1

E-1

D-1

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

Csync-I

P3.0–P3.3

P3.4–P3.7

I/O

General-purpose, 8-bit I/O port Selective

configuration port 3 pins to input or output

mode is supported. Multiplexed for alternative

use as A/D converter inputs AD0–AD3.

E-1

35–38

39–42

AD0–AD3

Hsync-I

Vsync-I

Clamp-O

Hsync-O

Vsync-O

SDA0

The pins are sync processor signal I/O and IIC-

bus clock and data I/O.

A-3

–

I/O

G-3

SCL0

V_DD1, V_SS1

V_DD2, V_SS2

–

Power pins

–

11, 12

34, 33

–

X_IN, X_OUT

–

System clock I/O pins

System RESET pin

–

14, 13

–

RESET

TEST

Factory test pin input

0 V: Normal operation, 5 V: Factory test mode

1-6

S3C8639/C863A/P863A

PRODUCT OVERVIEW

PIN CIRCUITS DIAGRAM

VDD

Input

Output

Data

Output

300 k

Typical

VSS

Figure 1-5. Pin Circuit Type A-3

Figure 1-4. Pin Circuit Type A

Data or

Other

Function

Output

VDD

Output

280 k

Disable

Noise

Filter

VSS

RESET

Digital Input,

TTL Input

NOTE:

The noise filter must be built in the

external interrupts.

Figure 1-7. Pin Circuit Type D-1

Figure 1-6. Pin Circuit Type B (RESET)

1-7

PRODUCT OVERVIEW

S3C8639/C863A/P863A

VDD

Typical

47 k

VDD

Pull-up

Enable

Data

VDD

Output

Open

Drain

Data

Output

Disable

Open

Drain

Digital Input

or ADC Input

Output

Disable

VSS

Input

Figure 1-8. Pin Circuit Type E

Figure 1-9. Pin Circuit Type E-1

Output

Data

Input

Figure 1-10. Pin Circuit Type G-3

1-8

S3C8639/C863A/P863A

ELECTRICAL DATA

19 ELECTRICAL DATA

OVERVIEW

In this section, S3C8639/C863A electrical characteristics are presented in tables and graphs. The information is

arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in stop mode

— Stop mode release timing when initiated by a reset

— I/O capacitance

— A/D Converter electrical characteristics

— A.C. electrical characteristics

— Input timing measurement points for P0.0–P0.2 and TM0CAP

— Oscillation characteristics

— Oscillation stabilization time

— Clock timing measurement points for X_IN

— Schmitt trigger characteristics

— Power-on reset circuit characteristics

19-1

ELECTRICAL DATA

S3C8639/C863A/P863A

Table 19-1. Absolute Maximum Ratings

(T_A= 25 C)

Parameter

Supply voltage

Input voltage

Symbol

V_DD

V_I1

Conditions

Rating

Unit

–

– 0.3 to + 6.5

– 0.3 to + 7.0

Type G-3 (n-channel open drain)

V_I2

All port pins except V

All output pins

– 0.3 to V_DD+ 0.3

– 10

V_O

Output voltage

I_OH

Output current

High

One I/O pin active

All I/O pins active

One I/O pin active

– 60

+ 30

I_OL

Output current

Low

Total pin current except port 3

+ 100

+ 150

Sync-processor I/O pins and IIC-bus

clock and data pins

T_A

Operating

temperature

–

– 40 to + 85

– 65 to + 150

T_STG

Storage

–

temperature

Table 19-2. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.0 V to 5.5 V)

Parameter

Input High

voltage

Symbol

V_IH1

V_IH2

V_IH3

V_IH4

V_IL1

Conditions

All input pins except V_IH2, V_IH3and V_IH4

X_IN

Min

Typ

Max

Unit

0.8 V_DD

V_DD–0.5

2.0

V_DD

–

V_DD

TTL input (Hsync-I, Vsync-I, and Csync-I)

SCL0/SDA0, SCL1/SDA1

All input pins except V_IL2and V_IL3

X_IN

0.7V_DD

–

V_DD

0.2 V_DD

0.4

Input Low

voltage

V_IL2

V_IL3

TTL input (Hsync-I, Vsync-I, and Csync-I)

SCL0/SDA0, SCL1/SDA1

0.8

V_IL4

0.3V_DD

–

V_OH1

V_DD– 1.0

Output High

voltage

V_DD= 5 V ± 10%; I_OH= – 15 mA;

Port 3.6–3.7

V_OH2

V_OH3

V_OH4

V_DD= 5 V ± 10%; I_OH= – 4 mA;

Port 1.2, Port 3.0–3.5

V_DD= 5 V ± 10%; I_OH= – 2 mA;

Port 0, 2, Clamp-O, H, and Vsync-O

V_DD= 5 V ± 10%; I_OH= – 6 mA;

Port 1.0–P1.1, SCL0 and SDA0

19-2

S3C8639/C863A/P863A

ELECTRICAL DATA

Table 19-2. D.C. Electrical Characteristics (Continued)

(T_A= – 40 C to + 85 C, V_DD= 3.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_OL1

Output Low

voltage

–

0.4

V_DD= 5 V ± 10%; I_OL= 15 mA

Port 3.6–3.7

V_OL2

V_OL3

V_OL4

I_LIH1

0.4

0.6

V_DD= 5 V ± 10%; I_OL= 4 mA

Port 3.0–3.5 and Port 1.2

V_DD= 5 V ± 10%; I_OL= 2 mA

Port 0, 2, Clamp-O, H, and Vsync-O

V_DD= 5 V ± 10%; I_OL= 6 mA

Port 1.0–1.1; SCL0 and SDA0

V_IN= V_DD

Input High

–

µA

leakage current

All input pins except X_IN

OUT

I_LIH2

I_LIH3

I_LIL1

V_IN= V_DDX_OUTonly

;

–

2.5

–

V_IN= V_DD

X_INonly

;

V_IN= 0 V; All input pins except X_IN

Input Low

– 3

leakage current

RESET , HsyncI & VsyncI

X_OUT

I_LIL2

I_LIL3

V_IN= 0 V; X_OUTonly

V_IN= 0 V; X_INonly

V_OUT= V_DD

–

– 2.5

–

– 6

–

– 20

I_LOH1

Output High

leakage current

I_LOL1

R_U1

V_OUT= 0 V

Output Low

leakage current

–

– 3

Pull-up resistor

V_IN= 0 V; V_DD= 5 V ± 10%

Ports 3.7–3.4

R_U2

R_D

150

–

280

300

480

500

V_IN= 0 V; V_DD= 5 V ± 10%

RESET only

Pull-down

resistor

V_IN= 0 V; V_DD= 5 V ± 10%

HsyncI & VsyncI

I_DD1

Supply current

(note)

µA

V_DD= 5 V ± 10%

Operation mode; 12 MHz crystal

C1 = C2 = 22pF

I_DD2

V_DD= 5 V ± 10%

Idle mode; 12 MHz crystal

C1 = C2 = 22pF

I_DD3

100

150

V_DD= 5 V ± 10%

Stop mode

NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.

19-3

ELECTRICAL DATA

S3C8639/C863A/P863A

Table 19-3. Data Retention Supply Voltage in Stop Mode

(T_A= – 40 C to + 85 C)

Parameter

Symbol

V_DDDR

Conditions

Stop mode

Min

Typ

Max

Unit

Data retention

supply voltage

–

5.5

I_DDDR

Stop mode, V_DDDR= 2.0 V

Data retention

supply current

–

µA

NOTES:

1. During the oscillator stabilization wait time (t

), all CPU operations must be stopped.

WAIT

2. Supply current does not include drawn through internal pull–up resistors and external output current loads.

RESET

Oscillation

occurs

Stabilzation

Time

Stop Mode

Data Retention Mode

Normal

Operating

Mode

VDDDR

Execution of

STOP Instrction

RESET

WAIT

NOTE:

tWAIT is the same as 4096 x 16 x 1/f OSC.

Figure 19-1. Stop Mode Release Timing When Initiated by a Reset

Table 19-4. Input/Output Capacitance

(T_A= –40 C to + 85 C, V_DD= 0 V)

Parameter

Input

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

f = 1 MHz; unmeasured pins

are connected to V_SS

–

capacitance

C_OUT

C_IO

Output

capacitance

I/O capacitance

19-4

S3C8639/C863A/P863A

ELECTRICAL DATA

Table 19-5. A/D Converter Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.0 V to 5.5 V, V_SS= 0 V)

Parameter

Resolution

Symbol

Conditions

Min

–

Typ

Max

–

Unit

bit

V_DD= 5 V

Total accuracy

–

LSB

± 2

Conversion time = 5 ms

AV_REF= 5 V

Integral linearity error

ILE

–

± 1

AV_SS= 0 V

Differential linearity error

DLE

Offset error of top

Offset error of bottom

Conversion time ⁽¹⁾

EOT

EOB

t_CON

± 1

± 0.5

–

± 2

170

8 bit conversion

(3) n=1,4,8,16

40 x n/f_OSC

AV_SS

AV_REF

Analog input voltage

Analog input impedance

Analog reference voltage

Analog ground

–

1000

–

IAN

–

V_DD

V_SS+ 0.3

2.5

V_SS

–

REF

–

AV_REF= V_DD= 5V

AV_REF= V_DD= 3V

Analog input current

–

ADIN

Analog block Current ⁽²⁾

–

ADC

0.5

100

1.5

AV_REF= V_DD= 5V

500

When power down mode

NOTES:

1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.

is an operating current during the A/D conversion.

ADC

OSC

is the main oscillator clock.

19-5

ELECTRICAL DATA

S3C8639/C863A/P863A

Table 19-6. A.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.0 V to 5.5V)

Parameter

Noise Filter

Symbol

Conditions

Min

Typ

Max

Unit

t_NF1H

t_NF1L

INT0–2 and TM0CAP (RC

delay)

300

–

t_NF2

RESET only (RC delay)

1000

–

NF1L

NF2

tNF1H

0.8 VDD

0.2 VDD

Figure 19-2. Input Timing Measurement Points for P0.0–P0.2 and TM0CAP

19-6

S3C8639/C863A/P863A

ELECTRICAL DATA

Table 19-7. Oscillation Characteristics

(T_A= – 40 C + 85 C)

Oscillator

Clock Circuit

Conditions

Min

Typ

Max

Unit

V_DD= 3.0 V to 5.5 V

Main crystal or

ceramic

–

MHz

X_IN

X_OUT

V_DD= 3.0 V to 5.5 V

External clock

(main)

–

MHz

X_IN

X_OUT

NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot

select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.

Table 19-8. Oscillation Stabilization Time

(T_A= – 40 C + 85 C, V_DD= 3.0 V to 5.5 V)

Oscillator Test Condition

V_DD= 3.0 V to 5.5 V

Min

Typ

Max

Unit

Crystal

–

V_DD= 3.0 V to 5.5V

Ceramic

–

X_INinput high and low level width

External clock

500

(t_XH, t_XL

)

NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a

power-on occurs, or when Stop mode is released.

1/fx

tXH

XIN

VDD - 0.5 V

0.4 V

Figure 19-3. Clock Timing Measurement Points for X_IN

19-7

ELECTRICAL DATA

S3C8639/C863A/P863A

OUT

A = 0.2 VDD

B = 0.4 VDD

C = 0.6 VDD

D = 0.8 VDD

VSS

VIN

Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)

Table 19-9. Power-on Reset Circuit Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_ODLVD

Power-on reset release

voltage

2.7

–

5.5

V_LVD

t_r

Power-on reset detection

voltage

2.2

2.4

–

2.6

(1)

Power supply voltage

rise time

t_off

Power supply voltage off

time

–

I_DDPR

Power-on reset circuit

consumption current ⁽²⁾

100

150

V_DD= 5 V ± 10%

V_DD= 3 V

100

NOTES:

(= 5.46 ms at f /12MHz)

OSC

2. Current contained when power-on reset circuit is provided internally.

19-8

S3C8639/C863A/P863A

ELECTRICAL DATA

VDDLVD

LVD

off

Figure 19-5. Power-on Reset Timing

19-9

S3C8639/C863A/P863A

MECHANICAL DATA

20 MECHANICAL DATA

OVERVIEW

The S3C8639/C863A microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-

600) and a 44-QFP package (Samsung part number 44-QFP-1010B).

#42

#22

0-15

42-SDIP-600

#21

39.50 MAX

39.10 ± 0.2

0.50

0.1

1.778

(1.77)

1.00 0.1

NOTE: Dimensions are in millimeters.

Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)

20-1

MECHANICAL DATA

S3C8639/C863A/P863A

13.20 ± 0.3

10.00 ± 0.2

0-8

+ 0.10

- 0.05

0.15

0.10 MAX

44-QFP-1010B

#44

+ 0.10

0.35 - 0.05

0.05 MIN

2.05 ± 0.10

2.30 MAX

0.80

(1.00)

NOTE: Dimensions are in millimeters.

Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)

20-2

S3C8639/C863A/P863A

S3P863A OTP

21 S3P863A OTP

OVERVIEW

The S3P863A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

S3C8639/C863A microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed

by serial data format.

The S3P863A is fully compatible with the S3C8639/C863A, both in function and in pin configuration. Because of

its simple programming requirements, the S3P863A is ideal for use as an evaluation chip for the

S3C8639/C863A.

P3.7

P3.6

P3.5

P3.4

P3.3/AD3

P3.2/AD2

P3.1/AD1

P3.0/AD0

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3

P0.4/TM0CAP

P0.5

P0.6

P0.7

SDAT/P1.0/SDA1

SCLK/P1.1/SCL1

DD2

SS2

S3P863A

42-SDIP

(Top View)

P2.7/Csync-I (SOG)

Hsync-I

Vsync-I

Vsync-O

Hsync-O

DD1

OUT

/TEST (GND)

Clamp-O

SDA0

SCL0

RESET/RESET

P2.6/PWM6

P2.5/PWM5

P2.4/PWM4

P2.3/PWM3

P2.2/PWM2

P1.2

P2.0/PWM0

P2.1/PWM1

NOTE:

The bolds indicate an OTP pin name.

Figure 21-1. S3P863A Pin Assignments (42-SDIP Package)

21-1

S3P863A OTP

S3C8639/C863A/P863A

P3.2/AD2

P3.1/AD1

P3.0/AD0

P0.5

P0.6

P0.7

DD2

SDAT/P1.0/SDA1

SCLK/P1.1/SCL1

S3P863A

44-QFP

(Top View)

SS2

P2.7/Csync-I (SOG)

Hsync-I

Vsync-I

Vsync-O

Hsync-O

DD1

SS1

XOUT

PP/TEST (GND)

Clamp-O

SDA0

NOTE:

The bolds indicate an OTP pin name.

Figure 21-2. S3P863A Pin Assignments (44-QFP Package)

21-2

S3C8639/C863A/P863A

Main Chip

S3P863A OTP

Table 21-1. Descriptions of Pins Used to Read/Write the EPROM

During Programming

Pin Name

Pin No.

I/O

Function

P1.0

SDAT

9 (4)

I/O

Serial data pin. Output port when reading and input

port when writing. Can be assigned as a

Input/push-pull output port.

P1.1

SCLK

10 (5)

Serial clock pin. Input only pin.

V_PP(TEST)

TEST

15 (10)

Power supply pin for EPROM cell writing (indicates

that OTP enters into the writing mode). When 12.5

V is applied, OTP is in writing mode and when 5 V

is applied, OTP is in reading mode. (Option)

18 (13)

Chip Initialization

RESET

V_DD1/V_SS1

Logic power supply pin. V_DDshould be tied to +5 V

during programming.

11/12 (6/7)

NOTE: Parentheses indicate 44-QFP OTP pin number.

Table 21-2. Comparison of S3P863A and S3C8639/C863A Features

Characteristic S3P863A S3C8639/C863A

48-Kbyte EPROM

Program Memory

32/48-Kbyte mask ROM

3.0 V to 5.5V

Operating Voltage (V_DD

)

3.0 V to 5.5 V

V_DD= 5 V, V_PP(TEST)=12.5V

OTP Programming Mode

Pin Configuration

42SDIP, 44QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V_PP(TEST) pin of the S3P863A, the EPROM programming mode is entered. The

operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 21-3 below.

Table 21-3. Operating Mode Selection Criteria

V_DD

V_PP(TEST) REG/MEM Address (A15–A0)

R/W

Mode

5 V

0000H

0E3FH

EPROM read

12.5 V

EPROM program

EPROM verify

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

21-3

S3P863A OTP

S3C8639/C863A/P863A

D.C. ELECTRICAL CHARACTERISTICS

Table 21-4. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 3.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

I_LIH1

V_IN= V_DD

All input pins except X_IN

Input High

leakage current

–

µA

OUT

I_LIH2

I_LIH3

I_LIL1

V_IN= V_DDX_OUTonly

;

–

2.5

–

V_IN= V_DD

X_INonly

;

V_IN= 0 V; All input pins except X_IN

Input Low

– 3

leakage current

RESET , Hsync-I and Vsync-I

X_OUT

I_LIL2

I_LIL3

V_IN= 0 V; X_OUTonly

V_IN= 0 V; X_INonly

V_OUT= V_DD

–

– 2.5

–

– 6

–

– 20

I_LOH1

Output High

leakage current

I_LOL1

R_U1

V_OUT= 0 V

Output Low

leakage current

–

– 3

Pull-up resistor

V_IN= 0 V; V_DD= 5 V ± 10%

Port 3.7–3.4

R_U2

R_D

150

–

280

300

480

500

V_IN= 0 V; V_DD= 5 V ± 10%

RESET only

Pull-down

resistor

V_IN= 0 V; V_DD= 5 V ± 10%

Hsync-I and Vsync-I

I_DD1

Supply current

(note)

µA

V_DD= 5 V ± 10%

Operation mode; 12 MHz crystal

C1 = C2 = 22pF

I_DD2

V_DD= 5 V ± 10%

Idle mode; 12 MHz crystal

C1 = C2 = 22pF

I_DD3

100

150

V_DD= 5 V ± 10%

Stop mode

NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.

21-4

S3P863A-QZ [SAMSUNG]

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