S5N8943B [SAMSUNG]
G.Lite ADSL Analog Front End IC; 的G.lite ADSL模拟前端IC
| 型号： | S5N8943B |
| 厂家： | 
SAMSUNG |
| 描述： | G.Lite ADSL Analog Front End IC |
| 文件： | 总22页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S5N8943B
G.Lite
ADSL Analog Front End IC
Preliminary Information
(Revision 1.0)
July 2000
SAMSUNG ELECTRONICS CONFIDENTIAL PROPRIETARY
Copyright ©1999-2000 Samsung Electronics, Inc. All Rights Reserved
S5N8943B
G.Lite ADSL Analog Front End IC
Contents
Page
1 Overview...................................................................................... 3
1.1 General Description.............................................................. 3
1.2 Features................................................................................. 3
1.3 Absolute Maximum Ratings.................................................. 4
1.4 Electrical Specifications........................................................ 4
2 Signal description ......................................................................... 6
2.1 Functional Block Diagram.................................................... 6
2.2 I/O Pins Descriptions ............................................................ 7
2.3 Pin Configurations ................................................................ 9
3 Block Description....................................................................... 10
3.1 ADC/DAC............................................................................ 10
3.2 Tx/Rx LPF........................................................................... 10
3.3 Tx/Rx AGC......................................................................... 10
4 Digital Signal Interface ...............................................................11
4.1 Command Signal Interface..................................................11
4.2 Data Signal Interface.......................................................... 18
5 Application Circuit...................................................................... 19
5.1 ATU-R ................................................................................. 19
5.2 ATU-C ................................................................................. 20
6 Package Information.................................................................... 21
CONFIDENTIAL
Preliminary Information (Rev.1.0)
2
S5N8943B
G.Lite ADSL Analog Front End IC
1. OVERVIEW
This chapter provides an overview of the S5N8943B01 ADSL ATU-C & ATU-R
Analog Front End Chip.
1.1
General
Descriptions
The S5N8943B01 is Analog Front End IC designed for DMT based universal
ADSL(Asymmetric Digital Subscribe Line) modems with 0.35u fully CMOS
technology.
It has 25.875 ~ 138KHz Upstream channel and 142.312 ~ 552KHz bandwidth
Downstream channel. The S5N8943B01 includes AGC, LPF, ADC, DAC. The
AGC has 42dB gain 0.4dB step in RX mode and –24dB gain 2dB step in TX
mode with 12bit/8bit control bits. Anti alias LPF has 552KHz passband
frequency in RX path and 138KHz in TX path. Samsung’ s ADSL AFE chip
provides 14bit ADC at 2.208M, 4.416M or 8.832M sample rates and 14bit
4.416MHz, 8.832MHz DAC.
An 10bit DAC support VCXO control for timing recovery. The VCXO is divided
into a crystal driver at 35.328MHz.
1.2 Features
l
l
l
l
l
l
l
l
l
l
l
l
Integrated Analog Front End(AFE) for ADSL ATU-C & ATU-R
Complies with G.lite
Up to 552Kbit/s down stream and 138Kbit/s upstream channel
14bit 2.208MS/s, 4.416MS/s or 8.832MS/s ADC
14bit 4.416MHz or 8.832MHz DAC
5th-order Low Pass anti-alias Filter TX/RX paths
RX 42dB 0.4dB step gain range with 12bit control signal
TX -24dB 2dB step gain range with 8bit control signal
10bit 4KHz VCXO DAC
Fully 0.35um CMOS technology
3.3V Power supply operation
0.4W Power comsumption
CONFIDENTIAL
Preliminary Information (Rev.1.0)
3
S5N8943B
G.Lite ADSL Analog Front End IC
1.3 Absolute
Maximum Ratings
Symbol
VDD
Parameter
DC Supply Voltage
DC input Voltage
5V tolerant
Min
-0.3
-0.3
-0.3
-10
Typ
Max
3.8
Units
V
VIN
VDD+0.3
5.5
V
V
IIN
DC input Current
10
mA
TOPR
TSTG
Operation Temperature
Storage Temperature
-40
85
degree C
degree C
-40
125
1.4 Electrical
Specifications
Parameter
Min
Typ
Max Units
Notes/Conditions
General
Power Supply
3.0
3.3
3.6
V
Power Consumption
450
mW
Normal Operation
12bit Control
Rx Path
70
THD
SNR
70
AGC Gain Range
AGC Step Size
0
42
dB
dB
0.4
AGC Step Error
0.2
2
dB
AGC Input Range
LPF Cut Off Frequency
LPF Output Range
LPF Pass Band Ripple
LPF Stop Band Attenuation
Vppd
KHz
Vppd
dB
552
5th Butterworth
at 4.416MHz
2
-0.5
60
0.5
dB
TX Path
70
THD
SNR
70
AGC Gain Range
AGC Step Size
-24
0
dB
dB
8bit Control
2
AGC Step Error
0.2
2
dB
AGC Output Range
LPF Cut Off Frequency
LPF Pass Band Ripple
LPF Stop Band Attenuation
LPF Input Range
Vppd
KHz
dB
138
5th Chebyshev
at 276KHz
-0.5
24
0.5
2
dB
Vppd
ADC
CONFIDENTIAL
Preliminary Information (Rev.1.0)
4
S5N8943B
G.Lite ADSL Analog Front End IC
Resolution
14
13
bits
bits
Effective Number Of Bits
Sampling Rate
2.208
2.0
MHz Selectable 4.416MHz, 8.832MHz
Vppd
Full Scale Input Range
DAC
Resolution
14
bits
bits
Effective Number Of Bits
Sampling Rate
12
4.416
MHz
Vppd
Selectable 8.832MHz
Full Scale Output Range
2.0
VCXO DAC
Resolution
10
4
bits
KHz
V
Sampling Rate
Maximum Output Range
Minimum Output Range
2.5
0.5
V
CONFIDENTIAL
Preliminary Information (Rev.1.0)
5
S5N8943B
G.Lite ADSL Analog Front End IC
2. SIGNAL DESCRIPTION
2.1 Functional Block Diagram
TX_OUTP
TX_DATA
[13:0]
14bit DAC
TX LPF
TX AGC
TX_OUTN
MCLK
AUXCLK
CONT_DAX
10bit DAC
CBG
BANDGAP
&
VI REF
AUTO
TUNNING
SCLK
REXT
SEN
CONTROL
LOGIC &
REGISTER
SDIN
SDOUT
RESETN
RX_INP
RX_INN
RX_DATA
[13:0]
14bit ADC
RX LPF
RX AGC
RX_INPG
RX_INNG
Figure 2.1.1 S5N8943B01 Functional Block Diagram
CONFIDENTIAL
Preliminary Information (Rev.1.0)
6
S5N8943B
G.Lite ADSL Analog Front End IC
2.2 I/O Pins Description
Signal Name
Num
Type
I/O
Description
General Pins
System Reset. Active Low
RESETN
CS1
48
49
50
51
52
CMOS
CMOS
CMOS
CMOS
CMOS
I
I
I
I
I
Chip Select
Chip Select
CS0
TM1
Digital Interface Selection “0” = 14bits , “1”=7bits*2
“0” = RT , “1” = CO
TM0
DAC Interface
TX_DATA[13:0]
94~100,
1~7
CMOS
I
DAC 14bit Data Inputs
If TM1=1, TX_DATA[13:7] is invalid
MCLK
8
CMOS
CMOS
I
I
Master Clock 4.416MHz(Selectable 8.832M or 17.664M)
AUXCLK
11
In 7bits Data Interface mode, AUXCLK=MCLK/2
In 14bits Data Interface mode, pin is open or ground.
DAC Current Positive Output for TX path
TX_DACOP
TX_DACON
COMP_DAC
IREF_DAC
90
89
88
87
Analog
Analog
Analog
Analog
-
-
-
-
DAC Current Negative Output for TX path
Compensation Capacitor 0.1uF Connection for TX path
External Resistor 1.24k Connection
ADC Interface
RX_DATA[13:0]
RX_ADCIP
RX_ADCIN
BGR_ADC
12 ~ 25
28
CMOS
Analog
Analog
Analog
Analog
Analog
O
-
ADC 14bit Data Outputs ( If TM1=1, [13:7] is always low)
ADC Positive Input
29
-
ADC Negative Input
32
-
ADC Band gap Reference Output
ADC Top Reference Output
REFT_ADC
REFB_ADC
33
-
34
-
ADC Bottom Reference Output
DSP Interface
SCLK
SEN
44
45
46
47
CMOS
CMOS
CMOS
CMOS
I
I
Serial Data Clock
Serial Data Enable
Serial Data Output
Serial Data Input
SDOUT
SDIN
O
I
TX Pass Interface
TX_OUTP
TX_OUTN
TX_FINP
TX_FINN
78
77
85
86
Analog
Analog
Analog
Analog
-
-
-
-
Tx Analog Positive Output
Tx Analog Positive Output
Tx Filter Analog Positive Input
Tx Filter Analog Negative Input
RX Pass Interface
RX_INP
RX_INN
58
57
56
55
31
30
Analog
Analog
Analog
Analog
Analog
Analog
-
-
-
-
-
-
Rx Analog Positive Input
Rx Analog Negative Input
RX_INPG
RX_INNG
RX_FOUTP
RX_FOUTN
Rx Analog External -14dB Gain Positive Input
Rx Analog External -14dB Gain Negative Input
Rx Filter Analog Positive Output
Rx Filter Analog Negative Output
Voltage Reference
CONFIDENTIAL
Preliminary Information (Rev.1.0)
7
S5N8943B
G.Lite ADSL Analog Front End IC
TX_VCOM
RX_VCOM
CBG_REF
REXT_REF
80
64
68
67
Analog
Analog
Analog
Analog
-
-
-
-
TX Pass Common Mode Voltage
Rx Pass Common Mode Voltage
Bandgap Reference Compensation Capacitor 100pF
Reference Current External Resistor 6.8K
VCXO Interface
CONT_DAX
40
Analog
-
VCXO Control Voltage Output
(Only RT)
CO Pass (TM0 = “1”)
RX_AOUTP
RX_AOUTN
RX_FINN
60
61
62
63
81
82
83
84
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
-
-
-
-
-
-
-
-
Rx AGC Analog Positive Output
Rx AGC Analog Negative Output
Rx Filter Analog Negative Input
Rx Filter Analog Positive Input
Tx AGC Analog Positive Input
Tx AGC Analog Positive Input
Tx Filter Analog Negative Output
Tx Filter Analog Negative Output
RX_FINP
TX_AINP
TX_AINN
TX_FOUTN
TX_FOUTP
Power Supply
AVDD_DAC
ASUB_DAC
AVSS_DAC
DVDD_DAC
DVSS_DAC
AVDD_DAX
AVSS_DAX
AVDD_ADC
ASUB_ADC
AVSS_ADC
DVDD_ADC
DVSS_ADC
AVDD_TX
AVSS_TX
91
92
93
10
9
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Tx Analog DAC VDD
Tx Analog DAC SUB
Tx Analog DAC VSS
Tx Digital DAC VDD
Tx Digital DAC VSS
VCXO DAC Analog VDD
VCXO DAC Analog VSS
Rx Analog ADC VDD
Rx Analog ADC SUB
Rx Analog ADC VSS
Rx Digital ADC VDD
Rx Digital ADC VSS
Tx Path VDD
38
39
35
36
37
27
26
79
76
75
74
71
59
54
53
69
66
65
41
42
43
Tx Path VSS
ASUB_TX
TX Path SUB
AVDD_FAT
AVSS_FAT
AVDD_RX
AVSS_RX
Filter Auto Tuning VDD
Filter Auto Tuning VSS
Rx Filter VDD
Rx Filter VSS
ASUB_RX
AVDD_REF
AVSS_REF
ASUB_REF
DVDD_CTL
DSUB_CTL
DVSS_CTL
Rx Filter SUB
Reference VDD
Reference VSS
Reference SUB
Control Logic VDD
Digital Substrate VSS
Control Logic VSS
CONFIDENTIAL
Preliminary Information (Rev.1.0)
8
S5N8943B
G.Lite ADSL Analog Front End IC
2.3 Pin Configurations ( Top View)
TX_DATA6
1
TX_VCOM
80
TX_DATA5
2
AVDD_TX
79
TX_DATA4
3
TX_OUTP
78
TX_DATA3
4
TX_OUTN
77
TX_DATA2
5
AVSS_TX
76
TX_DATA1
6
ASUB_TX
75
TX_DATA0
7
AVDD_FAT
74
MCLK
8
NC
73
DVSS_DAC
9
NC
72
DVDD_DAC
10
AVSS_FAT
71
11 AUX_CLK
NC 70
RX_DATA0
12
AVDD_REF
69
RX_DATA1
13
CBG_REF
68
RX_DATA2
14
REXT_REF
67
RX_DATA3
15
RX_DATA4
16
RX_DATA5
17
RX_DATA6
18
RX_DATA7
19
RX_DATA8
20
RX_DATA9
21
RX_DATA10
22
RX_DATA11
23
RX_DATA12
24
RX_DATA13
25
DVSS_ADC
26
DVDD_ADC
27
RX_ADCIP
28
RX_ADCIN
29
RX_FOUTN
30
AVSS_REF
66
S5N8943B01
ASUB_REF
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RX_VCOM
RX_FINP
(100- QFP)
RX_FINN
RX_AOUTN
RX_AOUTP
AVDD_RX
RX_INP
RX_INN
RX_INPG
RX_INNG
AVSS_RX
ASUB_RX
TM0
TM1
CONFIDENTIAL
Preliminary Information (Rev.1.0)
9
S5N8943B
G.Lite ADSL Analog Front End IC
3. BLOCK DESCRIPTIONS
3.1 ADC / DAC
S5N8943B01 has a 14bit resolution ADC 2.208M/4.416M/8.832M sample
frequency. The input of ADC is fully differential 2.0Vppd Max. The ADC
transforms the signal into a digital 14bit output.
There are two type of DAC’ s in S5N8943B01. One is for TX. It is 14bit
4.416MHz/8.832MHz frequency. Samsung’ s DMT(S5N8944) transmit 14bit
parallel data to the AFE chip. The other DAC is for VCXO control. It has 10bit
resolution 4KHz frequency. Internal registers of S5N8943B01 transform 10bit
VCXO control serial data from DSP into 10bit parallel data. And VCXO output
analog signal CONT_DAX(Pin #40).
3.2 TX/RX LPF
3.2.1 RX FILTERS
The combination of the external filter ( an LC ladder filter typically ) with the
integrated low pass filter must provide:
-
-
-
DMT sidelobe and out of band ( anti-aliasing ) attenuation
Anti alias filter ( 60dB rejection @ image frequency )
On chip tuning circuit included.
3.2.2 TX FILTERS
The TX Filters act not only to suppress the DMT sidebands but also as
smoothing filters on the D/A converter’ s output to suppress the image spectrum.
For this reason they are realized in a time continuous approach and on chip
tuning circuit included
3.3 TX/RX AGC
TX AGC has 0~-24dB gains with 2dB step. It is controlled through 8bit serial
digital signal from DSP. Internal registers of Samsung AFE Chips transform
8bit parallel control data. It outputs 2Vppd fully differential signal to line driver.
RX AGC has low noise 0~42dB gains with 0.4dB step and It is controlled
through 12bit + 1MSB control signal. If 1MSB is high, another RX input pass
pin#55 RX_INNG #56 RX_INNP(external -14dB gain pass) is seclected. It inputs
2Vppd fully differential signal to RX LPF.
CONFIDENTIAL
Preliminary Information (Rev.1.0)
10
S5N8943B
G.Lite ADSL Analog Front End IC
4. DIGITAL SIGNAL INTERFACE
4.1 Command Signal Interface
This description hold for ATU-R (S5N8943B01).
The chip consists of four kinds of register map:
-
-
-
-
-
Power Control
Transmitter AGC
Receiver AGC
VCXO Control
Clock Selection
Serial interfaces use three pins:
-
-
-
-
Clock
Serial data input(25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy)
Serial data output(16 bit data)
Enable
Serial Data Configuration
Serial Data (SDAT)
D
U
M
M
Y
R
/
W
CS
ADDRESS
DATA
REGISTER
C
S
1
C
S
1
C
S
1
C
S
0
C
S
0
C
S
0
R
/
W
R
/
W
R
/
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
A
4
A
3
A
2
A
1
A
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X
X
X
P
C
7
T
A
7
P
C
6
T
A
6
P
C
5
T
A
5
P
C
4
T
A
4
P
C
3
T
A
3
P
C
2
T
A
2
P
C
1
T
A
1
P
C
0
T
A
0
PWR_CTL
TX_AGC
X
X
X
X
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W
R
A
1
R
A
1
R
A
1
C
S
1
C
S
0
R
/
W
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
RX_AGC
X
X
0
1
0
X
X
X
X
2
1
0
C
S
1
C
S
1
C
S
0
C
S
0
R
/
W
R
/
V
C
9
V
C
8
V
C
7
V
C
6
V
C
5
V
C
4
V
C
3
V
C
2
V
C
1
C
K
1
V
C
0
C
K
0
VCXO_CTL
CLK_SEL
X
X
X
X
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W
X = Don’ t care
R/W =0 -> Read
R/W =1 -> Write
CONFIDENTIAL
Preliminary Information (Rev.1.0)
11
S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1 Register Map
4.1.1.1 Power Control
The power on/off control of AFE blocks on this chip is set by the PWR_CTL register, (XX000), as
described below:
PWR_CTL Register (A4A3A2A1A0=XX000)
DATA
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
RESET
VALUE
0
0
0
0
0
0
0
0
Power Control is as follow.
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
HEX
DESCRIPCION
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0000
0001
0002
0004
0008
0010
0020
0040
0080
Normal Operation
N/A
N/A
TX DAC Power Down
TX Filter & AGC Power Down
RX ADC Power Down
Rx Filter Power Down
Rx AGC Power Down
VCXO DAC Power Down
Adding Power Down (based on upper power down)
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0003
000C
0070
00FF
N/A
TX Path Power Down
Rx Path Power Down
Whole Chip Power Down
CONFIDENTIAL
Preliminary Information (Rev.1.0)
12
S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1.2 Transmitter AGC
The main functions of the TX path are controlled by the TX_AGC registers, as described below:
TX_AGC Register (A4A3A2A1A0=XX001)
DATA
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
RESET
VALUE
0
0
0
1
0
0
0
1
TA[7:0] TX path output attenuator gain setting. 0 to –24dB attenuation in 2 dB steps. (default is 0 dB).
TA[7]
TA[6]
TA[5]
TA[4]
TA[3]
TA[2]
TA[1]
TA[0]
HEX
GAIN(dB)
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0011
0012
0014
0018
0021
0022
0024
0028
0041
0042
0044
0048
0081
0082
0084
0088
0
-2
-4
-6
-6
-8
-10
-12
-12
-14
-16
-18
-18
-20
-22
-24
CONFIDENTIAL
Preliminary Information (Rev.1.0)
13
S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1.3 Recieve AGC
The main functions of the RX path are controlled by the RX_AGC register, as described below:
RX_AGC Register (A4A3A2A1A0=XX010)
DATA
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RA RA RA
RA9 RA8 RA7 RA6 RA4 RA4 RA3 RA2 RA1 RA0
12 11 10
RESET
VALUE
0
0
0
0
0
1
0
0
1
0
0
0
0
RA[11:0]: Receive path input gain setting 0 to 42dB gain in 0.4 dB steps. (default is 0 dB).
RA[12] is “ 1” ,the external attenuation gain(ex, –14dB) path pin#55 RX_INNG #56 RX_INPG will be
enable. RA[12] should only be utilized the short line conditions.
RA RA RA RA RA RA RA RA RA RA RA RA RA
HEX
GAIN(dB)
[12] [11] [10]
[9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0000 ~ 1111
0000 ~ 1111
0000 ~ 1111
1090~109F -14.0~-8.0
1110~111F
1210~121F
0090
-8.0~-2.0
-2.0~4.0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0091
0.4
0092
0.8
0093
1.2
0094
1.6
0095
2.0
0096
2.4
0097
2.8
0098
3.2
0099
3.6
009A
4.0
009B
4.4
009C
4.8
009D
5.2
009E
5.6
009F
6.0
0000 ~ 1111
0000 ~ 1111
0000 ~ 1111
0000 ~ 1111
0000 ~ 1111
0000 ~ 1111
0110~011F
6.0~12.0
0210~021F 12.0~18.0
0410~041F 18.0~24.0
0810~081F 24.0~30.0
0820~082F 30.0~36.0
0840~084F 36.0~42.0
CONFIDENTIAL
Preliminary Information (Rev.1.0)
14
S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1.4 VCXO Control
The VCXO DAC is 10-bit voltage-mode DAC designed to be monotonic and intended to be
operated at a 4 kHz update rate. In order to update the DAC, the user must write to the VCXO register
through the serial port. The individual bit definitions are given below.
VCXO_CTL Register (A4A3A2A1A0=XX011)
DATA
NAME
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VC9 VC8 VC7 VC6 VC4 VC4 VC3 VC2 VC1 VC0
RESET
VALUE
1
0
0
0
0
0
0
0
0
0
VC[9:0]: VCXO DAC 10-bit word. The DAC nominal output voltages for extreme and mid-scale
codes are as follows.
VC[9:0] = 0000000000 = 0.5 V
VC[9:0] = 1000000000 = 1.5 V (mid-range)
VC[9:0] = 1111111111 = 2.5 V
A general expression for the DAC output voltage is
0.5 V + (CODE / 1024) X (2.0 V)
where CODE is the decimal integer value of the 10-bit word formed by VCXO[9:0].
CONFIDENTIAL
Preliminary Information (Rev.1.0)
15
S5N8943B
G.Lite ADSL Analog Front End IC
4.1.1.5 Clock Selection
Main functions of Clock Selection are frequency selection of each MCLK/AUXCLK/ADC. The individual
bit definitions are given below.
CLK_SEL Register (A4A3A2A1A0=XX100)
DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
CK1 CK0
RESET
VALUE
0
0
TM1, CK[1:0] : Clock Selection has eight possible clocking configuration as follow.
TM1
2 Phase
OFF
OFF
OFF
OFF
ON
CK1
0
CK0
0
HEX
0000
0001
0002
0003
0000
0001
0002
0003
MCLK
AUXCLK
DAC
ADC
0
0
0
0
1
1
1
1
4.416 MHz
4.416 MHz
8.832MHz
8.832MHz
8.832MHz
8.832MHz
17.664MHz
17.664MHz
0
0
0
0
4.416 MHz 2.208 MHz
4.416 MHz 4.416 MHz
8.832MHz 4.416 MHz
8.832MHz 8.832MHz
0
1
1
0
1
1
0
0
4.416 MHz 4.416 MHz 4.416 MHz
4.416 MHz 4.416 MHz 2.204 MHz
8.832MHz 8.832MHz 8.832 MHz
8.832MHz 8.832MHz 4.416 MHz
ON
0
1
ON
1
0
ON
1
1
CONFIDENTIAL
Preliminary Information (Rev.1.0)
16
S5N8943B
G.Lite ADSL Analog Front End IC
4.1.2 Serial Data Interface
4.1.2.1 Physical Interface
Serial interfaces use three pins:
-
-
-
Clock
Serial data (25-bit: 2bit cs + 5bit address + 1bit r/w + 16 bit data + 1bit dummy)
Enable
AFE_SCLK
S 5 N 8 9 4 4
( D M T )
S 5 N 8 9 4 3 B 0 1
(AFE)
AFE_SEN
AFE_SDIN
4.1.2.2 Waveform
TPWL
TPWH
TH2TSU2
TH1 TPW
TSU1
TCYC
SEN
SCLK
SDIN
Dummy
CS1 CS0
A4
A3
A2
A1
A0
R/W D15 D14
D1
D0
TD3
TD4
D15 D14
D1
D0
SDOUT
Parameter
Symbol
TCYC
TPWH
TPWL
TSU1
TH1
Min
Typ
905
Max
Unit
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
SCLK Clock Period
SCLK High Time
SCLK Low Time
452
452
30
SEN Low To SCLK High
SCLK High To SEN High
SEN Inactive Pulse Time
SDIN Setup time
15
TPW
905
15
TSU2
TH2
SDIN Hold time
15
SCLK low to SDOUT delay
SEN inactive to SDOUT HiZ
TD3
30
30
TD4
CONFIDENTIAL
Preliminary Information (Rev.1.0)
17
S5N8943B
G.Lite ADSL Analog Front End IC
4.2 Data Interface
4.2.1 Physical Interface
l
l
l
ADC and DAC data transmission between S5N8943B01 and S5N8944
Parallel Interface(S5N8944) : 29 pin (14 ADC bit data, 14 DAC bit data, MCLK)
Parallel Interface
: 16 pin ( 7 ADC bit data, 7 DAC bit data, MCLK,AUXCLK)
TX_DATA[13:0]
MCLK
S5N8944
(DMT)
S5N8943B01
(AFE)
AUXCLK
RX_DATA[13:0]
4.2.2 Waveform
TCYC
TD
TPWH
TPWL
TD
MCLK
TX_DATA[13:0]
RX_DATA[13:0]
TX_DATA[13:0]
TX_DATA[13:0]
TSU
TX_DATA[13:0]
TH
TX_DATA
RX_DATA
RX_DATA[13:0]
Figure 4.2.1 Waveform of 14bit parallel interface (TM1=0)
TSU2
TD
TH2
MCLK
AUXCLK
TX_DATA
RX_DATA
N- 1
TX_DATA[6:0]
N- 1
TX_DATA[13:7]
N
TX_DATA[6:0]
N
TX_DATA13:7]
N- 1
RX_DATA[6:0]
N- 1
RX_DATA[13:7]
N
RX_DATA[6:0]
N
RX_DATA[13:7]
Figure 4.2.2 Waveform of 7bit parallel interface (TM1=1)
Parameter
Symbol
TCYC
TPWH
TPWL
TD
Min
Typ
226
113
113
Max
10
Unit
nS
nS
nS
nS
nS
nS
nS
nS
Note
MCLK Clock Period
MCLK High Time
MCLK=4.416MHz
MCLK=4.416MHz
MCLK=4.416MHz
MCLK Low Time
DATA Delay after MCLK
RX_DATA setup to MCLK
RX_DATA hold to MCLK
AUXCLK setup to MCLK
AUXCLK hold to MCLK
TSU
30
84
MCLK=4.416MHz
MCLK=4.416MHz
TH
TSU2
TH2
10
10
CONFIDENTIAL
Preliminary Information (Rev.1.0)
18
S5N8943B
G.Lite ADSL Analog Front End IC
5. Application Circuit
5.1 ATU-R
P1
P2
P3
P4
P8
P9
P10
0.1u
0.1u
0.0375k
0.0375k
1.24k
1k
1k
10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u
10u 0.1u 10u 0.1u 10u 0.1u
G1
G2
G3
G4
G8
G9
G10
0.1u
G1
P1
DA<13:0>
1u
1
2
3
4
5
6
7
8
9
TX_DATA6
TX_DATA5
TX_DATA4
TX_DATA3
TX_DATA2
TX_DATA1
TX_DATA0
MCLK
TX_VCOM
80
39n
39n
TX_OUTP
TX_OUTN
AVDD_TX
TX_OUTP
TX_OUTN
79
78
77
P10
5.1k
5.1k
AVSS_TX
ASUB_TX
76
75
G10
P9
MCLK
DVSS_DAC
G2
P2
AVDD_FAT
NC
74
73
72
71
10
DVDD_DAC
AUXCLK
NC
AVSS_FAT
P9
P8
11
AUXCLK
NC
70
AVDD_REF
CBG_REF
REXT_REF
69
68
67
100p
6.8k
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
RX_DATA0
RX_DATA1
RX_DATA2
RX_DATA3
RX_DATA4
RX_DATA5
RX_DATA6
RX_DATA7
RX_DATA8
RX_DATA9
RX_DATA10
RX_DATA11
RX_DATA12
RX_DATA13
DVSS_ADC
S5N8943B01
(100QFP)
G8
1u
AVSS_REF
ASUB_REF
RX_VCOM
RX_FINP
66
65
64
63
62
61
60
AD<13:0>
1k
1k
1k
1k
RX_FINN
RX_AOUTN
RX_AOUTP
P7
AVDD_RX
RX_INP
59
58
57
56
55
39n
39n
39n
39n
RX_INP
RX_INN
RX_INN
RX_INPG
RX_INNG
G3
P3
27
28
29
30
DVDD_ADC
RX_ADCIP
RX_ADCIN
RX_FOUTN
G7
4.3k
4.3k
AVSS_RX
ASUB_RX
TM0
54
53
52
51
0.1u
0.1u
TM1
P6
G6
P4
P5 G5
P6 G6
P5
P6
P7
10u 0.1u 10u 0.1u 10u 0.1u
10u 0.1u 10u 0.1u 10u 0.1u
G4
G5
G6
G7
SCLK
SEN
SDOUT
SDIN
System Interface
Preliminary Information (Rev.1.0)
CONFIDENTIAL
19
S5N8943B
G.Lite ADSL Analog Front End IC
5.2 ATU-C
P1
P2
P3
P4
P8
P9
P10
0.1u
0.1u
0.0375k
0.0375k
1.24k
1k
1k
10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u
10u 0.1u 10u 0.1u 10u 0.1u
G1
G2
G3
G4
G8
G9
G10
J2J1
0.1u
G1
P1
J6J5 J7J8 J4J3
DA<13:0>
1u
1
2
3
4
5
6
7
8
9
TX_DATA6
TX_DATA5
TX_DATA4
TX_DATA3
TX_DATA2
TX_DATA1
TX_DATA0
MCLK
TX_VCOM
80
39n
39n
TX_OUTP
TX_OUTN
AVDD_TX
TX_OUTP
TX_OUTN
79
78
77
P10
5.1k
5.1k
AVSS_TX
ASUB_TX
76
75
G10
P9
MCLK
DVSS_DAC
G2
P2
AVDD_FAT
NC
74
73
72
71
10
DVDD_DAC
AUXCLK
NC
AVSS_FAT
11
AUXCLK
G9
P8
NC
70
AVDD_REF
CBG_REF
REXT_REF
69
68
67
100p
6.8k
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
RX_DATA0
RX_DATA1
RX_DATA2
RX_DATA3
RX_DATA4
RX_DATA5
RX_DATA6
RX_DATA7
RX_DATA8
RX_DATA9
RX_DATA10
RX_DATA11
RX_DATA12
RX_DATA13
DVSS_ADC
S5N8943B01
(100QFP)
1u
G8
AVSS_REF
ASUB_REF
RX_VCOM
RX_FINP
66
65
64
63
62
61
60
AD<13:0>
1k
1k
1k
1k
J1
J2
J6
J5
RX_FINN
RX_AOUTN
RX_AOUTP
P7
AVDD_RX
RX_INP
59
58
57
56
55
39n
39n
39n
39n
RX_INP
RX_INN
RX_INN
RX_INPG
RX_INNG
G3
P3
27
28
29
30
DVDD_ADC
RX_ADCIP
RX_ADCIN
RX_FOUTN
G7
4.3k
4.3k
AVSS_RX
ASUB_RX
TM0
54
53
52
51
0.1u
0.1u
TM1
P6
J7
J8
J4
J3
G6
P4
P5 G5
P6 G6
P5
P6
P7
10u 0.1u 10u 0.1u 10u 0.1u
10u 0.1u 10u 0.1u 10u 0.1u
G4
G5
G6
G7
SCLK
SEN
SDOUT
SDIN
System Interface
CONFIDENTIAL
Preliminary Information (Rev.1.0)
20
S5N8943B
G.Lite ADSL Analog Front End IC
6. Package Information (100QFP-1420C)
CONFIDENTIAL
Preliminary Information (Rev.1.0)
21
S5N8943B
G.Lite ADSL Analog Front End IC
Revision History
Revision
No.
Date
Description
S5N8943B (Rev.1) Released.
2000-07-20
1.0
IMPORTANT NOTICE
The information furnished by Samsung Electronics in this document is belived to be accurate
and reliable. However, no resposibility is assumed by Samsung Electronics for its use, nor for
any infringements of patents or other rights of third parties resulting from its use. No license is
granted under any patents or patent rights of Samsung Electronics. Samsung Electronics
reserves the right to make changes to its products or to discontinue any semiconductor product
or service without notice, and advises its customers to obtain the latest version of relevant
information to verify, before placing orders, that the information being relied on is current and
complete.
For More Information
Tel: (82)-(31)-209-8301, Fax: (82)-(31)-209-8309
E-mail: kimil@sec.samsung.com
http://www.intl.samsungsemi.com
Copyright ©2000 Samsung Electronics, Inc. All Rights Reserved
CONFIDENTIAL
Preliminary Information (Rev.1.0)
22
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