S5PV210AA0-LA40_技术文档

S5PV210AA0-LA40

USER'S MANUAL

S5PV210X

RISC Microprocessor

Sep, 15, 2009

Preliminary REV 0.01

Confidential Proprietary of Samsung Electronics Co., Ltd

Tel:021-58998693

S5PV210AA0-LA40

PRODUCT OVERVIEW

1 ARCHITECTURAL OVERVIEW

S5PV210 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones

and general applications, and integrates an ARM Cortex-A8 which implements the ARM architecture V7-A with

supporting numerous peripherals.

To provide optimized Hardware (H/W) performance for the 3G and 3.5G communication services, S5PV210

adopts 64-bit internal bus architecture and includes many powerful hardware accelerators for tasks such as

motion video processing, display control and scaling. Integrated Multi Format Codec (MFC) supports encoding

and decoding of MPEG-1/2/4, H.263, H.264 and decoding of VC1, Divx. This Hardware accelerators support real-

time video conferencing and Analog TV out, HDMI for NTSC and PAL mode

The S5PV210 has an optimized interface to external memory capable of sustaining the demanding memory

bandwidths required in high-end communication services. The memory system has Flash/ ROM external memory

ports for parallel access and DRAM port for high bandwidth. DRAM port can be configured to support LPDDR1

(=mobile DDR), DDR2 or LPDDR2.

Flash/ROM Port supports NAND Flash, NOR-Flash, OneNAND, SRAM and ROM type external memory.

To reduce total system cost and enhance overall functionality, S5PV210 includes many hardware peripherals

such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI, CSI-2, System Manager for power

management, ATA I/F, 4 UART, 24-channel DMA, 4 Timers, General I/O Ports, 3 IIS, S/PDIF, 3 IIC-BUS

interface, 3 HS-SPI, USB Host 2.0, USB OTG 2.0 operating at high speed (480Mbps), 4 SD Host & High Speed

Multi-Media Card Interface and 4 PLLs for clock generation.

Package on Package (POP) option with MCP is available for small form factor applications.

Salient features of S5PV210 are summarized below:

1.1-1

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S5PV210AA0-LA40

2 FEATURES

This section summarizes the features of the S5PV210. Figure 1.1- 1 shows an overall block diagram of the

S5PV210.

System Peripheral

CPU Core

Multimedia

RTC

CortexA8

12MP Camera IF / MIPI CSI-2

PLL x 4

32KB/32KB I/D cache

Timer with PWM (4ch)

Watchdog Timer

DMA (24ch)

800MHz/1GHz @ 1.1V/1.2V

1080p 30fps MFC

Codec – H.263/H.264/MPEG4

Decoder – MPEG2/VC-1/Divx

512KB

NEON

L2 cache

Keypad (14x8)

2D VG / 3D Graphics engine

TS-ADC (12bit/10ch)

NTSC / PAL TV out

& HDMI

Connectivity

Audio IF

128KB

RAM

64KB

ROM

JPEG Codec

IIS x3 / PCM x 3

S/PDIF / AC97

TFT LCD controller

XGA resolution

Multi layer AHB/AXI Bus

Storage IF

Crypto

Engines

Audio

DSP

HSMMC/SD x 4

Memory Interface

ATA

SRAM / ROM

Connectivity

USB Host2.0 / OTG 2.0

(Flex) OneNAND

Power

Management

UART x 4

IIC x 3

SLC / MLC NAND

with 16bit ECC

HS-SPI x 3

Modem IF

Clock gating /

Power gating /

Dynamic Voltage

Frequency Scaling

LPDDR1 / OneDRAM

LPDDR2 / DDR2

GPIO

Figure 1.1- 1 S5PV210 Block Diagram

1.1-2

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S5PV210AA0-LA40

3 FEATURES SUMMARY

•

ARM Cortex^TM-A8 based CPU Subsystem with NEON

♦

32/32KB I/D Cache, 512KB L2 Cache

Operating frequency up to 800MHz at 1.1V, 1GHz at 1.2V

64-bit Multi-layer bus architecture

♦

MSYS domain for ARM Cortex^TM-A8, 3D engine, Multi Format Codec and Interrupt Controller

Operating frequency up to 200MHz at 1.1V

DSYS domain mainly for Display IPs such as LCD controller, Camera interface, TVout and for MDMA

Operating frequency up to 166MHz at 1.1V

PSYS domain mainly for other system component such as system peripherals, external memory interface,

peri DMAs, connectivity IPs, and Audio interfaces.

Operating frequency up to 133MHz at 1.1V

AUDIO domain for low-power audio play

♦

•

Advanced power management for mobile applications

64KB ROM for secure booting and 128KB RAM

8-bit ITU 601/656 Camera Interface support horizontal size up to 4224 pixels for scaled and 8192 pixels for

un-scaled resolution

•

Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30fps and

decoding of MPEG-2/VC1/Divx video up to 1080p@30fps.

•

JPEG codec support up to 80Mpixels/s

3D Graphics Acceleration with Programmable Shader up to 89M triangles/s and 1000Mpixels/s

1/2/4/8 bpp Palletized or 8/16/24bpp Non-Palletized Color-TFT recommend up to XGA resolution.

TV-out and HDMI interface support for NTSC and PAL mode with image enhancer

MIPI-DSI and MIPI-CSI interface support

1 AC-97 audio codec interface and 3-channel PCM serial audio interface

3 24-bit I2S interface support

1 TX only S/PDIF interface support for digital audio

3 I2C interface support

3 SPI support

4 UART which support 3Mbps port for Bluetooth 2.0

On-chip USB 2.0 OTG supporting high speed (480Mbps, on-chip transceiver)

On-chip USB 2.0 Host supporting

Asynchronous Modem Interface support

4 SD/SDIO/HS-MMC interface support.

ATA/ATAPI-6 standard interface support

24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)

1.1-3

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•

Supports 14x8 key matrix

10-channel 12-bit multiplexed ADC

Configurable GPIOs

Real time clock, PLL, timer with PWM and watch dog timer

System timer support for accurate tick time in power down mode except sleep mode

Memory Subsystem

♦

Asynchronous SRAM/ROM/NOR Interface with x8 or x16 data bus

NAND Interface with x8 data bus

Muxed/Demuxed OneNAND Interface with x16 data bus

LPDDR1 Interface with x16 or x32 data bus (266~400Mbps/pin DDR)

DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR)

LPDDR2 interface (400Mbps/pin DDR)

3.1 MICROPROCESSOR

•

The ARM Cortex^TM-A8 processor is the first application processor based on the ARMv7 architecture.

With the ability to scale in speed from 600MHz to greater than 1GHz, the ARM Cortex^TM-A8 processor meets

the requirements for power-optimized mobile devices needing operation in less than 300mW; and

performance-optimized consumer applications requiring 2000 Dhrystone MIPS.

•

ARM's first superscalar processor featuring technology for enhanced code density and performance,

NEONTM technology for multimedia and signal processing, and Jazelle® RCT technology for efficient support

of ahead-of-time and just-in-time compilation of Java and other byte code languages.

ARM Cortex^TM-A8 Features

♦

Thumb-2 technology for greater performance, energy efficiency, and code density

NEON^TMsignal processing extensions

Jazelle RCT Java-acceleration technology

TrustZone technology for secure transactions and DRM

13-stage main integer pipeline

10-stage NEON^TMmedia pipeline

Integrated L2 Cache using standard compiled RAMs

Optimized L1 caches for performance and power

1.1-4

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3.2 MEMORY SUBSYSTEM

•

High bandwidth Memory Matrix subsystem

Two independent external memory ports (1 x16 Static Hybrid Memory port and 2 x32 DRAM port)

Matrix architecture increases overall bandwidth with the simultaneous access capability

♦

SRAM/ROM/NOR Interface

∗ x8 or x16 data bus

∗ Address range support: 23-bit

∗ Supports asynchronous interface

∗ Supports byte and half-word access

♦

OneNAND Interface

∗ x16 data bus

∗ Address range support: 16-bit

∗ Supports byte and half-word access

∗ Supports 2KB page mode for OneNAND, 4KB page mode for Flex OneNAND

∗ Supports dedicated DMA

♦

NAND Interface

∗ Support industry standard NAND interface

∗ x8 data bus

LPDDR1 Interface

∗ x32 data bus with 400Mbps/pin double data rate (DDR)

∗ 1.8V interface voltage

∗ Density support up to 4-Gb per port (2CS)

♦

DDR2 Interface

∗ x32 data bus with 400Mbps/pin double data rate (DDR)

∗ 1.8V interface voltage

∗ Density support up to 1-Gb per port (2CS, when 4bank DDR2)

∗ Density support up to 4-Gb per port (1CS, when 8bank DDR2)

LPDDR2 interface

∗ x32 data bus with up to 400Mbps/pin

∗ 1.2V interface voltage

∗ Density support up to 4-Gb per port (2CS)

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3.3 MULTIMEDIA

•

Camera Interface

Multiple input support

♦

y

ITU-R BT 601/656 mode

DMA (AXI 64bit interface) mode

MIPI (CSI) mode

♦

Multiple output support

y

DMA (AXI 64bit interface) mode

Direct FIFO mode

♦

DZI (Digital Zoom In) capability

Multiple camera input support

Programmable polarity of video sync signals

Input horizontal size support up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution

Image mirror and rotation (X-axis mirror, Y-axis mirror, 90°, 180° and 270° rotation)

Various image format generation

Capture frame control support

Image effect support

•

Multi-Format video Codec (MFC)

♦

ITU-T H.264, ISO/IEC 14496-10

y

Decoding support Baseline / Main / High Profile Level 4.0 except FMO(Flexible Macro-block

Ordering), ASO (Arbitrary Slice Ordering) and RS (Redundant Slice)

y

Encoding support Baseline / Main / High Profile except FMO(Flexible Macro-block Ordering), ASO

(Arbitrary Slice Ordering) and RS (Redundant Slice)

♦

ITU-T H.263 Profile level 3

y

Decoding support Profile3, restricted up to SD resolution 30fps (H.263 Annexes to be supported)

- Annex I : Advanced Intra Coding

- Annex J : De-blocking (in-loop) filter

- Annex K : Slice Structured Mode without FMO & ASO

- Annex T : Modified Quantization

- Annex D : Unrestricted Motion Vector Mode

- Annex F : Advanced Prediction Mode except overlapped motion compensation for luminance

y

Encoding support Baseline Profile (support customer size upto 1920x1088)

♦

ISO/IEC 14496-2 MPEG-4 and DivX

y

Decoding support MPEG-4 Simple / Advanced Simple Profile Level5

Decoding support DivX Home Theater Profile (version 3.xx, 4.xx, 5.xx & 6.1), Xvid

Encoding support MPEG-4 Simple / Advanced Simple Profile

ISO/IEC 13818-2 MPEG-2

1.1-6

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y

Decoding support Main Profile High level

Decoding support MPEG-1 except D-picture

♦

SMPTE 421M VC-1

Decoding support Simple Profile Medium Level / Main Profile High Level / Advanced Profile Level4

y

•

JPEG Codec

♦

Compression/decompression up to 65536x65536.

Support format of compression

* Input raw image: YCbCr4:2:2 or RGB565

* Output JPEG file: Baseline JPEG of YCbCr4:2:2 or YCbCr4:2:0

♦

Support format of decompression (Refer to chapter 9.4)

* Input JPEG file: Baseline JPEG of YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0, gray

* Output raw image: YCbCr4:2:2 or YCbCr4:2:0

Support general-purpose color-space converter.

•

3D Graphic Engine

♦

3D graphics, vector graphics and video encode and decode supported on common hardware

Tile based architecture

♦

Universal Scalable Shader Engine – multi-threaded engine incorporating Pixel and Vertex Shader

functionality

♦

Advanced Shader Feature Set – in excess of Microsoft VS3.0, PS3.0 & OGL2.0

♦

Industry standard API support – Direct3D Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, OpenMax

Fine grained task switching, load balancing and power management

♦

Advanced geometry DMA driven operation for minimum CPU interaction

Programmable high quality image anti-aliasing

Fully virtualised memory addressing for OS operation in a unified memory architecture

•

Analog TV interface

Out video format: NTSC-M/NTSC-J/NTSC4.43/PAL-B, D, G, H, I/PAL-M/PAL-N/PAL-Nc/PAL-60

compliant

♦

Support input format: ITU-R BT.601 (YCbCr 4 :4 :4)

Support 480i/p and 576i resolution

Support Composite/S-Video/Component interface

Digital TV Interface

♦

High Definition Multimedia Interface (HDMI) 1.3

Support up to 1080p 60Hz and 8-channel/112kHz/24-bit audio

Support for 480p, 576p, 720p, 1080i (cannot support 480i)

Support for HDCP v1.1

1.1-7

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•

Rotator

♦

Supported image format: YCbCr422 (interleave), YCbCr420(non-interleave), RGB565 and

RGB888(unpacked)

♦

Supported rotate degree: 90, 180, 270, flip vertical and flip horizontal

Video processor

♦

Support BOB / 2D-IPC mode

Produce YCbCr 4:4:4 outputs to help MIXER to blend video and graphics

1/4X to 16X vertical scaling with 4-tap/16-phase poly-phase filter

1/4X to 16X horizontal scaling with 8-tap/16-phase poly-phase filter

Support Pan&Scan, Letterbox, and NTSC/PAL conversion using scaling

Flexible scaled video positioning within display area

Support 1/16 pixel resolution Pan&Scan mode

Flexible post video processing

* Color saturation, Brightness/Contrast enhancement, Edge enhancement

* Color space conversion between BT.601 and BT.709

Video input source size upto 1920x1080

♦

•

Video Mixer

♦

Support overlapping & blending input video & graphic layers

Support 480i/p, 576i/p, 720p and 1080i/p display size

Support 4 layers (1 video layer, 2 graphic layer, 1 background layer)

TFT-LCD Interface

♦

Support 24/18/16-bpp parallel RGB Interface LCD

Support 8/6 bpp serial RGB Interface

Support Dual i80 Interface LCD

1/2/4/8bpp Palletized or 8/16/24-bpp Non-Palletized Color-TFT support

Typical actual screen size: 1024x768, 800x480, 640x480, 320x240, 160x160, and others

Virtual image up to 16M pixel (4K pixel x4K pixel)

Support 5 Window Layer for PIP or OSD

Real-time overlay plane multiplexing

Programmable OSD window positioning

16-level alpha blending

ITU-BT601/656 format output

1.1-8

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3.4 AUDIO SUBSYSTEM

•

Audio processing is progressed by RP(Reconfigurable Processor)

Low power audio subsystem

♦

5.1ch I2S with 32-bit-width 64-depth FIFO

128KB audio play output buffer

HW mixer mixes primary sound and secondary sound.

1.1-9

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3.5 CONNECTIVITY

•

PCM Audio Interface

♦

16-bit mono audio I/F

Master mode only

Support 3 port PCM interface

•

AC97 Audio Interface

♦

Independent channels for stereo PCM In, stereo PCM Out, mono MIC In.

16-bit stereo (2-channel) audio.

Variable sampling rate AC97 Codec interface (48kHz and below)

Support AC97 Full Specification

•

SPDIF Interface (TX only)

♦

Linear PCM up to 24-bit per sample support

Non-Linear PCM formats such as AC3, MPEG1 and MPEG2 support

2x24-bit buffers, which is alternately filled with data

I2S Bus Interface

♦

3 IIS-bus for the audio-codec interface with DMA-based operation

Serial, 8/16/24-bit per channel data transfers

Supports IIS, MSB-justified and LSB-justified data format

Support PCM 5.1 channel

Various bit clock frequency and codec clock frequency support

∗ 16, 24, 32, 48 fs of bit clock frequency

∗ 256, 384, 512, 768 fs of codec clock

♦

Support 1 port for 5.1ch I2S (in Audio Subsystem) and 2 port for 2ch I2S

•

Modem Interface

♦

Asynchronous direct/indirect 16-bit SRAM-style interface

On-chip 16KB dual-ported SRAM buffer for direct interface

I2C Bus Interface

♦

3 Multi-Master IIC-Bus

Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard

mode

♦

Up to 400 Kbit/s in the fast mode

•

ATA Controller

Compatible with the ATA/ATAPI-6 standard

♦

1.1-10

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•

UART

♦

4 UART with DMA-based or interrupt-based operation

Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive

Rx/Tx independent 256-Byte FIFO for UART0, 64-Byte FIFO for UART1 and 16-Byte FIFO for UART2/3

Programmable baud rate

Supports IrDA 1.0 SIR (115.2Kbps) mode

Loop back mode for testing

Non-integer clock divides in Baud clock generation (BRM)

•

USB OTG 2.0

♦

Complies with the USB OTG 2.0

Supports high speed up to 480Mbps

On-chip USB transceiver

USB Host 2.0

♦

Complies with the USB Host 2.0

Supports high speed up to 480Mbps

On-chip USB transceiver

HS-MMC/SDIO Interface

♦

Multimedia Card Protocol version 4.0 compatible (HS-MMC)

SD Memory Card Protocol version 2.0 compatible

DMA based or Interrupt based operation

128 word FIFO for Tx/Rx

4 port HS-MMC or 4 port SDIO

•

SPI Interface

♦

3 Serial Peripheral Interface Protocol version 2.11 compatible

Rx/Tx independent 64-Word FIFO for SPI0 and 16-Word FIFO for SPI1/2

DMA-based or interrupt-based operation

GPIO

♦

237 multi-functional input/ output ports

Controls 178 External Interrupts

GPA0: 8 in/out port – 2xUART with flow control

GPA1: 4 in/out port – 2xUART without flow control or 1xUART with flow control

GPB: 8 in/out port – 2x SPI

GPC0: 5 in/out port – I2S, PCM, AC97

GPC1: 5 in/out port – I2S, SPDIF, LCD_FRM

1.1-11

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S5PV210_UM_REV0.00 (Preliminary Spec)

♦

GPD0: 4 in/out port – PWM

GPD1: 6 in/out port – 2xI2C, PWM, IEM

GPE0,1: 13 in/out port – Camera I/F

GPF0,1,2,3: 30 in/out port – LCD I/F

GPG0,1,2,3: 28 in/out port – 4xMMC channel (Channel 0 and 2 support 4-bit and 8-bit mode, but channel

1, channel 3 support only 4-bit mode), SPI

♦

GPH0,1,2,3: 32 in/out port – Key pad, External Wake-up (up-to 32-bit), HDMI

GPI: Low Power I2S, PCM

GPJ0,1,2,3,4: 35 in/out port – Modem IF, CAMIF, CFCON, KEYPAD, SROM ADDR[22:16]

MP0_1,2,3: 20 in/out port – Control signals of EBI(SROM, NF, CF, OneNAND)

MP0_4,5,6,7: 32 in/out memory port – EBI(refer chapter 5,6 for detail description of EBI configuration

1.1-12

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3.6 SYSTEM PERIPHERAL

•

Real Time Clock

♦

Full clock features: sec, min, hour, date, day, month, year

32.768kHz operation

Alarm interrupt

Time-tick interrupt

•

PLL

♦

Four on-chip PLLs, APLL/MPLL/EPLL/VPLL

APLL dedicates to ARM core and MSYS clocks

MPLL generates a system bus clock and several special clocks

EPLL generates several special clocks

♦

VPLL generates clocks for the Video interface

•

Keypad

♦

14x8 Key Matrix support

Provides internal de-bounce filter

Timer with Pulse Width Modulation

♦

5-ch 32-bit internal timer with interrupt-based operation

3-ch 32-bit Timer with PWM

Programmable duty cycle, frequency, and polarity

Dead-zone generation

Support external clock source

•

System timer

♦

Accurate timer providing exact 1ms tick at any power mode except sleep.

Changeable interrupt interval without stopping reference tick timer

DMA

♦

Micro-code programming based DMA

The specific instruction set provides flexibility for programming DMA transfers

Linked list DMA function is supported.

3 Enhanced DMA embedded. 8 channels supported per each DMA so then totally 24 channels is

supported

♦

1 Memory to memory type optimized DMA + 2 Peripheral to memory type optimized DMA

M2M DMA supports up to 16burst, P2M DMA supports up to 8burst.

1.1-13

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S5PV210_UM_REV0.00 (Preliminary Spec)

•

A/D Converter and Touch Screen Interface

♦

10-ch multiplexed ADC

Max. 500Ksamples/sec and 12-bit resolution

•

Watch Dog Timer

16-bit watch dog timer

♦

Vectored Interrupt Controller

♦

Multiple interrupt request inputs, one for each interrupt source, and one interrupt request output for the

processor interrupt request input

♦

Software can mask out particular interrupt requests

Prioritization of interrupt sources for interrupt nesting

•

Power Management

♦

Clock-off control for individual components

Various low-power modes are available such as Idle, Stop, Deep Stop, Deep Idle and Sleep mode

Sleep mode’s wake up sources are external interrupts, RTC alarm, Tick timer and the key interface.

Stop and Deep Stop mode’s wake up sources are MMC, Touch screen interface, Modem interface, MIPI

HSI and the system timer as well all the wake up sources of Sleep mode.

♦

Deep Idle mode’s wake up sources are 5.1ch I2S as well all the wake up source of Stop mode.

3.7 SYSTEM OPERATING FREQUENCIES

•

ARM Cortex^TM-A8 core clock rate maximum is 800MHz@ 1.1V and 1GHz@1.2V

System operating clock generation

♦

MSYS domain clock rate maximum is 200MHz@1.1V

DSYS domain clock rate maximum is 166MHz@1.1V

PSYS domain clock rate maximum is 133MHz@1.1V

NOTES: 1.S5PV210 has four system clock domains called MSYS, DSYS, PSYS and AUDIO. MSYS domain is for CPU

system, 3D engine and Multi Format Codec, while DSYS domain for Display. PSYS domain for Other system

component except low power audio which is in AUDIO domain. Nominal 133/166/200MHz represents that PSYS

system frequency is 133MHz, DSYS system frequency is 166MHz and MSYS system frequency is 200MHz at 1.1V

power level.

2. S5PV210 supports only sync mode between CPU and MSYS system.

3. The voltage of the external Memory & I/O interface depends on the attached device specification. Therefore, the

PMIC should supply an appropriate voltage to the interface.

1.1-14

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3.8 ELECTRICAL CHARACTERISTICS

•

Operating Conditions

♦

Supply Voltage for Logic Core: VDD_INT 1.1V ±5%, VDD_ARM depends on operating frequency

External Memory Interface: 1.2/1.8V

External I/O Interface: 1.8/2.5/3.3V

1.1-15

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1.2-1


型号：	S5PV210AA0-LA40
厂家：	SAMSUNG
描述：	RISC Microprocessor,S5PV210 is a 32-bit RISC cost-effective, low power, high performance microprocessor solution for mobile phones and general applications, and integrates an ARM Cortex-A8 which implements the ARM architecture V7-A with supporting numerous peripherals. RISC微处理器， S5PV210是一个32位RISC成本效益，低功耗，移动电话和一般应用的高性能的微处理器解决方案，并集成了ARM Cortex- A8 ，它实现了ARM体系结构v7 -A与支持众多外设。微处理器移动电话
文件：	总17页 (文件大小：1871K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S5PV210AA0-LA40 [SAMSUNG]

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