S6B0715A01-B0CY_技术文档

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The S6B0715 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 33 common

and 100 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel

display data and stores in an on-chip display data RAM of 65 x 132 bits. It provides a highly-flexible display section

due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display

data RAM read/write operation with no external operating clock to minimize power consumption. In addition,

because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system

with the fewest components.

FEATURES

Driver Output Circuits

-

33 common outputs / 100 segment outputs

On-chip Display Data RAM

-

Capacity: 65 x 132 = 8,580 bits

Bit data "1": a dot of display is illuminated.

Bit data "0": a dot of display is not illuminated.

Multi-chip Operation (Master, Slave) Available

Applicable Duty Ratios

Duty ratio

Applicable LCD bias

Maximum display area

1/33

1/5 or 1/6

33 ´ 100

Microprocessor Interface

-

8-bit parallel bi-directional interface with 6800-series or 8080-series

Serial interface (only write operation) available

Various Instruction Setting

On-chip Low Power Analog Circuit

-

On-chip oscillator circuit

Voltage converter (x2, x3 and x4)

Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C)

On-chip electronic contrast control function (32 steps)

Voltage follower (LCD bias: 1/5 or 1/6)

Operating Voltage Range

-

Supply voltage (VDD): 2.4 to 3.6 V

LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

Low Power Consumption

-

100 mA Typ. (VDD = 3V, x4 boosting, V0 = 8V, internal power supply ON and display OFF)

10 mA Max. (during power save [standby] mode)

Wide Operating Temperature Range

Ta = -40°C to +85°C

Package Type

Gold bumped chip or TCP

-

1

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Series Specifications

S6B0715

Product code

TEMPS pin

Temp. coefficient

Package

Chip thickness

S6B0715A01-B0CZ

670 mm

470 mm

670 mm

470 mm

670 mm

470 mm

670 mm

470 mm

0

-0.05%/°C

(VSS connected)

S6B0715A01-B0CY

S6B0715A11-B0CZ

S6B0715A11-B0CY

S6B0715A01-xxX0

S6B0715A11-xxX0

COG

1

-0.2%/°C

-0.05%/°C

-0.2%/°C

(VDD connected)

0

(VSS connected)

TCP

1

(VDD connected)

S6B0715A11-xxX0

* xx: TCP ordering number

2

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

BLOCK DIAGRAM

VDD

V0

V1

100 SEGMENT

DRIVER CIRCUITS

34 COMMON

DRIVER CIRCUITS

V2

V3

V4

VSS

SEGMENT CONTROLLER

DISPLAY DATA RAM

COMMON CONTROLLER

V / F

CIRCUIT

MS

CL

M

FRS

DISP

PAGE

ADDRESS

CIRCUIT

LINE

ADDRESS

CIRCUIT

I/O

BUFFER

DISPLAY

TIMING

V0

65 X 132 = 8,580 Bits

GENERATOR

CIRCUIT

VR

V / R

TEMPS

CIRCUIT

COLUMN ADDRESS

CIRCUIT

VOUT

OSCILLATOR

TESTL2

TESTL1

C1-

C1+

C2-

V / C

C2+

CIRCUIT

C3-

C3+

STATUS REGISTER

BUS HOLDER

INSTRUCTION REGISTER

INSTRUCTION DECODER

MPU INTERFACE (PARALLEL & SERIAL)

Figure 1. Block Diagram

3

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

PAD CONFIGURATION

108

209

- - - - - - - - - -

210

234

107

Y

S6B0715

(TOP VIEW)

(0,0)

X

83

- - - - - - - - - -

1

82

Figure 2. S6B0715 Chip Configuration

Table 1. S6B0715 Pad Dimensions

Size

Item

Pad No.

X

Unit

Y

Chip size

Pad pitch

-

7980

2700

1 to 82

90

70

83 to 234

1 to 82

56

108

50

114

50

mm

83 to 107

108 to 209

210 to 234

Bumped pad size

108

50

108

Bumped pad height

All pad

17 (Typ.)

COG Align Key Coordinate

ILB Align Key Coordinate

30 m 30 m 30 m

42 m

m

108 m

42 m

m

(+3870, +1230)

(-3870, +1230)

(-3832, -1055)

(+3832, -1070)

4

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: mm]

No.

Name

X

Y

No.

Name

X

Y

No.

Name

X

Y

1

DUMMY

TESTL1

VDD

FRS

M

-3645

-1226

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

C1+

855

945

-1226

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

COM1

3830

420

490

560

630

700

770

840

2

3

4

5

6

7

8

9

-3555

-3465

-3375

-3285

-3195

-3105

-3015

-2925

-2835

-2745

-2655

-2565

-2475

-2385

-2295

-2205

-2115

-2025

-1935

-1845

-1755

-1665

-1575

-1485

-1395

-1305

-1215

-1125

-1035

-945

-1226

C1+

C1-

C2+

C2-

VSS

VR

V0

V1

V2

V3

V4

-1226

-840

COM0

COMS

DUMMY

SEG0

SEG1

SEG2

SEG3

SEG4

1035

1125

1215

1305

1395

1485

1575

1665

1755

1845

1935

2025

2115

2205

2295

2385

2475

2565

2655

2745

2835

2925

3015

3105

3195

3285

3375

3465

3555

3645

3830

3535

3465

3395

3325

3255

3185

3115

3045

2975

2905

2835

2765

2695

2625

2555

2485

2415

2345

2275

2205

2135

2065

1995

1925

1855

1785

1715

1645

1575

1505

1435

1365

1295

1225

1155

1085

1015

945

CL

DISP

VDD

MS

VSS

RESETB

VDD

PS

VSS

CS1B

CS2

VDD

MI

VSS

VDD

RS

VSS

RW_WR

E_RD

VDD

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

VSS

VOUT

C3+

1190

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

V4

VSS

TEMPS

VDD

TESTL2

DUMMY

COM15

COM14

COM13

COM12

COM11

COM10

COM9

COM8

COM7

COM6

COM5

COM4

COM3

COM2

-855

-765

-675

-585

-495

-405

-315

-225

-770

-700

-630

-560

-490

-420

-350

-280

-135

-45

45

135

225

315

405

495

585

-210

-140

-70

0

70

140

210

280

350

875

805

735

665

595

C3+

C3-

675

765

5

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

Table 2. Pad Center Coordinates (Continued)

[Unit: mm]

No.

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Name

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

X

Y

No.

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

Name

SEG92

SEG93

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

DUMMY

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COMS

X

Y

No.

Name

X

Y

525

455

385

315

245

175

105

35

1190

-2975

1190

-3045

-3115

-3185

-3255

-3325

-3395

-3465

-3535

-3830

1190

840

-35

-105

-175

-245

-315

-385

-455

-525

-595

-665

-735

-805

-875

-945

-1015

-1085

-1155

-1225

-1295

-1365

-1435

-1505

-1575

-1645

-1715

-1785

-1855

-1925

-1995

-2065

-2135

-2205

-2275

-2345

-2415

-2485

-2555

-2625

-2695

-2765

-2835

-2905

770

700

630

560

490

420

350

280

210

140

70

0

-70

-140

-210

-280

-350

-420

-490

-560

-630

-700

-770

-840

DUMMY

6

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Power Supply Pin Description

Description

Name

VDD

VSS

I/O

Supply Power supply

Supply Ground

LCD driver supply voltages

The voltage determined by LCD pixel is impedance-converted by an operational amplifier

for application.

V0

V1

V2

V3

V4

Voltages should have the following relationship;

V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS

When the internal power circuit is active, these voltages are generated as following table

according to the state of LCD Bias.

I/O

LCD bias

1/6 bias

1/5 bias

V1

V2

V3

V4

(5/6) x V0

(4/5) x V0

(4/6) x V0

(3/5) x V0

(2/6) x V0

(2/5) x V0

(1/6) x V0

(1/5) x V0

LCD DRIVER SUPPLY

Table 4. LCD Driver Supply Pin Description

Name

C1-

I/O

O

I/O

I

Description

Capacitor 1 negative connection pin for voltage converter

Capacitor 1 positive connection pin for voltage converter

Capacitor 2 negative connection pin for voltage converter

Capacitor 2 positive connection pin for voltage converter

Capacitor 3 negative connection pin for voltage converter

Capacitor 3 positive connection pin for voltage converter

Voltage converter input / output pin

C1+

C2-

C2+

C3-

C3+

VOUT

VR

V0 voltage adjustment pin

7

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

SYSTEM CONTROL

Table 5. System Control Pin Description

Description

Name

I/O

Master / Slave operation select pin

- MS = "H": master operation

- MS = "L": slave operation

The following table depends on the MS status.

Power

OSC

circuit

MS

I

MS

supply

circuit

CL

M

FRS

DISP

H

L

Enabled

Disabled

Input

Output

Input

Output

Input

Output

Input

Disabled

Display clock input / output pin

CL

I/O

When the S6B0715 is used in master/slave mode (multi-chip), the CL pins must be

connected each other for sync.

LCD AC signal input / output pin

When the S6B0715 is used in master/slave mode (multi-chip), the M pins must be

connected each other.

- MS = “ H” : output

- MS = “ L” : input

M

I/O

O

Static driver segment output pin

This pin is used together with the M pin.

FRS

DISP

LCD display blanking control input/output.

When S6B0715 is used in master/slave mode

(multi-chip), the DISP pins must be connected each other.

- MS = “ H” : output

I/O

- MS = “ L” : input

Selects temperature coefficient of the reference voltage

- TEMPS = "L": -0.05%/°C

TEMPS

I

- TEMPS = "H": -0.2%/°C

8

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

MICROPROCESSOR INTERFACE

Table 6. Microprocessor Interface Pin Description

Description

Name

I/O

Reset input pin

When RESETB is “L”, initialization is executed.

RESETB

I

Parallel / serial data input select input

Interface

mode

Chip

select

Data /

instruction

PS

H

Data

Read / write

Serial clock

-

CS1B,

CS2

E_RD

RW_WR

Parallel

Serial

RS

DB0 to DB7

SID (DB7)

PS

MI

I

CS1B,

CS2

L

Write only

SCLK (DB6)

*NOTE: When PS is “L”, DB0 to DB5 a re high impedance and E_RD and RW_WR

should be fixed to either “H” or “L”.

Microprocessor interface select input pin

- MI = "H": 6800-series MPU interface

- MI = "L": 8080-series MPU interface

I

Chip select input pins

Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.

When chip select is non-active, DB0 to DB7 may be high impedance.

CS1B

CS2

Register select input pin

- RS = "H": DB0 to DB7 are display data.

- RS = "L": DB0 to DB7 are control data.

RS

Read / Write execution control pin

MI

MPU type

RW_WR

Description

Read/Write control input pin

H

6800-series

RW

- RW = “H”: read

- RW = “L”: write

RW_WR

I

Write enable clock input pin

L

8080-series

/WR

The data on DB0 to DB7 are latched at the rising

edge of the /WR signal.

9

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

Table 6. Microprocessor Interface Pin Description (Continued)

Description

Name

I/O

Read / Write execution control pin

MI

H

MPU Type

6800-series

E_RD

E

Description

Read / Write control input pin

- RW = “H”: When E is “ H”, DB0 to DB7 are in an

output status.

- RW = “L”: The data on DB0 to DB7 are latched at

the falling edge of the E signal.

E_RD

I

Read enable clock input pin

When /RD is “L”, DB0 to DB7 are in an output status.

L

8080-series

/RD

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data

bus. When the serial interface selected (PS = "L");

- DB0 to DB5: high impedance

- DB6: serial input clock (SCLK)

- DB7: serial input data (SID)

DB0

to

DB7

I/O

When chip select is not active, DB0 to DB7 may be high impedance.

10

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

LCD DRIVER OUTPUTS

Table 8. LCD Driver Outputs Pin Description

Description

Name

I/O

LCD segment driver outputs

The display data and the M signal control the output voltage of segment driver.

Segment driver output voltage

Display data

M

Normal display

Reverse display

H

L

H

L

V0

VSS

V2

V3

SEG0

to

SEG99

O

H

L

V0

L

V3

VSS

Power save mode

VSS

LCD common driver outputs

The internal scanning data and M signal control the output voltage of common driver.

Scan data

M

H

L

Common driver output voltage

H

L

VSS

V0

COM0

to

COM31

O

H

L

V1

L

V4

Power save mode

VSS

Common output for the icons

The output signals of two pins are same. When not used, these pins should be left open. In

multi-chip (master/slave) mode, all COMS pins on both master and slave units are the

same signal.

COMS

TEST PINS

Table 8. Test Pin Description

Description

Name

I/O

TESTL1

TESTL2

IC test pins with pull-up

These pins must be open.

I

NOTE: DUMMY – These pins should be opened (floated).

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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for Chip Selection. The S6B0715 can interface with an MPU only when CS1B is “L”

and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and

DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are

reset.

Parallel / Serial Interface

S6B0715 has three types of interface with an MPU, which are one serial and two parallel interface. This parallel or

serial interface is determined by PS pin as shown in table 9.

Table 9. Parallel / Serial Interface Mode

PS

H

Type

Parallel

Serial

CS1B

CS2

MI

H

L

Interface mode

6800-series MPU mode

8080-series MPU mode

Serial-mode

L

*´

*´ : Don't care

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table

10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11.

Table 10. Microprocessor Selection for Parallel Interface

MI

H

CS1B

CS2

RS

E_RD

E

RW_WR

RW

DB0 to DB7

MPU bus

6800-series

8080-series

L

/RD

/WR

Table 11. Parallel Data Transfer

8080-series

Common

RS

6800-series

Description

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

H

L

H

L

H

L

H

L

Display data read out

Display data write

H

L

H

L

Register status read

L

H

Writes to internal register (instruction)

12

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Serial interface (PS = "L")

When the S6B0715 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal

8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into

DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high

and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by

the line length, the operation check on the actual machine is recommended.

CS1B

CS2

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

SID

SCLK

RS

Figure 3. Serial Interface Timing

Busy Flag

The Busy Flag indicates whether the S6B0715 is operating or not. When DB7 is “H” in read status operation, this

device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor

needs not to check this flag before each instruction, which improves the MPU performance.

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33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Data Transfer

S6B0715

The S6B0715 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the

MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And

when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder

(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5.

This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of

address sets is executed. Therefore, the data of the specified address cannot be output with the read display data

instruction right after the address sets, but can be output at the second read of data.

MPU signals

RS

/WR

N

D(N)

D(N+1)

D(N+2)

D(N+3)

DB0 to DB7

Internal signals

/WR

BUS HOLDER

N

N+1

N+2

N+3

COLUMN ADDRESS

Figure 4. Write Timing

14

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

MPU signals

RS

/WR

/RD

Dummy

D(N)

D(N+1)

N

DB0 to DB7

Internal signals

/WR

/RD

BUS HOLDER

COLUMN ADDRESS

N

D(N)

N+1

D(N+1)

N+2

D(N+2)

N+3

N

Figure 5. Read Timing

15

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can

be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and

the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through

DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as

shown in figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD

controller operates independently, data can be written into RAM at the same time as data is being displayed without

causing the LCD flicker.

DB0

DB1

DB2

DB3

DB4

COM0

COM1

COM2

COM3

COM4

0

1

0

1

0

1

0

1

0

1

0

- -

0

1

0

1

- -

Display Data RAM

Figure 6. RAM-to-LCD Data Transfer

LCD Display

Page Address Circuit

This circuit is for providing a page address to Display Data RAM shown in figure 8. It incorporates 4-bit Page

Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0

are “L”) is a special RAM area for the icons and display da ta DB0 is only valid. When Page Address is above 8, it is

impossible to access to on-chip RAM.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by

setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing

the contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the

initial display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register

are copied to the line counter which is increased by CL signal and generates the Line Address for transferring the

132-bit RAM data to the 100 display data latch circuit. However, display data of icons are not scrolled because the

MPU can not access Line Address of icons.

16

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column Address circuit has an 8-bit preset counter that provides column address to the Display Data RAM as shown

in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this

address is increased by 1 each a read or write Data instruction, microprocessor can access the display data

continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked

if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is

independent of page address register.

ADC select instruction makes it possible to invert the relationship between the column address and the segment

outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the

following figure 7.

SEG

0

SEG

1

SEG

2

SEG

97

SEG

98

SEG

99

SEG output

-

... ...

-

00H~

0FH

74H~

83H

Column address [Y7:Y0]

10H

1

01H

0

02H

0

71H

0

72H

1

73H

1

Display data

LCD panel display

( ADC = 0 )

0

´

Not

outputted

Not

outputted

... ...

LCD panel display

( ADC = 1 )

Not

outputted

Not

outputted

... ...

Figure 7. The Relationship between the Column Address and the Segment Outputs

Segment Control Circuit

This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF

instructions without changing the data in the display data RAM.

17

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

Line

Address

COM

Output

Page Address

Data

DB3

DB2

DB1

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

-

Page0

Page1

Page2

Page3

Page4

Page5

Page6

Page7

0

1

0

1

0

1

0

1

0

1

0

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

-

Start

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

-

0

1

0

1

0

-

COMS

Page8

0

ADC=0

ADC=1

00

83

-

0F 10 11 12

74 73 72 71 - - - - -

71 72 73 74

12 11 10 1F

-

83

00

- - - - -

Column

Address

Initial start line address = 1CH

- - - - -

-

LCD Output

Figure 8. Display Data RAM Map

18

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

LCD DISPLAY CIRCUITS

Oscillator

This is completely on-chip Oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in

the voltage converter and display timing generation circuit.

* Test Condition: Temperature: 25°C & 85°C, TEMPS = ” L” , No Load

DD

V

vs. fosc

4.00

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

°C

1/33 Duty (25

1/33 Duty (85

)

fosc

[kHz]

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5

DD

V

[V]

Figure 9. VDD vs. fOSC

Display Timing Generator Circuit

This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation

clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip

RAM is generated in synchronization with the display clock (CL) and the 100-bit display data is latched by the

display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver,

is completely independent of the access to the display data RAM from the microprocessor. The display clock

generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an

internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and

internal timing signal are shown in figure 10.

In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 12 shows

the M, CL, and DISP status.

Table 12. Master and Slave Timing Signal Status

M

CL

DISP

Operation mode

Master

Oscillator

ON (internal clock used)

OFF (external clock used)

-

Output

Input

Output

Input

Output

Input

Slave

Input

19

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

32

33

1

2

3

4

5

6

7

8

9

10

11

12

26

27

28

29

30

31

32

33

1

2

3

4

5

6

CL

M

V0

V1

V2

V3

V4

VSS

COM0

COM1

SEGn

V0

V1

V2

V3

V4

VSS

V0

V1

V2

V3

V4

VSS

Figure 9. 2-frame AC Driving Waveform

Common Output Control Circuit

This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select

Instruction specifies the scanning direction of the common output pins.

Table 13. The Relationship between Duty Ratio and Common Output

Common output pins

Duty SHL

COM0 to COM31

COMS

COM0 to COM31

0

1

1/33

COMS

COM31 to COM0

20

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

LCD DRIVER CIRCUIT

This driver circuit is configured by 34-channel (including 2 COMS channel) common driver and 100-channel

segment driver. This LCD panel driver voltage depends on the combination of display data and M signal.

VDD

COM0

M

VSS

COM1

V0

V1

COM2

V2

COM3

COM0

V3

V4

VSS

COM4

V0

V1

COM5

V2

COM6

COM1

V3

V4

COM7

VSS

V0

V1

V2

COM8

COM9

COM2

SEG0

SEG1

SEG2

V3

V4

VSS

V0

V1

V2

COM10

COM11

V3

V4

VSS

COM12

COM13

COM14

COM15

V0

V1

V2

V3

V4

VSS

S

E

G

0

S

E

G

1

S

E

G

2

S

E

G

3

S

E

G

4

V0

V1

V2

V3

V4

VSS

Figure 10. Segment and Common Timing

21

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

POWER SUPPLY CIRCUITS

The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power

consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and

voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For

details, refers to "Instruction Description". Table 14 shows the referenced combinations in using Power Supply

circuits.

Table 14. Recommended Power Supply Combinations

Power

V/C

circuits

V/R

V/F

User setup

VOUT

V0

V1 to V4

control

(VC VR VF)

circuits circuits

Only the internal power

supply circuits are used

1 1 1

0 1 1

ON

Open

Only the voltage

regulator circuits and

voltage follower circuits

are used

External

input

OFF

Open

Only the voltage follower

circuits are used

External

input

0 0 1

0 0 0

OFF

ON

Open

Only the external power

supply circuits are used

External

input

External

input

OFF

22

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Voltage Converter Circuits

These circuits boost up the electric potential between VDD and VSS to 2, 3, or 4 times toward positive side and

boosted voltage is outputted from VOUT pin.

[C1 = 1.0 to 4.7 F]

m

DD

V

DD

V

-

C1

+

VOUT

C3+

C3 -

C2+

C2 -

C1+

C1 -

C3+

C3 -

C2+

C2 -

C1+

C1 -

DD

V

VOUT = 3

´

+

C1

-

+

DD

V

VOUT = 2

´

+

-

DD

SS

V

DD

SS

V

SS

V

GND

Figure 11. Two Times Boosting Circuit

Figure 12. Three Times Boosting Circuit

DD

V

-

C1

+

VOUT

DD

V

VOUT = 4

+

´

C3+

C3 -

C2+

C2 -

C1+

C1 -

C1

-

+

-

+

-

VDD

SS

V

SS

V

GND

Figure 13. Four Times Boosting Circuit

23

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Voltage Regulator Circuits

S6B0715

The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by

adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of

operational-amplifier circuits shown in figure 14, it is necessary to be applied internally or externally.

For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS

pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter a is the value

selected by instruction, "Set Reference Voltage Register", within the range 0 to 31. VREF voltage at Ta = 25°C is

shown in table 15-1.

Rb

V0 = ( 1 + ¾ ¾ ¾ ¾ ) x VEV [V] ------ (Eq. 1)

Ra

(31 - a )

VEV = ( 1 - ¾ ¾ ¾ ¾ ¾ ¾ ) x VREF [V] ------ (Eq. 2)

150

Table 15-1. VREF Voltage at Ta = 25°C

TEMPS

Temp. coefficient

-0.05% / °C

VREF [V]

1.9

L

H

2.1

-0.2% / °C

Table 15-2. Reference Voltage Parameter (a)

SV4

SV3

SV2

SV1

SV0

Reference voltage parameter (a)

0

:

0

:

0

:

0

:

0

1

:

0

1

:

1

0

1

30

31

24

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

VOUT

+

V0

-

V_EV

Rb

VR

Ra

SS

V

GND

Figure 14. Internal Voltage Regulator Circuit

25

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

In Case of Using External Resistors, Ra and Rb

S6B0715

It is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR.

Example: For the following requirements

1. LCD driver voltage, V0 = 8V

2. 5-bit reference voltage register = (1, 1, 1, 1, 1)

3. Maximum current flowing Ra, Rb = 1 uA

From Eq. 1

Rb

8 = ( 1 + ¾ ¾ ¾ ) x VEV [V] ------ (Eq. 3)

Ra

From Eq. 2

(31 - 31)

VEV = ( 1 - ¾ ¾ ¾ ¾ ¾ ¾ ) x 1.9 = 1.9 [V] ------ (Eq. 4)

150

From requirement 3.

8

¾ ¾ ¾ ¾ ¾ ¾ = 1 [uA] ------ (Eq. 5)

Ra + Rb

From equations Eq. 3, 4 and 5

Ra = 1.9 [MW]

Rb = 6.1 [MW]

The following table shows the range of V0 depending on the above requirements.

Table 16. V0 depending on Electronic Volume Level

Electronic volume level

0

.......

16

.......

31

V0

6.33

.......

7.19

.......

8

26

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Voltage Follower Circuits

VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are

converted by the Voltage Follower for increasing drive capability. Table 17 shows the relationship between V1 to V4

level and bias.

Table 17. The Relationship between V1 to V4 Level and Bias

Duty ratio

LCD bias

V1

V2

V3

V4

1/6

1/5

(5/6) x V0

(4/5) x V0

(4/6) x V0

(3/5) x V0

(2/6) x V0

(2/5) x V0

(1/6) x V0

(1/5) x V0

1/33

27

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

REFERECE CIRCUIT EXAMPLES

VDD

MS

VOUT

C3+

C3-

C2+

C2-

C1+

C1-

MS

VOUT

C3+

C3-

C2+

C2-

C1+

C1-

C1

External

Power

Supply

C1

Ra

VR

Rb

C2 -

+

C2 -

+

V0

V1

V2

V3

V4

V0

V1

V2

V3

V4

C2 -

+

C2 -

+

SS

V

Figure 15. When Using all LCD Power Circuits

(4-time V/C: ON, V/R: ON, V/F: ON)

Figure 16. When not Using V/C Circuit

DD

V

DD

V

MS

VOUT

C3+

C3-

C2+

C2-

C1+

C1-

VOUT

C3+

Value of external Capacitance

C3-

C2+

C2-

C1+

C1-

Item

C1

Value

Unit

External

Power

Supply

1.0 to 4.7

mF

C2

0.47 to 1.0

VR

C2 -

+

V0

V1

V2

V3

V4

V0

V1

V2

V3

V4

External

Power

Supply

SS

V

Figure 17. When Using some LCD Power Circuits

(V/C: OFF, V/R: OFF, V/F: ON)

Figure 18. When not Using Internal

LCD Power Supply Circuit

28

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

RESET CIRCUIT

Setting RESETB to “L” or Reset instruction can initialize internal function.

When RESETB becomes “L”, following procedure is occurred.

Display ON / OFF: OFF

Entire display ON / OFF: OFF (normal)

ADC select: OFF (normal)

Reverse display ON / OFF: OFF (normal)

Power control register (VC, VR, VF) = (0, 0, 0)

LCD bias ratio: 1/6

Read-modify-write: OFF

SHL select: OFF (normal)

Static indicator mode: OFF

Display start line: 0 (first)

Column address: 0

Page address: 0

Reference voltage set: off

Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)

When RESET instruction is issued, following procedure is occurred.

Read-modify-write: OFF

Static indicator mode: OFF

SHL select: 0

Display start line: 0 (first)

Column address: 0

Page address: 0

Reference voltage set: OFF

Reference voltage control register: (SV4, SV3, SV2, SV1, SV0) = (0, 0, 0, 0, 0)

While RESETB is “L” or reset instruction is executed, no instruction except read status could be accepted. Reset

status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the

reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential

before used.

29

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

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INSTRUCTION DESCRIPTION

Table 18. Instruction Table

´ : Don’t care

Instruction

Read display data

Write display data

Read status

Description

RS

1

RW

1

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Read data

Write data

Read data from DDRAM

Write data into DDRAM

Read the internal status

Turn ON / OFF LCD panel

1

0

1

BUSY ADC

ON/OFF

RESETB

0

1

0

1

0

Display ON / OFF

0

1

0

1

0

1

DON When DON = 0: display OFF

When DON = 1: display ON

Initial display line

0

1

0

ST5

0

ST4

0

ST3

0

ST2

0

ST1

0

ST0 Specify DDRAM line for COM0

Set reference voltage

mode

1

Set reference voltage mode

Set reference voltage

register

0

1

0

SV4

SV3

SV2

SV1

SV0 Set reference voltage register

Set page address

0

1

0

1

0

1

0

P3

0

P2

Y6

Y2

P1

Y5

Y1

P0

Y4

Y0

Set page address

Set column address MSB

Set column address LSB

Set column address MSB

Set column address LSB

Y3

Select SEG output direction

When ADC = 0: normal direction

(SEG0® SEG99)

ADC select

0

1

0

1

0

ADC

When ADC = 1: reverse direction

(SEG99® SEG0)

Select normal / reverse display

When REV = 0: normal display

When REV = 1: reverse display

Reverse display ON / OFF

Entire display ON / OFF

0

1

0

1

0

1

0

REV

EON

Select normal/ entire display ON

When EON = 0: normal display.

When EON = 1: entire display

ON

LCD bias select

Set modify-read

Reset modify-read

Reset

0

1

0

1

0

1

0

1

0

1

0

1

BIAS Select LCD bias

0

Set modify-read mode

release modify-read mode

Initialize the internal functions

Select COM output direction

When SHL = 0: normal direction

(COM0® COM31)

SHL select

0

1

0

SHL

´

When SHL = 1: reverse direction

(COM31® COM0)

Power control

0

1

0

1

0

1

VC

1

VR

0

VF

SI

Control power circuit operation

Set static indicator register

SI = 0 (OFF), SI = 1 (ON)

Set static indicator register

Compound instruction of display

OFF and entire display ON

Power save

-

Test instruction

0

1

Don't use this instruction.

´

30

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Read Display Data

8-bit data from Display Data RAM specified by the column address and page address could be read by this

instruction. As the column address is increased by 1 automatically after each this instruction, the

microprocessor can continuously read data from the addressed page. A dummy read is required after loading

an address into the column address register. Display data cannot be read through the serial interface.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

Read data

Write Display Data

8-bit data of display data from the microprocessor can be written to the RAM location specified by the column

address and page address. The column address is increased by 1 automatically so that the microprocessor can

continuously write data to the addressed page.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

Write data

Set Page Address

Set Column Address

Data Write

Set Page Address

Set Column Address

Dummy Data Read

Column = Column + 1

Data Read

Column = Column + 1

YES

Data Write Continue ?

Column = Column + 1

NO

Optional Status

YES

Data Read Continue ?

NO

Optional Status

Figure 19. Sequence for Writing Display Data

Figure 20. Sequence for Reading Display Data

31

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

Read Status

Indicates the internal status of the S6B0715

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

BUSY

ADC

ON / OFF RESETB

0

Flag

Description

The device is busy when internal operation or reset

BUSY

Any instruction is rejected until BUSY goes Low.

0: chip is active, 1: chip is being busy.

Indicates the relationship between RAM column address and segment driver.

0: reverse direction (SEG99 ® SEG0), 1: normal direction (SEG0 ® SEG99)

ADC

Indicates display ON / OFF status

0: display ON, 1: display OFF

ON / OFF

RESETB

Indicates the initialization is in progress by RESETB signal

0: chip is active, 1: chip is being reset

Display ON / OFF

Turns the display ON or OFF

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

1

DON

DON = 1: display ON

DON = 0: display OFF

Initial Display Line

Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at

the top row (COM0 when SHL = L, COM31 when SHL = H) of LCD panel.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

ST5

ST4

ST3

ST2

ST1

ST0

ST5

ST4

ST3

ST2

ST1

ST0

Line address

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

:

1

0

1

62

63

32

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Reference Voltage Select

Consists of 2-byte Instruction

The 1^stinstruction sets reference voltage mode, the 2^ndone updates the contents of reference voltage

register. After second instruction, reference voltage mode is released.

The 1^stInstruction: Set Reference Voltage Select Mode

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

The 2^ndInstruction: Set Reference Voltage Register

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

SV4

SV3

SV2

SV1

SV0

SV4

SV3

SV2

SV1

SV0

Reference voltage parameter (a)

0

:

0

:

0

:

0

:

0

1

:

0

1

:

1

0

1

30

31

Setting Reference Voltage Start

1^stInstruction for Mode Setting

2^ndInstruction for Register Setting

Setting Reference Voltage End

Figure 21. Sequence for Setting the Reference Voltage

33

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Set Page Address

S6B0715

Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM

data bit can be accessed when its Page Address and column address are specified. Along with the column

address, the Page Address defines the address of the display RAM to write or read display data. Changing the

Page Address doesn't effect to the display status.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

P3

P2

P1

P0

P3

0

P2

0

P1

0

P0

0

Page

0

1

:

0

1

:

0

1

7

8

1

0

Set Column Address

Sets the Column Address of display RAM from the microprocessor into the column address register. Along with

the Column Address, the Column Address defines the address of the display RAM to write or read display data.

When the microprocessor reads or writes display data to or from display RAM, Column Addresses are

automatically increased.

Set Column Address MSB

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

Y6

Y5

Y4

Set Column Address LSB

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

Y3

Y2

Y1

Y0

Y6

0

Y5

0

Y4

0

Y3

0

Y2

0

Y1

0

Y0

0

Column address

0

1

0

1

:

1

0

1

0

98

99

1

0

1

34

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

ADC Select

Changes the relationship between RAM column address and segment driver. The direction of segment driver

output pins could be reversed by software. This makes IC layout flexible in LCD module assembly.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

ADC

ADC = 0: normal direction (SEG0 ® SEG99)

ADC = 1: reverse direction (SEG99 ® SEG0)

Reverse Display ON / OFF

Reverses the display status on LCD panel without rewriting the contents of the display data RAM.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

1

REV

RAM bit data = “1”

LCD pixel is illuminated

LCD pixel is not illuminated

RAM bit data = “0”

LCD pixel is not illuminated

LCD pixel is illuminated

0 (normal)

1 (reverse)

Reverse Display ON / OFF

Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,

the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF

instruction.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

1

0

EON

EON = 0: normal display

EON = 1: entire display ON

Select LCD Bias

Selects LCD bias ratio of the voltage required for driving the LCD.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

1

Bias

LCD bias

Duty

ratio

Bias = 0

Bias = 1

1/33

1/6

1/5

35

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Set Modify-read

S6B0715

This instruction stops the automatic increment of the column address by the read display data instruction, but

the column address is still increased by the write display data instruction. And it reduces the load of

microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This

mode is canceled by the reset Modify-read instruction.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

Reset Modify-read

This instruction cancels the Modify-read mode, and makes the column address return to its initial value just

before the set Modify-read instruction is started.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

Set Page Address

Set Column Address (N)

Set Modify-Read

Dummy Read

Data Read

Data Process

Data Write

NO

Change Complete ?

YES

Reset Modify-Read

Return Column Address (N)

Figure 22. Sequence for Cursor Display

36

S6B0715

Reset

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

This instruction Resets initial display line, column address, page address, and common output status select to

their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD

power supply, which is initialized by the RESETB pin.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

SHL Select

COM output scanning direction is selected by this instruction which determines the LCD driver output status.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

SHL

´

´ : Don’ t care

SHL = 0: normal direction (COM0 ® COM31)

SHL = 1: reverse direction (COM31 ® COM0)

Power Control

Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal

power supply functions can be used simultaneously.

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

VC

VR

VF

VC

VR

VF

Status of internal power supply circuits

0

1

Internal voltage converter circuit is OFF

Internal voltage converter circuit is ON

0

1

Internal voltage regulator circuit is OFF

Internal voltage regulator circuit is ON

0

1

Internal voltage follower circuit is OFF

Internal voltage follower circuit is ON

Set Static Indicator State

This instruction sets the Static Indicator ON / OFF. When it is on, the static indicator operates and blinks at an

interval of approximately 1second.

Set Static Indicator Register

RS

RW

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

0

1

0

SI

0

Status of static indicator output

OFF

1

ON (about 1 second blinking)

37

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Power Save (Compound Instruction)

S6B0715

If the entire display ON / OFF instruction is issued during the display OFF state, S6B0715 enters the Power

Save status to reduce the power consumption to the static power consumption value. According to the status of

static indicator mode, Power Save is entered to one of two modes (sleep and standby mode). When static

indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released

by the display ON & entire display OFF instruction.

Static Indicator OFF

Static Indicator ON

Power Save (Compound Instruction)

[Display OFF]

[Entire Display ON]

Sleep Mode

[Oscillator Circuit: OFF]

[LCD Power Supply Circuit: OFF]

[All COM / SEG Outputs: V

Standby Mode

[Oscillator Circuit: ON]

[LCD Power Supply Circuit: OFF]

[All COM / SEG Outputs: VSS]

[Consumption Current: < 10 A]

SS

]

[Consumption Current: < 2 A]

m

Power Save OFF (Compound Instruction)

[Entire Display OFF]

Power Save OFF (Compound Instruction)

[Entire Display OFF]

[Static Indicator ON]

[Display ON]

Release Sleep Mode

Release Standby Mode

Figure 23. Power Save Routine

38

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow (1)

User System Setup by External Pins

Start of Initialization

Power ON (VDD - VSS) Keeping the RESETB Pin = “L”

Waiting for Stabilizing the Power

RESETB Pin = “H”

User Application Setup by Internal Instructions

[ADC Select]

[SHL Select]

[LCD Bias Select]

User LCD Power Setup by Internal Instructions

[Reference Voltage Register Set]

User LCD Power Setup by Internal Instructions

[Voltage Converter ON]

Waiting for 1ms

³

User LCD Power Setup by Internal Instructions

[Voltage Regulator ON]

Waiting for 1ms

³

User LCD Power Setup by Internal Instructions

[Voltage Follower ON]

Waiting for Stabilizing the LCD Power Levels

End of Initialization

Figure 24. Initializing with the Built-in Power Supply Circuits

39

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow (2)

S6B0715

User System Setup by External Pins

Start of Initialization

DD

SS

Power ON (V - V ) Keeping the RESETB Pin = “ L”

Waiting for Stabilizing the Power

RESETB Pin = “H”

Set Power Save

User Application Setup by Internal Instructions

[ADC Select]

[SHL Select]

[LCD Bias Select]

User LCD Power Setup by Internal Instructions

[Reference Voltage Register Set]

Release Power Save

Waiting for Stabilizing the LCD Power Levels

End of Initialization

Figure 25. Initializing without the Built-in Power Supply Circuits

40

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow (3)

End of Initialization

Display Data RAM Addressing by Instruction

[Initial Display Line]

[Set Page Address]

[Set Column Address]

Write Display ON / OFF by Instruction

[Display ON / OFF]

Turn Display ON / OFF by Instruction

[Display ON / OFF]

End of Data Display

Figure 26. Data Displaying

41

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow (4)

S6B0715

Optional Status

Turn Display ON / OFF by Instruction

[Display OFF]

User LCD Power Setup by Internal Instructions

[Voltage Regulator OFF]

Waiting for 50ms

³

User LCD Power Setup by Internal Instructions

[Voltage Follower OFF]

Waiting for 1ms

³

User LCD Power Setup by Internal Instructions

[Voltage Converter OFF]

Waiting for 1ms

³

DD SS

Power OFF (V -V

)

Figure 27. Power OFF

42

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Table 19. Absolute Maximum Ratings

Parameter

Symbol

VDD

Rating

- 0.3 to +7.0

- 0.3 to +17.0

- 0.3 to VDD +0.3

- 40 to +85

Unit

V

Supply voltage range

VLCD

VIN

V

Input voltage range

V

Operating temperature range

TOPR

TSTR

°C

Storage temperature range

- 55 to +125

NOTES:

1. VDD and VLCD are based on VSS = 0V.

2. Voltages V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS must always be satisfied. (VLCD = V0 – VSS)

3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.

It is desirable to use this LSI under electrical characteristic conditions during general operation.

Otherwise, this LSI may malfunction or reduced LSI reliability may result.

43

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

DC CHARACTERISTICS

Table 20. DC Characteristics

( VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C )

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Pin used

Operating voltage (1)

Operating voltage (2)

VDD

V0

2.4

4.0

-

3.6

15.0

V

VDD *1

V0 *2

High

Input voltage

Low

VIH

VIL

0.8VDD

VSS

VDD

V

*3

*4

0.2VDD

VDD

High

VOH

VOL

IIL

IOH = -0.5mA

IOL = 0.5mA

0.8VDD

VSS

Output

voltage

Low

0.2VDD

+ 1.0

+ 3.0

Input leakage current

Output leakage current

VIN = VDD or VSS

- 1.0

- 3.0

*5

*6

mA

IOZ

LCD driver ON

resistance

SEGn

COMn *7

RON

Ta = 25°C, V0 = 8V

Ta = 25°C

-

2.0

3.0

kW

Internal

External

fOSC

fCL

17

2.13

2.4

22.5

2.81

-

27

3.37

3.6

Oscillator

frequency (1)

kHz

CL *8

VDD

´ 2

´ 3

´ 4

Voltage converter

input voltage

VDD

V

2.4

-

3.6

´ 2 / ´ 3 / ´ 4

voltage conversion

(no-load )

Voltage converter

output voltage

VOUT

95

99

-

%

VOUT

Voltage regulator

operating voltage

VOUT

4.0

-

15.0

V

VOUT

V0 *9

Voltage follower

operating voltage

V0

VREF0

VREF1

1.84

2.04

1.9

2.1

1.96

2.16

V

*10

-0.05%/

°C

Reference voltage

Ta = 25°C

-0.2%/

°

C

44

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Dynamic Current Consumption (1): when the Built-in Power Circuit is OFF (At Operate Mode)

(Ta = 25°C)

Unit Pin used

Item

Symbol

Condition

Min.

Typ.

Max.

VDD = 3.0V

V0 – VSS = 8.0V

Display OFF, checker pattern

Dynamic current

consumption (1)

IDD1

-

5

20

mA

*11

Dynamic Current Consumption (2): when the built-in power circuit is ON (At operate mode)

(Ta = 25°C)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit Pin used

VDD = 3.0V,

quad boosting,

V0 – VSS = 8.0V,

1/65 duty ratio,

-

47

70

Display OFF, checker pattern

Normal power mode

Dynamic current

consumption (2)

IDD2

*12

mA

VDD = 3.0V,

quad boosting,

-

75

100

V0 – VSS = 8.0V,

Display ON, checker pattern

Normal power mode

Current Consumption during Power Save mode

(Ta = 25°C)

Item

Symbol

IDDS1

Condition

During sleep

During standby

Min.

Typ.

Max.

2.0

Unit Pin used

Sleep mode

Standby mode

-

mA

IDDS2

10.0

45

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

Table 21. The relationship between oscillation frequency and frame frequency

Duty ratio

Item

fCL

fM

fOSC

¾ ¾ ¾ ¾

fOSC

¾ ¾ ¾ ¾

16 ´ 33

On-chip oscillator circuit is

used

8

1/33

fOSC

¾ ¾ ¾ ¾

2 ´ 33

On-chip oscillator circuit is

not used

External input (fCL)

(fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency)

[* Remark Solves]

*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage

assurance during access from the MPU.

*2. In case of external power supply is applied.

*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.

*4. DB0 to DB7, M, FRS, DISP, CL pins.

*5. CS1B, CS2, RS, DB[7:0], E_RD, RW_WR, RESETB, MS, MI, PS, TEMPS, CL, M, DISP pins.

*6. Applies when the DB[7:0], M, DISP, and CL pins are in high impedance.

*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.

RON= DV / 0.1 [kW] (DV: voltage change when ± 0.1[mA] is applied in the ON status.)

*8. See table 21 for the relationship between oscillation frequency and frame frequency.

*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range.

*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.

*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.

The current consumption, when the built-in power supply circuit is ON or OFF.

The current flowing through voltage regulation resistors (Ra and Rb) is not included.

It does not include the current of the LCD panel capacity, wiring capacity, etc.

46

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

REFERENCE DATA

IDD1 vs. VDD

l

Test Condition: Temperature (25°C & 85°C), V0 = 8V (External), TEMPS = 'L', 1/33 Duty, Ra = 1 [MW],

Rb = 3 [MW], Normal Power Mode

VDD vs. IDD1(Pattern OFF)

12.00

10.00

8.00

8.0V, 1/33 Duty (25°C)

8.0V, 1/33 Duty (85°C)

IDD1

[uA]

6.00

4.00

2.00

0.00

2.7

3.0

3.3

3.6

4.0

4.5

5.0

5.5

VDD [V]

Figure 28. Display Pattern is OFF

47

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

IDD2 vs. VDD

S6B0715

l

Test Condition: Temperature (25°C & 85°C), Quad boosting, RR = 6, EV = 32, TEMPS = 'L', 1/33 duty,

Ra = 1 [MW], Rb = 3 [MW], Normal Power Mode

VDD vs. IDD2 (Pattern OFF)

50.00

45.00

40.00

35.00

30.00

25.00

20.00

15.00

10.00

5.00

1/33 Duty (25°C)

1/33 Duty (85°C)

I

DD2

[uA]

0.00

2.7

3.0

3.3

3.6

V

4.0

[V]

4.5

5.0

5.5

DD

Figure 29. Display Pattern is OFF

DD

V

DD2

(Checker Pattern)

vs. I

250.00

200.00

150.00

100.00

50.00

°C

1/33 Duty (25

)

DD2

I

[uA]

1/33 Duty (85

0.00

2.7

3.0

3.3

3.6

4.0

4.5

5.0

5.5

DD

V

[V]

Figure 30. Display Pattern is Checker

48

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

AC CHARACTERISTICS

Read / Write Characteristics (8080-series MPU)

RS

AS80

AH80

t

CS1B

(CS2 = 1)

CY80

t

PW80(R)

PW80(W)

t

,

t

RD, WR

DD

0.9V

0.1V

DS80

DH80

t

DB0 to DB7

(Write)

ACC80

OD80

t

DB6 to DB7

(Read)

Figure 31. Read / Write Characteristics (8080-series MPU)

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item

Signal

Symbol

Min.

Typ.

Max.

Unit

Remark

Address setup time

Address hold time

System cycle time

Pulse width (WR)

Pulse width (RD)

Data setup time

Data hold time

Read access time

Output disable time

tAS80

tAH80

tCY80

13

17

400

55

125

35

13

-

RS

-

ns

-

ns

RW_WR tPW80(W)

E_RD

tPW80(R)

tDS80

tDH80

tACC80

tOD80

DB7

to

DB0

-

ns

125

90

CL = 100 pF

10

49

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Read / Write Characteristics (6800-series Microprocessor)

S6B0715

RS

AS68

AH68

t

CS1B

(CS2 = 1)

tCY68

tPW68(R), tPW68(W)

E

0.1VDD

0.9VDD

tDS68

tDH68

DB0 to DB7

(Write)

tACC68

tOD68

DB0 to DB7

(Read)

Figure 32. Read / Write Characteristics (6800-series Microprocessor)

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item

Signal

Symbol

Min.

Typ.

Max.

Unit

Remark

Address setup time

Address hold time

tAS68

tAH68

13

17

RS

-

ns

System cycle time

RS

tCY68

400

ns

Data setup time

Data hold time

Access time

tDS68

tDH68

tACC68

tOD68

tPW68(R)

tPW68(W)

35

13

-

10

125

55

DB7

to

DB0

ns

125

90

-

ns

-

CL = 100 pF

Output disable time

Read

Write

Enable pulse width

E_RD

-

50

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Serial Interface Characteristics

tCSS

tCHS

tAHS

CS1B

(CS2 = 1)

tASS

RS

tCYS

DB6

0.9VDD

(SCLK)

0.1VDD

tWLS

tWHS

t_DSS

t_DHS

DB7

(SID)

Figure 33. Serial Interface Characteristics

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C )

Item

Signal

Symbol

Min

Typ

Max

Unit

Remark

tCYS

tWHS

tWLS

Serial clock cycle

SCLK high pulse width

SCLK low pulse width

450

180

135

-

DB6

(SCLK)

ns

tASS

tAHS

Address setup time

Address hold time

90

360

-

RS

ns

tDSS

tDHS

Data setup time

Data hold time

DB7

(SID)

90

-

tCSS

tCHS

CS1B setup time

CS1B hold time

55

180

-

CS1B

51

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Reset Input Timing

S6B0715

tRW

RESETB

Figure 34. Reset Input Timing

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Typ.

Remark

Item

Signal

Symbol

Min.

Max.

Unit

Reset low pulse width

RESETB

tRW

900

-

ns

Display Control Output Timing

DM

t

CL

M

Figure 35. Display Control Output Timing

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Typ.

Remark

Item

Signal

Symbol

Min.

Max.

Unit

M delay time

M

tDM

-

13

70

ns

52

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

REFERENCE APPLICATIONS

MICROPROCESSOR INTERFACE

IN CASE OF INTERFACING WITH 6800-SERIES (PS = “H”, MI = “H”)

C S 1 B

C S 2

R S

K S 0 7 1 5

6 8 0 0 - s e r i e s

M P U

E

E _ R D

R W

R W _ W R

D B 0 t o D B 7

R E S E T B

M I

D B 0 t o D B 7

R E S E T B

V

D D

P S

Figure 36. Interfacing with 6800-series (PS = “H”, MI = “H”)

In Case of Interfacing with 8080-series (PS = “H”, MI = “L”)

C S 1 B

C S 2

C S 1 B

C S 2

R S

/R D

S 6 B 0 7 1 5

8080-series

M P U

E _ R D

R W _ W R

/W R

D B 0 t o D B 7

R E S E T B

D B 0 t o D B 7

R E S E T B

M I

V

S S

D D

P S

Figure 37. Interfacing with 8080-series (PS = “H”, MI = “L”)

In Case of Serial Interface (PS = “L”, MI = “H/L”)

C S 1 B

C S 2

C S 1 B

C S 2

R S

SID

S 6 B 0715

DB7(SID)

S C L K

R E S E T B

M P U

D B 6 ( S C L K )

R E S E T B

D B 0 t o D B 5

M I

O P E N

V D D or VS S

V S S

P S

Figure 38. Serial Interface (PS = “L”, MI = “H/L”)

53

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

CONNECTIONS BETWEEN S6B0715 AND LCD PANEL

Single Chip Configuration (1/33 Duty Configurations)

COMS

COM31

:

COM15

:

COM0

COMS

COM15

:

COM0

COMS

COM31

:

S6B0715

(Bottom View)

S6B0715

(Top View)

COM16

SEG99

...........

SEG0

............

SEG99

§

¨

©

ª

X

â

§

¨

©

ª

X

â

32 ´ 100 pixels

§

¨

©

ª

X

â

§

¨

©

ª

X

Figure 39. SHL = 0, ADC = 1

Figure 40. SHL = 0, ADC = 0

§

¨

©

ª

X â

§

¨

©

ª

X

â

32 ´ 100 pixels

¨

©

ª

X â

§

¨

©

ª

X

SEG99

COM16

:

COM31

COMS

...........

SEG0

COMS

SEG0

COMS

COM0

:

...........

SEG99

COM16

S6B0715

(Top View)

S6B0715

(Bottom View)

:

COM0

:

COM15

COM31

COMS

COM15

Figure 41. SHL = 1, ADC = 0

Figure 42. SHL = 1, ADC = 1

54

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

Multiple Chip Configuration

-

33COM (32COM + 1COMS) ´ 200SEG (100SEG ´ 2)

COMS

COM31

:

COM15

:

COM0

COMS

COM31

:

COM15

:

COM0

COMS

S6B0715

( Bottom View )

S6B0715

( Bottom View )

COM16

( Master )

...................

( Slave )

SEG99

SEG0

SEG99

...................

SEG0

§

¨

©

ª

X â

32 ´ 200 pixels

§

¨

©

ª

X â

Figure 43. SHL = 0, ADC = 1

¨ Connect the following pins of two chips each other

- Display clock pins: CL, M

- Display control pin: DISP

- LCD power pins: V0, V1, V2, V3, V4

§

¨

©

ª

X â

32 ´ 200 pixels

¨

©

ª

X

â

SEG0

...............

S6B0715

( Bottom View )

( Master )

SEG99

SEG0

...............

S6B0715

( Bottom View )

( Slave )

SEG99

COMS

COM0

:

COM16

:

COM31

COMS

COM16

:

COM31

COMS

COM0

:

COM15

Figure 44. SHL = 1, ADC = 0

¨ Connect the following pins of two chips each other

- Display clock pins: CL, M

- Display control pin: DISP

- LCD power pins: V0, V1, V2, V3, V4

55

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

S6B0715

-

66COM (64COM + 2COMS) ´ 100SEG

COM15

:

COM0

COMS

COM31

:

S6B0715

( Top View )

( Master )

...................

COM16

SEG0

SEG99

§

¨

©

ª

X â

64 ´ 100 pixels

§

¨

©

ª

X â

SEG99

COM16

:

COM31

COMS

...................

SEG0

COMS

S6B0715

( Top View )

( Slave )

COM0

:

COM15

Figure 45. 66COM (64COM + 2COMS)

´ 100SEG

¨ Connect the following pins of two chips each other

- Display clock pins: CL, M

- Display control pin: DISP

- LCD power pins: V0, V1, V2, V3, V4

¨ Common / Segment output direction select

- Master chip: SHL = 0, ADC = 0

- Slave chip: SHL = 1, ADC = 1

56

S6B0715

33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD

TCP PIN LAYOUT (SAMPLE)

COMS

COM31

COM30

:

COM26

COM25

COM24

FRS

M

CL

DISP

MS

RESETB

:

COM19

COM18

COM17

COM16

SEG99

SEG98

SEG97

SEG96

:

PS

CS1B

CS2

MI

RS

RW_WR

E_RD

DD

V

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

:

SEG66

SEG65

SEG64

SEG63

:

SEG3

SEG2

SEG1

SEG0

COMS

COM0

COM1

:

SS

V

VOUT

C3+

C3-

C1+

C1-

C2+

C2-

SS

V

VR

V0

V1

V2

V3

V4

:

COM7

COM8

COM9

:

SS

V

TEMPS

:

COM13

COM14

COM15

COMS

Figure 46. TCP Pin Layout

57


型号：	S6B0715A01-B0CY
厂家：	SAMSUNG
描述：	33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD 33 COM / 100 SEG驱动器和控制器的STN LCD 驱动器控制器 CD
文件：	总61页 (文件大小：881K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S6B0715A01-B0CY [SAMSUNG]

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