S6C0647 [SAMSUNG]
256 CHANNEL TFT-LCD GATE DRIVER; 256道TFT -LCD栅极驱动器
| 型号： | S6C0647 |
| 厂家： | 
SAMSUNG |
| 描述： | 256 CHANNEL TFT-LCD GATE DRIVER |
| 文件： | 总14页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S6C0647
256 CHANNEL TFT-LCD GATE DRIVER
November. 1999.
Ver. 0.1
Prepared by:
Jae il Byeon
kerigma@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6C0647
256 CH. TFT-LCD GATE DRIVER
S6C0647 Specification Revision History
Content
Version
Date
0.0
0.1
Original
The contents of page 9, 10 and 13 have been modified
Aug.1999
Nov.1999
2
256 CH. TFT-LCD GATE DRIVER
S6C0647
CONTENTS
INTRODUCTION .................................................................................................... 4
FEATURES............................................................................................................. 4
BLOCK DIAGRAM................................................................................................. 5
PIN ASSIGNMENTS .............................................................................................. 6
PIN DESCRIPTIONS.............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................ 8
RECOMMENDED OPERATION RATINGS........................................................... 8
DC CHARACTERISTICS ....................................................................................... 9
AC CHARACTERISTICS ..................................................................................... 10
AC TIMING DIAGRAM......................................................................................... 11
OPERATION DESCRIPTION............................................................................... 12
OPERATION METHOD.........................................................................................................12
OUTPUT PIN.........................................................................................................................12
VOLTAGE BIASING ..............................................................................................................13
RECOMMENDED TIMING ....................................................................................................14
3
S6C0647
256 CH. TFT-LCD GATE DRIVER
INTRODUCTION
The S6C0647 is a TFT-LCD gate driver having 256 outputs. It can drive TFT panel gate ON voltage up to 40
V. It can operate within the logic voltage 3.0 to 5.5 V.
FEATURES
·
·
·
·
·
256 outputs
Maximum TFT panel gate ON voltage = 40 V
Bi - directional shift register
Logic supply voltage = 3.0 to 5.5 V
TCP available
4
256 CH. TFT-LCD GATE DRIVER
S6C0647
BLOCK DIAGRAM
VDD
VLO
VSS1
U/D
CPV
S / R S / R
001 002
S / R S / R
255 256
DI/O
DO/I
256 Shift Register
Level Shifter
OE1
OE2
OE3
VGG
256 Ouput Buffer
VSS2
G001 G002
G255 G256
Figure 1. Block Diagram
5
S6C0647
256 CH. TFT-LCD GATE DRIVER
PIN ASSIGNMENTS
G256
G255
G254
G253
VGG
VSS2
VSS1
VDD
DO/I
OE3
OE2
OE1
CPV
VLO
U/D
DI/O
VLO
VSS1
VSS2
VGG
G004
G003
G002
G001
Figure 2. Pin Assignments
6
256 CH. TFT-LCD GATE DRIVER
S6C0647
PIN DESCRIPTIONS
Symbol
Pin Name
I / O
Description
When these inputs operate as the input, the start pulse data is
read at the rising edge of shift clock, CPV.
When these inputs operate as the output, the start pulse output
is the next chip’s start pulse input. The output pulse is
generated
at the falling edge of the 256th shift clock, CPV.
When U/D = H, the shift register does right shifting operation.
(Input = DI/O and output = DO/I)
DI/O
DO/I
Start pulse input/output
I / O
When U/D = L, the shift register does left shifting operation.
(Input = DO/I and output = DI/O)
When U/D = H, DI/O ® G001 ® ¼ ¼ ® G256 ® DO/I
When U/D = L, DO/I ® G256 ® ¼ ¼ ® G001 ® DI/O
U/D
Shift direction control input
Shift clock input
I
I
The shift register operates in synchronization with the rising
edge of this input
CPV
These inputs control the state of the driver outputs.
When OE = H, the driver output is fixed to VSS2.
When OE = L, the driver output is VGG or VSS2 corresponding
to the data.
OE1
OE2
OE3
Output enable input
Driver output
I
G001
to
G256
The output signals change in synchronization with the rising
edge of shift clock input, CPV.
The amplitude of the driver output is VGG - VSS2.
O
I
The input is internally connected to the logic ground, VSS1.
The input operates as the TFT panel gate OFF voltage.
VSS2 Driver negative power supply
VLO
VGG
VDD
Logic input low voltage
Driver positive power supply
Logic positive power supply
I
I
I
Logic input range: VDD - VLO
The TFT gate ON voltage is VGG - VSS2.
3.0 to 5.5 V
The logic negative power supply, VSS1, is internally connected
to the driver negative power supply, VSS2.
VSS1
Logic negative power supply
I
7
S6C0647
256 CH. TFT-LCD GATE DRIVER
ABSOLUTE MAXIMUM RATINGS (VSS1 = VSS2 = 0 V)
Table 1. Absolute Maximum Ratings
Parameter
Symbol
VDD
VGG
VLO
VIN
Ratings
Unit
V
Logic positive power supply
Driver positive power supply
Logic input low voltage
Input voltage
- 0.3 to 21.0
- 0.3 to 45.0
V
- 0.3 to VDD + 0.3
- 0.3 to VDD + 0.3
- 20 to 75
V
V
Operation temperature
Storage temperature
Top
°C
°C
Tstg
- 55 to 150
CAUTIONS
If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded.
It is desirable to use this product within the range of the absolute maximum ratings.
The power supplying order is as follows.
ON: VLO ® VDD ® VSS1, VSS2 ® Control Input ® VGG
OFF: VGG ® Control Input ® VSS1, VSS2 ® VDD ® VLO
RECOMMENDED OPERATION RATINGS (VLO = 0 V VSS1 = VSS2)
Table 2. Recommended Operation Ratings
Parameter
Symbol
VDD
Min.
3.0
6
Typ.
Max.
5.5
40
Unit
V
Logic positive power supply
Driver positive power supply
Logic negative power supply
Driver negative power supply
Power supply voltage
Operation frequency
-
-
-
-
-
-
-
VGG
V
VSS1
- 15
- 15
21
-
0
V
VSS2
0
V
VGG - VSS2
fCPV
40
V
100
500
kHz
pF
Output load
CL
-
8
256 CH. TFT-LCD GATE DRIVER
S6C0647
DC CHARACTERISTICS (VLO = 0 V VSS1 = VSS2)
Table 3. DC Characteristics
(Ta = - 20 to 75 °C, VGG - VSS2 = 21 to 40 V, VLO - VSS1 = 15 to 0 V, VDD - VLO = 3.0 to 5.5 V)
Parameter
Symbol
Condition
Min.
Max.
Unit
Pin used
High input voltage
VIH
VLO + 0.9VX
VDD
V
(1)
VX = VDD - VLO
VLO +
0.1VX
Low input voltage
VIL
VSS1
V
High output voltage
Low output voltage
VOH
VOL
VDD - 0.4
VSS1
VDD
V
V
IOH = - 40 mA
IOL = 40 mA
(2)
VSS1 + 0.4
VOUT = VGG - 0.5 V,
VGG = 40 V, VSS2 = 0 V
G001 to
G256
500
500
ROH
-
-
W
W
LCD driver output
ON resistance
VOUT = 0.5 V,
VGG = 40 V, VSS2 = 0 V
G001 to
G256
ROL
IGG
High output current
Low output current
Without output load
VDD - VSS1 = 3.3 V
VDD - VSS1 = 19 V
-
-
-
400
400
1000
5
VGG
mA
mA
mA
mA
(1)
IDD
ILK
(3)
-
(1)
Input leak current
- 5
NOTES:
1. DI/O, DO/I, CPV, OE1, OE2, OE3, U/D used.
2. When U/D = H, DO/I used, and when U/D = L, DI/O used.
3. Input swing voltage = VDD to VDD - 3.0 V
9
S6C0647
256 CH. TFT-LCD GATE DRIVER
AC CHARACTERISTICS (VLO = 0 V VSS1 = VSS2)
Table 4. AC Characteristics
(Ta = - 20 to 75 °C, VGG - VSS2 = 21 to 40 V, VLO - VSS1 = 15 to 0 V, VDD - VLO = 3.0 to 5.5 V)
Parameter
Operation frequency
Clock pulse width
Symbol
fCPV
Condition
Min.
Max.
Unit
-
10
-
tCPVH, tCPVL
twOE
Duty = 50 %
4
-
-
ms
Output enable input width
Data setup time
-
1
tsDI
-
700
-
Data hold time
thDI
-
700
-
ns
Output delay time (1)
Output delay time (2)
Output delay time (3)
tpdDO
tpdG
CL = 30 pF
-
-
-
800
800
800
CL = 300 pF
tpdOE
10
256 CH. TFT-LCD GATE DRIVER
S6C0647
AC TIMING DIAGRAM
Figure 3. AC Timing Diagram
11
S6C0647
256 CH. TFT-LCD GATE DRIVER
OPERATION DESCRIPTION
OPERATION METHOD
The start pulse input, DI/O (when U/D is “ H” ) or DO/I (when U/D = “ L” ), is synchronized with the rising edge of
CPV and stored in the first shift register.
While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored
simultaneously.
Output pin (G1 to G256) supplies VGG voltage or VSS2 voltage to the TFT-LCD panel depending on the pulse of
the shift register.
The start pulse output, DO/I (when U/D is “ H” ) or DI/O (when U/D = “ L” ), is synchronized with the falling edge of
CPV and the pulse of the last register (G1 or G256) is transferred to the next IC.
The voltage level of the start pulse output is VDD with “ H” data, VSS1 with “ L” data
The relationship between U/D and shift data inout pin is as follows:
Table 5. The relationship between U/D and the start pulse input / output
Start pulse input / output
U/D Pin
Data shift direction
Input
DI/O
DO/I
Output
DO/I
“ H” (VDD)
G1 ® G2 ® G3 ® G4 ® G5 ® ¼ ¼ ® G256
G256 ® G255 ® G254 ® G253 ® ¼ ¼ ® G1
“ L” (VSS1 - VLO)
DI/O
OUTPUT PIN (G1 TO G256)
If the data of the shift register to an output drive pin is “ H” , the voltage level of the output is VGG and if the data
is “ L” , the level of the output is VSS2.
But, when OE is “ H” , the voltage level of the output is VSS2 irrespective of the data of the shift register.
Table 6. The voltage level of the output
Condition
Control pin to LCD panel
Controlled output pin by OE signal
Pin
State
“ H”
Output level
VSS2
OE1
OE2
OE3
OE1
OE2
OE3
G1, G4, G7, ¼ ¼ , G250, G253, G256
G2, G5, G8, ¼ ¼ , G251, G254
G3, G6, G9, ¼ ¼ , G252, G255
G1, G4, G7, ¼ ¼ , G250, G253, G256
G2, G5, G8, ¼ ¼ , G251, G254
G3, G6, G9, ¼ ¼ , G252, G255
Normal output
(VGG or VSS2)
“ L”
12
256 CH. TFT-LCD GATE DRIVER
S6C0647
VOLTAGE BIASING
The driver negative power supply, VSS2, can be any value between VLO and VLO - 15V.
And VSS2 is internally connected to the logic negative power supply, VSS1.
G1 to G256
VGG (40 V)
G1 to G256
VGG (33 V)
Input
Logic
Input
Logic
signal
Output
signal
Output
VDD (3.3 V)
VLO (0 V)
VDD (3.3 V)
VLO (0 V)
= VOFF = VSS1
VSS1 (-7 V)
= VOFF
Figure 4. Example of Voltage Biasing
13
S6C0647
256 CH. TFT-LCD GATE DRIVER
RECOMMENDED TIMING
When U/D = "H"
Input
DI/O
CPV
OE1
OE2
OE3
G1
G2
G3
G4
VGG
G256
VSS2
VSS1
VDD
Output
DO/I
When U/D = "L"
Input
DO/I
CPV
OE1
OE3
OE2
G256
G255
G254
G253
G1
VGG
VSS2
VSS1
VDD
Output
DI/O
Figure 5. Recommended Timing
14
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