首页 |元器件品牌

S6C1652 [SAMSUNG]

6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER; 6位三百〇九分之三百沟道TFT -LCD源极驱动器
S6C1652
型号： S6C1652
厂家： SAMSUNG    SAMSUNG
描述：

6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
6位三百〇九分之三百沟道TFT -LCD源极驱动器

驱动器 CD
文件： 总19页 (文件大小：201K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
August. 1999.  
Ver. 0.0  
Prepared by:  
Dae-Young, Ahn  
Mail: jesus9@samsung.co.kr  
Contents in this document are subject to change without notice. No part of this document may be reproduced  
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express  
written permission of LCD Driver IC Team.  
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652 Specification Revision History  
Content  
Version  
0.0  
Date  
Original  
Aug.1999  
2
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
CONTENTS  
INTRODUCTION................................................................................................................................................. 4  
FEATURES ......................................................................................................................................................... 4  
BLOCK DIAGRAM.............................................................................................................................................. 5  
PIN ASSIGNMENTS............................................................................................................................................ 6  
PIN DESCRIPTIONS........................................................................................................................................... 7  
OPERATION DESCRIPTION .............................................................................................................................. 8  
DISPLAY DATA TRANSFER............................................................................................................................ 8  
EXTENSION OF OUTPUT ............................................................................................................................... 8  
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8  
ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 15  
RECOMMENDED OPERATION CONDITIONS................................................................................................. 15  
DC CHARACTERISTICS................................................................................................................................... 16  
AC CHARACTERISTICS................................................................................................................................... 17  
WAVEFORMS................................................................................................................................................... 18  
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 19  
3
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
INTRODUCTION  
The S6C1652 is a 300 / 309 channel output, TFT-LCD source driver for an 64 gray-scale LCD panel. Data input  
is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 color by  
output of 64 values gamma-corrected.  
This device has an internal D/A (digital-to-analog) converter for each output and 18 (9-by-2) reference voltages.  
Because the output dynamic range is as large as 6.0 - 12.6 Vp-p, it is unnecessary to operate level inversion of  
the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side,  
output gray-scale voltages with different polarity can be output to the odd number output pins and the even output  
pins.  
S6C1652 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel  
connection conveniently. Maximum operation clock frequency is 55 MHz at 2.7 V logic operation, single edge  
and it can be applied to the TFT-LCD panel of SVGA to XGA standard.  
FEATURES  
·
·
·
·
·
·
·
·
·
·
·
·
TFT active matrix LCD source driver LSI  
64 gray-scale is possible through 18 (9-by-2) reference voltages and D/A converter  
Dot inversion display is possible  
CMOS level input  
Compatible with gamma-correction  
Input of 6bits (gray-scale data) by 3 dots (R,G,B)  
Logic supply voltage: 2.7 - 3.6 V  
LCD driver supply voltage: 6.4 - 13.0 V  
Output dynamic range: 6.0 - 12.6 Vp-p  
Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 2.7 V operation)  
Output: 300 / 309 outputs  
TCP available  
4
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
BLOCK DIAGRAM  
BIAS  
Output Buffer  
D/A Converter  
Data Latch  
TESTB  
POL  
VGMA1 -  
VGMA18  
18  
6
6
6
6
6
6
CLK1  
6
6
6
6
6
6
6
6
6
6
6
6
Data Register  
6
6
6
D00 - D05  
D10 - D15  
D20 - D25  
18  
103bit Shift Register  
SHL  
DIO2  
DIO1  
CLK2  
Figure 1. S6C1652 Block Diagram  
5
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
PIN ASSIGNMENTS  
Y001  
Y002  
Y003  
Y004  
VSS2  
VDD2  
VSS1  
D05  
D04  
D03  
D02  
D01  
D00  
D15  
D14  
D13  
D12  
D11  
D10  
DIO1  
VGMA1  
VGMA2  
VGMA3  
VGMA4  
VGMA5  
VGMA6  
VGMA7  
VGMA8  
VGMA9  
VGMA10  
VGMA11  
VGMA12  
VGMA13  
VGMA14  
VGMA15  
VGMA16  
VGMA17  
VGMA18  
SELT  
CLK2  
DIO2  
CLK1  
POL  
D25  
D24  
D23  
D22  
D21  
D20  
SHL  
TESTB  
VDD1  
VDD2  
VSS2  
Y306  
Y307  
Y308  
Y309  
Figure 2. S6C1652 Pin Assignments  
6
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
PIN DESCRIPTIONS  
Symbol  
VDD1  
Pin Name  
Logic power supply  
Driver power supply  
Logic ground  
Description  
2.7 - 3.6 V  
VDD2  
6.4 - 13.0 V  
Ground (0 V)  
Ground (0 V)  
VSS1  
VSS2  
Driver ground  
Y1 - Y309  
Driver outputs  
The D/A converted 64 gray-scale analog voltage is output.  
D0<0:5>  
- D2<0:5>  
The display data is input with a width of 18 bits,  
gray-scale data (6 bits) by 3 dots (R,G,B) DX0: LSB, DX5: MSB  
Display data input  
This pin controls the direction of shift register in cascade connection.  
The shift direction of the shift registers is as follows.  
SHL = H: DIO1 input, Y1 ® Y309, DIO2 output  
SHL  
Shift direction control input  
SHL = L: DIO2 input, Y309 ® Y1, DIO1 output  
SHL = H: Used as the start pulse input pin  
SHL = L: Used as the start pulse output pin  
DIO1  
DIO2  
Start pulse input / output  
Start pulse input / output  
SHL = H: Used as the start pulse output pin  
SHL = L: Used as the start pulse input pin  
POL = H: The reference voltage for odd number outputs are VGMA1 –  
VGMA9 and those for even number outputs are VGMA10 – VGMA18  
POL = L: The reference voltage for odd number outputs are VGMA10  
– VGMA18 and those for even number outputs are VGMA1 – VGMA9  
POL  
Polarity input  
Refer to the shift register's shift clock input. The display data is loaded  
to the data register at the rising edge of CLK2.  
CLK2  
Shift clock input  
Latches the contents of the data register at rising edge and transfers  
them to the D/A converter. Also, after CLK1 input, clears the internal  
shift register contents. After 1 pulse input on start, operates normally.  
CLK1 input timing refers to the "Relationships between CLK1 start  
pulse (DIO1, DIO2) and blanking period" of the switching characteristic  
waveform. Outputs the gray-scale data at rising edge.  
CLK1  
Latch input  
Input the gamma corrected power supplies from external source.  
VDD2 > VGMA1 > VGMA2 > ¼ ¼ ¼ > VGMA17 > VGMA18 > VSS2  
Keep gray-scale power supply unchanged during the gray-scale  
voltage output.  
VGMA1  
–
VGMA18  
Gamma corrected power  
supplies  
SELT = H: 300 Output (Y151 - Y159 are disabled)  
SELT = L: 309 Output  
SELT  
Output selection input  
Test input  
TESTB = H: Normal operation mode  
TESTB = L: Test mode (OP AMP CUT-OFF, Rpu = 30kW)  
TESTB  
7
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
OPERATION DESCRIPTION  
DISPLAY DATA TRANSFER  
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse  
enables the data transfer operation. After the falling edge of DIO1 (or DIO2), display data is valid on the rising  
edge of CLK2. Once all the data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state  
automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2)  
input. When next DIO1 (or DIO2) is provided, new display data is valid on the next rising edge of CLK2 after  
the falling edge of DIO1 (or DIO2).  
EXTENSION OF OUTPUT  
Output pin can be adjusted to an extended screen by cascade connection.  
(1) SHL = "L"  
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins  
except DIO1 and DIO2 are connected together in each device.  
(2)SHL = "H"  
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins  
except DIO2 and DIO1 are connected together in each device.  
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE  
The LCD drive output voltages are determined by the input data and 18 (9-by-2) gamma corrected power  
supplies (VGMA1 - VGMA18). Besides, to be able to deal with dot-line inversion when mounted on a single-  
side, gradation voltages with different polarity can be output to the odd number output pins and the even  
number output pins. Among 9-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity  
with respect to the common voltage, for the respective 9 gamma corrected voltages of VGMA1 - VGMA9 and  
VGMA10 - VGMA18.  
SHL = H  
Y1  
Y2  
......  
......  
Y307  
Y308  
Last  
Y309  
OUTPUT  
Y3  
-
First  
DATA  
D00 - D05 D10 - D15 D20 - D25  
D00 - D05 D10 - D15 D20 - D25  
SHL = L  
OUTPUT  
-
Y1  
Y2  
Y3  
......  
......  
Y307  
Y308  
First  
Y309  
Last  
DATA  
D00 - D05 D10 - D15 D20 - D25  
D00 - D05 D10 - D15 D20 - D25  
Figure 3. Relationship between Shift Direction and Output Data  
8
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
VDD2  
VGMA1  
VGMA2  
VGMA3  
VGMA4  
VGMA5  
VGMA6  
VGMA7  
VGMA8  
VGMA9  
VCOM  
VGMA10  
VGMA11  
VGMA12  
VGMA13  
VGMA14  
VGMA15  
VGMA16  
VGMA17  
VGMA18  
VSS2  
00H  
08H  
10H  
18H  
20H  
28H  
30H  
38H  
3FH Input data  
Figure 4. Gamma Correction Curve  
9
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
Table 1. Resistor Strings (R0 - R63, unit:  
W)  
Name  
Value  
510  
510  
510  
510  
510  
510  
510  
510  
255  
255  
255  
255  
255  
255  
255  
255  
Name  
R16  
R17  
R18  
R19  
R20  
R21  
R22  
R23  
R24  
R25  
R26  
R27  
R28  
R29  
R30  
R31  
Value  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
Name  
R32  
R33  
R34  
R35  
R36  
R37  
R38  
R39  
R40  
R41  
R42  
R43  
R44  
R45  
R46  
R47  
Value  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
170  
Name  
R48  
R49  
R50  
R51  
R52  
R53  
R54  
R55  
R56  
R57  
R58  
R59  
R60  
R61  
R62  
R63  
Value  
255  
255  
255  
255  
255  
255  
255  
255  
510  
510  
510  
510  
510  
510  
510  
510  
R0  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
R9  
R10  
R11  
R12  
R13  
R14  
R15  
10  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
Table 2. Relationship between Input Data and Output Voltage Value  
Input data  
G/S  
Output voltage  
DX5 DX4 DX3 DX2 DX1 DX0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VGMA1  
00H  
01H  
02H  
03H  
04H  
05H  
06H  
07H  
VH0  
VH1  
VH2  
VH3  
VH4  
VH5  
VH6  
VH7  
VGMA1 + (VGMA2 - VGMA1) ´ 1 / 8  
VGMA1 + (VGMA2 - VGMA1) ´ 2 / 8  
VGMA1 + (VGMA2 - VGMA1) ´ 3 / 8  
VGMA1 + (VGMA2 - VGMA1) ´ 4 / 8  
VGMA1 + (VGMA2 - VGMA1) ´ 5 / 8  
VGMA1 + (VGMA2 - VGMA1) ´ 6 / 8  
VGMA1 + (VGMA2 - VGMA1) ´ 7 / 8  
VGMA2  
VH8  
VH9  
08H  
09H  
0AH  
0BH  
0CH  
0DH  
0EH  
0FH  
VGMA2 + (VGMA3 - VGMA2) ´ 1 / 8  
VGMA2 + (VGMA3 - VGMA2) ´ 2 / 8  
VGMA2 + (VGMA3 - VGMA2) ´ 3 / 8  
VGMA2 + (VGMA3 - VGMA2) ´ 4 / 8  
VGMA2 + (VGMA3 - VGMA2) ´ 5 / 8  
VGMA2 + (VGMA3 - VGMA2) ´ 6 / 8  
VGMA2 + (VGMA3 - VGMA2) ´ 7 / 8  
VH10  
VH11  
VH12  
VH13  
VH14  
VH15  
VGMA3  
VH16  
VH17  
VH18  
VH19  
VH20  
VH21  
VH22  
VH23  
10H  
11H  
12H  
13H  
14H  
15H  
16H  
17H  
VGMA3 + (VGMA4 - VGMA3) ´ 1 / 8  
VGMA3 + (VGMA4 - VGMA3) ´ 2 / 8  
VGMA3 + (VGMA4 - VGMA3) ´ 3 / 8  
VGMA3 + (VGMA4 - VGMA3) ´ 4 / 8  
VGMA3 + (VGMA4 - VGMA3) ´ 5 / 8  
VGMA3 + (VGMA4 - VGMA3) ´ 6 / 8  
VGMA3 + (VGMA4 - VGMA3) ´ 7 / 8  
VGMA4  
VH24  
VH25  
VH26  
VH27  
VH28  
VH29  
VH30  
VH31  
18H  
19H  
1AH  
1BH  
1CH  
1DH  
1EH  
1FH  
VGMA4 + (VGMA5 - VGMA4) ´ 1 / 8  
VGMA4 + (VGMA5 - VGMA4) ´ 2 / 8  
VGMA4 + (VGMA5 - VGMA4) ´ 3 / 8  
VGMA4 + (VGMA5 - VGMA4) ´ 4 / 8  
VGMA4 + (VGMA5 - VGMA4) ´ 5 / 8  
VGMA4 + (VGMA5 - VGMA4) ´ 6 / 8  
VGMA4 + (VGMA5 - VGMA4) ´ 7 / 8  
NOTE: VDD2>VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9  
11  
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
Table 2. Relationship between Input Data and Output Voltage Value (Continued)  
Input data  
G/S  
Output voltage  
DX5 DX4 DX3 DX2 DX1 DX0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGMA5  
20H  
21H  
22H  
23H  
24H  
25H  
26H  
27H  
VH32  
VH33  
VH34  
VH35  
VH36  
VH37  
VH38  
VH39  
VGMA5 + (VGMA6 - VGMA5) ´ 1 / 8  
VGMA5 + (VGMA6 - VGMA5) ´ 2 / 8  
VGMA5 + (VGMA6 - VGMA5) ´ 3 / 8  
VGMA5 + (VGMA6 - VGMA5) ´ 4 / 8  
VGMA5 + (VGMA6 - VGMA5) ´ 5 / 8  
VGMA5 + (VGMA6 - VGMA5) ´ 6 / 8  
VGMA5 + (VGMA6 - VGMA5) ´ 7 / 8  
VGMA6  
VH40  
VH41  
VH42  
VH43  
VH44  
VH45  
VH46  
VH47  
28H  
29H  
2AH  
2BH  
2CH  
2DH  
2EH  
2FH  
VGMA6 + (VGMA7 - VGMA6) ´ 1 / 8  
VGMA6 + (VGMA7 - VGMA6) ´ 2 / 8  
VGMA6 + (VGMA7 - VGMA6) ´ 3 / 8  
VGMA6 + (VGMA7 - VGMA6) ´ 4 / 8  
VGMA6 + (VGMA7 - VGMA6) ´ 5 / 8  
VGMA6 + (VGMA7 - VGMA6) ´ 6 / 8  
VGMA6 + (VGMA7 - VGMA6) ´ 7 / 8  
VGMA7  
VH48  
VH49  
VH50  
VH51  
VH52  
VH53  
VH54  
VH55  
30H  
31H  
32H  
33H  
34H  
35H  
36H  
37H  
VGMA7 + (VGMA8 - VGMA7) ´ 1 / 8  
VGMA7 + (VGMA8 - VGMA7) ´ 2 / 8  
VGMA7 + (VGMA8 - VGMA7) ´ 3 / 8  
VGMA7 + (VGMA8 - VGMA7) ´ 4 / 8  
VGMA7 + (VGMA8 - VGMA7) ´ 5 / 8  
VGMA7 + (VGMA8 - VGMA7) ´ 6 / 8  
VGMA7 + (VGMA8 - VGMA7) ´ 7 / 8  
VGMA8  
VH56  
VH57  
VH58  
VH59  
VH60  
VH61  
VH62  
VH63  
38H  
39H  
3AH  
3BH  
3CH  
3DH  
3EH  
3FH  
VGMA8 + (VGMA9 - VGMA8) ´ 1 / 8  
VGMA8 + (VGMA9 - VGMA8) ´ 2 / 8  
VGMA8 + (VGMA9 - VGMA8) ´ 3 / 8  
VGMA8 + (VGMA9 - VGMA8) ´ 4 / 8  
VGMA8 + (VGMA9 - VGMA8) ´ 5 / 8  
VGMA8 + (VGMA9 - VGMA8) ´ 6 / 8  
VGMA8 + (VGMA9 - VGMA8) ´ 7 / 8  
12  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
Table 2. Relationship between Input Data and Output Voltage Value (Continued)  
Input data  
G/S  
Output voltage  
DX5 DX4 DX3 DX2 DX1 DX0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VGMA18  
00H  
01H  
02H  
03H  
04H  
05H  
06H  
07H  
VL0  
VL1  
VL2  
VL3  
VL4  
VL5  
VL6  
VL7  
VGMA18 + (VGMA17 - VGMA18) ´ 1 / 8  
VGMA18 + (VGMA17 - VGMA18) ´ 2 / 8  
VGMA18 + (VGMA17 - VGMA18) ´ 3 / 8  
VGMA18 + (VGMA17 - VGMA18) ´ 4 / 8  
VGMA18 + (VGMA17 - VGMA18) ´ 5 / 8  
VGMA18 + (VGMA17 - VGMA18) ´ 6 / 8  
VGMA18 + (VGMA17 - VGMA18) ´ 7 / 8  
VGMA17  
VL8  
VL9  
08H  
09H  
0AH  
0BH  
0CH  
0DH  
0EH  
0FH  
VGMA17 + (VGMA16 - VGMA17) ´ 1 / 8  
VGMA17 + (VGMA16 - VGMA17) ´ 2 / 8  
VGMA17 + (VGMA16 - VGMA17) ´ 3 / 8  
VGMA17 + (VGMA16 - VGMA17) ´ 4 / 8  
VGMA17 + (VGMA16 - VGMA17) ´ 5 / 8  
VGMA17 + (VGMA16 - VGMA17) ´ 6 / 8  
VGMA17 + (VGMA16 - VGMA17) ´ 7 / 8  
VL10  
VL11  
VL12  
VL13  
VL14  
VL15  
VGMA16  
VL16  
VL17  
VL18  
VL19  
VL20  
VL21  
VL22  
VL23  
10H  
11H  
12H  
13H  
14H  
15H  
16H  
17H  
VGMA16 + (VGMA15 - VGMA16) ´ 1 / 8  
VGMA16 + (VGMA15 - VGMA16) ´ 2 / 8  
VGMA16 + (VGMA15 - VGMA16) ´ 3 / 8  
VGMA16 + (VGMA15 - VGMA16) ´ 4 / 8  
VGMA16 + (VGMA15 - VGMA16) ´ 5 / 8  
VGMA16 + (VGMA15 - VGMA16) ´ 6 / 8  
VGMA16 + (VGMA15 - VGMA16) ´ 7 / 8  
VGMA15  
VL24  
VL25  
VL26  
VL27  
VL28  
VL29  
VL30  
VL31  
18H  
19H  
1AH  
1BH  
1CH  
1DH  
1EH  
1FH  
VGMA15 + (VGMA14 - VGMA15) ´ 1 / 8  
VGMA15 + (VGMA14 - VGMA15) ´ 2 / 8  
VGMA15 + (VGMA14 - VGMA15) ´ 3 / 8  
VGMA15 + (VGMA14 - VGMA15) ´ 4 / 8  
VGMA15 + (VGMA14 - VGMA15) ´ 5 / 8  
VGMA15 + (VGMA14 - VGMA15) ´ 6 / 8  
VGMA15 + (VGMA14 - VGMA15) ´ 7 / 8  
NOTE: VGMA10>VGMA11>VGMA12>VGMA13>VGMA14>VGMA15>VGMA16>VGMA17>VGMA18>VSS2  
13  
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
Table 2. Relationship between Input Data and Output Voltage Value (Continued)  
Input data  
G/S  
Output voltage  
DX5 DX4 DX3 DX2 DX1 DX0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGMA14  
20H  
21H  
22H  
23H  
24H  
25H  
26H  
27H  
VL32  
VL33  
VL34  
VL35  
VL36  
VL37  
VL38  
VL39  
VGMA14 + (VGMA13 - VGMA14) ´ 1 / 8  
VGMA14 + (VGMA13 - VGMA14) ´ 2 / 8  
VGMA14 + (VGMA13 - VGMA14) ´ 3 / 8  
VGMA14 + (VGMA13 - VGMA14) ´ 4 / 8  
VGMA14 + (VGMA13 - VGMA14) ´ 5 / 8  
VGMA14 + (VGMA13 - VGMA14) ´ 6 / 8  
VGMA14 + (VGMA13 - VGMA14) ´ 7 / 8  
VGMA13  
VL40  
VL41  
VL42  
VL43  
VL44  
VL45  
VL46  
VL47  
28H  
29H  
2AH  
2BH  
2CH  
2DH  
2EH  
2FH  
VGMA13 + (VGMA12 - VGMA13) ´ 1 / 8  
VGMA13 + (VGMA12 - VGMA13) ´ 2 / 8  
VGMA13 + (VGMA12 - VGMA13) ´ 3 / 8  
VGMA13 + (VGMA12 - VGMA13) ´ 4 / 8  
VGMA13 + (VGMA12 - VGMA13) ´ 5 / 8  
VGMA13 + (VGMA12 - VGMA13) ´ 6 / 8  
VGMA13 + (VGMA12 - VGMA13) ´ 7 / 8  
VGMA12  
VL48  
VL49  
VL50  
VL51  
VL52  
VL53  
VL54  
VL55  
30H  
31H  
32H  
33H  
34H  
35H  
36H  
37H  
VGMA12 + (VGMA11 - VGMA12) ´ 1 / 8  
VGMA12 + (VGMA11 - VGMA12) ´ 2 / 8  
VGMA12 + (VGMA11 - VGMA12) ´ 3 / 8  
VGMA12 + (VGMA11 - VGMA12) ´ 4 / 8  
VGMA12 + (VGMA11 - VGMA12) ´ 5 / 8  
VGMA12 + (VGMA11 - VGMA12) ´ 6 / 8  
VGMA12 + (VGMA11 - VGMA12) ´ 7 / 8  
VGMA11  
VL56  
VL57  
VL58  
VL59  
VL60  
VL61  
VL62  
VL63  
38H  
39H  
3AH  
3BH  
3CH  
3DH  
3EH  
3FH  
VGMA11 + (VGMA10 - VGMA11) ´ 1 / 8  
VGMA11 + (VGMA10 - VGMA11) ´ 2 / 8  
VGMA11 + (VGMA10 - VGMA11) ´ 3 / 8  
VGMA11 + (VGMA10 - VGMA11) ´ 4 / 8  
VGMA11 + (VGMA10 - VGMA11) ´ 5 / 8  
VGMA11 + (VGMA10 - VGMA11) ´ 6 / 8  
VGMA11 + (VGMA10 - VGMA11) ´ 7 / 8  
14  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
ABSOLUTE MAXIMUM RATINGS  
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)  
Parameter  
Symbol  
VDD1  
Ratings  
-0.3 to 6.5  
Unit  
V
Logic supply voltage  
Driver supply voltage  
VDD2  
-0.3 to 15.0  
V
VGMA1 - 18  
Others  
DIO1, 2  
Y1 - Y309  
Pd  
-0.3 to VDD2 + 0.3  
-0.3 to VDD1 + 0.3  
-0.3 to VDD1 + 0.3  
-0.3 to VDD2 + 0.3  
150 (1)  
Input voltage  
V
V
Output voltage  
Operating power dissipation  
Operation temperature  
Storage temperature  
mW  
°C  
Top  
-20 to 75  
Tstg  
-55 to 125  
°C  
NOTE: Relationship between TFT-LCD panel and Pd (Pd µ CL* (VDD2)2 * fCLK1)  
CAUTIONS:  
If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently  
destroyed. These are stress ratings only, and functional operation of the device at these or any other  
condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to  
absolute maximum rated conditions for extended periods may affect device reliability.  
Turn on power order: VDD1  
®
control signal input  
®
VDD2  
®
VGMA1  
-
VGMA18  
Turn off power order: VGMA1 - VGMA18 ® VDD2 ® control signal input ® VDD1  
RECOMMENDED OPERATION CONDITIONS  
Table 4. Recommended Operation Conditions (Ta = -20 to 75 °C, VSS1 = VSS2 = 0 V)  
Parameter  
Symbol  
VDD1  
VDD2 (1)  
Min.  
2.7  
Typ.  
Max.  
3.6  
Unit  
Logic supply voltage  
Driver supply voltage  
3.0  
V
6.4  
9.0  
13.0  
V
VGMA1 - VGMA9  
VGMA10 - VGMA18  
Vyo  
0.5VDD2  
VSS2 + 0.2  
VSS2 + 0.2  
-
-
-
VDD2 - 0.2  
0.5VDD2  
VDD2 - 0.2  
55  
V
V
Gamma corrected voltage  
Driver part output voltage  
Maximum clock frequency  
Output load capacitance  
V
fmax  
CL(1)  
VDD1 = 2.7 V  
-
MHz  
pF / PIN  
-
150  
NOTE: Relationship between TFT-LCD panel and Pd (Pd µ CL* (VDD2)2 * fCLK1)  
15  
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
DC CHARACTERISTICS  
Table 5. DC Characteristics (Ta = -20 to 75  
°C, VDD1 = 2.7 to 3.6 V, VDD2 = 6.4 to 13.0 V, VSS1 = VSS2 =  
0V)  
Parameter  
Symbol  
VIH  
Condition  
Min.  
Typ.  
Max.  
Unit  
V
High level input voltage  
Low level input voltage  
Input leakage current  
High level output voltage  
Low level output voltage  
0.75VDD1  
-
-
-
-
-
VDD1  
SHL, CLK2, D00 - D25,  
CLK1, SELT, POL, DIO1  
(DIO2)  
VIL  
0
0.25VDD1  
IL  
-1  
1
-
mA  
V
VOH  
VOL  
DIO1 (DIO2), IO = -1.0 mA  
DIO1 (DIO2), IO = +1.0 mA  
VDD1 - 0.5  
-
0.5  
Refer to Table 1. Resistor  
Strings  
Resistor  
R0 - R63  
IVOH  
-
Rn ´ 0.7  
Rn ´ 1.3  
W
VDD2 = 9.0 V,  
-
-1.0  
1.0  
-0.5  
-
mA  
mA  
Vx = 2.5 V, Vyo = 8.5 V(1)  
Driver output current  
VDD2 = 9.0 V,  
IVOL  
0.5  
Vx = 6.5 V, Vyo = 0.5 V(1)  
Input data: 00H to 3FH  
Input data: 00H to 3FH  
Output voltage deviation  
Output voltage range  
DVO  
-
±8  
±15  
mV  
V
Vyo  
VSS2 + 0.2  
-
VDD2 - 0.2  
Logic part dynamic  
current  
IDD1  
IDD2  
VDD1 = 3.0 V (2)  
-
-
2.0  
5.0  
3.5  
7.0  
mA  
Driver part dynamic  
current  
VDD1 = 3.0 V, VDD2 = 9.0 V  
(2)(3)(4)  
NOTES:  
1. Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309.  
2. CLK1 period is defined to be 20 ms at fCLK2 = 33 MHz, data pattern = 101010(checkerboard pattern), Ta = 25 °C.  
3. The current consumption per driver when XGA single-sided mounting (10 drivers) is connected in cascade  
4. Yout Load Condition  
5kW  
10kW  
10kW  
YOUT  
25pF  
25pF  
25pF  
5k  
W
10k  
10k  
W
W
VCOM = 0.5VDD2  
Figure 5. Yout Load Condition  
16  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
AC CHARACTERISTICS  
Table 6. AC Characteristics  
°C, VDD1 = 2.7 to 3.6 V, VDD2 = 6.4 to 13.0 V, VSS1 = VSS2 = 0 V)  
(Ta = -20 to 75  
Parameter  
Symbol  
Condition  
Min.  
18  
4
Typ.  
Max.  
Unit  
Clock pulse width  
Clock pulse low period  
Clock pulse high period  
Data setup time  
PWCLK  
-
-
-
-
-
-
-
-
-
-
-
PWCLK (L)  
PWCLK (H)  
tSETUP1  
tHOLD1  
-
-
4
-
-
4
-
ns  
Data hold time  
-
0
-
Start pulse setup time  
Start pulse hold time  
Start pulse delay time  
tSETUP2  
tHOLD2  
-
4
-
-
0
-
tPLH1  
CL = 20pF  
-
12  
CLK1 – DIO (input)  
setup time  
tSETUP3  
-
1
-
-
CLK2  
period  
CLK1 pulse high period  
Driver output delay time1  
Driver output delay time2  
Data invalid period  
PWCLK1  
tPHL1(1)  
tPHL2(2)  
-
3
-
-
-
-
Refer to Figure 5  
Refer to Figure 5  
DIO1 (2)• ® CLK2•  
-
5
ms  
-
-
10  
tINV  
1
-
CLK2  
period  
Last data timing  
tLDT  
1
6
-
-
-
CLK1 - CLK2 time  
tCLK1 - CLK2  
tPOL - CLK1  
-
ns  
ns  
CLK1• ® CLK2•  
POL• or¯ ® CLK1•  
POL - CLK1 time  
-9  
-
NOTES:  
1. The value is specified when the drive voltage value reaches the target output voltage level of 90%  
2. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.  
17  
S6C1652  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
WAVEFORMS (VIH = 0.75VDD1, VIL = 0.25VDD1)  
Figure 6. Waveforms  
18  
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER  
S6C1652  
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND  
BLANKING PERIOD  
Figure 7. Waveforms  
19  

相关型号：

S6C31SS-10.0000

 Oscillator,
PERICOM

S6C31SS-10.0000(T)

 Oscillator,
PERICOM

S6C31SS-30.0000(T)

 Oscillator,
PERICOM

S6C31SS-FREQ

 Clipped Sine Output Oscillator, 10MHz Min, 30MHz Max, CERAMIC, SMD, 8 PIN
PERICOM

S6C31SS-FREQ(T)

 Clipped Sine Output Oscillator, 10MHz Min, 30MHz Max, CERAMIC, SMD, 8 PIN
PERICOM

S6C31SSVA-10.0000

 Oscillator,
PERICOM

S6C31SSVA-10.0000(T)

 Oscillator,
PERICOM

S6C31SSVA-30.0000

 Oscillator,
PERICOM

S6C31SSVB-10.0000

 Oscillator,
PERICOM

S6C31SSVB-10.0000(T)

 Oscillator,
PERICOM

S6C31SSVB-30.0000

 Oscillator,
PERICOM

S6C31SSVB-30.0000(T)

 Oscillator,
PERICOM
©2020 ICPDF网 联系我们和版权申明