SIM6800M [SANKEN]
500V / 600V High Voltage 3-phase Motor Driver ICs;
| 型号： | SIM6800M |
| 厂家： | 
SANKEN ELECTRIC |
| 描述： | 500V / 600V High Voltage 3-phase Motor Driver ICs |
| 文件： | 总52页 (文件大小：2101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
500V / 600V High Voltage 3-phase Motor Driver ICs
SIM6800M Series
Data Sheet
Description
Package
The SIM6800M series are high voltage 3-phase motor
driver ICs in which transistors, a pre-driver IC (MIC),
and bootstrap circuits (diodes and resistors) are highly
integrated.
DIP40
Mold Dimensions: 36.0 mm × 14.8 mm × 4.0 mm
40
These products can run on a 3-shunt current detection
system and optimally control the inverter systems of
small- to medium-capacity motors that require universal
input standards.
21
1
Features
● Built-in Bootstrap Diodes with Current Limiting
Resistors (60 Ω)
Leadform 2971
Not to scale
20
● CMOS-compatible Input (3.3 V or 5 V)
● Bare Lead Frame: Pb-free (RoHS Compliant)
● Isolation Voltage: 1500 V (for 1 min)
UL-recognized Component (File No.: E118037)
(SIM6880M UL Recognition Pending)
● Fault Signal Output at Protection Activation (FO Pin)
● High-side Shutdown Signal Input (SD Pin)
● Protections Include:
Selection Guide
Part
Number
VDSS/VCES
IO
2.0 A
Feature
SIM6811M
Overcurrent Limit (OCL): Auto-restart
Overcurrent Protection (OCP): Auto-restart
Undervoltage Lockout for Power Supply
High-side (UVLO_VB): Auto-restart
Low-side (UVLO_VCC): Auto-restart
Thermal Shutdown (TSD): Auto-restart
500 V
2.5 A Power MOSFET SIM6812M
3.0 A
3.0 A
SIM6813M
SIM6880M
SIM6822M
SIM6827M
IGBT with FRD,
low switching
dissipation
600 V
5.0 A
Typical Application (SIM681xM)
VB1A
21
VCC
VB1B
VCC1
17
30
20
23
Applications
CBOOT1
VB2
VB3
For motor drives such as:
CBOOT2
● Refrigerator Compressor Motor
● Fan Motor and Pump Motor for Washer and Dryer
● Fan Motor for Air Conditioner, Air Purifier, and
Electric Fan
CBOOT3
COM1
HIN3
HIN2
HIN1
SD
16
15
14
13
12
VDC
HIN3
HIN2
HIN1
VBB
28
U
V
31
19
OCL
LIN3
LIN2
LIN1
COM2
VCC2
FO
10
9
MIC
LIN3
LIN2
LIN1
V1
V2
W1
W2
26
35
M
8
7
5 V
RFO
6
24
37
5
4
OCP
Fault
3
LS1
11
2
CFO
LS2
LS2
33
40
RO
LS3A
LS3B
1
CS CDC
RS
CO
GND
SIM6800M-DSE Rev.1.5
Jul. 18, 2018
SANKEN ELECTRIC CO., LTD
http://www.sanken-ele.co.jp/en
1
© SANKEN ELECTRIC CO., LTD. 2014
SIM6800M Series
Contents
Description ------------------------------------------------------------------------------------------------------1
Contents ---------------------------------------------------------------------------------------------------------2
1. Absolute Maximum Ratings-----------------------------------------------------------------------------4
2. Recommended Operating Conditions -----------------------------------------------------------------5
3. Electrical Characteristics--------------------------------------------------------------------------------6
3.1 Characteristics of Control Parts------------------------------------------------------------------6
3.2 Bootstrap Diode Characteristics -----------------------------------------------------------------7
3.3 Thermal Resistance Characteristics -------------------------------------------------------------7
3.4 Transistor Characteristics-------------------------------------------------------------------------8
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
SIM6811M --------------------------------------------------------------------------------------9
SIM6812M --------------------------------------------------------------------------------------9
SIM6813M ------------------------------------------------------------------------------------ 10
SIM6880M ------------------------------------------------------------------------------------ 10
SIM6822M ------------------------------------------------------------------------------------ 11
SIM6827M ------------------------------------------------------------------------------------ 11
4. Mechanical Characteristics --------------------------------------------------------------------------- 12
5. Insulation Distance-------------------------------------------------------------------------------------- 12
6. Truth Table----------------------------------------------------------------------------------------------- 13
7. Block Diagrams------------------------------------------------------------------------------------------ 14
8. Pin Configuration Definitions------------------------------------------------------------------------- 15
9. Typical Applications------------------------------------------------------------------------------------ 16
10. Physical Dimensions ------------------------------------------------------------------------------------ 17
11. Marking Diagram --------------------------------------------------------------------------------------- 18
12. Functional Descriptions-------------------------------------------------------------------------------- 19
12.1 Turning On and Off the IC---------------------------------------------------------------------- 19
12.2 Pin Descriptions ----------------------------------------------------------------------------------- 19
12.2.1 U, V, V1, V2, W1, and W2----------------------------------------------------------------- 19
12.2.2 VB1A, VB1B, VB2, and VB3-------------------------------------------------------------- 19
12.2.3 VCC1 and VCC2 ---------------------------------------------------------------------------- 20
12.2.4 COM1 and COM2--------------------------------------------------------------------------- 20
12.2.5 HIN1, HIN2, and HIN3; LIN1, LIN2, and LIN3 -------------------------------------- 21
12.2.6 VBB -------------------------------------------------------------------------------------------- 21
12.2.7 LS1, LS2, LS3A, and LS3B---------------------------------------------------------------- 22
12.2.8 OCP and OCL ------------------------------------------------------------------------------- 22
12.2.9 SD----------------------------------------------------------------------------------------------- 22
12.2.10 FO ---------------------------------------------------------------------------------------------- 22
12.3 Protection Functions------------------------------------------------------------------------------ 23
12.3.1 Fault Signal Output------------------------------------------------------------------------- 23
12.3.2 Shutdown Signal Input--------------------------------------------------------------------- 23
12.3.3 Undervoltage Lockout for Power Supply (UVLO) ----------------------------------- 23
12.3.4 Overcurrent Limit (OCL) ----------------------------------------------------------------- 24
12.3.5 Overcurrent Protection (OCP) ----------------------------------------------------------- 25
12.3.6 Thermal Shutdown (TSD) ----------------------------------------------------------------- 26
13. Design Notes---------------------------------------------------------------------------------------------- 26
13.1 PCB Pattern Layout ------------------------------------------------------------------------------ 26
13.2 Considerations in Heatsink Mounting -------------------------------------------------------- 26
13.3 Considerations in IC Characteristics Measurement --------------------------------------- 27
14. Calculating Power Losses and Estimating Junction Temperatures--------------------------- 28
14.1 IGBT------------------------------------------------------------------------------------------------- 28
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SIM6800M Series
14.1.1 IGBT Steady-state Loss, PON -------------------------------------------------------------- 28
14.1.2 IGBT Switching Loss, PSW----------------------------------------------------------------- 28
14.1.3 Estimating Junction Temperature of IGBT-------------------------------------------- 28
14.2 Power MOSFET----------------------------------------------------------------------------------- 29
14.2.1 Power MOSFET Steady-state Loss, PRON----------------------------------------------- 29
14.2.2 Power MOSFET Switching Loss, PSW--------------------------------------------------- 29
14.2.3 Body Diode Steady-state Loss, PSD ------------------------------------------------------- 30
14.2.4 Estimating Junction Temperature of Power MOSFET------------------------------ 30
15. Performance Curves------------------------------------------------------------------------------------ 31
15.1 Transient Thermal Resistance Curves -------------------------------------------------------- 31
15.2 Performance Curves of Control Parts--------------------------------------------------------- 32
15.3 Performance Curves of Output Parts --------------------------------------------------------- 37
15.3.1 Output Transistor Performance Curves------------------------------------------------ 37
15.3.2 Switching Losses----------------------------------------------------------------------------- 39
15.4 Allowable Effective Current Curves----------------------------------------------------------- 42
15.4.1 SIM6811M ------------------------------------------------------------------------------------ 42
15.4.2 SIM6812M ------------------------------------------------------------------------------------ 43
15.4.3 SIM6813M ------------------------------------------------------------------------------------ 44
15.4.4 SIM6880M ------------------------------------------------------------------------------------ 45
15.4.5 SIM6822M ------------------------------------------------------------------------------------ 46
15.4.6 SIM6827M ------------------------------------------------------------------------------------ 47
15.5 Short Circuit SOAs (Safe Operating Areas) ------------------------------------------------- 48
16. Pattern Layout Example------------------------------------------------------------------------------- 49
17. Typical Motor Driver Application ------------------------------------------------------------------- 51
Important Notes---------------------------------------------------------------------------------------------- 52
SIM6800M-DSE Rev.1.5
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SIM6800M Series
1. Absolute Maximum Ratings
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, COM1 = COM2 = COM.
Parameter
Symbol
VDC
Conditions
VBB–LSx
Rating
400
Unit
V
Remarks
SIM681xM
SIM682xM
SIM6880M
SIM681xM
SIM682xM
SIM6880M
Main Supply Voltage (DC)
450
450
500
VBB–LSx
Main Power Voltage (Surge)
VDC(SURGE)
VDSS
V
V
VCC = 15 V,
ID = 1 µA, VIN = 0 V
VCC = 15 V,
IC = 1 mA, VIN = 0 V
500
SIM681xM
IGBT / Power MOSFET
Breakdown Voltage
SIM682xM
SIM6880M
VCES
VCC
600
20
VCCx–COM
VB1B–U,
VB2–V,
VB3–W1
Logic Supply Voltage
Output Current (1)
V
A
VBS
20
2
SIM6811M
SIM6812M
SIM6813M
SIM6880M
SIM6822M
SIM6827M
2.5
TC = 25 °C, Tj < 150 °C
IO
3
5
3
SIM6811M
SIM6812M
3.75
TC = 25 °C,
VCC = 15 V,
PW ≤ 1 ms,
single pulse
SIM6813M
SIM6880M
SIM6822M
SIM6827M
Output Current (Pulse)
Input Voltage
IOP
A
V
4.5
7.5
HINx–COM,
LINx–COM
VIN
− 0.5 to 7
FO–COM
OCP–COM
SD–COM
FO Pin Voltage
OCP Pin Voltage
SD Pin Voltage
VFO
VOCP
VSD
−0.5 to 7
−10 to 5
−0.5 to 7
V
V
V
Operating Case
Temperature(2)
Junction Temperature(3)
Storage Temperature
TC(OP)
−30 to 100
°C
Tj
150
°C
°C
Tstg
−40 to 150
Between surface of the
case and each pin; AC,
60 Hz, 1 min
Isolation Voltage(4)
VISO(RMS)
1500
V
(1) Should be derated depending on an actual case temperature. See Section 15.4.
(2) Refers to a case temperature measured during IC operation.
(3) Refers to the junction temperature of each chip built in the IC, including the controller IC (MIC), transistors, and fast
recovery diodes.
(4) Refers to voltage conditions to be applied between the case and all pins. All pins have to be shorted.
SIM6800M-DSE Rev.1.5
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© SANKEN ELECTRIC CO., LTD. 2014
SIM6800M Series
2. Recommended Operating Conditions
Unless specifically noted, COM1 = COM2 = COM.
Parameter
Symbol
VDC
Conditions
VBB–COM
Min.
—
Typ.
300
Max.
400
Unit
V
Remarks
Main Supply Voltage
VCCx–COM
VCC
13.5
15.0
16.5
V
VB1B–U,
VB2–V,
VB3–W1
Logic Supply Voltage
VBS
VIN
13.5
0
—
—
16.5
5.5
V
V
Input Voltage
(HINx, LINx, OCP, SD, FO)
tIN(MIN)ON
tIN(MIN)OFF
tDEAD
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
μs
μs
μs
kΩ
V
Minimum Input Pulse Width
Dead Time of Input Signal
FO Pin Pull-up Resistor
FO Pin Pull-up Voltage
FO Pin Noise Filter Capacitor
Bootstrap Capacitor
1.5
—
RFO
3.3
10
VFO
3.0
5.5
0.01
220
—
CFO
0.001
1
μF
μF
CBOOT
IP ≤ 3 A
390
270
SIM6811M
SIM6812M
IP ≤ 3.75 A
—
SIM6813M
SIM6880M
SIM6822M
SIM6827M
Shunt Resistor
RS
mΩ
IP ≤ 4.5 A
IP ≤ 7.5 A
270
—
—
150
—
—
—
—
RC Filter Resistor
RC Filter Capacitor
RO
CO
100
Ω
SIM6822M
SIM6827M
SIM6880M
SIM6811M
SIM6812M
SIM6813M
1000
1000
—
—
2200
pF
10000
PWM Carrier Frequency
fC
—
—
—
—
20
kHz
°C
Operating Case Temperature
TC(OP)
100
SIM6800M-DSE Rev.1.5
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© SANKEN ELECTRIC CO., LTD. 2014
SIM6800M Series
3. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 15 V, COM1 = COM2 = COM.
3.1 Characteristics of Control Parts
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Remarks
Power Supply Operation
VCCx–COM
VCC(ON)
VBS(ON)
VCC(OFF)
VBS(OFF)
10.5
9.5
11.5
10.5
11.0
10.0
12.5
11.5
12.0
11.0
V
V
V
V
Logic Operation Start
Voltage
VB1B–U,
VB2–V,
VB3–W1
VCCx–COM
10.0
9.0
Logic Operation Stop
Voltage
VB1B–U,
VB2–V,
VB3–W1
VCC1 = VCC2,
VCC pin current in 3-phase
operation
VB1B–U or VB2–V or
VB3–W1; HINx = 5 V;
VBx pin current in 1-phase
operation
ICC
—
—
3.2
4.5
mA
Logic Supply Current
IBS
140
400
μA
Input Signal
High Level Input
Threshold Voltage
(HINx, LINx, SD, FO)
Low Level Input
Threshold Voltage
(HINx, LINx, SD, FO)
High Level Input
Current (HINx, LINx)
Low Level Input Current
(HINx, LINx)
VIH
VIL
—
2.0
1.5
2.5
—
V
V
1.0
VIN = 5 V
VIN = 0 V
IIH
IIL
—
—
230
—
500
2
μA
μA
Fault Signal Output
FO Pin Voltage at Fault
Signal Output
FO Pin Voltage in
Normal Operation
VFO = 5 V, RFO = 10 kΩ
VFO = 5 V, RFO = 10 kΩ
VFOL
VFOH
0
—
—
0.5
—
V
V
4.8
Protection
OCL Pin Output Voltage
(L)
OCL Pin Output Voltage
(H)
Current Limit Reference
Voltage
VOCL(L)
VOCL(H)
VLIM
0
—
—
0.5
5.5
V
V
V
4.5
0.6175 0.6500 0.6825
OCP Threshold Voltage
OCP Hold Time
VTRIP
tP
0.9
20
—
1.0
25
2
1.1
—
—
V
μs
μs
OCP Blanking Time
tBK(OCP)
Current Limit Blanking
Time
tBK(OCL)
—
2
—
μs
SIM6800M-DSE Rev.1.5
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SIM6800M Series
Parameter
Symbol
TDH
Conditions
Min.
135
Typ.
150
Max.
—
Unit
°C
Remarks
TSD Operating
Temperature
TSD Releasing
Temperature
TDL
105
120
—
°C
3.2 Bootstrap Diode Characteristics
Parameter
Symbol
ILBD
Conditions
VR = 500 V
Min.
—
Typ.
—
Max.
10
Unit
Remarks
Bootstrap Diode Leakage
Current
μA
Bootstrap Diode Forward
Voltage
Bootstrap Diode Series
Resistor
IFB = 0.15 A
VFB
—
45
1.0
60
1.3
75
V
RBOOT
Ω
3.3 Thermal Resistance Characteristics
Parameter
Symbol
Rj-C
Conditions
Min.
—
Typ.
—
Max.
3.6
Unit
Remarks
All power MOSFETs
operating
°C/W SIM681xM
Junction-to-Case Thermal
Resistance(1)
SIM682xM
°C/W
(2)
R(j-C)Q
All IGBTs operating
—
—
—
—
—
—
—
—
—
—
3.6
4.2
25
SIM6880M
All freewheeling diodes
operating
All power MOSFETs
operating
SIM682xM
SIM6880M
(3)
R(j-C)F
°C/W
Rj-A
°C/W SIM681xM
Junction-to-Ambient
Thermal Resistance
SIM682xM
°C/W
R(j-A)Q All IGBTs operating
25
SIM6880M
All freewheeling diodes
operating
SIM682xM
SIM6880M
R(j-A)F
29
°C/W
(1) Refers to a case temperature at the measurement point described in Figure 3-1, below.
(2) Refers to steady-state thermal resistance between the junction of the built-in transistors and the case. For transient
thermal characteristics, see Section 15.1.
(3) Refers to steady-state thermal resistance between the junction of the built-in freewheeling diodes and the case.
SIM6800M-DSE Rev.1.5
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SIM6800M Series
Measurement point
21
40
5 mm
1
20
Figure 3-1. Case Temperature Measurement Point
3.4 Transistor Characteristics
Figure 3-2 provides the definitions of switching characteristics described in this and the following sections.
HINx/
LINx
0
trr
toff
ton
td(off) tf
td(on) tr
ID / IC
90%
10%
0
VDS
/
VCE
0
Figure 3-2. Switching Characteristics Definitions
SIM6800M-DSE Rev.1.5
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SIM6800M Series
3.4.1
SIM6811M
Parameter
Symbol
IDSS
Conditions
VDS = 500 V, VIN = 0 V
ID = 1.0 A, VIN = 5 V
Min.
—
Typ.
—
Max.
100
4.0
Unit
µA
Ω
Drain-to-Source Leakage Current
Drain-to-Source On Resistance
RDS(ON)
—
3.2
Source-to-Drain Diode Forward
Voltage
ISD =1.0 A, VIN = 0 V
VSD
—
1.0
1.5
V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
td(on)
tr
td(off)
tf
—
150
—
ns
VDC = 300 V, IC = 1.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-on Delay Time
Rise Time
—
—
—
—
770
70
—
—
—
—
ns
ns
ns
ns
Turn-off Delay Time
Fall Time
690
30
Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
—
150
—
ns
VDC = 300 V, IC = 1.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-on Delay Time
Rise Time
td(on)
tr
td(off)
tf
—
—
—
—
690
90
—
—
—
—
ns
ns
ns
ns
Turn-off Delay Time
Fall Time
650
50
3.4.2
SIM6812M
Parameter
Symbol
ICES
Conditions
VDS = 500 V, VIN = 0 V
ID = 1.25 A, VIN = 5 V
Min.
—
Typ.
—
Max.
100
2.4
Unit
µA
Ω
Drain-to-Source Leakage Current
Drain-to-Source On Resistance
VCE(SAT)
—
2.0
Source-to-Drain Diode Forward
Voltage
ISD =1.25 A, VIN = 0 V
VF
—
1.0
1.5
V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
td(on)
tr
td(off)
tf
—
140
—
ns
V
DC = 300 V, IC = 1.25 A,
Turn-on Delay Time
Rise Time
—
—
—
—
910
100
700
40
—
—
—
—
ns
ns
ns
ns
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
—
155
—
ns
V
DC = 300 V, IC = 1.25 A,
Turn-on Delay Time
Rise Time
td(on)
tr
td(off)
tf
—
—
—
—
875
110
775
35
—
—
—
—
ns
ns
ns
ns
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
SIM6800M-DSE Rev.1.5
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SIM6800M Series
3.4.3
SIM6813M
Parameter
Symbol
IDSS
Conditions
Min.
—
Typ.
—
Max.
100
1.7
Unit
µA
Ω
Drain-to-Source Leakage Current
Drain-to-Source On Resistance
VDS = 500 V, VIN = 0 V
RDS(ON) ID = 1.5 A, VIN = 5 V
—
1.4
Source-to-Drain Diode Forward
Voltage
VSD
ISD =1.5 A, VIN = 0 V
—
1.0
1.5
V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
td(on)
tr
td(off)
tf
—
170
—
ns
VDC = 300 V, IC = 1.5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-on Delay Time
Rise Time
—
—
—
—
820
100
810
50
—
—
—
—
ns
ns
ns
ns
Turn-off Delay Time
Fall Time
Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr
—
180
—
ns
VDC = 300 V, IC = 1.5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-on Delay Time
Rise Time
td(on)
tr
td(off)
tf
—
—
—
—
760
130
750
50
—
—
—
—
ns
ns
ns
ns
Turn-off Delay Time
Fall Time
3.4.4
SIM6880M
Parameter
Symbol
ICES
Conditions
Min.
—
Typ.
—
Max.
1
Unit
mA
Collector-to-Emitter Leakage
Current
VCE = 300 V, VIN = 0 V
Collector-to-Emitter Saturation
Voltage
VCE(SAT) IC = 3.0 A, VIN = 5 V
—
—
1.85
2.0
2.30
2.4
V
V
Diode Forward Voltage
High-side Switching
Diode Reverse Recovery Time
Turn-on Delay Time
Rise Time
VF
IF = 3.0 A, VIN = 0 V
trr
td(on)
tr
—
—
—
—
—
100
880
120
740
210
—
—
—
—
—
ns
ns
ns
ns
ns
VDC = 300 V, IC = 3.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
td(off)
tf
Low-side Switching
Diode Reverse Recovery Time
Turn-on Delay Time
Rise Time
trr
td(on)
tr
—
—
—
—
—
100
820
140
660
200
—
—
—
—
—
ns
ns
ns
ns
ns
VDC = 300 V, IC = 3.0 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
td(off)
tf
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SIM6800M Series
3.4.5
SIM6822M
Parameter
Symbol
ICES
Conditions
Min.
—
Typ.
—
Max.
1
Unit
mA
Collector-to-Emitter Leakage
Current
VCE = 600 V, VIN = 0 V
Collector-to-Emitter Saturation
Voltage
VCE(SAT) IC = 5 A, VIN = 5 V
—
—
1.75
2.0
2.2
2.4
V
V
Diode Forward Voltage
High-side Switching
Diode Reverse Recovery Time
Turn-on Delay Time
Rise Time
VF
IF = 5 A, VIN = 0 V
trr
td(on)
tr
—
—
—
—
—
80
740
70
—
—
—
—
—
ns
ns
ns
ns
ns
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
td(off)
tf
570
100
Low-side Switching
Diode Reverse Recovery Time
Turn-on Delay Time
Rise Time
trr
td(on)
tr
—
—
—
—
—
80
—
—
—
—
—
ns
ns
ns
ns
ns
690
100
540
100
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
td(off)
tf
3.4.6
SIM6827M
Parameter
Symbol
ICES
Conditions
Min.
—
Typ.
—
Max.
1
Unit
mA
Collector-to-Emitter Leakage
Current
VCE = 600 V, VIN = 0 V
Collector-to-Emitter Saturation
Voltage
VCE(SAT) IC = 5 A, VIN = 5 V
—
—
1.75
2.0
2.2
2.4
V
V
Diode Forward Voltage
High-side Switching
Diode Reverse Recovery Time
Turn-on Delay Time
Rise Time
VF
IF = 5 A, VIN = 0 V
trr
td(on)
tr
—
—
—
—
—
100
1030
180
—
—
—
—
—
ns
ns
ns
ns
ns
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
td(off)
tf
590
150
Low-side Switching
Diode Reverse Recovery Time
Turn-on Delay Time
Rise Time
trr
td(on)
tr
—
—
—
—
—
100
1030
240
—
—
—
—
—
ns
ns
ns
ns
ns
VDC = 300 V, IC = 5 A,
inductive load,
VIN = 0→5 V or 5→0 V,
Tj = 25 °C
Turn-off Delay Time
Fall Time
td(off)
tf
540
150
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SIM6800M Series
4. Mechanical Characteristics
Parameter
Heatsink Mounting
Screw Torque
Conditions
Min.
Typ.
—
Max.
0.441
Unit
Remarks
*
0.294
N∙m
Flatness of Heatsink
Attachment Area
See Figure 4-1.
0
—
60
—
μm
Package Weight
—
5.2
g
* When mounting a heatsink, it is recommended to use a metric screw of M2.5 and a plain washer of 6.0 mm (φ)
together at each end of it. For more details about screw tightening, see Section 13.2.
Heatsink
Measurement position
-
+
-
+
Heasink
Figure 4-1. Flatness Measurement Position
5. Insulation Distance
Parameter
Clearance
Conditions
Min.
1.5
Typ.
—
Max.
Unit
mm
mm
Remarks
2.1
—
Between heatsink* and
leads. See Figure 5-1.
Creepage
1.7
—
* Refers to when a heatsink to be mounted is flat. If your application requires a clearance exceeding the maximum
distance given above, use an alternative (e.g., a convex heatsink) that will meet the target requirement.
Creepage
Clearance
Heatsink
Figure 5-1. Insulation Distance Definitions
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6. Truth Table
Table 6-1 is a truth table that provides the logic level definitions of operation modes.
In the case where HINx and LINx signals in each phase are high at the same time, both the high- and low-side
transistors become on (simultaneous on-state). Therefore, HINx and LINx signals, the input signals for the HINx and
LINx pins, require dead time setting so that such a simultaneous on-state event can be avoided.
After the IC recovers from a UVLO_VCC condition, the low-side transistors resume switching in accordance with
the input logic levels of the LINx signals (level-triggered), whereas the high-side transistors resume switching at the
next rising edge of an HINx signal (edge-triggered).
After the IC recovers from a UVLO_VB condition, the high-side transistors resume switching at the next rising edge
of an HINx signal (edge-triggered).
Table 6-1. Truth Table for Operation Modes
Mode
HINx
L
LINx
L
High-side Transistor
OFF
ON
Low-side Transistor
OFF
OFF
ON
H
L
L
Normal Operation
H
H
L
OFF
ON
H
L
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
H
L
L
External Shutdown Signal Input
FO = Low Level
H
H
L
OFF
ON
H
L
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
Undervoltage Lockout for
High-side Power Supply
(UVLO_VB)
H
L
L
H
H
L
H
L
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
Undervoltage Lockout for
Low-side Power Supply
(UVLO_VCC)
H
L
L
H
H
L
H
L
H
L
L
Overcurrent Protection (OCP)
H
H
L
OFF
ON
H
L
OFF
OFF
OFF
OFF
OFF
ON
H
L
L
Overcurrent Limit (OCL)
(OCL = SD)
H
H
L
H
L
ON
OFF
OFF
OFF
OFF
H
L
L
Thermal Shutdown (TSD)
H
H
OFF
ON
H
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7. Block Diagrams
VB1B
30
21
20
23
VB1A
VB2
VB3
17
VCC1
UVLO
UVLO
UVLO
UVLO
28
VBB
15
14
13
12
16
HIN3
HIN2
HIN1
SD
Input
Logic
High Side
Level Shift Driver
24
19
26
31
35
37
W1
V
COM1
V1
U
10
9
OCL
LIN3
LIN2
LIN1
V2
W2
Input Logic
(OCP reset)
8
Low
Side
7
Driver
11
33
2
LS1
6
COM2
LS2
5
4
VCC2
FO
UVLO
LS2
Thermal
Shutdown
40
1
LS3B
LS3A
OCP and OCL
3
OCP
Figure 7-1. SIM681xM
VB1B
30
21
20
23
VB1A
VB2
VB3
17
VCC1
UVLO
UVLO
UVLO
UVLO
28
VBB
15
14
13
12
16
HIN3
HIN2
HIN1
SD
Input
Logic
High Side
Level Shift Driver
24
19
26
31
35
37
W1
V
COM1
V1
U
10
9
OCL
LIN3
LIN2
LIN1
V2
W2
Input Logic
(OCP reset)
8
Low
Side
7
Driver
11
33
2
LS1
6
COM2
LS2
5
4
VCC2
FO
UVLO
LS2
Thermal
Shutdown
40
1
LS3B
LS3A
OCP and OCL
3
OCP
Figure 7-2. SIM682xM or SIM688xM
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SIM6800M Series
8. Pin Configuration Definitions
Top view
40
21
20
40
1
1
21
20
Pin Number
Pin Name
LS3A
LS2
Description
1
2
3
W-phase IGBT emitter, or power MOSFET source
V-phase IGBT emitter, or power MOSFET source
Overcurrent protection signal input
OCP
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
FO
Fault signal output and shutdown signal input
Low-side logic supply voltage input
Low-side logic ground
Logic input for U-phase low-side gate driver
Logic input for V-phase low-side gate driver
Logic input for W-phase low-side gate driver
Overcurrent limit signal input
U-phase IGBT emitter, or power MOSFET source
High-side shutdown signal input
Logic input for U-phase high-side gate driver
Logic input for V-phase high-side gate driver
Logic input for W-phase high-side gate driver
High-side logic ground
VCC2
COM2
LIN1
LIN2
LIN3
OCL
LS1
SD
HIN1
HIN2
HIN3
COM1
VCC1
—
High-side logic supply voltage input
(Pin removed)
V-phase high-side floating supply voltage input, bootstrap capacitor connection
for V-phase
19
V
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VB2
VB1A
—
VB3
W1
NC
V1
V-phase high-side floating supply voltage input
U-phase high-side floating supply voltage input
(Pin removed)
W-phase high-side floating supply voltage input
W-phase output (connected to W2 externally)
(No connection)
V-phase output (connected to V2 externally)
(Pin removed)
Positive DC bus supply voltage
(No connection)
U-phase high-side floating supply voltage input
U-phase output
—
VBB
NC
VB1B
U
—
LS2
—
(Pin removed)
(Pin trimmed) V-phase IGBT emitter, or power MOSFET source
(Pin removed)
V-phase output (connected to V1 externally)
(No connection)
W-phase output (connected to W1 externally)
(Pin removed)
(Pin removed)
V2
NC
W2
—
—
LS3B
W-phase IGBT emitter, or power MOSFET source
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SIM6800M Series
9. Typical Applications
CR filters and Zener diodes should be added to your application as needed. This is to protect each pin against surge
voltages causing malfunctions, and to avoid the IC being used under the conditions exceeding the absolute maximum
ratings where critical damage is inevitable. Then, check all the pins thoroughly under actual operating conditions to
ensure that your application works flawlessly.
VB2
20
CBOOT2
V
19
VB1A
VB3
21
23
VCC
VCC1
17
CBOOT3
COM1
HIN3
HIN2
HIN1
SD
W1
V1
GND
16
15
14
13
12
11
10
9
24
26
HIN3
HIN2
HIN1
VDC
VBB
VB1B
U
28
LS1
30
31
OCL
LIN3
LIN2
LIN1
COM2
VCC2
FO
MIC
LIN3
LIN2
LIN1
M
8
CBOOT1
LS2
V2
7
33
35
37
5 V
RFO
6
5
W2
4
CS CDC
OCP
LS2
Fault
3
CFO
2
LS3A
LS3B
RO
CO
1
40
RS
Figure 9-1. SIM681xM Typical Application Using a Single Shunt Resistor
VB2
20
CBOOT2
V
19
VB1A
VB3
21
23
VCC
VCC1
17
CBOOT3
COM1
HIN3
HIN2
HIN1
SD
W1
V1
GND
16
15
14
13
12
11
10
9
24
26
HIN3
HIN2
HIN1
VDC
VBB
VB1B
U
28
LS1
30
31
OCL
LIN3
LIN2
LIN1
COM2
VCC2
FO
MIC
LIN3
LIN2
LIN1
M
8
CBOOT1
LS2
V2
7
33
35
37
5 V
RFO
6
5
W2
4
CS CDC
OCP
LS2
Fault
3
RO1
RO2
RO3
2
CO1
CO2
CO3
CFO
LS3A
LS3B
1
40
RS1 RS2 RS3
Figure 9-2. SIM681xM Typical Application Using Three Shunt Resistors
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SIM6800M Series
10. Physical Dimensions
● DIP40 Package
+0.4
-0.3
7.6
1.8±0.3
2-R1.5
21
40
Top view
Pin 1 indicator
1
20
Gate burr
1.8±0.1
36±0.3
+0.1
0.52
-0.05
1.778 ±0.25
33.782±0.3
(Ends of pins)
1
.
NOTES:
- Dimensions in millimeters
7
m
i
n
.
- Bare lead frame: Pb-free (RoHS compliant)
- The leads illustrated above are for reference only, and may not be actual states of
being bent.
- Maximum gate burr height is 0.3 mm.
● Reference Through Hole Size and Layout
40
21
φ1.1 typ.
33.7
0.04
Center of screw hole
1
20
Pin pich: 1.778
33.782
Unit: mm
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SIM6800M Series
11. Marking Diagram
40
21
S I M 6 8 x x M
Y M D D X
Part Number
1
20
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
DD is the day of the month (01 to 31)
X is the control number
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12. Functional Descriptions
12.2.2 VB1A, VB1B, VB2, and VB3
Unless specifically noted, this section uses the
following definitions:
These pins are connected to bootstrap capacitors for
the high-side floating supply.
In actual applications, use either of the VB1A or
VB1B pin because they are internally connected.
Voltages across the VBx and these output pins should be
maintained within the recommended range (i.e., the
Logic Supply Voltage, VBS) given in Section 2.
A bootstrap capacitor, CBOOTx, should be connected in
each of the traces between the VB1A (VB1B) and U
pins, the VB2 and V pins, the VB3 and W1 (W2) pins.
For proper startup, turn on the low-side transistor first,
then charge the bootstrap capacitor, CBOOTx, up to its
maximum capacity.
● All the characteristic values given in this section are
typical values.
● All the circuit diagrams listed in this section represent
the type of IC that incorporates power MOSFETs. All
the functional descriptions in this section are also
applicable to the type of IC that incorporates IGBTs.
● For pin and peripheral component descriptions, this
section employs a notation system that denotes a pin
name with the arbitrary letter “x”, depending on
context. Thus, “the VCCx pin” is used when referring
to either or both of the VCC1 and VCC2 pins.
For the capacitance of the bootstrap capacitors,
CBOOTx, choose the values that satisfy Equations (1) and
(2). Note that capacitance tolerance and DC bias
characteristics must be taken into account when you
● The COM1 pin is always connected to the COM2 pin.
12.1 Turning On and Off the IC
choose appropriate values for CBOOTx
.
The procedures listed below provide recommended
startup and shutdown sequences. To turn on the IC
properly, do not apply any voltage on the VBB, HINx,
and LINx pins until the VCCx pin voltage has reached a
stable state (VCC(ON) ≥ 12.5 V).
(
)
CBOOTx µF > 800 × tL(OFF)
(1)
(2)
1 µF ≤ CBOOTx ≤ 220 µF
It is required to charge bootstrap capacitors, CBOOTx
up to full capacity at startup (see Section 12.2.2).
To turn off the IC, set the HINx and LINx pins to
logic low (or “L”), and then decrease the VCCx pin
voltage.
,
In Equation (1), let tL(OFF) be the maximum off-time of
the low-side transistor (i.e., the non-charging time of
CBOOTx), measured in seconds.
Even while the high-side transistor is not on, voltage
across the bootstrap capacitor keeps decreasing due to
power dissipation in the IC. When the VBx pin voltage
decreases to VBS(OFF) or less, the high-side undervoltage
lockout (UVLO_VB) starts operating (see Section
12.3.3.1). Therefore, actual board checking should be
done thoroughly to validate that voltage across the VBx
pin maintains over 11.0 V (VBS > VBS(OFF)) during a low-
frequency operation such as a startup period.
As Figure 12-1 shows, a bootstrap diode, DBOOTx, and
a current-limiting resistor, RBOOTx, are internally placed
in series between the VCC1 and VBx pins.
Time constant for the charging time of CBOOTx, τ, can
be computed by Equation (3):
12.2 Pin Descriptions
12.2.1 U, V, V1, V2, W1, and W2
These pins are the outputs of the three phases, and
serve as the connection terminals to the 3-phase motor.
The V1 and W1 pins must be connected to the V2 and
W2 pins on a PCB, respectively.
The U, V (V1) and W1 pins are the grounds for the
VB1A (VB1B), VB2, and VB3 pins.
The U, V and W1 pins are connected to the negative
nodes of bootstrap capacitors, CBOOTx. The V pin is
internally connected to the V1 pin.
,
(3)
τ = CBOOTx × RBOOTx
Since high voltages are applied to these output pins
(U, V, V1, V2, W1, and W2), it is required to take
measures for insulating as follows:
where CBOOTx is the optimized capacitance of the
bootstrap capacitor, and RBOOTx is the resistance of the
current-limiting resistor (60 Ω ± 25%).
● Keep enough distance between the output pins and
low-voltage traces.
● Coat the output pins with insulating resin.
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DBOOT1 RBOOT1
DBOOT2 RBOOT2
VB1B
30
HINx
CBOOT1
0
VB2
VB3
VBB
20
23
28
Set
CBOOT2
DBOOT3 RBOOT3
0
Reset
0
17
VCC1
CBOOT3
VDC
HO3
5
HO2
VCC2
HO1
VCC
VBx–HSx
VBS(OFF)
31
19
26
VBS(ON)
U
V
MIC
0
M
16
6
Stays logic high
V1
COM1
Q
COM2
37
24
W2
0
W1
Figure 12-3. Waveforms at VBx–HSx Voltage Drop
Figure 12-1. Bootstrap Circuit
Figure 12-2 shows an internal level-shifting circuit. A
high-side output signal, HOx, is generated according to
an input signal on the HINx pin. When an input signal
on the HINx pin transits from low to high (rising edge),
a “Set” signal is generated. When the HINx input signal
transits from high to low (falling edge), a “Reset” signal
is generated. These two signals are then transmitted to
the high-side by the level-shifting circuit and are input to
the SR flip-flop circuit. Finally, the SR flip-flop circuit
feeds an output signal, Q (i.e., HOx).
Figure 12-3 is a timing diagram describing how noise
or other detrimental effects will improperly influence the
level-shifting process. When a noise-induced rapid
voltage drop between the VBx and output pins (U, V or
W1; hereafter “VBx–HSx”) occurs after the Set signal
generation, the next Reset signal cannot be sent to the
SR flip-flop circuit. And the state of an HOx signal stays
logic high (or “H”) because the SR flip-flop does not
respond. With the HOx state being held high (i.e., the
high-side transistor is in an on-state), the next LINx
signal turns on the low-side transistor and causes a
simultaneously-on condition, which may result in
critical damage to the IC. To protect the VBx pin against
such a noise effect, add a bootstrap capacitor, CBOOTx, in
each phase. CBOOTx must be placed near the IC, and be
connected between the VBx and HSx pins with a
minimal length of traces. To use an electrolytic capacitor,
add a 0.01 μF to 0.1 μF bypass capacitor, CPx, in parallel
near these pins used for the same phase.
12.2.3 VCC1 and VCC2
These are the power supply pins for the built-in
control IC. The VCC1 and VCC2 pins must be
externally connected on a PCB because they are not
internally connected. To prevent malfunction induced by
supply ripples or other factors, put a 0.01 μF to 0.1 μF
ceramic capacitor, CVCC, near these pins. To prevent
damage caused by surge voltages, put an 18 V to 20 V
Zener diode, DZ, between the VCCx and COMx pins.
Voltages to be applied between the VCCx and COMx
pins should be regulated within the recommended
operational range of VCC, given in Section 2.
17
VCC1
5
MIC
VCC2
VCC
CVCC
DZ
16
COM1
COM2
6
Figure 12-4. VCCx Pin Peripheral Circuit
U1
12.2.4 COM1 and COM2
VBx
These are the logic ground pins for the built-in control
IC. The COM1 and COM2 pins should be connected
externally on a PCB because they are not internally
connected. Varying electric potential of the logic ground
can be a cause of improper operations. Therefore,
connect the logic ground as close and short as possible
to shunt resistors, RSx, at a single-point ground (or star
ground) which is separated from the power ground (see
Figure 12-5).
HOx
S
Q
R
Set
Input
logic
Pulse
generator
HSx
HINx
Reset
COM1
16
Figure 12-2. Internal Level-shifting Circuit
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SIM6800M Series
slightly lower than the output voltage of the
microcontroller.
U1
VDC
28
VBB
CS
Table 12-1. Input Signals for HINx and LINx Pins
CDC
Parameter High Level Signal
Low Level Signal
0 V < VIN < 0.5 V
RS1
Input
COM1
COM2
16
6
11
2
LS1
LS2
3 V < VIN < 5.5 V
RS2
RS3
Voltage
Input
1
LS3A
Pulse
Width
≥0.5 μs
≥0.5 μs
PWM
Create a single-point
ground (a star ground)
near RSx, but keep it
separated from the
power ground.
OCP
Carrier
Frequency
Dead
≤20 kHz
≥1.5 μs
Connect COM1 and
COM2 on a PCB.
Time
Figure 12-5. Connections to Logic Ground
U1
5 V
2 kΩ
2 kΩ
HINx
12.2.5 HIN1, HIN2, and HIN3;
LIN1, LIN2, and LIN3
(LINx)
20 kΩ
These are the input pins of the internal motor drivers
for each phase. The HINx pin acts as a high-side
controller; the LINx pin acts as a low-side controller.
Figure 12-6 shows an internal circuit diagram of the
HINx or LINx pin. This is a CMOS Schmitt trigger
circuit with a built-in 20 kΩ pull-down resistor, and its
input logic is active high.
COM1
(COM2)
Figure 12-6. Internal Circuit Diagram of HINx or
LINx Pin
Input signals across the HINx–COMx and the LINx–
COMx pins in each phase should be set within the
ranges provided in Table 12-1, below. Note that dead
time setting must be done for HINx and LINx signals
because the IC does not have a dead time generator.
The higher PWM carrier frequency rises, the more
switching loss increases. Hence, the PWM carrier
frequency must be set so that operational case
temperatures and junction temperatures have sufficient
margins against the absolute maximum ranges, specified
in Section 1.
U1
RIN1x
Input
signal
HINx/
LINx
RIN2x
CINx
SIM68xxM
Controller
Figure 12-7. Filter Circuit for HINx or LINx Pin
If the signals from the microcontroller become
unstable, the IC may result in malfunctions. To avoid
this event, the outputs from the microcontroller output
line should not be high impedance.
Also, if the traces from the microcontroller to the
HINx or LINx pin (or both) are too long, the traces may
be interfered by noise. Therefore, it is recommended to
add an additional filter or a pull-down resistor near the
HINx or LINx pin as needed (see Figure 12-7).
Here are filter circuit constants for reference:
- RIN1x: 33 Ω to 100 Ω
12.2.6 VBB
This is the input pin for the main supply voltage, i.e.,
the positive DC bus. All of the IGBT collectors (power
MOSFET drains) of the high-side are connected to this
pin. Voltages between the VBB and COMx pins should
be set within the recommended range of the main supply
voltage, VDC, given in Section 2.
To suppress surge voltages, put a 0.01 μF to 0.1 μF
bypass capacitor, CS, near the VBB pin and an
electrolytic capacitor, CDC, with a minimal length of
PCB traces to the VBB pin.
- RINx: 1 kΩ to 10 kΩ
- CINx: 100 pF to 1000 pF
Care should be taken when adding RIN1x and RIN2x to
the traces. When they are connected each other, the
input voltage of the HINx and LINx pins becomes
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SIM6800M Series
● Overcurrent Pprotection (OCP)
12.2.7 LS1, LS2, LS3A, and LS3B
This function detects inrush currents larger than those
detected by the OCL. When the OCP pin voltage
exceeds the OCP Threshold Voltage, VTRIP, the IC
operates as follows: the OCL pin = logic high, the low-
side transistors = off, the FO pin = logic low.
In addition, if the OCL pin is connected to the SD pin,
the high-side transistors can be turned off. For a more
detailed OCP description, see Section 12.3.5.
These are the emitter (source) pins of the low-side
IGBTs (power MOSFETs). For current detection, the
LS1, LS2, and LS3 (LS3B) pins should be connected
externally on a PCB via shunt resistors, RSx, to the
COMx pin. In actual applications, use either of the
LS3A or LS3B pin because they are internally connected.
When connecting a shunt resistor, place it as near as
possible to the IC with a minimum length of traces to the
LSx and COMx pins. Otherwise, malfunction may occur
because a longer circuit trace increases its inductance
and thus increases its susceptibility to improper
operations. In applications where long PCB traces are
required, add a fast recovery diode, DRSx, between the
LSx and COMx pins in order to prevent the IC from
malfunctioning.
12.2.9 SD
When a 5 V or 3.3 V signal is input to the SD pin, the
high-side transistors turn off independently of any HINx
signals. This is because the SD pin does not respond to a
pulse shorter than an internal filter of 3.3 μs (typ.).
The SD-OCL pin connection, as described in Section
12.2.8, allows the IC to turn off the high-side transistors
at OCL or OCP activation. Also, connecting the FO and
SD pins permits all the high- and low-side transistors to
turn off owing to an inverted signal from the FO pin,
even if the IC falls into an abnormal condition in which
some or all of the protections (TSD, OCP, UVLO) are
activated.
U1
28
VBB
VDC
CS
DRS1
RS1
RS2
CDC
11
2
LS1
LS2
DRS2
COM1
COM2
16
6
DRS3
RS3
1
LS3A
12.2.10 FO
This pin operates as the fault signal output and the
low-side shutdown signal input. Sections 12.3.1 and
12.3.2 explain the two functions in detail, respectively.
Figure 12-9 illustrates a schematic diagram of the FO
pin and its peripheral circuit.
Put a shunt resistor near
the IC with a minimum
length to the LSx pin.
Add a fast recovery
diode to a long trace.
Figure 12-8. Connections to LSx Pin
VFO
5 V
U1
FO
RFO
1 MΩ
3.0 µs (typ.)
2 kΩ
12.2.8 OCP and OCL
Blanking
filter
INT
The OCP pin serves as the input for the overcurrent
protections which monitor the currents going through
the output transistors.
50 Ω
QFO
Output SW turn-off
and QFO turn-on
CFO
In normal operation, the OCL pin logic level is low.
In case one or more of the protections listed below are
activated by an OCP input signal, the OCL pin logic
level becomes high. If the OCL pin is connected to the
SD pin so that the SD pin will respond to the OCL input
signal, the high-side transistors can be turned off when
the protections (OCP and OCL) are activated.
COM
Figure 12-9. Internal Circuit Diagram of FO Pin and
Its Peripheral Circuit
Because of its open-collector nature, the FO pin
should be tied by a pull-up resistor, RFO, to the external
power supply. The external power supply voltage (i.e.,
the FO Pin Pull-up Voltage, VFO) should range from 3.0
V to 5.5 V. When the pull-up resistor, RFO, has a too
small resistance, the FO pin voltage at fault signal output
becomes high due to the saturation voltage drop of a
built-in transistor, QFO. Therefore, it is recommended to
use a 3.3 kΩ to 10 kΩ pull-up resistor. To suppress noise,
add a filter capacitor, CFO, near the IC with minimizing a
● Overcurrent Limit (OCL)
When the OCP pin voltage exceeds the Current Limit
Reference Voltage, VLIM, the OCL pin logic level
becomes high. While the OCL is in working, the output
transistors operate according to an input signal (HINx or
LINx). If the OCL pin is connected to the SD pin, the
high-side transistors can be turned off. For a more
detailed OCL description, see Section 12.3.4.
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SIM6800M Series
trace length between the FO and COMx pins.
Table 12-2. Shutdown Signals
High Level Signal Low Level Signal
To avoid the repetition of OCP activations, the
external microcontroller must shut off any input signals
to the IC within an OCP hold time, tP, which occurs after
the internal transistor (QFO) turn-on. tP is 15 μs where
minimum values of thermal characteristics are taken into
account. (For more details, see Section 12.3.5.) Our
recommendation is to use a 0.001 μF to 0.01 μF filter
capacitor.
Parameter
Input Voltage 3 V < VIN < 5.5 V
0 V < VIN < 0.5 V
Input Pulse
—
≥6 μs
Width
12.3.3 Undervoltage Lockout for
Power Supply (UVLO)
12.3 Protection Functions
In case the gate-driving voltages of the output
transistors decrease, their steady-state power dissipations
increase. This overheating condition may cause
permanent damage to the IC in the worst case. To
prevent this event, the SIM6800M series has the
undervoltage lockout (UVLO) circuits for both of the
high- and low-side power supplies in the monolithic IC
(MIC).
This section describes the various protection circuits
provided in the SIM6800M series. The protection
circuits include the undervoltage lockout for power
supplies (UVLO), the overcurrent protection (OCP), and
the thermal shutdown (TSD). In case one or more of
these protection circuits are activated, the FO pin
outputs a fault signal; as a result, the external
microcontroller can stop the operations of the three
phases by receiving the fault signal. The external
microcontroller can also shut down the IC operations by
inputting a fault signal to the FO pin.
12.3.3.1. Undervoltage Lockout for
High-side Power Supply
(UVLO_VB)
In the following functional descriptions, “HOx”
denotes a gate input signal on the high-side transistor,
whereas “LOx” denotes a gate input signal on the low-
side transistor..
Figure 12-10 shows operational waveforms of the
undervoltage lockout operation for high-side power
supply (i.e., UVLO_VB).
12.3.1 Fault Signal Output
HINx
In case one or more of the following protections are
actuated, an internal transistor, QFO, turns on, then the
FO pin becomes logic low (≤0.5 V).
0
LINx
0
1) Low-side undervoltage lockout (UVLO_VCC)
2) Overcurrent protection (OCP)
UVLO_VB
operation
VBx-HSx
VBS(ON)
3) Thermal shutdown (TSD)
VBS(OFF)
UVLO release
While the FO pin is in the low state, all the low-side
transistors turn off. In normal operation, the FO pin
outputs a high signal of 5 V.. The fault signal output
time of the FO pin at OCP activation is the OCP hold
time (tP) of 25 μs (typ.), fixed by a built-in feature of the
IC itself (see Section 12.3.5). The external
microcontroller receives the fault signals with its
interrupt pin (INT), and must be programmed to put the
HINx and LINx pins to logic low within the
predetermined OCP hold time, tP.
0
HOx restarts at
positive edge after
About 3 µs
UVLO_VB release.
HOx
0
LOx
0
No FO output at
FO
UVLO_VB.
0
12.3.2 Shutdown Signal Input
Figure 12-10. UVLO_VB Operational Waveforms
The FO pin also acts as the input pin of shutdown
signals. When the FO pin becomes logic low, all the
low-side transistors turn off.
The voltages and pulse widths of the shutdown signals
to be applied between the FO and COMx pins are listed
in Table 12-2.
When the voltage between the VBx and output pins
(VBx–HSx shown in Figure 12-10) decreases to the
Logic Operation Stop Voltage (VBS(OFF), 10.0 V) or less,
the UVLO_VB circuit in the corresponding phase gets
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SIM6800M Series
activated and sets an HOx signal to logic low. When the
voltage between the VBx and HSx pins increases to the
Logic Operation Start Voltage (VBS(ON), 10.5 V) or more,
the IC releases the UVLO_VB condition. Then, the HOx
signal becomes logic high at the rising edge of the first
input command after the UVLO_VB release. The FO
pin does not transmit any fault signals during the
UVLO_VB operation. In addition, the VBx pin has an
internal UVLO_VB filter of about 3 μs, in order to
prevent noise-induced malfunctions.
12.3.4 Overcurrent Limit (OCL)
The overcurrent limit (OCL) is a protection against
relatively low overcurrent conditions. Figure 12-12
shows an internal circuit of the OCP and OCL pins;
Figure 12-13 shows OCL operational waveforms.
When the OCP pin voltage increases to the Current
Limit Reference Voltage (VLIM, 0.6500 V) or more, and
remains in this condition for a period of the Current
Limit Blanking Time (tBK(OCP), 2 μs) or longer, the OCL
circuit is activated. Then, the OCL pin goes logic high.
During the OCL operation, the gate logic levels of the
low-side transistors respond to an input command on the
LINx pin. If the OCL and SD pins are connected on a
PCB, the high-side transistors can be turned off even
during the OCL operation. The SD pin has an internal
filter of about 3.3 μs (typ.).
When the OCP pin voltage falls below VLIM (0.6500
V), the OCL pin logic level becomes low. After the OCL
pin logic has become low, the high-side transistors
remain turned off until the first low-to-high transition on
an HINx input signal occurs (i.e., rising edge triggering).
12.3.3.2. Undervoltage Lockout for
Low-side Power Supply
(UVLO_VCC)
Figure 12-11 shows operational waveforms of the
undervoltage lockout operation for low-side power
supply (i.e., UVLO_VCC).
When the VCC2 pin voltage decreases to the Logic
Operation Stop Voltage (VCC(OFF), 11.0 V) or less, the
UVLO_VCC circuit in the corresponding phase gets
activated and sets both of HOx and LOx signals to logic
low. When the VCC2 pin voltage increases to the Logic
Operation Start Voltage (VCC(ON), 11.5 V) or more, the
IC releases the UVLO_VCC condition. Then, the IC
resumes the following transmissions: an LOx signal
according to an LINx pin input command; an HOx
signal according to the rising edge of the first HINx pin
input command after the UVLO_VCC release. During
the UVLO_VCC operation, the FO pin becomes logic
low and sends fault signals. In addition, the VCC2 pin
has an internal UVLO_VCC filter of about 3 μs, in order
to prevent noise-induced malfunctions.
U1
2 kΩ
10
0.65 V
Filter
OCL
2 kΩ
3
6
OCP
200 kΩ
200 kΩ
COM2
Figure 12-12. Internal Circuit of OCP and OCL Pins
HINx
HINx
0
0
LINx
LINx
0
0
OCP
UVLO_VCC
operation
VLIM
VCC2
VCC(ON)
VCC(OFF)
0
0
tBK(OCP)
OCL
(SD)
HOx
0
HOx restarts at
positive edge after
OCL release.
0
3.3 µs (typ.)
HOx
LOx responds to input signal.
About 3 µs
LOx
0
0
LOx
FO
0
0
Figure 12-13. OCL Operational Waveforms
(OCL = SD)
Figure 12-11. UVLO_VCC Operational Waveforms
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are shorted to ground (ground fault). In case any of these
pins falls into a state of ground fault, the output
transistors may be destroyed.
12.3.5 Overcurrent Protection (OCP)
The overcurrent protection (OCP) is a protection
against large inrush currents (i.e., high di/dt). Figure
12-14 is an internal circuit diagram describing the OCP
pin and its peripheral circuit.
The OCP pin detects overcurrents with the input
voltages across external shunt resistors, RSx. Because the
OCP pin is internally pulled down, the OCP pin voltage
increases proportionally to a rise in the currents running
through the shunt resistors, RSx.
Figure 12-15 is a timing chart that represents
operation waveforms during OCP operation. When the
OCP pin voltage increases to the OCP Threshold
Voltage (VTRIP, 1.0 V) or more, and remains in this
condition for a period of the OCP Blanking Time (tBK, 2
μs) or longer, the OCP circuit is activated. The enabled
OCP circuit shuts off the low-side transistors and puts
the FO pin into a low state. Then, output current
decreases as a result of the output transistors turn-off.
Even if the OCP pin voltage falls below VTRIP, the IC
holds the FO pin in the low state for a fixed OCP hold
time (tP) of 25 μs (typ.). Then, the output transistors
operate according to input signals.
U1
VTRIP
2 kΩ
VBB
28
-
+
OCP
3
Blanking
filter
200 kΩ
1.65 µs (typ.)
CO
Output SW turn-off
and QFO turn-on
COM2
6
LSx
RSx
A/D
ROx
DRSx
COM
Figure 12-14. Internal Circuit Diagram of OCP Pin
and Its Peripheral Circuit
HINx
The OCP is used for detecting abnormal conditions,
such as an output transistor shorted. In case short-circuit
conditions occur repeatedly, the output transistors can be
destroyed. To prevent such event, motor operation must
be controlled by the external microcontroller so that it
can immediately stop the motor when fault signals are
detected.
0
LINx
0
tBK
tBK
tBK
OCP
VTRIP
VLIM
For proper shunt resistor setting, your application
must meet the following:
0
● Use the shunt resistor that has a recommended
resistance, RSx (see Section 2).
HOx responds to input signal.
HOx
● Set the OCP pin input voltage to vary within the rated
OCP pin voltages, VOCP (see Section 1).
● Keep the current through the output transistors below
the rated output current (pulse), IOP (see Section 1).
0
LOx
0
FO restarts
automatically after tP.
FO
It is required to use a resistor with low internal
inductance because high-frequency switching current
will flow through the shunt resistors, RSx. In addition,
choose a resistor with allowable power dissipation
according to your application.
tP
0
Figure 12-15. OCP Operational Waveforms
When you connect a CR filter (i.e., a pair of a filter
resistor, RO, and a filter capacitor, CO) to the OCP pin,
care should be taken in setting the time constants of RO
and CO. The larger the time constant, the longer the time
that the OCP pin voltage rises to VTRIP. And this may
cause permanent damage to the transistors.
Consequently, a propagation delay of the IC must be
taken into account when you determine the time
constants. For RO and CO, their time constants must be
set to the values listed in Table 12-3. And place CO as
close as possible to the IC with minimizing a trace
length between the OCP and COMx pins.
Table 12-3. Reference Time Constants for CR Filter
Time Constant
Part Number
(µs)
SIM681x
≤2
SIM682x
SIM688x
≤0.2
Note that overcurrents are undetectable when one or
more of the U, V/V1/V2, and W1/W2 pins or their traces
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12.3.6 Thermal Shutdown (TSD)
13. Design Notes
The SIM6800M series incorporates
a thermal
shutdown (TSD) circuit. Figure 12-16 shows TSD
operational waveforms. In case of overheating (e.g.,
increased power dissipation due to overload, a rise in
ambient temperature at the device, etc.), the IC shuts
down the low-side output transistors.
The TSD circuit in the monolithic IC (MIC) monitors
temperatures (see Section 7). When the temperature of
the monolithic IC (MIC) exceeds the TSD Operating
Temperature (TDH, 150 °C), the TSD circuit is activated.
When the temperature of the monolithic IC (MIC)
13.1 PCB Pattern Layout
Figure 13-1 shows a schematic diagram of a motor
driver circuit. The motor driver circuit consists of
current paths having high frequencies and high voltages,
which also bring about negative influences on IC
operation, noise interference, and power dissipation.
Therefore, PCB trace layouts and component placements
play an important role in circuit designing.
Current loops, which have high frequencies and high
voltages, should be as small and wide as possible, in
order to maintain a low-impedance state. In addition,
ground traces should be as wide and short as possible so
that radiated EMI levels can be reduced.
decreases to the TSD Releasing Temperature (TDL
,
120 °C) or less, the shutdown condition is released. The
output transistors then resume operating according to
input signals.
During the TSD operation, the FO pin becomes logic
low and transmits fault signals.
Note that junction temperatures of the output
transistors themselves are not monitored; therefore, do
not use the TSD function as an overtemperature
prevention for the output transistors.
VDC
VBB
28
HINx
U
31
0
Ground traces
should be wide
and short.
LINx
MIC
V1
V2
26
35
0
M
W1
W2
TSD operation
24
37
TDH
Tj(MIC)
TDL
0
LS1
HOx
11
LS2
2
1
0
LS3A
LOx responds to input signals.
LOx
High-frequency, high-voltage
current loops should be as
small and wide as possible.
0
FO
Figure 13-1. High-frequency, High-voltage Current
Paths
0
Figure 12-16. TSD Operational Waveforms
13.2 Considerations in Heatsink Mounting
The following are the key considerations and the
guidelines for mounting a heatsink:
● It is recommended to use a pair of a metric screw of
M2.5 and a plain washer of 6.0 mm (φ). To tighten
the screws, use a torque screwdriver. Tighten the two
screws firstly up to about 30% of the maximum screw
torque, then finally up to 100% of the prescribed
maximum screw torque. Perform appropriate
tightening within the range of screw torque defined in
Section 4.
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SIM6800M Series
● When mounting a heatsink, it is recommended to use
silicone greases. If a thermally conductive sheet or an
electrically insulating sheet is used, package cracks
may be occurred due to creases at screw tightening.
Therefore, you should conduct thorough evaluations
before using these materials.
● When applying a silicone grease, make sure that there
must be no foreign substances between the IC and a
heatsink. Extreme care should be taken not to apply a
silicone grease onto any device pins as much as
possible. The following requirements must be met for
proper grease application:
typical measurement circuits for breakdown voltage:
Figure 13-3 shows the high-side transistor (Q1H) in the
U-phase; Figure 13-4 shows the low-side transistor (Q1L)
in the U-phase. And all the pins that are not represented
in these figures are open.
When measuring the high-side transistors, leave all
the pins not be measured open. When measuring the
low-side transistors, connect the LSx pin to be measured
to the COMx pin, then leave other unused pins open.
- Grease thickness: 100 µm
- Heatsink flatness: ±100 µm
VBB
28
- Apply silicone grease within the area indicated in
Figure 13-2, below.
V
Q1H
Q2H Q3H
31
U
V
Screw hole
Screw hole
19
26
MIC
V1
COM1
COM2
16
6
W1
24
35
37
7.4
7.4
V2
Thermal silicone
grease application area
Q1L Q2L Q3L
M2.5
1.25
W2
M2.5
1.25
Heatsink
31.3
LS1
11
2
Unit: mm
LS2
LS2
33
40
LS3A
LS3B
1
Figure 13-2. Reference Application Area for Thermal
Silicone Grease
Figure 13-3. Typical Measurement Circuit for High-
side Transistor (Q1H) in U-phase
13.3 Considerations in IC Characteristics
Measurement
When measuring the breakdown voltage or leakage
current of the transistors incorporated in the IC, note that
the gate and emitter (source) of each transistor should
have the same potential. Moreover, care should be taken
when performing the measurements, because each
transistor is connected as follows:
VBB
28
Q1H
Q2H Q3H
31
U
V
19
26
● All the high-side collectors (drains) are internally
connected to the VBB pin.
● In the U-phase, the high-side emitter (source) and the
low-side collector (drain) are internally connected,
and are also connected to the U pin.
V
MIC
V1
COM1
COM2
16
6
W1
24
35
37
V2
Q1L Q2L Q3L
W2
(In the V- and W-phases, the high- and low-side
transistors are unconnected inside the IC.)
LS1
The gates of the high-side transistors are pulled down
to the corresponding output (U, V/V1, and W1) pins;
similarly, the gates of the low-side transistors are pulled
down to the COM2 pin.
11
2
LS2
LS2
33
40
LS3A
LS3B
1
When measuring the breakdown voltage or leakage
current of the transistors, note that all of the output (U,
V/V1, and W1), LSx, and COMx pins must be
appropriately connected. Otherwise the switching
transistors may result in permanent damage.
Figure 13-4. Typical Measurement Circuit for Low-
side Transistor (Q1L) in U-phase
The following are circuit diagrams representing
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SIM6800M Series
DT is the duty cycle, which is given by
14. Calculating Power Losses and
Estimating Junction Temperatures
(
)
1 + M × sin φ + θ
DT =
,
This section describes the procedures to calculate
power losses in switching transistors, and to estimate a
junction temperature. Note that the descriptions listed
here are applicable to the SIM6800M series, which is
controlled by a 3-phase sine-wave PWM driving
strategy.
For quick and easy references, we offer calculation
support tools online. Please visit our website to find out
more.
2
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear approximation in the
VCE(SAT) vs. IC curve, and
β is the intercept of the linear approximation in the
VCE(SAT) vs. IC curve.
● DT0026: SIM682xM Calculation Tool
http://www.semicon.sanken-ele.co.jp/en/calc-
tool/sim682xm_caltool_en.html
VCC = 15 V
2.0
125 °C
1.8
y = 0.2051x + 0.8859
1.6
● DT0027: SIM681xM Calculation Tool
http://www.semicon.sanken-ele.co.jp/en/calc-
tool/sim681xm_caltool_en.html
75 °C
25 °C
1.4
1.2
1.0
0.8
● DT0030: SIM688xM Calculation Tool
http://www.semicon.sanken-ele.co.jp/en/calc-
tool/sim688xm_caltool_en.html
0.0
1.0
2.0
3.0
IC (A)
4.0
5.0
Figure 14-1. Linear Approximate Equation of
CE(SAT) vs. IC Curve
14.1 IGBT
V
Total power loss in an IGBT can be obtained by
taking the sum of steady-state loss, PON, and switching
loss, PSW. The following subsections contain the
mathematical procedures to calculate these losses (PON
and PSW) and the junction temperature of all IGBTs
operating.
14.1.2 IGBT Switching Loss, PSW
Switching loss in an IGBT can be calculated by
Equation (5), letting IM be the effective current value of
the motor:
2
VDC
√
14.1.1 IGBT Steady-state Loss, PON
(5)
P
SW
=
× fC × αE × IM ×
.
π
300
Steady-state loss in an IGBT can be computed by
using the VCE(SAT) vs. IC curves, listed in Section 15.3.1.
As expressed by the curves in Figure 14-1, linear
approximations at a range the IC is actually used are
obtained by: VCE(SAT) = α × IC + β. The values gained by
the above calculation are then applied as parameters in
Equation (4), below. Hence, the equation to obtain the
IGBT steady-state loss, PON, is:
Where:
fC is the PWM carrier frequency (Hz),
VDC is the main power supply voltage (V), i.e., the
VBB pin input voltage, and
αE is the slope of the switching loss curve (see Section
15.3.2).
ꢀ
1
14.1.3 Estimating Junction Temperature
of IGBT
( )
( )
PON
=
� VCE(SAT) φ × IC φ × DT × dφ
2π
0
The junction temperature of all IGBTs operating, Tj,
can be estimated with Equation (6):
1
1
4
2
=
α ꢁ +
M × cos θꢂ IM
2
2
3π
(4)
2
1
π
√
{(
)
}
× 6 + TC .
SW
T = R(j−C)Q
j
×
PON + P
(6)
+
β ꢁ + M × cos θꢂ IM .
π
2
8
Where:
Where:
R(j-C)Q is the junction-to-case thermal resistance
(°C/W) of all the IGBTs operating, and
TC is the case temperature (°C), measured at the point
V
CE(SAT) is the collector-to-emitter saturation voltage of
the IGBT (V),
IC is the collector current of the IGBT (A),
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SIM6800M Series
defined in Figure 3-1.
VCC = 15 V
8
7
6
5
4
3
2
1
0
y = 0.5281x + 5.6394
125 °C
14.2 Power MOSFET
75 °C
25 °C
Total power loss in a power MOSFET can be
obtained by taking the sum of the following losses:
steady-state loss, PRON; switching loss, PSW; the steady-
state loss of a body diode, PSD. In the calculation
procedure we offer, the recovery loss of a body diode,
PRR, is considered negligibly small compared with the
ratios of other losses.
The following subsections contain the mathematical
procedures to calculate these losses (PRON, PSW, and PSD)
and the junction temperature of all power MOSFETs
operating.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ID (A)
Figure 14-2. Linear Approximate Equation of
RDS(ON) vs. ID Curve
14.2.2 Power MOSFET Switching Loss,
PSW
14.2.1 Power MOSFET Steady-state Loss,
PRON
Switching loss in a power MOSFET can be calculated
by Equation (8), letting IM be the effective current value
of the motor:
Steady-state loss in a power MOSFET can be
computed by using the RDS(ON) vs. ID curves, listed in
Section 15.3.1. As expressed by the curves in Figure
14-2, linear approximations at a range the ID is actually
used are obtained by: RDS(ON) = α × ID + β. The values
gained by the above calculation are then applied as
parameters in Equation (7), below. Hence, the equation
to obtain the power MOSFET steady-state loss, PRON, is:
VDC
(8)
P
SW
= √2 × fC × αE × IM ×
.
300
Where:
fC is the PWM carrier frequency (Hz),
VDC is the main power supply voltage (V), i.e., the
VBB pin input voltage, and
αE is the slope of the switching loss curve (see Section
15.3.2).
ꢀ
1
( )2
( )
× RDS(ON) φ × DT
PRON
=
� ID
φ
2π
0
× dφ
1
3
3
= 2√2α ꢁ
+
M × cos θꢂ IM
3π 32
(7)
1
1
2
+2β ꢁ +
M × cos θꢂ IM .
8
3π
Where:
ID is the drain current of the power MOSFET (A),
RDS(ON) is the drain-to-source on-resistance of the
power MOSFET (Ω),
DT is the duty cycle, which is given by
(
)
1 + M × sin φ + θ
DT =
,
2
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear approximation in the RDS(ON)
vs. ID curve, and
β is the intercept of the linear approximation in the
RDS(ON) vs. ID curve.
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SIM6800M Series
14.2.3 Body Diode Steady-state Loss, PSD
14.2.4 Estimating Junction Temperature
of Power MOSFET
Steady-state loss in the body diode of a power
MOSFET can be computed by using the VSD vs. ISD
curves, listed in Section 15.3.1. As expressed by the
curves in Figure 14-3, linear approximations at a range
the ISD is actually used are obtained by: VSD = α × ISD + β.
The values gained by the above calculation are then
applied as parameters in Equation (9), below. Hence, the
equation to obtain the body diode steady-state loss, PSD,
is:
The junction temperature of all power MOSFETs
operating, Tj, can be estimated with Equation (10):
{(
)
SD
}
T = Rj−C
j
× PON + PSW + P × 6 + TC .
(10)
Where:
Rj-C is the junction-to-case thermal resistance (°C/W)
of all the power MOSFETs operating, and
TC is the case temperature (°C), measured at the point
defined in Figure 3-1.
ꢀ
1
( )
( )
(
)
P
SD
=
� VSD φ × ISD φ × 1 ꢃ DT × dφ
2π
0
1
2
1
4
2
=
α ꢁ ꢃ M × cos θꢂ IM
2
3π
2
1
π
(9)
√
+
β ꢁ ꢃ M × cos θꢂ IM .
π
2
8
Where:
VSD is the source-to-drain diode forward voltage of the
power MOSFET (V),
ISD is the source-to-drain diode forward current of the
power MOSFET (A),
DT is the duty cycle, which is given by
(
)
1 + M × sin φ + θ
DT =
,
2
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear approximation in the VSD vs.
ISD curve, and
β is the intercept of the linear approximation in the
VSD vs. ISD curve.
VCC = 15 V
2.5
2.0
125 °C
y = 0.2888x + 0.8758
1.5
75 °C
25 °C
1.0
0.5
0.0
0.0
1.0
2.0
3.0
ISD (A)
4.0
5.0
Figure 14-3. Linear Approximate Equation of
VSD vs. ISD Curve
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SIM6800M Series
15. Performance Curves
15.1 Transient Thermal Resistance Curves
The following graphs represent transient thermal resistance (the ratios of transient thermal resistance), with steady-
state thermal resistance = 1.
1.00
0.10
0.01
0.001
0.01
0.1
Time (s)
1
10
Figure 15-1. Transient Thermal Resistance Curve: SIM681xM
1.00
0.10
0.01
0.001
0.01
0.1
1
10
Time (s)
Figure 15-2. Transient Thermal Resistance Curve: SIM682xM
1.00
0.10
0.01
0.001
0.01
0.1
1
10
Time (s)
Figure 15-3. Transient Thermal Resistance Curve: SIM6818M
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SIM6800M Series
15.2 Performance Curves of Control Parts
Figure 15-4 to Figure 15-28 provide performance curves of the control parts integrated in the SIM6800M series,
including variety-dependent characteristics and thermal characteristics. Tj represents the junction temperature of the
control parts.
Table 15-1. Typical Characteristics of Control Parts
Figure Number
Figure 15-4
Figure Caption
Logic Supply Current, ICC vs. TC (INx = 0 V)
Figure 15-5
Figure 15-6
Figure 15-7
Figure 15-8
Figure 15-9
Figure 15-10
Figure 15-11
Figure 15-12
Figure 15-13
Figure 15-14
Figure 15-15
Figure 15-16
Figure 15-17
Figure 15-18
Figure 15-19
Figure 15-20
Figure 15-21
Figure 15-22
Figure 15-23
Figure 15-24
Figure 15-25
Figure 15-26
Figure 15-27
Figure 15-28
Logic Supply Current, ICC vs. TC (INx = 5 V)
VCCx Pin Voltage, VCC vs. Logic Supply Current, ICC curve
Logic Supply Current (1-phase) IBS vs. TC (HINx = 0 V)
Logic Supply Current (1-phase) IBS vs. TC (HINx = 5 V)
VBx Pin Voltage, VB vs. Logic Supply Current IBS curve (HINx = 0 V)
Logic Operation Start Voltage, VBS(ON) vs. TC
Logic Operation Stop Voltage, VBS(OFF) vs. TC
Logic Operation Start Voltage, VCC(ON) vs. TC
Logic Operation Stop Voltage, VCC(OFF) vs. TC
UVLO_VB Filtering Time vs. TC
UVLO_VCC Filtering Time vs. TC
High Level Input Threshold Voltage, VIH vs. TC
Low Level Input Threshold Voltage, VIL vs. TC
Input Current at High Level (HINx or LINx), IIN vs. TC
High-side Turn-on Propagation Delay vs. TC (from HINx to HOx)
Low-side Turn-on Propagation Delay vs. TC (from LINx to LOx)
Minimum Transmittable Pulse Width for High-side Switching, tHIN(MIN) vs. TC
Minimum Transmittable Pulse Width for Low-side Switching, tLIN(MIN) vs. TC
SD Pin Filtering Time vs. TC
FO Pin Filtering Time vs. TC
Current Limit Reference Voltage, VLIM vs. TC
OCP Threshold Voltage, VTRIP vs. TC
OCP Hold Time, tP vs. TC
OCP Blanking Time, tBK(OCP) vs. TC; Current Limit Blanking Time, tBK(OCL) vs. TC
VCCx = 15 V, HINx = 0 V, LINx = 0 V
VCCx = 15 V, HINx = 5 V, LINx = 5 V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-30
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max.
Typ.
Min.
Max.
Typ.
Min.
-30
0
30
60
90
120
150
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-4. Logic Supply Current, ICC vs. TC
(INx = 0 V)
Figure 15-5. Logic Supply Current, ICC vs. TC
(INx = 5 V)
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SIM6800M Series
HINx = 0 V, LINx = 0 V
VBx = 15 V, HINx = 0 V
250
200
150
100
50
3.8
3.6
3.4
3.2
3.0
2.8
2.6
Max.
Typ.
Min.
125°C
25°C
−30°C
0
12
13
14
15
16
17
18
19
20
-30
0
30
60
90
120
150
VCC (V)
TC (°C)
Figure 15-6. VCCx Pin Voltage, VCC vs. Logic
Supply Current, ICC curve
Figure 15-7. Logic Supply Current (1-phase) IBS vs. TC
(HINx = 0 V)
VBx = 15 V, HINx = 5 V
300
VBx = 15 V, HINx = 0 V
180
250
200
150
100
50
160
140
Max.
Typ.
Min.
120
125°C
100
25°C
80
−30°C
60
0
40
-30
0
30
60
90
120
150
12
13
14
15
16
17
18
19
20
TC (°C)
VB (V)
Figure 15-8. Logic Supply Current (1-phase) IBS vs.
TC (HINx = 5 V)
Figure 15-9. VBx Pin Voltage, VB vs. Logic Supply
Current IBS curve (HINx = 0 V)
11.0
10.8
11.5
Max.
11.3
11.1
10.9
10.7
10.5
10.3
10.1
9.9
Max.
10.6
10.4
10.2
10.0
9.8
Typ.
Min.
Typ.
Min.
9.6
9.4
9.2
9.7
9.0
9.5
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-10. Logic Operation Start Voltage, VBS(ON)
vs. TC
Figure 15-11. Logic Operation Stop Voltage, VBS(OFF)
vs. TC
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SIM6800M Series
12.5
12.3
12.1
11.9
11.7
11.5
11.3
11.1
10.9
10.7
10.5
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
Max.
Max.
Typ.
Min.
Typ.
Min.
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-12. Logic Operation Start Voltage, VCC(ON)
vs. TC
Figure 15-13. Logic Operation Stop Voltage, VCC(OFF)
vs. TC
5.0
4.5
4.0
5.0
4.5
4.0
Max.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Max.
Typ.
Min.
Typ.
Min.
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-14. UVLO_VB Filtering Time vs. TC
Figure 15-15. UVLO_VCC Filtering Time vs. TC
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.0
1.8
Max.
1.6
1.4
1.2
1.0
0.8
Max.
Typ.
Min.
Typ.
Min.
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-16. High Level Input Threshold Voltage,
VIH vs. TC
Figure 15-17. Low Level Input Threshold Voltage, VIL
vs. TC
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SIM6800M Series
INHx or INLx = 5 V
800
700
600
500
400
300
200
100
0
400
350
300
250
200
150
100
50
Max.
Typ.
Min.
Max.
Typ.
Min.
0
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-18. Input Current at High Level (HINx or
LINx), IIN vs. TC
Figure 15-19. High-side Turn-on Propagation Delay vs.
TC (from HINx to HOx)
400
700
600
350
300
250
200
150
100
50
Max.
Max.
500
400
300
200
100
0
Typ.
Min.
Typ.
Min.
0
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-20. Low-side Turn-on Propagation Delay
vs. TC (from LINx to LOx)
Figure 15-21. Minimum Transmittable Pulse Width for
High-side Switching, tHIN(MIN) vs. TC
400
6
5
4
350
300
250
200
150
100
50
Max.
Typ.
Min.
Max.
3
2
1
0
Typ.
Min.
0
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-22. Minimum Transmittable Pulse Width
for Low-side Switching, tLIN(MIN) vs. TC
Figure 15-23. SD Pin Filtering Time vs. TC
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SIM6800M Series
6
5
4
3
2
1
0
0.750
0.725
0.700
0.675
0.650
0.625
0.600
0.575
0.550
Max.
Typ.
Min.
Max.
Typ.
Min.
-30
0
30
60
90
120
150
-30
0
30
60
90
120
150
TC (°C)
TC (°C)
Figure 15-24. FO Pin Filtering Time vs. TC
Figure 15-25. Current Limit Reference Voltage, VLIM vs.
TC
50
45
40
35
30
25
20
15
10
5
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
Max.
Typ.
Max.
Typ.
Min.
Min.
0
-30
0
30
60
90
120
150
-30
0
30
60
TC (°C)
90
120
150
TC (°C)
Figure 15-26. OCP Threshold Voltage, VTRIP vs. TC
Figure 15-27. OCP Hold Time, tP vs. TC
4.0
3.5
3.0
Max.
2.5
2.0
1.5
1.0
0.5
0.0
Typ.
Min.
-30
0
30
60
90
120
150
TC (°C)
Figure 15-28. OCP Blanking Time, tBK(OCP) vs. TC;
Current Limit Blanking Time, tBK(OCL) vs. TC
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SIM6800M Series
15.3 Performance Curves of Output Parts
15.3.1 Output Transistor Performance Curves
15.3.1.1. SIM6811M
VCC = 15V
8
1.2
1.0
0.8
0.6
0.4
0.2
0.0
7
25°C
75°C
125°C
6
5
75°C
4
3
25°C
125°C
2
1
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ISD (A)
ID (A)
Figure 15-29. Power MOSFET RDS(ON) vs. ID
Figure 15-30. Power MOSFET VSD vs. ISD
15.3.1.2. SIM6812M
VCC = 15 V
VCC = 15 V
5
1.2
1
125°C
4
25°C
75°C
0.8
0.6
0.4
0.2
0
3
25°C
2
75°C
125°C
1
0
0.0
0.5
1.0
1.5
ID (A)
2.0
2.5
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ISD (A)
Figure 15-31. Power MOSFET RDS(ON) vs. ID
Figure 15-32. Power MOSFET VSD vs. ISD
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SIM6800M Series
15.3.1.3. SIM6813M
VCC = 15 V
VCC = 15 V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1
125°C
25°C
75°C
25°C
0.8
0.6
0.4
0.2
0
75°C
125°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ID (A)
ISD (A)
Figure 15-33. Power MOSFET RDS(ON) vs. ID
Figure 15-34. Power MOSFET VSD vs. ISD
15.3.1.4. SIM6880M
VCC = 15 V
VCC = 15 V
2.5
2.0
1.5
1.0
0.5
0.0
2.0
125°C
1.8
25°C
1.6
75°C
1.4
1.2
1.0
0.8
25°C
75°C
125°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
IF (A)
IC (A)
Figure 15-35. IGBT VCE(SAT) vs. IC
Figure 15-36. FRD VF vs. IF
15.3.1.5. SIM6822M and SIM6827M
VCC = 15 V
125°C
VCC = 15 V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
2.5
2.0
1.5
1.0
0.5
0.0
25°C
75°C
25°C
75°C
125°C
0.0
1.0
2.0
3.0
IC (A)
4.0
5.0
0.0
1.0
2.0
3.0
IF (A)
4.0
5.0
Figure 15-37. IGBT VCE(SAT) vs. IC
Figure 15-38. FRD VF vs. IF
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SIM6800M Series
15.3.2 Switching Losses
Conditions: VBB = 300 V, half-bridge circuit with inductive load.
Switching Loss, E, is the sum of turn-on loss and turn-off loss.
15.3.2.1. SIM6811M
VB = 15 V
VCC = 15 V
250
200
150
100
50
250
200
150
100
50
Tj = 125°C
Tj = 125°C
Tj = 25°C
Tj = 25°C
0
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ID (A)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ID (A)
Figure 15-39. High-side Switching Loss
Figure 15-40. Low-side Switching Loss
15.3.2.2. SIM6812M
VB = 15 V
VCC = 15 V
250
200
250
200
150
100
50
Tj = 125°C
Tj = 125°C
150
100
50
Tj = 25°C
Tj = 25°C
0
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ID (A)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ID (A)
Figure 15-41. High-side Switching Loss
Figure 15-42. Low-side Switching Loss
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SIM6800M Series
15.3.2.3. SIM6813M
VB = 15 V
VCC = 15 V
300
250
200
300
250
200
150
100
50
Tj = 125°C
Tj = 125°C
150
100
50
Tj = 25°C
Tj = 25°C
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
ID (A)
2.0
2.5
3.0
ID (A)
Figure 15-43. High-side Switching Loss
Figure 15-44. Low-side Switching Loss
15.3.2.4. SIM6880M
VB = 15 V
VB = 15 V
300
250
300
250
200
150
100
50
Tj = 125°C
Tj = 125°C
200
150
100
50
Tj = 25°C
2.0
Tj = 25°C
2.0
0
0
0.0
0.5
1.0
1.5
2.5
3.0
0.0
0.5
1.0
1.5
2.5
3.0
IC (A)
IC (A)
Figure 15-45. High-side Switching Loss
Figure 15-46. Low-side Switching Loss
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SIM6800M Series
15.3.2.5. SIM6822M
VB = 15 V
VCC = 15 V
400
350
300
250
400
350
300
250
200
150
100
50
Tj = 125°C
Tj = 125°C
200
150
100
50
Tj = 25°C
Tj = 25°C
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IC (A)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IC (A)
Figure 15-47. High-side Switching Loss
Figure 15-48. Low-side Switching Loss
15.3.2.6. SIM6827M
VCC = 15 V
VB = 15 V
450
400
350
450
400
350
300
250
200
150
100
50
300
Tj = 125°C
Tj = 125°C
250
200
150
100
50
Tj = 25°C
Tj = 25°C
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IC (A)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IC (A)
Figure 15-49. High-side Switching Loss
Figure 15-50. Low-side Switching Loss
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SIM6800M Series
15.4 Allowable Effective Current Curves
The following curves represent allowable effective currents in 3-phase sine-wave PWM driving with parameters such
as typical RDS(ON) or VCE(SAT), and typical switching losses.
Operating conditions: VBB pin input voltage, VDC = 300 V; VCC pin input voltage, VCC = 15 V; modulation index,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, Tj = 150 °C.
15.4.1 SIM6811M
fC = 2 kHz
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-51. Allowable Effective Current (fC = 2 kHz): SIM6811M
fC = 16 kHz
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-52. Allowable Effective Current (fC = 16 kHz): SIM6811M
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SIM6800M Series
15.4.2 SIM6812M
fC = 2 kHz
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-53. Allowable Effective Current (fC = 2 kHz): SIM6812M
fC = 16 kHz
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-54. Allowable Effective Current (fC = 16 kHz): SIM6812M
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SIM6800M Series
15.4.3 SIM6813M
fC = 2 kHz
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-55. Allowable Effective Current (fC = 2 kHz): SIM6813M
fC = 16 kHz
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-56. Allowable Effective Current (fC = 16 kHz): SIM6813M
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SIM6800M Series
15.4.4 SIM6880M
fC = 2 kHz
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-57. Allowable Effective Current (fC = 2 kHz): SIM6880M
fC = 16 kHz
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-58. Allowable Effective Current (fC = 16 kHz): SIM6880M
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SIM6800M Series
15.4.5 SIM6822M
fC = 2 kHz
5.0
4.0
3.0
2.0
1.0
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-59. Allowable Effective Current (fC = 2 kHz): SIM6822M
fC = 16 kHz
5.0
4.0
3.0
2.0
1.0
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-60. Allowable Effective Current (fC = 16 kHz): SIM6822M
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SIM6800M Series
15.4.6 SIM6827M
fC = 2 kHz
5.0
4.0
3.0
2.0
1.0
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-61. Allowable Effective Current (fC = 2 kHz): SIM6827M
fC = 16 kHz
5.0
4.0
3.0
2.0
1.0
0.0
25
50
75
100
125
150
TC (°C)
Figure 15-62. Allowable Effective Current (fC = 16 kHz): SIM6827M
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SIM6800M Series
15.5 Short Circuit SOAs (Safe Operating Areas)
This section provides the graphs illustrating the short circuit SOAs of the SIM6800M series devices whose output
transistors consist of built-in IGBTs.
Conditions: VDC ≤ 400 V, 13.5 V ≤ VCC ≤ 16.5 V, Tj = 125 °C, 1 pulse.
40
30
20
Short Circuit SOA
10
0
0
1
2
3
4
5
Pulse Width (µs)
Figure 15-63. Short Circuit SOA: SIM6880M
100
75
50
25
0
Short Circuit SOA
0
1
2
3
4
5
Pulse Width (µs)
Figure 15-64. Short Circuit SOA: SIM6822M, SIM6827M
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SIM6800M Series
16. Pattern Layout Example
This section contains the schematic diagrams of a PCB pattern layout example using an SIM6800M series device.
For more details on through holes, see Section 10.
Figure 16-1. Top View
Figure 16-2. Bottom View
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SIM6800M Series
20
19
17
21
23
24
VB2 VB1A
C2
C6
V
VB3
W1
C7
C3
VCC1
C8
16
15
14
13
COM1
HIN3
HIN2
26
28
30
31
33
V1
CN1
1
CX1
HIN1 VBB
CN3
12
11
10
SD
VB1B
U
2
R1
1
LS1
OCL
C5
R2
R3
R4
R5
R6
2
3
4
5
6
C1
R17
CN2
9
8
7
LIN3
LIN2
LIN1
LS2
3
2
1
35
37
V2
W2
6
5
4
3
COM2
VCC2
FO
C9
CN4
OCP
R16
R10
10
9
8
7
6
5
4
3
2
1
LS3B 40
2
1
LS2
LS3A
R19
R18
R20
Figure 16-3. Circuit Diagram of PCB Pattern Layout Example
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SIM6800M Series
17. Typical Motor Driver Application
This section contains the information on the typical motor driver application listed in the previous section, including
a circuit diagram, specifications, and the bill of the materials used.
● Motor Driver Specifications
IC
Main Supply Voltage, VDC 300 VDC (typ.)
Rated Output Power 500 W
SIM6822M
● Circuit Diagram
See Figure 16-3.
● Bill of Materials
Symbol
C1
Part Type
Ratings
Symbol
R3
Part Type
General
Ratings
100 Ω, 1/8 W
Electrolytic
Electrolytic
Electrolytic
Electrolytic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Film
47 μF, 50 V
47 μF, 50 V
47 μF, 50 V
100 μF, 50 V
0.1 μF, 50 V
0.1 μF, 50 V
0.1 μF, 50 V
0.1 μF, 50 V
0.1 μF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
100 pF, 50 V
0.01 μF, 50 V
100 pF, 50 V
0.033 μF, 630 V
100 Ω, 1/8 W
100 Ω, 1/8 W
C2
R4
General
100 Ω, 1/8 W
100 Ω, 1/8 W
100 Ω, 1/8 W
0.15 Ω, 2 W
0.15 Ω, 2 W
0.15 Ω, 2 W
100 Ω, 1/8 W
3.3 kΩ, 1/8 W
0 kΩ, 1/8 W
100 Ω, 1/8 W
100 Ω, 1/8 W
100 Ω, 1/8 W
Open
C3
R5
General
C4
R6
General
C5
R7*
R8*
R9*
R10
R16
R17
R18
R19
R20
R21
R22
R23
ZD1
IPM1
CN1
CN2
CN3
CN4
Metal plate
Metal plate
Metal plate
General
C6
C7
C8
C9
General
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
CX1
R1
General
General
General
General
General
General
Open
General
Open
Zener diode
IC
VZ = 21 V (max.)
SIM6822M
Pin header
Pin header
Connector
Connector
Equiv. to B2P3-VH
Equiv. to B2P5-VH
Equiv. to MA06-1
Equiv. to MA10-1
General
R2
General
* Refers to a part that requires adjustment based on operation performance in an actual application.
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SIM6800M Series
Important Notes
● All data, illustrations, graphs, tables and any other information included in this document (the “Information”) as to Sanken’s
products listed herein (the “Sanken Products”) are current as of the date this document is issued. The Information is subject to any
change without notice due to improvement of the Sanken Products, etc. Please make sure to confirm with a Sanken sales
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your name and seal, on the specification documents of the Sanken Products and return them to Sanken, prior to the use of the
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DSGN-CEZ-16003
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