SLA7077MSLF2151 [SANKEN]
Stepper Motor Controller;
| 型号： | SLA7077MSLF2151 |
| 厂家： | 
SANKEN ELECTRIC |
| 描述： | Stepper Motor Controller 电动机控制 |
| 文件： | 总38页 (文件大小：2215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Unipolar 2-Phase Stepper Motor
Driver ICs
SLA7070MS Series
Datasheet
December, 2015 Ver.1.45
This document describes the SLA7070MS series, which are unipolar
2-phase stepping motor driver ICs.
This document contains preliminary information on the products
under development. If you have any questions, including information
on options, please contact your nearest sales or representative office.
Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
General Description .................................................................................2
Features and Benefits..............................................................................2
Part Numbers and Functional Characteristics......................................3
Specifications............................................................................................4
Power Derating Chart..............................................................................8
Package Outline Drawing........................................................................9
Functional Block Diagram and Pin Assignment..................................10
Application Example..............................................................................12
Truth Tables............................................................................................13
10. Logic Input Pins .....................................................................................14
11. Logic Input Timing.................................................................................15
12. Step Sequence Diagrams .......................................................................16
13. Individual Circuit Descriptions.............................................................22
14. Functional Descriptions.........................................................................24
15. Application Information.........................................................................31
16. Thermal Design Information.................................................................36
17. Characteristics Data ..............................................................................38
Sanken Electric Co., Ltd.
http://www.sanken-ele.co.jp/en/
1 / 38
SLA7070MS Series Datasheet Ver.1.45
1. General Description
Thank you for your long years of patronage for each series of our unipolar 2-phase
stepping motor driver ICs. The SLA7070MS series is our latest release.
This document describes summaries of our latest products.
2. Features and Benefits
(1) Main power supply voltages, VBB: 46 V (max.), 10 to 44 V normal operating range
(2) Logic supply voltages, VDD: 3.0 to 5.5 V
(3) Maximum output currents, IO(max): 2.0 A, 3.0 A
(4) Clock-in stepping control (built-in sequencer)
(5) Full-, half-, and microstep products are available
Microstepping options are capable of full-, half-, quarter-, eighth-, and
sixteenth-stepping
(6) Built-in “sense resistor” detects motor current
(7) All variants are pin-compatible for enhanced design flexibility
(8) ZIP type 23-pin molded package (SLA package)
(9) Self-excitation PWM current control with fixed OFF-time
For microstepping variants, OFF-time adjusted automatically by step reference
current ratio (3 levels)
(10) Built-in synchronous rectifying circuit reduces power dissipation at PWM-OFF
(11) Synchronous PWM chopping function prevents motor noise in Hold mode
(12) Sleep mode to reduce IC input current in a stand-by state
(13) Built-in protection circuitry against motor coil opens/shorts and thermal shutdown
protection
(14) The following are the product variants optional features available in the SLA7070MS
series:
1. Blanking Time
• Full/Half step products:
• Microstep products:
3.2 µs (standard), 5.2 µs (optional type B)
1.7 µs (standard), 3.2 µs (optional type B)
2. Input Clock Edge
• Standard type:
• Optional type W:
POS (positive) edge
POS/NEG (positive and negative) edge
NOTE: The optional types listed above, “type B” and “type W”, are abbreviated and
referred to “B” and “W” as the letters for product branding codes, respectively. These
terms and abbreviations are also used throughout this document. See also Section 6
for more details.
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SLA7070MS Series Datasheet Ver.1.45
3. Part Numbers and Functional Characteristics
Table 3-1 provides the product variants available in the SLA7070MS series.
Table 3-1. Part Numbers and Functional Characteristics
Functional Characteristics
Sequencer
Rated Current
(Maximum Setting
Value)
Part Number
Full/Half
Microstep
Step
2.0 A
X
3.0 A
SLA7072MS
SLA7073MS
SLA7077MS
SLA7078MS
X
X
X
X
X
X
X
In addition, the following functional options are available in the SLA7070MS series:
● Blanking Time
• Full/Half step products: 3.2 µs (standard), 5.2 µs (optional type B)
• Microstep products:
● Input Clock Edge
• Standard type:
1.7 µs (standard), 3.2 µs (optional type B)
POS (positive) edge
POS/NEG (positive and negative) edge
• Optional type W:
NOTE: The optional types listed above, “type B” and “type W”, are abbreviated and
referred to “B” and “W” as the letters for product branding codes, respectively. These
terms and abbreviations are also used throughout this document. See also Section 6 for
more details.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
4. Specifications
Table 4-1. Absolute Maximum Ratings
Unless specifically noted, TA = 25°C
Characteristics
Load (Motor Supply)
Voltage
Symbol
Ratings
Unit
Remarks
VM
46
V
Main Power Supply
Voltage
VBB
VDD
46
V
6
7
V
V
Power supply to DC
≤1 μs (5% duty)
Supply Voltage
SLA7072MS
Control
current
value
2.0
3.0
A
A
SLA7077MS
SLA7073MS
SLA7078MS
Output Current
IO
Logic Input Voltage
REF Input Voltage
Sense Voltage
VIN
VREF
VRS
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
±1
V
V
V
Allowable Power
Dissipation
Junction Temperature
Operating Ambient
Temperature
PD
TJ
4.7
W
°C
°C
°C
Without heat sink
150
TA
−20 to 85
Storage Temperature
Tstg
−30 to 150
NOTE: Output current ratings may be limited by duty cycles, ambient temperatures, and heat
sinking. Please do not exceed the maximum output currents and the maximum junction
temperature (TJ) given above under any conditions of use.
Table 4-2. Recommended Operating Conditions
Unless specifically noted, TA = 25°C
Standard Values
Characteristics
Symbol
Unit
Remarks
Min.
Max.
Load (Motor Supply)
Voltage
VM
44
V
Main Power Supply
Voltage
VBB
10
44
5.5
90
V
Surge voltage at VDD pin
should be less than ±0.5
V to avoid malfunctioning
in operation
Measured at Pin 12 (lead
portion), without heat sink
Logic Supply Voltage
VDD
3.0
V
Case Temperature
TC
°C
NOTE: As the motor supply voltage, VM, becomes higher, it also approaches the breakdown
voltage of the OUTx pins (100 V min.); and breakdown will be more likely to happen. Even if
one of the OUTx pins breaks down (due to surge noise or other factors), the SLA7070MS
series will recognize it as abnormality (coil open) and will run appropriate protection
functions. Therefore, a thorough evaluation is recommended.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
Table 4-3. Electrical Characteristics-1
Unless specifically noted, TA = 25°C, VBB = 24 V, and VDD = 5 V
Ratings
Typ.
Characteristics
Symbol
Unit
Conditions
Min.
Max.
15
100
5
IBB
IBBS
IDD
mA
µA
mA
Normal mode
Sleep1 & Sleep2 mode
MainPowerSupplyCurrent
LogicPowerCurrent
MOSFETBreakdown
Voltage
MaximumResponse
Frequency
VDSS
fclk
100
250
V
VBB = 44V, ID = 1 mA
KHz Clock duty cycle = 50%
0.25 x
VDD
VIL
V
V
LogicInputVoltage
LogicInputCurrent
0.75 x
VDD
VIH
IIL
IIH
±1
±1
µA
µA
VREF
VREFS
IREF
0.04
2.0
V
V
µA
Table 4-5, Figure 4-1
Output OFF, Sleep11)
REFInputVoltage
REFInputCurrent
VDD
±10
VREF
− 0.03
VREF
+ 0.03
VREF = 0 to1.5 V
Step reference ratio: 100%
SENSEDetectionVoltage VSENSE
VREF
V
Sleep-EnableRecovery
tSE
100
µs
Sleep1 & Sleep2
Time
tcon
2.0
1.5
µs
µs
Clock
Clock
Output ON
Output OFF
SwitchingTime
tcoff
OvercurrentDetection
VOCP
0.65
0.7
0.75
V
Motor coils shorted
Voltage2)
2.3
3.5
4.6
A
A
A
1.0 A and 1.5 A devices
2.0 A devices
3.0 A devices
OvercurrentDetection
Current
VOCP/RS
LoadDisconnection
UndetectedTime
IOCP
topp
2
µs
From PWM-OFF
Measured at back of
device case (after heat
has saturated)
OverheatProtection
Temperature
T
tsd
140
°C
VFlagL
VFlagH
1.25
1.25
V
V
IFlagL = 1.25 mA
FLAGOutputVoltage
VDD
1.25
−
IFlagH = −1.25 mA
IFlagL
IFlagH
mA
mA
FLAGOutputCurrent
−1.25
NOTE: Unless specifically noted, negative current is defined as output current flow from a
specified pin.
1) In a state of: IBBS, output OFF, and sequencer enabled.
2) Protection circuit operates when VSENSE ≥ VOCP
.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
Table 4-4. Electrical Characteristics-2 (Varying with Step Sequence)
[1] Full-/Half-step products: SLA7072MS, SLA7073MS
Unless specifically noted, TA = 25°C, VBB = 24 V, and VDD = 5 V
Ratings
Characteristics
Symbol
Unit
Conditions
Min.
Typ.
100
70
Max.
ModeF
Mode8
%
%
StepReferenceCurrent
Ratio
VREF ≈ VSENSE = 100%
VREF = 0 to 1.0 V
Standard type
(w/o branding codes)
Optional type B
3.2
µs
MinimumPWMON-Time
PWMOFF-Time
ton(min)
toff
5.2
12
µs
µs
(w/ branding codes)
[2] Microstep products: SLA7077MS, SLA7078MS
Unless specifically noted, TA = 25°C, VBB = 24 V, and VDD = 5 V
Ratings
Typ.
100
Characteristics
Symbol
Unit
Conditions
Min.
Max.
ModeF
ModeE
ModeD
ModeC
ModeB
ModeA
Mode9
Mode8
Mode7
Mode6
Mode5
Mode4
Mode3
Mode2
Mode1
VMOL
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
V
98.1
95.7
92.4
88.2
83.1
77.3
70.7
63.4
55.5
47.1
38.2
29
StepReferenceCurrent
Ratio
VREF ≈ VSENSE = 100%
VREF = 0 to 1.0 V
19.5
9.8
1.25
1.25
IMOL = 1.25 mA
MOOutputVoltage
MOOutputCurrent
VDD
−
VMOH
V
IMOH = −1.25 mA
1.25
IMOL
IMOH
mA
mA
−1.25
Standard type
(w/o branding codes)
Optional type B
(w/ branding codes)
Mode 8 to Mode F
Mode 4 to Mode 7
Mode 1 to Mode 3
1.7
3.2
µs
µs
MinimumPWMON-Time
PWMOFF-time
ton(min)
toff 1
toff 2
toff 3
12
9
7
µs
µs
µs
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SLA7070MS Series Datasheet Ver.1.45
Table 4-5. Electrical Characteristics-3 (Varying with Output Current Range)
[1] IO = 2.0 A
Unless specifically noted, TA = 25°C, VBB = 24 V, and VDD = 5 V
Ratings
Characteristics
Symbol
Unit
Conditions
Min.
Typ.
Max.
OutputMOSFET
ON-Voltage
RDS(on)
0.25
0.4
Ω
ID = 2.0 A
OutputMOSFETBody
DiodesForwardVoltage
SenseResistor1)
VF
RS
0.95
1.2
0.211
0.4
V
Ω
V
IF = 2.0 A
0.199
0.04
0.205
Tolerance: ±3%
Within specified current
limit
REFInputVoltage
VREF
1)
Includes approximately 5 mΩ circuit resistance in addition to the resistance of the built-in
resistor itself.
[2] IO = 3.0 A
Unless specifically noted, TA = 25°C, VBB = 24 V, and VDD = 5 V
Ratings
Characteristics
Symbol
Unit
Conditions
Min.
Typ.
Max.
OutputMOSFET
ON-Resistance
RDS(on)
0.18
0.24
Ω
ID = 3.0 A
OutputMOSFETBody
DiodesForwardVoltage
SenseResistor1)
VF
RS
0.95
2.1
V
Ω
V
IF = 3.0 A
0.150
0.04
0.155
0.160
0.45
Tolerance: ±3%
Within specified current
limit
REFInputVoltage
VREF
1) Includes approximately 5 mΩ circuit resistance in addition to the resistance of the built-in
resistor itself.
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SLA7070MS Series Datasheet Ver.1.45
Figure 4-1. Setting Range of Reference Voltage, VREF
VDD
Sleep1 Set Range
2.0 V
Prohibition Zone
VOCP = 0.7 V
0.45 V
0.4 V
Motor Current Set
Range
2.0 A
Devices
3.0 A
Devices
0.04 V
NOTE: Please pay extra attention to a changeover between the motor current specification
range and the Sleep1 set range. VOCP falls on the “prohibition zone” threshold. If the
changeover takes too long, OCP operation will start when VSENSE > VOCP
.
5. Power Derating Chart
Figure 5-1. Power Derating Chart
5.0
θJ-A=26.6℃/W
4.0
3.0
2.0
1.0
0.0
0
10
20
30
40
50
60
70
80
90
周囲温度 TA [℃]
Ambient Temperature
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
6. Package Outline Drawing
Leadform 2151
1 23 4 5
･
･
･
･
･
･
23
NOTES:
● Dimensions in millimeters
● Pin material: Cu
● Pin plating:
Solder plating (Pb-free)
● Branding codes:
Part number 1: SLA707xMS
• The lowercase letter x represents a number of either of 2, 3, 7, or 8, according to the
combination of rated currents and step sequencers. See also Table 3-1, which lists
the part numbers and corresponding features.
Part number 2: W, B, or WB
• Only optional products have this area labeled with either of the letters listed above.
W, B, and WB stand for optional type W (selectable clock inputs), type B (selectable
blanking times), and type WB (a combined version of types W and B), respectively.
Lot number: YMDD
• Y is the last digit of the year of manufacture
• M is the month of the year (1 to 9, O, N, or D)
• DD is the day of the month (01 to 31)
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
7. Functional Block Diagram and Pin Assignment
Figure 7-1. FullR-/Half-Step Products: SLA7072MS, SLA7073MS
E
F
C
/
S
W
C
L
C
K
R
E
S
E
T
L
O
U
T
O
U
T
O
U
T
O
U
T
O
U
T
O
U
T
O
U
T
O
U
T
F
L
E
E
P
1
/
C
O
N
V
D
D
C
V
A
G
M
M
M
.
C
B
B
W
A
A
A
A
B
B
B
B
2
3
1
.
1
2
3
4
14
13
18
7
8
9
16 10 15
6
11
20 21 22 23
Reg.
MIC
Pre-
Driver
Pre-
Driver
Sequencer
&
Sleep Circuit
Protection
Protection
DAC
TSD
DAC
+
+
-
Synchro
Control
Comp
Comp
19
5
SENSEA
SENSEB
-
PWM
Control
PWM
Control
OSC
OSC
Rs
Rs
17
12
SYNC
GND
Pin No.
1
Symbol
OUTA
Functions
Phase A output
2
___________
___
3
OUTA
Phase A output
4
5
6
SENSEA
NC
Phase A current sensing
No connection
7
M1
8
M2
Input for excitation mode & Sleep2 setting
9
M3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLOCK
VBB
GND
Step clock input
Main power supply voltage (for motor)
Ground
REF/SLEEP1
VDD
Input for control current / Sleep1 setting
Power supply to logic
RESET
CW/CCW
SYNC
Reset input for internal logic
Forward / reverse input
Synchronous PMW control switch input
Output from protection circuit monitor
Phase B current sensing
FLAG
SENSEB
___________
___
OUTB
Phase B output
OUTB
Phase B output
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SLA7070MS Series Datasheet Ver.1.45
Figure 7-2. Microstep Products: SLA7077MS, SLA7078MS
1
2
3
4
14
13
18
6
7
8
9
16 10 15
11
20 21 22 23
Reg.
MIC
Pre-
Driver
Pre-
Driver
Sequencer
&
Sleep Circuit
Protection
Protection
DAC
TSD
DAC
+
+
Synchro
Control
Comp
Comp
19
5
SENSEA
SENSEB
-
-
PWM
Control
PWM
Control
OSC
OSC
Rs
Rs
17
12
SYNC GND
Pin No.
Symbol
OUTA
Functions
1
2
Phase A output
___________
___
3
OUTA
Phase A output
4
Phase A current sensing
5
SENSEA
MO
Output from 2-phase excitation status monitor
6
7
M1
Input for excitation mode & Sleep2 setting
8
M2
9
M3
10
11
12
13
14
15
16
17
CLOCK
VBB
Step clock input
Main power supply voltage (for motor)
Ground
Input for control current / Sleep1 setting
Power supply to logic
GND
REF/SLEEP1
VDD
RESET
CW/CCW
SYNC
Reset input for internal logic
Forward / reverse input
Synchronous PMW control switch input
Output from protection circuit monitor for
detecting coil opens/shorts
Phase B current sensing
18
FLAG
19
20
21
22
23
SENSEB
___________
___
OUTB
Phase B output
OUTB
Phase B output
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SLA7070MS Series Datasheet Ver.1.45
8. Application Example
Figure 8-1. Application Example for Microstep Products
VBB = 10 to 44 V
＋CA
VDD = 3.0 to 5.5 V
OUTA OUTA
VDD
VBB
OUTB OUTB
SLEEP
C1
R1
Q1
RESET/SLEEP1
CLOCK
＋
CB
CW/CCW
M1
SLA7070MS Series
Micro-
Controller
M2
M3
SYNC
MO
FLAG
REF/SLEEP
SENSEB
GND
SENSEA
R2
R3
C2
Single-Point
Ground
Logic Ground
Constants, for reference use only:
Power Ground
R1 = 10 kΩ
R2 = 1 kΩ (VR)
R3 = 10 kΩ
CA = 100 µF / 50 V
CB = 10 µF / 10 V
C1 = 0.1 µF
C2 = 0.1 µF
NOTES:
● Take precautions to avoid noise on the VDD line; noise levels greater than 0.5 V on the VDD
line may cause device malfunction. Noise can be reduced by separating the logic ground
and the power ground on a PCB from the GND pin (Pin 12).
● Unused logic input pins (CW/CCW, M1, M2, M3, RESET, and SYNC) must be pulled up or
down to VDD or ground. If those unused pins are left open, the device malfunctions.
● Unused logic output pins (MO, FLAG) must be kept open.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
9. Truth Tables
(1) Common Input Pins
Table 9-1 shows the truth table for the input pins common to both full-/half-stepping and
microstepping products available in the SLA7070MS series.
Table 9-1.Truth Table for Common Input Pins
Clock
Pin Name
Low Level
High Level
POS Edge
(Standard)
POS/NEG Edge
(OptionaltypeW)
RESET
CW/CCW
M1
Normal operation
Forward (CW)
Logic reset
—
Reverse (CCW)
M2
Commutation (Sleep2 is not included)
M3
REF/SLEEP1
SYNC
Normal operation
Non-sync PWM
control
Sleep1 function
—
—
Sync PWM control
The Reset function is asynchronous. If an input on the RESET pin is high, the internal
logic circuit is reset. At this point, if the REF/SLEEP1 pin stays low, outputs turn on at
the starting point of excitation. Note that a signal on the RESET pin cannot control an
output disable command.
Voltage at the REF/SLEEP1 pin controls PWM current and the Sleep1 function.
• When VREF ≤ 1.5 V (low level), the REF/SLEEP1 pin functions as the reference
voltage input for normal operation.
• When VREF ≥ 2.0 V (high level), the REF/SLEEP1 pin disables all outputs. This is
the Sleep1 mode that disables the internal linear circuitry and minimizes the main
power supply current, IBB. Although much of the internal circuitry is disabled, the
logic circuit is still active. If a clock input signal is transmitted, the internal
sequencer/translator circuit reacts and sets a step starting point for the next
operation.
The Sleep2 function operates in the same way as the Sleep1 function does, except that
the internal logic circuit enters the Hold mode. Therefore, in the Sleep2 mode, the
internal sequencer/translator circuit is not activated even if a step command signal
occurs on the CLOCK input pin.
The Sync function runs only at “2-phase excitation timing." If this function is used at
other than the 2-phase excitation timing, an overall balance might collapse because PWM
OFF-times and setting currents are different in each of phase A and phase B control
scenario. (If this function is used at a point of 1-phase excitation, it does not react as the
Sync function does. But there is no problem.) The 2-phase excitation timing is a point
where the step reference current ratio of both phases A and B is either of Mode 8 or F.
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SLA7070MS Series Datasheet Ver.1.45
(2) Commutation/Sleep2 Function Setting
Table 9-2 provides the logic of the pins (M1, M2, and M3) which set commutation.
Table 9-2. Truth Table for Commutation/Sleep2 Functions
Function (Pin Name)
Full/Half Step
Microstep
M1
L
M2
L
M3
L
Full step (Mode 8 fixed)
Full step (Mode F fixed)
Half step (1-2 Phase)
Half step (Mode F fixed)
Full step (Mode 8 fixed)
Full step (Mode F fixed)
Half step (1-2 Phase)
Half step (Mode F fixed)
Quarter step (W1-2 Phase)
Eighth step (2W1-2 Phase)
Sixteenth step (4W1-2 Phase)
Sleep2 function
H
L
H
L
L
L
H
H
L
L
L
H
H
H
H
H
L
L
Sleep2 function
H
H
H
NOTE: The Sleep2 function disables outputs and reduces the driver supply current (IBB) in
the same way as the Sleep1 function does. However, unlike the Sleep1 function, the logic
circuitry is put into a “standby” state in the Sleep2 function. Therefore, the
sequencer/translator is not activated even if a step command signal occurs on the CLOCK
input pin. When awaking from the Sleep2 mode, a delay of 100 µs or longer before sending
a clock pulse is recommended.
(3) Monitor Output Pins
The SLA7070MS series provides two device status monitor outputs:
• MO pin (microstepping products only) – Step sequence
• FLAG pin – Protection feature operation
Table 9-3 shows the logic for the monitor output pins.
Table 9-3. Truth Table for Monitor Output Pins
Pin Name
MO
FLAG
Low Level
Other than 2-phase excitation timing
Normal operation
High Level
2-phase excitation timing
Protection circuit operation
NOTE: Outputs turn off at the point where the protection circuit starts operating.
To release the protection state, cycle the logic supply voltage, VDD
.
10.Logic Input Pins
The low pass filter (LPF) incorporated with the logic input pins (CLOCK, RESET,
CW/CCW, M1, M2, M3, and SYNC) improves noise rejection.
The logic inputs are CMOS input compatible; therefore, they are in a high impedance
state. Please use the IC at a fixed input level, either low or high.
If there is a possibility that signals from the microcontroller are in high impedance, please
add a pull-up/-down resistor. Since outputs from the logic input pins, which function as output
ON/OFF controllers, may result in abnormal oscillation, leading to MOSFET breakdown as
the worst-case scenario.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
11.Logic Input Timing
(1) Clock Signal
a. A low-to-high transition (rising, or POS edge) or a low-to-high then high-to-low
transition (rising and falling, or POS/NEG edge) on the CLOCK input advances the
sequencer/translator. Clock pulse width should be set at 2 μs or longer in both positive
and negative polarities. Therefore, clock response frequency is set to 250 kHz.
b. Clock Edge Timing
With regard to the input logic of the CW/CCW, M1, M2, and M3 pins, a 1 μs delay
should occur both before and after a pulse edge, as setup and hold times (see Figure
11-1). The sequencer logic circuitry might malfunction if the logic polarity is changed
during these setup and hold times.
Figure 11-1. Input Signal Timing
POS Edge (Standard Type)
Reset
2 µs (min)
5 µs (min)
4 µs (min)
2 µs (min)
Clock
2 µs (min)
CW/CCW
M1
1 µs (min) 1 µs (min)
M2
M3
1 µs (min) 1 µs (min)
POS/NEG Edge (Optional Type W)
Reset
2 µs (min)
5 µs (min)
4 µs (min)
2 µs (min)
Clock
2 µs (min)
CW/CCW
M1
1 µs (min) 1 µs (min)
M2
M3
1 µs (min) 1 µs (min)
1 µs (min) 1 µs (min)
NOTE: When awaking from the Sleep1 or Sleep2 mode, a delay of 100 µs or longer before
sending a clock pulse is recommended.
(2) Reset Signal
a. Reset Signal Pulse Width
Reset pulse width is equivalent to the hold time of a high level input. It should be
greater than 2 µs, same as the clock input pulse width.
b. Reset Release and Clock Input Timing
When the timing of a reset release (falling edge) and a clock edge is simultaneous, the
internal logic might cause an unexpected operation. Therefore, a greater than 5 µs delay
is required between the falling edge of the RESET input and the next rising edge of the
CLOCK input (see Figure 11-1).
(3) Logic Level Change
Logic level inputs on CW/CCW, M1, M2, and M3 set the translator step direction
(CW/CCW) and step mode (M1, M2, and M3; see also Table 9-2, the commutation truth
table). Changes to those inputs do not take effect until the rising edge of the CLOCK input.
However, depending on the type and state of a motor, there may be errors in motor
operation such as step-out. A thorough evaluation on the changes of sequence should be
carried out.
Sanken Electric Co., Ltd.
15 / 38
SLA7070MS Series Datasheet Ver.1.45
12.Step Sequence Diagrams
Figure 12-1. Full Step (2-Phase Excitation)
M1: L, M2: L, M3: L (Mode 8)
RESET
CLOCK
0
…
2
1
B
CW
A
A
0
70.7
CCW
B
M1: H, M2: L, M3: L (Mode F)
RESET
CLOCK
0
…
1
2
B
CW
A
A
0
CCW
B
NOTE: All illustrations in this section are based on step sequencing at the POS edge
(standard type). For POS/NEG edge (optional type W) products, both of the rising and
falling edges of a clock input signal activate the step sequencer.
Sanken Electric Co., Ltd.
16 / 38
SLA7070MS Series Datasheet Ver.1.45
Figure 12-2. Half Step (1-2 Phase Excitation)
M1: L, M2: H, M3: L (1 Phase: Mode F / 2 Phase: Mode 8)
RESET
CLOCK
…
0
1
2
3
4
B
CW
A
A
0
70.7
CCW
B
M1: H, M2: H, M3: L (Mode F)
RESET
CLOCK
…
0
1
2
3
4
B
CW
A
A
0
CCW
B
NOTE: All illustrations in this section are based on step sequencing at the POS edge
(standard type). For POS/NEG edge (optional type W) products, both of the rising and
falling edges of a clock input signal activate the step sequencer.
Sanken Electric Co., Ltd.
17 / 38
SLA7070MS Series Datasheet Ver.1.45
Figure 12-3. Quarter Step (W1-2 Phase Excitation); for microstep products only
M1: L, M2: L, M3: H
RESET
CLOCK
…
0
1
2
3
4
5
6
7
８
B
CW
A
A
0
38.2
70.7
92.4
CCW
B
NOTE: All illustrations in this section are based on step sequencing at the POS edge (standard type). For POS/NEG edge
(optional type W) products, both of the rising and falling edges of a clock input signal activate the step sequencer.
Sanken Electric Co., Ltd.
18 / 38
SLA7070MS Series Datasheet Ver.1.45
Figure 12-4. Eighth Step (2W1-2 Phase Excitation); for microstep products only
M1: H, M2: L, M3: H
RESET
CLOCK
…
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
B
CW
A
A
0
19.5
38.2
55.5
70.7
83.1
CCW
92.4
98.1
B
NOTE: All illustrations in this section are based on step sequencing at the POS edge (standard type). For POS/NEG
edge (optional type W) products, both of the rising and falling edges of a clock input signal activate the step sequencer.
Sanken Electric Co., Ltd.
19 / 38
SLA7070MS Series Datasheet Ver.1.45
Figure 12-5. Sixteenth Step (4W1-2 Phase Excitation); for microstep products only
M1: L, M2: H, M3: H
RESET
CLOCK
…
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
B
CW
A
A
0
9.8
19.5
29.0
38.2
47.1
55.5
63.4
70.7
77.3
83.1
88.2
CCW
92.4
98.1
95.7
B
NOTE: All illustrations in this section are based on step sequencing at the POS edge (standard type). For POS/NEG edge
(optional type W) products, both of the rising and falling edges of a clock input signal activate the step sequencer.
Sanken Electric Co., Ltd.
20 / 38
SLA7070MS Series Datasheet Ver.1.45
Excitation Change Sequence
The change of excitation modes is determined by the settings of the excitation pins (M1, M2,
and M3) before and after a step signal. Table 12-1 shows each excitation mode state setting.
Table 12-1. Excitation Mode States
）
Internal Sequence State1)
Phase A Phase B
PWM PWM PWM PWM
Step Sequencing2
2 Phase (Full Step)
Mode 8 Mode F
XX
1-2 Phase (Half Step)
2W1-2
Phase
(1/8 Step)
4W1-2
Phase
(1/16 Step)
Direction
W1-2 Phase
(1/4 Step)
Mode 8/F
Mode F
A
A
A
A
A
A
A
A
-
8
7
6
5
4
3
2
1
-
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
-
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
/B
-
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
-
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
-
X
X
XX
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XX
X
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
-
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
-
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
E
D
C
B
A
9
CCW
X
X
X
XX
XX
XX
XX
X
XX
CW
X
A
A
A
B
B
B
1
2
3
4
5
6
7
A
A
A
A
B
B
B
B
1) Each mode is defined accordingly to the SLA7070M series.
2)
“XX” indicates that sequence state is Mode 8; but step reference current ratio is Mode F.
Mode F has a step reference current ratio of 100%, and a PWM OFF-time of 12 μs.
Sanken Electric Co., Ltd.
21 / 38
SLA7070MS Series Datasheet Ver.1.45
13.Individual Circuit Descriptions
(1) Monolithic IC (MIC)
• Sequencer Logic
The single clock strategy is employed for step timing. The CW/CCW input determines
the direction of motor rotation. The excitation mode is controlled by the combination of
the M1, M2, and M3 input logic levels. See Section 9 for truth tables, and Section 11 for
input timings.
• PWM Control
Outputs are controlled by a pair of self-excitation PWM current-control circuits with a
fixed OFF-time. Each of built-in oscillators (OSC) sets a PWM OFF-time and a blanking
time the PWM controls. Operation mechanism of the PWM control circuitry is identical
to that of the SLA7070M family. For more detailed functional descriptions, see Section
14.
• Synchronous Control
The SLA7070MS series has a synchronous chopping circuit to prevent noise which
may occasionally be generated during the motor Hold state. This function can be
operated by setting the SYNC pin to logic high, which generates a timing signal to
simultaneously turn off the chopping of phases A and B.
This function adopts the same operation mechanism as applied to the SLA7070M
series. Therefore, the use of the synchronous control during normal stepping is not
recommended because it produces less motor torque or may cause motor vibration due
to staircase current.
The use of the synchronous control when the motor is not in operation is allowed only
in 2-phase excitation timing, due to the differences in currents controlled and PWM
OFF-times between phases A and B at other excitation timings. And consequently, these
two phases may not be synchronized or may be greatly disrupted in their control current
values.
• DAC (D-to-A Converter)
DACs that determine reference voltage for the control current are provided. In
microstep sequencing, the current at each step is set by the values of sense resistors (RS),
reference voltage (VREF), and output voltage of the DACs, controlled by the output of the
sequencer/translator circuit. For the step reference current ratios, see the electrical
characteristics tables given in Section 4.
• Regulator Circuit
An integrated regulator circuit is used for powering the output MOSFET gate drive
circuit (Pre-Driver) and other internal linear circuits.
• Protection Circuit
Built-in protection circuit against motor coil opens or shorts are provided. This
protection is activated by sensing voltage on the internal sense resistors, RS. Therefore,
an overcurrent condition cannot be detected which results from the OUTx pins or
SENSEx pins, or both, shorting to the GND. The protection against motor coil opens is
available only during PWM operation; therefore, it does not work at constant voltage
driving, when the motor is rotating at a high speed.
Operation of the protection circuit disables all outputs. To come out of the protection
mode, cycle the logic supply, VDD. For more details, see the next section.
• TSD Circuit
A TSD circuit protects the driver by shifting an output to the Disable mode when the
temperature of the monolithic IC (MIC) rises and becomes higher than its threshold. To
reset, perform the same steps as described in the Protection Circuit description, above.
Sanken Electric Co., Ltd.
22 / 38
SLA7070MS Series Datasheet Ver.1.45
(2) Output MOSFET Chip
The type of MOSFET chips to be mounted varies according to which of the two different
output current ratings has been selected. For specifications, see Table 4-5.
Rated Current
Resistance
(ΩTyp.)
0.25
(A)
2.0
3.0
0.18
NOTE: Each resistance shown above includes approximately 5 mΩ circuit resistance in
addition to the resistance of the built-in resistor itself.
(3) Sense Resistor
Sense resistors are incorporated in this series to detect motor current. The resistance
varies according to which of the two different output current ratings has been selected.
For specifications, see Table 4-5.
Rated Current
(A)
Resistance
(ΩTyp.)
2.0
3.0
0.205
0.155
NOTE: Each resistance shown above includes approximately 5 mΩ circuit resistance in
addition to the resistance of the built-in resistor itself.
Sanken Electric Co., Ltd.
23 / 38
SLA7070MS Series Datasheet Ver.1.45
14.Functional Descriptions
(1) PWM Current Control
[1] Blanking Time
An actual operating waveform on the SENSEx pin when driving a motor is shown in
Figure 14-1.
Figure 14-1. Operating Waveform on SENSEx Pin during PWM Chopping
(Circled area of the left panel is shown in expanded scale in the right panel)
ITRIP
OUT
0
OUT
Immediately after PWM turns off, ringing (or spike) noise on the SENSEx pin is
observed for a period of a few microseconds. Ringing noise can be generated by various
causes, such as capacitance between motor coils or inappropriate motor wiring.
Each pair of outputs is controlled by a fixed OFF-time PWM current-control circuit
that limits the load current to a target value, ITRIP. Initially, an output is enabled and
current flows through the motor winding and the current sense resistors. When the
voltage across the current sense resistors equals the DAC output voltage, VTRIP, the
current sense comparator resets PWM latch. This turns off the driver for the fixed
OFF-time, during which the load inductance causes the current to recirculate for the
OFF-time period. Therefore, if the ringing noise on the current sense resistor(s) equals
and surpasses VTRIP, the PWM turns off (i.e., a hunting phenomenon).
To prevent this phenomenon, a blanking time is set to override signals from the
current sense comparator for a certain period immediately after the PWM turns on
(Figure 14-2).
Figure 14-2. SENSEx Pin Waveform Pattern during PMW Control
PWM Pulse Width
OFF
(Fixed)
ON
ITRIP
A
A
0
Blanking Time
Sanken Electric Co., Ltd.
24 / 38
SLA7070MS Series Datasheet Ver.1.45
Figure 14-3. Example of SENSEx Pin
Waveform during Hunting
Phenomenon
[2] Blanking Time and Hunting Phenomenon
Although current control can be improved by
shortening a blanking time, the degree of
margin to
a
ringing noise decreases
simultaneously. For this reason, when a motor
is driven by the device, a hunting phenomenon
may occur. Figure 14-3 shows an example of the
waveform pattern when the phenomenon
occurs.
ITRIP
In order to overcome this problem, Sanken
has released a new option, “type B”, which
offers a longer blanking time.
0
Having the longer blanking time, the
optional type B can improve problems such as
torque reduction and huge motor noise that are
occasionally found during the hunting
phenomenon.
20μs/div
[3] Blanking Time Difference
Difference in blanking times is shown in Table 14-1.
This comparison is based on the case where drive conditions, such as a motor, motor
power supply voltage, REF input voltage, and circuit constant were kept the same
while only the indicated parameters were changed.
Table 14-1. Characteristics Comparison by the Difference in Blanking Time
Parameter
Characteristics Comparison
Short Long
Small
Internal blanking time setting
Minimum PWM ON-time
Ringing noise suppression
Minimum coil current
Large
Small
Coil current waveform
distortion at a high rotation
(mainly microstep)
Large
Brief descriptions for each parameter are as follows:
• Minimum PWM ON-time, tON(min)
Each of the SLA7070MS series has a blanking time fixed by PWM control. Thus,
when its ON-time is shortened in order to reduce currents across the device, it
would not go below a predetermined blanking time. Minimum PWM ON-time
refers to the time when an output is on during this blanking time period, that is,
when an output MOSFET is actually turned on. In other words, a blanking time
determines a minimum ON-time (“Small” in Table 14-1).
• Minimum Coil Current
This refers to a coil current when PWM control is performed during a minimum
PWM ON-time. In other words, the device with a shorter blanking time can
reduce more current.
• Coil Current Waveform Distortion during High-Velocity Revolution
While a microstep drive is active, ITRIP value changes with the CLOCK input to
a predetermined value. The ITRIP value (internal reference voltage splitting ratio)
is then set up to be a sine wave. Because the PWM control of motor coil current is
set according to the ITRIP value, (the envelope of) the motor coil current will also be
controlled to be sine wave-like.
Sanken Electric Co., Ltd.
25 / 38
SLA7070MS Series Datasheet Ver.1.45
In fact, due to the inductance characteristic of the coil, the device requires some
time to bring the coil current completely to a targeted value (ITRIP).
Roughly, the relationship between the convergence time (tconv), a time until the
coil current settles to its ITRIP value, and the duty cycle (tclk) of an input clock pulse
in any mode is
tCONV tclk
,
where the coil current waveform amplitude serves as a limit for ITRIP
.
When the current attempts to increase, the full limit of tconv is determined by
power supply voltage and the time constant of the motor coil used. While the
current attempts to decrease, the full limit is determined by the power supply
voltage, the damping time constant of the motor coil used, and the minimum
ON-time.
The duty cycle (tclk) is determined by the frequency of an input clock. It becomes
smaller as the frequency of the input clock increases.
When the frequency of the input clock is raised, because tclk becomes small, it is
normal that the coil current cannot be raised to the ITRIP value within a single
clock period. In this situation, the waveform amplitude of the coil current
degenerates from the sine wave, referred to as “waveform distortion.”
Figure 14-4 illustrates the comparison result of waveform distortions. Devices
with different blanking times were compared under the operating conditions that
power supply voltages, current preset values, motors, and so forth were kept the
same.
As shown in the areas circled (blanking times) in the figure below, the
amplitude envelope of the SENSEx pin waveform in the 1.7 µs case, which is the
same as the current waveform, has become sine wave-like whereas the waveform
in the 3.2 µs blanking time case has degenerated from an ideal sine wave.
The meaning of the team "Large" in Table 14-1 is as follows: if making a
comparison under the same operating conditions, a device with a longer blanking
time will result in less waveform distortion due to a lower clock frequency. But if
the clock frequency is the same, waveform distortion will be larger due to a
shorter blanking time.
If such distortion is confirmed, there is still uncertainty over whether or not the
motor characteristics will be affected. Therefore, thorough evaluations should be
carried out for a final judgment.
Figure 14-4. Comparison of SENSEx Pin Waveforms during High-Speed Revolution
Blanking Time: 1.7 µs (typ.) [Standard]
Blanking Time: 3.2 µs (typ.) [Optional Type B]
CLOCK
SENSEA
SENSEB
Sanken Electric Co., Ltd.
26 / 38
SLA7070MS Series Datasheet Ver.1.45
[4] PWM OFF-time
PWM OFF-time for the SLA7070MS series is controlled at a fixed time generated by
the corresponding internal oscillator. It also is switched in three levels by step current
reference ratios. (See Table 4-4 for more details.)
In addition, the SLA7070MS series provides a function that decreases power losses
occurring when PWM turns off. This function dissipates the back EMF stored in a motor
coil at MOSFET turn-on, as well as at PWM turn-on (synchronous rectification
operation).
Figure 14-5 explains difference between two back EMF generation mechanisms.
Whereas the older version of our product series only performs ON/OFF operations using
a MOSFET on the PWM-ON side, the new SLA7070MS series can perform ON/OFF
operations using a MOSFET on the PWM-OFF side.
To prevent simultaneous switching of the output MOSFETs at the synchronous
rectification operation, the IC has a dead time of approximately 0.5 μs. During this dead
time, the back EMF flows through the body diodes of the MOSFETs.
Figure 14-5. Difference in Back EMF Generation
Vcc
Vcc
[Normal Rectification Operation]
[Synchronous Rectification Operation]
Ion
Ioｆｆ
Ion
Ioｆｆ
SPM
SPM
Vg
Vg
Vg
Vg
Rs
Back EMF at Dead Time
Rs
Vrs
Vrs
PWM ON
PWM OFF
PWM ON
PWM ON
PWM OFF
Dead Time
PWM ON
FET Gate Signal
Vg
FET Gate Signal
Vg
0
0
FET Gate Signal
Vg
FET Gate Signal
Vg
VREF
VREF
Sense Voltage
Sense Voltage
0
0
VRS
VRS
Back EMF flows through the body diode of MOFSET during dead time.
Sanken Electric Co., Ltd.
27 / 38
SLA7070MS Series Datasheet Ver.1.45
(2) Protection Functions
The SLA7070MS series includes a motor coil short protection circuit, a motor coil open
protection circuit, and an overheat protection circuit. Detailed explanations of each
protection circuit are provided below.
[1] Motor Coil Short Protection (Load Short) Circuit
This protection circuit, embedded in the SLA7070MS series, begins to operate when
the device detects an increase in the sense resistor voltage, VRS. The threshold voltage
of this protection circuit, VOCP, is set at approximately 0.7 V. Outputs are disabled at a
time when this protection circuit starts, where VRS exceeds VOCP
.
Figure 14-6. Motor Coil Short Protection Circuit Operation
VM
Coil Short Circuit
SPM
Coil Short
Circuit
VOCP
VREF
Normal Operation
Vg
VRS
0
Rs
VRS
Output Disable
NOTES:
● Overcurrent that flows without passing the sense resister is undetectable.
● To recover the circuit after protection operates, VDD must be cycled and started up again.
[2] Motor Coil Open Protection Circuit (Patent acquired)
Driver destruction can occur when one output pin (motor coil) is disconnected in
unipolar drive operation. This is because a MOSFET connected after disconnection
will be in an avalanche breakdown state, where very high energy is added with back
EMF when PWM is off. With the avalanche state, an output cancels the energy stored
in the motor coil where the resisting pressure between the drain and source of the
MOSFET is reached (i.e., the condition in which the breakdown occurred).
Although MOSFETs with a certain amount of an avalanche energy tolerance rating
are used in the SLA7070MS series, the avalanche energy tolerance falls as a
temperature increases.
Because high energy is added repeatedly whenever PWM operation disconnects the
MOSFET, the temperature of the MOSFET rises; and when the applied energy
exceeds the tolerance, the driver will be destroyed. Therefore, a circuit which detects
this avalanche state and protects the driver is added in the SLA7070MS series.
As explained above, when the motor coil is disconnected, accumulated voltage in the
MOSFET causes a reverse current to flow during a PWM OFF-time. For this reason,
VRS that is negative during a PWM OFF-time in normal operation becomes positive
when the motor coil is disconnected. Thus, the disconnected motor is detectable by
sensing that VRS in the PWM OFF-time is positive.
Sanken Electric Co., Ltd.
28 / 38
SLA7070MS Series Datasheet Ver.1.45
In order to avoid detection malfunctions, the SLA7070MS series actuates a
dedicated protection function, the motor coil open protection circuit, when the motor
disconnection state is detected three times continuously (see Figure 14-7).
Figure 14-7. Coil Open Protection Operation
PWM Operation
at Normal Device Operation
PWM Operation
at Motor Disconnection
VM
VM
SPM
SPM
Ion
Ioff
Disconnecton
Vg
Vg
Vout
Vout
Rs
Rs
Vrs
Vrs
Motor
Disconnection
FET Gate Signal
Vg
FET Gate Signal
Vg
0
0
VDSS
Vout
2 VM
VM
Vout
0
0
Breakdown (Avalanche State)
VREF
VREF
VRS
VRS
0
0
Motor Disconnection Detectable
NOTE: This protection feature may operate even the load is not actually disconnected
when the breakdown of an output, which is confirmed by surge noise occurred after
PWM turn-off, still continues even after an overload disconnection undetected time
(topp) has elapsed. Please review the placements of motor, wiring, and so forth to
improve and to settle the breakdown time within the load disconnection undetected
time (topp). (Application variations also must be taken into consideration.) If no
breakdown is found, there will be no problem in operations. Moreover, the device may
be made to operate normally by inserting a capacitor for surge noise suppression
between the OUTx pins and the GND pin as one of possible corrective strategies.
Surge remains under VDSS
Breakdown ends w/in topp
Breakdown continues after topp
VDSS
VDSS
VDSS
VOUT
VOUT
VOUT
[No Problem]
[Improvement Req’d]
[No Problem]
Sanken Electric Co., Ltd.
29 / 38
SLA7070MS Series Datasheet Ver.1.45
[3] Overheat Protection Circuit
When a product temperature rises and exceeds Ttsd, this protection circuit starts
operating and sets all outputs to be disabled.
NOTE: This product series has multichip composition (one IC for control, four
MOSFETs, and two chip resistors). Although main heat sources are the MOSFETs and
the chip resisters, the location which actually detects temperature is the monolithic IC
(MIC). Separated from these main heat sources, the monolithic IC cannot detect a
rapid temperature change. Accordingly, please perform worst-case thermal
evaluations, in which junction temperatures must not exceed a guaranteed value of
150°C, in your application design phase.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
15.Application Information
(1) Motor Current Ratio Setting
The motor current, IO, for the SLA7070MS series is determined by the values chosen for
the external components, R1 and R2, and the current sense resistors, RS, in the case of the
sample application circuit shown in Figure 8-1. The formula to calculate IO is shown below:
R2
Io
VDD / Rs .
(1)
R1 R2
The double-underlined term represents the reference voltage, VREF
.
If VREF is set to less than 0.1 V, variation or impedance of wiring patterns may influence
the IC and the possibility of less accurate current sensing becomes high.
The standard voltage for current ITRIP that the SLA7070MS series controls is partially
divided by internal DACs:
VREF
ITRIP
(Mode Proportion).
(2)
RS
(2) Lower Limit of Control Current
The SLA7070MS series uses a self-oscillating PWM current-control topology in which
an OFF-time is fixed. As energy stored in a motor coil is eliminated within the fixed PWM
OFF-time, coil current flows intermittently, as shown in Figure 15-1. Thus, average
current decreases as well as motor torque decreases. The point at which current starts
flowing to the coil is considered as the lower limit of the control current, IO(min), where IOUT
is a target current level.
The lower limit of control current differs by application conditions of the motor or other
factors, but it can be calculated from the following formula:
Lm
with
, and
tC
R
VM
R
1
,
1
(3)
R
Rm
IO min
tOFF
R
.
RS
.
exp
DS (on)
tC
Where:
VM is the motor supply voltage,
RDS(on) is the MOS FET on-resistance,
Rm is the motor winding resistance,
Lm is the motor winding inductance,
tOFF is the PWM OFF-time, and
RS is the current sense resistor.
Even if the control current value is set at less than its lower limit, there is no setting at
which the IC fails to operate. However, the control current will worsen against its target
current.
Figure 15-1. Model Waveform of Control Current Lower Limit
ITRIP (Large)
A
ITRIP (Small)
0
A
The circled area indicates interval when the coil current generated is 0 A.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
(3) Avalanche Energy
In the unipolar topology of the SLA7070MS series, a surge voltage (ringing noise) that
exceeds the MOSFET capacity to withstand might be applied to the IC. To prevent
damage, the SLA7070MS series is designed with built-in MOSFETs having sufficient
avalanche resistance to withstand this surge voltage.
Therefore, even if surge voltages occur, users will be able to
use the IC without any problems.
However, in the cases in which the motor harness used is
too long or the IC is used above its rated current or voltage,
there is a possibility that an avalanche energy could be
applied that exceeds Sanken design expectations. Thus,
users must test the avalanche energy applied to the IC under
actual application conditions.
The following procedure can be used to check the
avalanche energy in your application. Figures 15-2 and 15-3
show test points and waveform characteristics resultant,
respectively.
Figure 15-2. Test Points
From the waveform test result shown in Figure 15-3:
VDS(AV) = 140 V,
ID = 1 A, and
t = 0.5 µs.
The avalanche energy, EAV, then can be calculated using
the following formula:
EAV ≈ VDS(AV) × 1/2 × ID × t
= 140 (V) × 1/2 × 1 (A) × 0.5 × 10-6 (μs)
= 0.035 (mJ).
(4)
Figure 15-3. Waveform at
Avalanche Breakdown
By comparing the calculated EAV values with the graph
shown in Figure 15-4, your application can be evaluated if it
is safe for the IC by being within the avalanche
energy-tolerated dose range of the MOFSETs.
Figure 15-4. Iterated Avalanche Energy Tolerated Level, EAV
20
16
12
8
SLA7073MS/78MS
SLA7072MS/77MS
4
0
0
25
50
75
100
125
150
Product Temperature, TC [°C]
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
(4) ON/OFF Sequence of Power Supply (VBB and VDD
There is no restriction for the ON/OFF sequences of the main power supply, VBB, and
the logic supply, VDD
)
.
(5) Motor Supply Voltage (VM) and Main Power Supply Voltage (VBB)
Because the SLA7070MS series has a structure that separates the monolithic IC (MIC)
and the power MOSFETs as shown in Figure 7-1, the motor supply and the main power
supply are electrically separated. Therefore, it is possible to drive the IC with using
different power supplies and different voltages for the motor supply and the main power
supply.
(6) Internal Logic Circuits
a. Reset for the Internal Sequencer
The sequencer/translator circuit embedded in this product series is initialized by the
built-in power-on reset function, which is activated at a time when the logic supply
(VDD) is applied. Therefore, the output immediately after power-on indicates a status
that the power circuits are in the home state.
When the sequencer/translator must be reset after the motor has been operating, a
signal must be input on the RESET pin. When external reset controlling is not
necessary and the RESET pin is not used, the RESET pin must be pulled to logic low
on an application circuit board.
b. Clock Input
The SLA7070MS series is designed to move one sequence increment at a time when
a clock pulse edge is detected. And there are two different types of sequencer timings:
positive-edge-triggered (standard type, active at
a
rising edge) and
double-edge-triggered (optional type W, active at a rising edge and a falling edge).
When a CLOCK input signal stops, the present excitation state enters the motor
Hold state. At this time, there is no difference to the IC if the CLOCK input signal is at
low level or high level.
c. Chopping Synchronous Circuit
The SLA7070MS series has a chopping synchronous function to protect from
abnormal noises that may occasionally occur during the motor Hold state. This
function can be operated by setting the SYNC pin at high level.
However, if this function is used during motor rotation, control current does not
stabilize; and that may result in reduced motor torque and/or increased vibration.
In addition, the synchronous circuit should
be disabled in order to control the motor
current properly even when it is used in other
than the 2-phase excitation state (Modes 8 and
F) or the 1-phase excitation Hold state.
Figure 15-5. Clock Signal Shutoff
Detection Circuit
In
normal
operation,
an
external
microcomputer sends an input signal for
switching. However, in applications where any
input
signals
cannot
be
transmitted
adequately due to a limited number of ports,
the following method can be taken to use the
function.
The schematic diagram in Figure 15-5 shows
how the IC is designed so that the SYNC signal
can be determined by the CLOCK input signal.
Figure 15-6. Clock Signal Edge
Detection Circuit
a
Step
Clock
Edge
Clock
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SLA7070MS Series Datasheet Ver.1.45
When the CLOCK pin receives a logic high signal, the internal capacitor, C, is
charged, and the SYNC signal is set to logic low. However, if a clock signal cannot rise
above a logic low level, the capacitor is discharged by the internal resistor, R, and the
SYNC signal is set to logic high, causing the IC to shift to the synchronous mode. RC
time constant in this circuit should be determined by the minimum clock frequency
used.
When using a sequence that keeps a clock input signal at logic high, an inverter
circuit must be added.
When a clock signal is set at an undetermined level or when using a POS/NEG edge
product (optional type W), an edge detection circuit (Figure 15-6) can be added to
prepare an input signal for the CLOCK pin, allowing correct processing by the circuit
illustrated in Figure 15-5.
d. Output Disable Circuits (Sleep1 and Sleep2)
There are two methods to set the IC at a motor free-state (coast, with outputs
disabled). One is to set the REF pin to more than 2 V (Sleep1). And the other is to set
all the excitation mode setting pins (M1, M2, and M3) to high (Sleep2). In either way,
the IC is put into the Sleep mode, which stops the main power supply and reduces
circuit current.
Difference between the two methods is that the Sleep1 keeps the internal sequencer
enabled, whereas the Sleep2 puts the internal sequencer into the Hold state. In short,
in the Sleep2 mode, the excitation sequence still remains in the Sleep state even when
a signal is input on the CLOCK pin.
When awaking to normal operation mode (motor rotation) from the Disable (Sleep1
or Sleep2) mode, set an appropriate delay time, a time period from cancellation of the
Disable mode to an initial CLOCK input edge. In doing so, consider not only a rise
time for the IC, but also a rise time for the motor excitation current, which is
important (Figure 15-7).
Figure 15-7. Timing Delay between Disable Mode
Cancellation and the Next Clock Input
REF/SLEEP1 or
M1, M2, and M3
Clock Signal
NOTE: In applications where POS/NEG edge (optional type W) products are used, the
initial CLOCK signal after the Disable mode cancellation can be a high-to-low
transition.
e. REF/SLEEP1 Pin
The REF pin provides access to the following functions:
[1] Reference voltage setting for output current level setting:
Low level (VREF ≤ 0.4 to 0.45 V, depends on rated currents)
[2] Output Enable-Disable control input:
High level (VREF ≥ 2.0 V)
These functions are further described in Section 9, and in the discussion of output
disabling, above. Moreover, the threshold voltage to switch the output enable-disable
signals is set at approximately 1.75 V.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
To control the REF voltage, please pay attention to the following points:
Range A – Control current value also varies in accordance with VREF, not only
within the range specified in [1], but also within the range from [1] to the
threshold voltage (typically 1.75 V). Therefore, power dissipation in the IC and the
sense resistors must be given extra consideration. OCP operation may start
depending on the reference voltage splitting ratio.
Range B – In this range, the voltage that switches output enable and disable
exists. At enable, the same cautions apply as in Range A. In addition, for some
cases, there are possibilities that an output status will become unstable as a
result of iterations between enable and disable states.
f. Logic Input Pins (CLOCK, RESET, CW/CCW, M1, M2, M3, and SYNC)
When a logic input pin (CLOCK, RESET, CW/CCW, M1, M2, M3, or SYNC) is not
used, the pin must be tied to VDD or GND.
Please do not leave any of these pins floating, because there is possibility of undefined
effects on IC performance when they are left open.
g. Monitor Output Pins (MO and FLAG)
MO and FLAG pins are designed as monitor outputs. Moreover, the IC consists of an
inverter output configuration, as can be seen in Figure 15-8. Therefore, let these pins
open when they are not used.
Figure 15-8. MO/FLAG Pin General Internal Circuit Layout
VDD
Static Electricity
MO or
Protection
FLAG
Circuit
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SLA7070MS Series Datasheet Ver.1.45
16.Thermal Design Information
It is not practical to calculate the power dissipation of the SLA7070MS series accurately,
because that would require factors that are variable during operation, such as time periods
and excitation modes during motor rotation, input frequencies and sequences, and so forth.
Given this situation, it is preferable to perform approximate calculations at worst
conditions. The following is a simplified formula for calculation of power dissipation using
extracted minimum necessary parameters:
P I2 (RDS(on)＋Rs) 2,
where:
P is the power dissipation in the IC,
I is the operation current (≈ IO),
RDS(on) is the on-resistance of the output MOSFET, and
Rs is the current sense resistance.
Based on the power dissipation in the IC calculated using the above formula, the expected
increase in operating junction temperature, ΔTJ, of the IC can be estimated using Figure 16-1.
This result must be added to the worst-case ambient temperature when operating, TA(max)
.
Based on the calculation, there is no problem unless TA(max) + ΔTJ > 150°C. However, final
confirmation must be made by measuring the IC temperature during operation and then
verifying power dissipation and junction temperature in the corresponding graph of Figure
16-1.
Figure 16-1. Temperature Increase
150
ΔTJ-A = 26.6 × PD
125
100
75
ΔTC-A = 21.3 × PD
50
25
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Allowable Package Power Dissipation, PD [W]
When the IC is used with a heat sink mounted, product package thermal resistance, θJ-A, is
a variable used in calculating ΔTJ-A. The value of θJ-A is calculated from the following
formula:
θJ-A ≈ θJ-C + θFIN = (θJ-A – θC-A) + θFIN
,
where θFIN is the thermal resistance of the heat sink. Then, ΔTJ-A can be calculated with
using the value of θJ-A
.
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
The following procedure should be used to measure product temperature and to estimate
junction temperature in actual operation.
First, measure a temperature rise in the center of backside of mold resin used for the
device (ΔTC-A).
Second, estimate power dissipation (P) and junction temperature (TJ) from the
temperature rise with reference to Figure 16-1, the Temperature Increase graph. At this
point, the device temperature rise (ΔTC-A) and the junction temperature rise (TJ) become
almost equivalent in the following formula:
ΔTJ ≈ ΔTC-A + P × θJ-C .
CAUTION
The SLA7070MS series is designed as a multichip, consisting of four separate power
elements (MOSFETs), one monolithic IC (MIC), and two sense resistors. Moreover, because
the monolithic IC cannot accurately detect the temperature of the built-in power elements,
which are the primary sources of heat, the SLA7070MS series does not provide a protection
function against overheating. For thermal protection, users must conduct sufficient thermal
evaluations to ensure that the junction temperature of the IC does not exceed a guaranteed
level of 150°C.
This thermal design information is provided for preliminary design estimations only.
Before operating the IC in an actual application, users must experimentally determine its
actual thermal performance (the case temperature of Pin 12). The maximum recommended
case temperatures (Pin 12) for the IC are:
● With no external heat sink connection: 90°C
● With external heat sink connection:
80°C
Sanken Electric Co., Ltd.
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SLA7070MS Series Datasheet Ver.1.45
17.Characteristics Data
(1) Output MOSFET On-Voltage, VDS(on)
SLA7073MS/SLA7078MS
SLA7072MS/SLA7077MS
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
Io = 3.0 A
1.2
1.0
Io = 2.0 A
0.8
0.6
0.4
Io = 2.0 A
Io = 1.0 A
Io = 1.0 A
0.2
0.0
-25
0
25
50
75 100 125
-25
0
25
50
75 100 125
Product Temperature, Tc [℃]
Product Temperature, Tc [°C]
(2) Output MOSFET Body Diodes Forward Voltage, VF
SLA7072MS/SLA7077MS
SLA7073MS/SLA7078MS
1.0
1.0
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
Io=3.0A
Io = 2.0 A
Io=2.0A
Io = 1.0 A
Io=1.0A
-25
0
25
50
75 100 125
-25
0
25
50
75 100 125
Product Temperature, Tc [℃]
Product Temperature, Tc[℃]
Sanken Electric Co., Ltd.
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