STR3A463HDL [SANKEN]
Off-Line PWM Controllers with Integrated Power MOSFET;
| 型号： | STR3A463HDL |
| 厂家： | 
SANKEN ELECTRIC |
| 描述： | Off-Line PWM Controllers with Integrated Power MOSFET |
| 文件： | 总24页 (文件大小：774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Off-Line PWM Controllers with Integrated Power MOSFET
STR3A400HDL Series
Data Sheet
Description
Package
The STR3A400HDL series are power ICs for
switching power supplies, incorporating a MOSFET and
a current mode PWM controller IC.
DIP8
The low standby power is accomplished by the
automatic switching between the PWM operation in
normal operation and the burst-oscillation under light
load conditions. The product achieves high
cost-performance power supply systems with few
external components.
Not to Scale
Selection Guide
● Electrical Characteristics
fOSC(AVG)(typ.) = 100 kHz
Features
● Low Thermal Resistance Package
● Improving circuit efficiency (Since the step drive
control can keep VRM of secondary rectification
diodes low, the circuit efficiency can be improved by
low VF)
Part Number
VDSS (min.)
700 V
RDS(ON) (max.)
3.2 Ω
STR3A462HDL
STR3A463HDL
2.2 Ω
● Noise Reduction
● Current Mode Type PWM Control
● Soft Start Function
● Automatic Standby Function
No Load Power Consumption < 15mW
● Operation Mode
Normal Operation -----------------------------PWM Mode
Light Load Operation ------------------------ Green-Mode
Standby---------------------------- Burst Oscillation Mode
● Random Switching Function
● Output Power, POUT
*
POUT
(Adapter)
AC85
POUT
(Open frame)
AC85
Part Number
AC230V
AC230V
~265V
~265V
STR3A462HDL 31 W
STR3A463HDL 34 W
24 W
42 W
48 W
30 W
26 W
34 W
● Slope Compensation Function
● Leading Edge Blanking Function
● Bias Assist Function
* The output power is actual continues power that is measured
at 50 °C ambient. The peak output power can be 120 to
140 % of the value stated here. Core size, ON Duty, and
thermal design affect the output power. It may be less than
the value stated here.
● Protections
Two Types of Overcurrent Protection (OCP):
Pulse-by-Pulse, built-in compensation circuit to
minimize OCP point variation on AC input voltage
Overload Protection (OLP): Auto-restart
Overvoltage Protection (OVP): Auto-restart
Thermal Shutdown (TSD): Auto-restart with
hysteresis
Applications
● AC/DC adapter
● White goods
● Other SMPS
Typical Application
L51
BR1
D51
C51
VOUT
T1
VAC
R54
R51
R1
C5
PC1
R52
C1
P
R55
D1
S
C53
C52 R53
U51
6
5
8
7
R56
D2 R2
D/ST D/ST
U1
DN/SCT D/ST
C4
GND
STR3A400HDL
D
C2
S/OCP VCC
FB/OLP
4
GND
3
1
2
C3
ROCP
CY
PC1
TC_STR3A400HDL_1_R1
STR3A400HDL-DSE Rev.1.0
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STR3A400HDL Series
Contents
Description ------------------------------------------------------------------------------------------------------1
Contents ---------------------------------------------------------------------------------------------------------2
1. Absolute Maximum Ratings-----------------------------------------------------------------------------3
2. Electrical Characteristics --------------------------------------------------------------------------------4
3. Performance Curves --------------------------------------------------------------------------------------5
3.1 Derating Curves -------------------------------------------------------------------------------------5
3.2 MOSFET Safe Operating Area Curves---------------------------------------------------------6
3.3 Ambient Temperature versus Power Dissipation Curves -----------------------------------6
3.4 Transient Thermal Resistance Curves ----------------------------------------------------------7
4. Block Diagram ---------------------------------------------------------------------------------------------8
5. Pin Configuration Definitions---------------------------------------------------------------------------8
6. Typical Application ---------------------------------------------------------------------------------------9
7. Physical Dimensions ------------------------------------------------------------------------------------ 10
8. Marking Diagram --------------------------------------------------------------------------------------- 10
9. Operational Description ------------------------------------------------------------------------------- 11
9.1 Startup Operation--------------------------------------------------------------------------------- 11
9.2 Undervoltage Lockout (UVLO) ---------------------------------------------------------------- 11
9.3 Bias Assist Function------------------------------------------------------------------------------- 11
9.4 Soft Start Function-------------------------------------------------------------------------------- 12
9.5 Constant Output Voltage Control-------------------------------------------------------------- 12
9.6 Leading Edge Blanking Function -------------------------------------------------------------- 13
9.7 Random Switching Function -------------------------------------------------------------------- 13
9.8 Automatic Standby Function ------------------------------------------------------------------- 13
9.9 Step Drive Control -------------------------------------------------------------------------------- 14
9.10 Overcurrent Protection (OCP) ----------------------------------------------------------------- 14
9.10.1 OCP Operation ------------------------------------------------------------------------------ 14
9.10.2 OCP Input Compensation Function ----------------------------------------------------- 15
9.10.3 Overload Protection (OLP)---------------------------------------------------------------- 15
9.10.4 Overvoltage Protection (OVP)------------------------------------------------------------ 16
9.10.5 Thermal Shutdown (TSD) ----------------------------------------------------------------- 16
10. Design Notes---------------------------------------------------------------------------------------------- 17
10.1 External Components ---------------------------------------------------------------------------- 17
10.1.1 Input and Output Electrolytic Capacitor----------------------------------------------- 17
10.1.2 S/OCP Pin Peripheral Circuit ------------------------------------------------------------ 17
10.1.3 VCC Pin Peripheral Circuit--------------------------------------------------------------- 17
10.1.4 FB/OLP Pin Peripheral Circuit ---------------------------------------------------------- 17
10.1.5 Snubber Circuit------------------------------------------------------------------------------ 17
10.1.6 Peripheral Circuit of Secondary-side Shunt Regulator------------------------------ 18
10.1.7 Transformer---------------------------------------------------------------------------------- 18
10.2 PCB Trace Layout and Component Placement --------------------------------------------- 19
11. Pattern Layout Example------------------------------------------------------------------------------- 21
12. Reference Design of Power Supply ------------------------------------------------------------------ 22
Important Notes---------------------------------------------------------------------------------------------- 24
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STR3A400HDL Series
1. Absolute Maximum Ratings
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless otherwise specified TA = 25 °C, 5 pin = 6 pin = 7 pin = 8 pin.
Parameter
Symbol
IDPEAK
Conditions
Pins
Rating
4.0
Units
A
Notes
STR3A462HDL
STR3A463HDL
STR3A462HDL
STR3A463HDL
Drain Peak Current(1)
Single pulse
8 – 1
4.8
ILPEAK = 1.58 A
ILPEAK = 1.88 A
29
Avalanche Energy(2)(3)
EAS
8 – 1
mJ
41
S/OCP Pin Voltage
VCC Pin Voltage
VS/OCP
VCC
1 – 3
2 – 3
4 – 3
4 – 3
8 − 3
−2 to 6
32
V
V
FB/OLP Pin Voltage
FB/OLP Pin Sink Current
D/ST Pin Voltage
VFB
−0.3 to 14
1.0
V
IFB
mA
V
VD/ST
−1 to VDSS
1.68
STR3A462HDL
STR3A463HDL
MOSFET Power
Dissipation(4)
(5)
PD1
8 – 1
W
1.76
Control Part Power
Dissipation
Operating Ambient
Temperature
VCC × ICC
PD2
TOP
2 – 3
1.3
W
−
−40 to 125
°C
Storage Temperature
Junction Temperature
Tstg
TJ
−
−
−40 to 125
°C
°C
150
(1) See 3.2 MOSFET Safe Operating Area Curves
(2) See Figure 3-2 Avalanche Energy Derating Coefficient Curve
(3) Single pulse, VDD = 99 V, L = 20 mH
(4) See Section 3.3 Ta-PD1 Curve
(5) When embedding this hybrid IC onto the printed circuit board (cupper area in a 15 mm × 15 mm)
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STR3A400HDL Series
2. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless otherwise specified TA = 25 °C, VCC = 18 V, 5 pin = 6 pin = 7 pin = 8 pin.
Parameter
Symbol Conditions Pins
Min.
Typ.
Max.
Units
Notes
Power Supply Startup Operation
Operation Start Voltage
Operation Stop Voltage(1)
Circuit Current in Operation
VCC(ON)
VCC(OFF)
ICC(ON)
VST(ON)
ICC(ST)
2 − 3
2 − 3
2 − 3
13.8
7.6
—
15.0
8.5
16.2
9.2
V
V
VCC = 12 V
1.7
3.0
mA
Startup Circuit Operation
Voltage
8 − 3
2 − 3
2 − 3
40
−4.5
8.0
47
− 2.5
9.6
55
V
mA
V
VCC = 13.5 V
Startup Current
−1.2
10.5
Startup Current Biasing
Threshold Voltage
ICC=−500µA
VCC(BIAS)
Normal Operation
Average Switching Frequency fOSC(AVG)
8 − 3
8 − 3
90
100
8.4
110
kHz
kHz
Switching Frequency
Δf
—
—
Modulation Deviation
VCC = 12 V
Maximum Feedback Current
Minimum Feedback Current
Light Load Operation
IFB(MAX)
IFB(MIN)
4 − 3
4 − 3
−110
−21
−72
−13
−40
−5
µA
µA
FB/OLP Pin Starting Voltage
of Frequency Decreasing
FB/OLP Pin Ending Voltage
of Frequency Decreasing
Minimum Switching
VFB(FDS)
VFB(FDE)
fOSC(MIN)
1 − 8
1 − 8
5 − 8
2.88
2.48
22
3.60
3.10
30
4.32
3.72
38
V
V
kHz
Frequency
Standby Operation
Oscillation Stop FB Voltage
Protection
VFB(OFF)
4 − 3
1.62
1.77
1.92
V
Maximum ON Duty
Leading Edge Blanking Time
DMAX
tBW
8 − 3
70
75
80
%
ns
—
—
330
—
OCP Compensation
Coefficient
DPC
DDPC
—
—
—
—
25.8
36
—
—
mV/μs
%
OCP Compensation ON Duty
OCP Threshold Voltage at
Zero ON Duty
VOCP(L)
1 − 3
0.735
0.795
0.855
V
OCP Threshold Voltage at
36% ON Duty
OCP Threshold Voltage
VOCP(H)
1 − 3
1 − 3
0.843
0.888
1.69
0.933
V
V
VOCP(LEB)
—
—
During LEB (tBW
)
VCC = 32 V
VCC = 12 V
OLP Threshold Voltage
OLP Operation Current
OLP Delay Time
VFB(OLP)
ICC(OLP)
tOLP
4 − 3
2 − 3
—
6.8
—
7.3
260
75
7.8
—
V
µA
ms
V
55
90
FB/OLP Pin Clamp Voltage
OVP Threshold Voltage
VFB(CLAMP)
VCC(OVP)
4 − 3
2 − 3
10.5
27.0
11.8
29.1
13.5
31.2
V
(1)
V
> VCC(OFF) always.
CC(BIAS)
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STR3A400HDL Series
Parameter
Symbol Conditions Pins
Min.
127
Typ.
145
Max.
Units
°C
Notes
Thermal Shutdown Operating
Temperature
Thermal Shutdown Hysteresis
Temperature
Tj(TSD)
—
—
—
Tj(TSD)HYS
—
80
—
°C
MOSFET
Drain-to-Source Breakdown
Voltage
IDS = 300 µA
VDS = VDSS
VDSS
IDSS
8 – 1
8 – 1
700
—
—
V
Drain Leakage Current
—
—
—
—
—
—
—
—
300
3.2
μA
STR3A462HDL
STR3A463HDL
IDS = 0.4 A
On Resistance
RDS(ON)
tf
8 – 1
8 – 1
Ω
2.2
Switching Time
250
ns
Thermal Resistance
Junction to Case Thermal
Resistance(2)
θJ-C
—
—
—
18
°C/W
(2)
θ
is thermal resistance between junction and case. Case temperature (TC) is measured at the center of the case top
J-C
surface.
3. Performance Curves
3.1 Derating Curves
100
100
80
60
40
20
0
80
60
40
20
0
25
50
75
100
125
150
0
25
50
75
100 125 150
JunctionTemperature, TJ Tch (°C)
JunctionTemperature, TJ (°C)
Figure 3-1 SOA Temperature Derating Coefficient Curve
Figure 3-2 Avalanche Energy Derating Coefficient Curve
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STR3A400HDL Series
3.2 MOSFET Safe Operating Area Curves
When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient
derived from Figure 3-1. The broken line in the safe operating area curve is the drain current curve limited by
on-resistance.
Unless otherwise specified, TA = 25 °C, Single pulse.
● STR3A462HDL
● STR3A463HDL
10
10
0.1ms
0.1ms
1
1
1ms
1ms
0.1
0.1
0.01
1
0.01
1
10
100
1000
10
100
1000
Drain-to-Source Voltage (V)
Drain-to-Source Voltage (V)
3.3 Ambient Temperature versus Power Dissipation Curves
● STR3A462HDL
● STR3A463HDL
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
PD1 = 1.76 W
PD1 = 1.68 W
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Ambient Temperature, TA (°C )
Ambient Temperature, TA (°C )
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STR3A400HDL Series
3.4 Transient Thermal Resistance Curves
● STR3A462HDL
100
10
1
0.1
0.01
1µ
10µ
100µ
1m
10m
100m
Time (s)
● STR3A463HDL
10
1
0.1
0.01
1µ
10µ
100µ
1m
10m
100m
Time (s)
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STR3A400HDL Series
4. Block Diagram
VCC
2
D/ST
STARTUP
5~8
UVLO
REG
OVP
TSD
VREG
DRV
PWM OSC
S
Q
R
OCP
VCC
Drain Peak Current
Compensation
OLP
Feedback
Control
S/OCP
GND
FB/OLP
4
LEB
1
3
Slope
Compensation
BD_STR3A400_R1
5. Pin Configuration Definitions
Pin
1
Name
Descriptions
MOSFET source and input of Overcurrent
Protection (OCP) signal
Power supply voltage input for control part and
input of Overvoltage Protection (OVP) signal
S/OCP
D/ST
D/ST
D/ST
1
2
3
4
8
7
6
S/OCP
VCC
GND
2
3
4
VCC
GND
Ground
Input of constant voltage control signal and input
of Overload Protection (OLP) signal
FB/OLP
FB/OLP
D/ST
5
5
6
7
8
D/ST
MOSFET drain and input of startup current
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STR3A400HDL Series
6. Typical Application
The PCB traces D/ST pins should be as wide as possible, in order to enhance thermal dissipation.
In applications having a power supply specified such that VDS has large transient surge voltages, a clamp snubber
circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a damper
snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D/ST pin and
the S/OCP pin.
CRD clamp snubber
L51
BR1
C1
D51
VOUT
T1
VAC
R54
R51
R1
C5
PC1
R52
P
R55
C51
D1
S
C53
C52 R53
U51
6
5
8
7
R56
D2 R2
D/ST D/ST DN/SCT D/ST
C4
U1
GND
STR3A400HDL
D
C2
C（RC）
dumper snubber
S/OCP VCC
FB/OLP
4
GND
3
1
2
C3
ROCP
CY
PC1
TC_STR3A400HDL_2_R1
Figure 6-1 Typical Application
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STR3A400HDL Series
7. Physical Dimensions
● DIP8
NOTES:
- Dimensions in millimeters
- Pb-free
8. Marking Diagram
8
3 A 4 x x H
Part Number
S K Y M D D L
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N, or D)
D is a period of days:
1
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10–11 days of the month (21st to 31st)
Control number
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STR3A400HDL Series
The startup time of the IC is determined by C2
capacitor value. The approximate startup time tSTART is
calculated as follows:
9. Operational Description
All the characteristic values given in this section are
typical values, unless they are specified as minimum or
maximum. Current polarities are defined as follows:
current going into the IC (sinking) is positive current
(+); current coming out of the IC (sourcing) is negative
current (−).
ꢀꢀꢁꢌꢝꢆ ꢞ
ꢀꢀꢁꢃꢝꢘꢆ
ꢗꢅꢘꢄꢙꢘ ꢚ ꢛꢕ ꢜ
(2)
ꢟꢠꢀꢀꢁꢅꢘꢆ
ꢟ
where,
tSTART: Startup time of the IC (s)
VCC(INT): Initial voltage on the VCC pin (V)
9.1 Startup Operation
Figure 9-1 shows the circuit around the VCC pin.
9.2 Undervoltage Lockout (UVLO)
T1
BR1
Figure 9-2 shows the relationship of VCC pin voltage
and circuit current ICC. When the VCC pin voltage
decreases to VCC(OFF) = 8.5 V, the control circuit stops
operation by UVLO (Undervoltage Lockout) circuit, and
reverts to the state before startup.
VAC
C1
P
5-8
D/ST
Circuit current, ICC
D2 R2
U1
2
VCC
D
C2
VD
3
Stop
Start
GND
Figure 9-1. VCC Pin Peripheral Circuit
VCC pin
voltage
VCC（OFF）
VCC（ON）
The IC incorporates the startup circuit. The circuit is
connected to the D/ST pin. When D/ST pin voltage
reaches to Startup Circuit Operation Voltage
VST(ON) = 47 V, the startup circuit starts operation.
During the startup process, the constant current,
ICC(ST) = − 2.5 mA, charges C2 at the VCC pin. When
VCC pin voltage increases to VCC(ON) = 15.0 V, the
control circuit starts switching operation. During the IC
operation, the voltage rectified the auxiliary winding
voltage, VD, of Figure 9-1 becomes a power source to
the VCC pin.
After switching operation begins, the startup circuit
turns off automatically so that its current consumption
becomes zero. The approximate value of auxiliary
winding voltage is about 18V, taking account of the
winding turns of D winding so that the VCC pin voltage
becomes Equation (1) within the specification of input
and output voltage variation of power supply.
Figure 9-2. Relationship between
VCC Pin Voltage and ICC
9.3 Bias Assist Function
By the Bias Assist Function, the startup failure is
prevented.
When FB pin voltage decreases to VFB(OFF)= 1.77 V or
less and VCC pin voltage decreases to the Startup
Current Biasing Threshold Voltage, VCC(BIAS) = 9.6 V,
the Bias Assist Function is activated.
When the Bias Assist Function is activated, the VCC
pin voltage is kept almost constant voltage, VCC(BIAS) by
providing the startup current, ICC(ST), from the startup
circuit. Thus, the VCC pin voltage is kept more than
VCC(OFF)
.
ꢆꢁꢇꢈꢉꢊ ꢆ ꢋ ꢋ
ꢆꢁꢇꢏꢐꢊ ꢆ
ꢁ
ꢁ
ꢀꢀ ꢂꢃꢄꢅ
ꢀꢀ
ꢀꢀ ꢌꢍꢎ
Since the startup failure is prevented by the Bias
Assist Function, the value of C2 connected to the VCC
pin can be small. Thus, the startup time and the response
time of the Overvoltage Protection (OVP) become
shorter.
(1)
⇒ꢑꢒꢊꢓꢔꢁ ꢆ ꢔꢋ ꢋ ꢔꢕꢖꢊꢒꢔꢁ ꢆ
ꢀꢀ
The operation of the Bias Assist Function in startup is
as follows. It is necessary to check and adjust the startup
process based on actual operation in the application, so
that poor starting conditions may be avoided.
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STR3A400HDL Series
Figure 9-3 shows the VCC pin voltage behavior
during the startup period. After the VCC pin voltage
increases to VCC(ON) = 15.0 V at startup, the IC starts the
operation. Then circuit current increases and the VCC
pin voltage decreases. At the same time, the auxiliary
winding voltage, VD, increases in proportion to output
voltage. These are all balanced to produce the VCC pin
voltage.
that the tLIM is less than tOLP = 55 ms (min.).
Startup of IC Startup of SMPS
VCC pin
voltage
Normal opertion
tSTART
VCC(ON)
VCC(OFF)
When the VCC pin voltage is decrease to
VCC(OFF) = 8.5 V in startup operation, the IC stops
switching operation and a startup failure occurs. When
the output load is light at startup, the output voltage may
become more than the target voltage due to the delay of
feedback circuit. In this case, the FB pin voltage is
decreased by the feedback control. When the FB pin
voltage decreases to VFB(OFF) or less, the IC stops
switching operation and the VCC pin voltage decreases.
When the VCC pin voltage decreases to VCC(BIAS), the
Bias Assist Function is activated and the startup failure
is prevented.
Time
Soft start period
approximately 8.75 ms (fixed)
D/ST pin
current, ID
Limited by OCP operation
tLIM < tOLP (min.)
Time
Figure 9-4. VCC and ID Behavior during Startup
VCC pin
voltage
Startup success
Target operating
IC starts operation
9.5 Constant Output Voltage Control
VCC(ON)
voltage
Increase with rising of
output voltage
The IC achieves the constant voltage control of the
power supply output by using the current-mode control
method, which enhances the response speed and
provides the stable operation. The FB/OLP pin voltage
is internally added the slope compensation at the
feedback control (see Section 4), and the target voltage,
VCC(BIAS)
Bias assist period
VCC(OFF)
Startup failure
VSC, is generated. The IC compares the voltage, VROCP
,
Time
of a current detection resistor with the target voltage,
VSC, by the internal FB comparator, and controls the
peak value of VROCP so that it gets close to VSC, as
shown in Figure 9-5 and Figure 9-6.
Figure 9-3. VCC Pin Voltage during Startup Period
9.4 Soft Start Function
● Light Load Conditions
When load conditions become lighter, the output
voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
FB/OLP pin voltage decreases. Thus, VSC decreases,
and the peak value of VROCP is controlled to be low,
and the peak drain current of ID decreases.
Figure 9-4 shows the behavior of VCC pin voltage
and drain current during the startup period.
The IC activates the soft start circuitry during the
startup period. Soft start time is fixed to around 8.75 ms.
during the soft start period, overcurrent threshold is
increased step-wisely (7 steps). This function reduces
the voltage and the current stress of a power MOSFET
and the secondary side rectifier diode.
This control prevents the output voltage from
increasing.
Since the Leading Edge Blanking Function (see
Section 9.6) is deactivated during the soft start period,
there is the case that ON time is less than the leading
edge blanking time, tBW = 330 ns.
● Heavy Load Conditions
After the soft start period, D/ST pin current, ID, is
limited by the Overcurrent Protection (OCP), until the
output voltage increases to the target operating voltage.
When load conditions become greater, the IC
performs the inverse operation to that described above.
Thus, VSC increases and the peak drain current of ID
increases.
This period is given as tLIM
.
In case tLIM is longer than the OLP Delay Time, tOLP
the output power is limited by the Overload Protection
(OLP) operation.
,
This control prevents the output voltage from
decreasing.
Thus, it is necessary to adjust the value of output
capacitor and the turn ratio of auxiliary winding D so
In the current mode control method, when the drain
current waveform becomes trapezoidal in continuous
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operating mode, even if the peak current level set by the
target voltage is constant, the on-time fluctuates based
on the initial value of the drain current.
9.6 Leading Edge Blanking Function
The constant voltage control of output of the IC uses
the peak-current-mode control method.
This results in the on-time fluctuating in multiples of
the fundamental operating frequency as shown in Figure
9-7. This is called the subharmonics phenomenon.
In order to avoid this, the IC incorporates the Slope
Compensation Function. Because the target voltage is
added a down-slope compensation signal, which reduces
the peak drain current as the on-duty gets wider relative
to the FB/OLP pin signal to compensate VSC, the
subharmonics phenomenon is suppressed.
Even if subharmonic oscillations occur when the IC
has some excess supply being out of feedback control,
such as during startup and load shorted, this does not
affect performance of normal operation.
In peak-current-mode control method, there is a case
that the power MOSFET turns off due to unexpected
response of a FB comparator or Overcurrent Protection
(OCP) circuit to the steep surge current in turning on a
power MOSFET. In order to prevent this response to the
surge voltage in turning-on the power MOSFET, the
Leading Edge Blanking, tBW = 330 ns is built-in. During
tBW
,
the
OCP
threshold
voltage
becomes
VOCP(LEB) = 1.69 V in order not to respond to the turn-on
drain current surge (see Section 9.10).
9.7 Random Switching Function
The IC modulates its switching frequency randomly
by superposing the modulating frequency on fOSC(AVG) in
normal operation. This function reduces the conduction
noise compared to others without this function, and
simplifies noise filtering of the input lines of power
supply.
U1
S/OCP
1
FB/OLP
4
GND
3
PC1
ROCP
VROCP
IFB
C3
9.8 Automatic Standby Function
The IC has Automatic Standby Function to achieve
higher efficiency at light load. In order to reduce the
switching loss, the Automatic Standby Function
automatically changes the oscillation mode to green
mode or burst oscillation mode (see Figure 9-8).
Figure 9-5. FB/OLP Pin Peripheral Circuit
Target voltage including
slope compensation
When the output load becomes lower, FB/OLP pin
voltage decreases. When the FB/OLP pin voltage
decreases to VFB(FDS) = 3.60 V or less, the green mode is
activated and the oscillation frequency starts decreasing.
When the FB/OLP pin voltage becomes VFB(FDE) = 3.10
V, the oscillation frequency stops decreasing. At this
point, the oscillation frequency becomes fOSC(MIN) = 30
kHz. When the FB/OLP pin voltage further decreases
and becomes the standby operation point, the burst
oscillation mode is activated. As shown in Figure 9-9,
the burst oscillation mode consists of the switching
period and the non-switching period. The oscillation
frequency during the switching period is the Minimum
Frequency, fOSC(MIN) = 30 kHz.
VSC
-
+
VROCP
Voltage on both
sides of ROCP
FB comparator
Drain current,
ID
Figure 9-6. Drain Current, ID, and FB Comparator
Operation in Steady Operation
Target voltage
without slope compensation
Switching
frequency
fOSC
fOSC(AVG)
Normal
operation
fOSC(MIN)
Green mode
Burst oscillation
tON1
T
tON2
T
T
Standby power
Output power, PO
Figure 9-7. Drain Current, ID, Waveform
in Subharmonic Oscillation
Figure 9-8. Relationship between PO and fOSC
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The IC optimally controls the gate drive of the
internal power MOSFET (Step drive control) depending
on the load condition. The step drive control reduces the
surge voltage of D51 when the power MOSFET turns on
(See Figure 9-11). Since VRM of D51 can be set to lower
value than usual, the price reduction and the increasing
circuit efficiency are achieved by using a diode of low
VF.
Switching period
ID
Non-switching period
Time
fOSC(MIN)
Figure 9-9. Switching Waveform at Burst Oscillation
ID
Generally, in order to improve efficiency under light
load conditions, the frequency of the burst mode
becomes just a few kilohertz. Because the IC suppresses
the peak drain current well during burst mode, audible
noises can be reduced.
The IC has some detection delay time. The higher the
AC input voltage is, the steeper the slope of the drain
current, ID is. Thus, the peak of ID at automatic standby
mode becomes high at a high AC input voltage.
Time
Time
Reducing surge voltage
VD51
Time
Time
Without step drive
control
With step drive
control
It is necessary to consider that the burst frequency
becomes low at a high AC input.
If VCC pin voltage decreases to VCC(BIAS) = 9.6 V
during the transition to the burst mode, Bias Assist
Function is activated and stabilizes the standby mode,
because the Startup Current, ICC(ST), is provided to the
VCC pin so that the VCC pin voltage does not decrease
to VCC(OFF). However, if the Bias Assist Function is
always activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than VCC(BIAS), for
example, by adjusting the turns ratio of the auxiliary
winding and the secondary-side winding and/or reducing
the value of R2 in Figure 10-2 (see Section 10.1).
Figure 9-11. ID and VD51 Waveforms
9.10 Overcurrent Protection (OCP)
9.10.1 OCP Operation
Overcurrent Protection (OCP) detects each drain peak
current level of a power MOSFET on pulse-by-pulse
basis, and limits the output power when the current level
reaches to OCP threshold voltage.
During Leading Edge Blanking Time, the OCP
threshold voltage becomes VOCP(LEB) = 1.69 V which is
higher than the normal OCP threshold voltage as shown
in Figure 9-12. Changing to this threshold voltage
prevents the IC from responding to the surge voltage in
turning-on the power MOSFET. This function operates
as protection at the condition such as output windings
shorted or unusual withstand voltage of secondary-side
rectifier diodes.
9.9 Step Drive Control
Figure 9-10 shows a flyback control circuit. The both
end of secondary rectification diode (D51) is generated
surge voltage when a power MOSFET turns on. Thus,
VRM of D51 should be set in consideration of the surge.
VD51
BR1
T1
VAC
tBW
D51
VOCP(LEB)
P1
S1
C1
C51
VOCP’
ID
5-8
D/ST
U1
S/OCP
1
Surge pulse voltage width at turning-on
Figure 9-12. S/OCP Pin Voltage
ROCP
Figure 9-10. Flyback Control Circuit
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When the power MOSFET turns on, the surge voltage
width of the S/OCP pin should be less than tBW, as
shown in Figure 9-12. In order to prevent surge voltage,
pay extra attention to ROCP trace layout (see Section
10.2). In addition, if a C (RC) damper snubber of Figure
9-13 is used, reduce the capacitor value of damper
snubber.
1.0
VOCP(H)
VOCP(L)
C（RC）
Damper snubber
T1
DDPC=36%
DMAX=75%
0.5
0
50
100
D51
C1
U1
C51
ON Duty (%)
5~8
Figure 9-14. Relationship between ON-duty and Drain
Current Limit after Compensation
D/ST
C（RC）
Damper snubber
S/OCP
1
ROCP
VOCP ' VOCP(L) DPCONTime
Figure 9-13. Damper Snubber
ONDuty
VOCP(L) DPC
(3)
fOSC (AVG )
9.10.2 OCP Input Compensation Function
where,
ICs with PWM control usually have some propagation
delay time. The steeper the slope of the actual drain
current at a high AC input voltage is, the larger the
detection voltage of actual drain peak current is,
compared to VOCP. Thus, the peak current has some
variation depending on AC input voltage in OCP state.
In order to reduce the variation of peak current in OCP
state, the IC has Input Compensation Function.
This function corrects OCP threshold voltage
depending on the AC input voltage, as shown in Figure
9-14.
When the AC input voltage is low (ON Duty is broad),
the OCP threshold voltage is controlled to become high.
The difference of peak drain current become small
compared with the case where the AC input voltage is
high (ON Duty is narrow).
VOCP(L): OCP Threshold Voltage at Zero ON Duty (V)
DPC: OCP Compensation Coefficient (mV/μs)
ONTime: On-time of power MOSFET (μs)
ONDuty: On duty of power MOSFET (%)
fOSC(AVG): Average PWM Switching Frequency (kHz)
9.10.3 Overload Protection (OLP)
Figure 9-15 shows the FB/OLP pin peripheral circuit,
and Figure 9-16 shows each waveform for Overload
Protection (OLP) operation.
When the peak drain current of ID is limited by
Overcurrent Protection operation, the output voltage,
VOUT, decreases and the feedback current from the
secondary photo-coupler becomes zero. Thus, the
feedback current, IFB, charges C5 connected to the
FB/OLP pin and FB/OLP pin voltage increases. When
the FB/OLP pin voltage increases to VFB(OLP) = 7.3 V or
more for the OLP delay time, tOLP = 75 ms or more, the
OLP is activated, the IC stops switching operation.
During OLP operation, the intermittent operation by
VCC pin voltage repeats and reduces the stress of parts
such as a power MOSFET and secondary side rectifier
diodes.
The compensation signal depends on ON Duty. The
relation between the ON Duty and the OCP threshold
voltage after compensation VOCP' is expressed as
Equation (3). When ON Duty is broader than 36 %, the
VOCP' becomes a constant value VOCP(H) = 0.888 V
When the OLP is activated, the IC stops switching
operation, and the VCC pin voltage decreases.
During OLP operation, the Bias Assist Function is
disabled. When the VCC pin voltage decreases to
VCC(OFF)SKP (about 9 V), the startup current flows, and
the VCC pin voltage increases. When the VCC pin
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voltage increases to VCC(ON), the IC starts operation, and
the circuit current increases. After that, the VCC pin
voltage decreases. When the VCC pin voltage decreases
to VCC(OFF) = 8.5 V, the control circuit stops operation.
Skipping the UVLO operation of VCC(OFF) (see Section
9.2), the intermittent operation makes the non-switching
interval longer and restricts the temperature rise of the
power MOSFET.
voltage VOUT(OVP) in OVP condition is calculated by
using Equation (4).
VOUT (NORMAL )
VOUT(OVP)
29.1 (V)
(4)
VCC(NORMAL )
where,
VOUT(NORMAL): Output voltage in normal operation
VCC(NORMAL): VCC pin voltage in normal operation
When the abnormal condition is removed, the IC
returns to normal operation automatically.
VCC pin voltage
VCC(OVP)
U1
VCC
2
GND
FB/OLP
4
VCC(ON)
VCC(OFF)
3
D2 R2
PC1
Drain current,
ID
C5
C4
D
Figure 9-17. OVP Operational Waveforms
Figure 9-15. FB/OLP Pin Peripheral Circuit
9.10.5 Thermal Shutdown (TSD)
Non-switching
interval
Non-switching
interval
VCC pin voltage
VCC(ON)
When the temperature of control circuit increases to
Tj(TSD) = 145 °C or more, Thermal Shutdown (TSD) is
activated.
Figure 9-18 shows the TSD operational waveforms.
TSD has the thermal hysteresis.
VCC(OFF)SKP
VCC(OFF)
tOLP
tOLP
tOLP
FB/OLP pin voltage
VFB(OLP)
Junction Temperature,
Tj
Tj(TSD)
Tj(TSD)−Tj(TSD)HYS
Drain current,
ID
Bias assist
ON
ON
function
OFF
OFF
Figure 9-16. OLP Operational Waveforms
VCC pin voltage
VCC(ON)
VCC(BIAS)
VCC(OFF)
9.10.4 Overvoltage Protection (OVP)
Drain current
ID
When a voltage between the VCC pin and the GND
pin increases to VCC(OVP) = 29.1 V or more, Overvoltage
Protection (OVP) is activated, and the IC stops
switching operation. During OVP operation, the Bias
Assist Function is disabled, the intermittent operation by
the UVLO is repeated (see Section 9.10.3). When the
fault condition is removed, the IC returns to normal
operation automatically (see Figure 9-17).
When VCC pin voltage is provided by using auxiliary
winding of transformer, the VCC pin voltage is
proportional to output voltage. Thus, the VCC pin can
detect the overvoltage conditions such as output voltage
detection circuit open. The approximate value of output
Figure 9-18. TSD Operational Waveforms
When TSD is activated, and the IC stops switching
operation. After that, VCC pin voltage decreases. When
the VCC pin voltage decreases to VCC(BIAS), the Bias
Assist Function is activated and the VCC pin voltage is
kept to over the VCC(OFF)
When the temperature reduces to less than
.
Tj(TSD)−Tj(TSD)HYS, the Bias Assist Function is disabled
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and the VCC pin voltage decreases to VCC(OFF). At that
time, the IC stops operation and reverts to the state
before startup. After that, the startup circuit is activated,
the VCC pin voltage increases to VCC(ON), and the IC
starts switching operation again.
In this way, the intermittent operation by the TSD and
the UVLO is repeated while there is an excess thermal
condition.
10.1.3 VCC Pin Peripheral Circuit
The value of C2 in Figure 10-1 is generally
recommended to be 10 µF to 47 μF (see Section 9.1,
because the startup time is determined by the value of
C2)
In actual power supply circuits, there are cases in
which the VCC pin voltage fluctuates in proportion to
the output current, IOUT (see Figure 10-2), and the
Overvoltage Protection (OVP) on the VCC pin may be
activated. This happens because C2 is charged to a peak
voltage on the auxiliary winding D, which is caused by
the transient surge voltage coupled from the primary
winding when the power MOSFET turns off. For
alleviating C2 peak charging, it is effective to add some
value R2, of several tenths of ohms to several ohms, in
series with D2 (see Figure 10-1). The optimal value of
R2 should be determined using a transformer matching
what will be used in the actual application, because the
variation of the auxiliary winding voltage is affected by
the transformer structural design.
When the fault condition is removed, the IC returns to
normal operation automatically.
10. Design Notes
10.1 External Components
Take care to use properly rated, including derating as
necessary and proper type of components.
CRD clamp snubber
BR1
T1
VAC
Without R2
VCC pin voltage
C5 R1
P
C1
D1
D2 R2
6
5
8
7
With R2
D/ST D/ST DN/SCT D/ST
U1
C4
D
C2
C（RC）
Damper snubber
STR3A400HDL
Output current, IOUT
S/OCP VCC
FB/OLP
GND
1
2
3
4
Figure 10-2. Variation of VCC Pin Voltage and Power
C3
ROCP
PC1
10.1.4 FB/OLP Pin Peripheral Circuit
Figure 10-1. The IC Peripheral Circuit
C3 (see Figure 10-1) is for high frequency noise
rejection and phase compensation, and should be
connected close to the FB/OLP pin and the GND pin.
The value of C3 is recommended to be about 2200 pF to
0.01 µF, and should be selected based on actual
operation in the application.
10.1.1 Input and Output Electrolytic
Capacitor
Apply proper derating to ripple current, voltage, and
temperature rise. Use of high ripple current and low
impedance types, designed for switch mode power
supplies, is recommended.
10.1.5 Snubber Circuit
In case the serge voltage of VDS is large, the circuit
should be added as follows (see Figure 10-1);
10.1.2 S/OCP Pin Peripheral Circuit
● A clamp snubber circuit of a capacitor-resistor- diode
(CRD) combination should be added on the primary
winding P.
● A damper snubber circuit of a capacitor (C) or a
resistor-capacitor (RC) combination should be added
between the D/ST pin and the S/OCP pin.
In case the damper snubber circuit is added, this
components should be connected near D/ST pin and
S/OCP pin.
In Figure 10-1, ROCP is the resistor for the current
detection. Since high frequency switching current flows
to ROCP, choose the resistor of low inductance and high
power dissipation capability.
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● The coupling of the winding P and the secondary
output winding S should be maximized to reduce the
leakage inductance.
● The coupling of the winding D and the winding S
should be maximized.
10.1.6 Peripheral Circuit of
Secondary-side Shunt Regulator
Figure 10-3 shows the secondary-side detection
circuit with the standard shunt regulator IC (U51).
C52 and R53 are for phase compensation. The value
of C52 and R53 are recommended to be around 0.047 μF
to 0.47 μF and 4.7 kΩ to 470 kΩ, respectively. They
should be selected based on actual operation in the
application.
● The coupling of the winding D and the winding P
should be minimized.
In the case of multi-output power supply, the coupling
of the secondary-side stabilized output winding, S1, and
the others (S2, S3…) should be maximized to improve
the line-regulation of those outputs
Figure 10-4 shows the winding structural examples of
two outputs.
L51
T1
VOUT
(+)
D51
R54
R51
● Winding structural example (a):
S1 is sandwiched between P1 and P2 to maximize the
coupling of them for surge reduction of P1 and P2. D
is placed far from P1 and P2 to minimize the coupling
to the primary for the surge reduction of D.
PC1
R52
R55
C51
S
C53
● Winding structural example (b)
C52 R53
P1 and P2 are placed close to S1 to maximize the
coupling of S1 for surge reduction of P1 and P2.。
D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2. This
structure reduces the surge of D, and improves the
line-regulation of outputs.
U51
R56
(-)
Figure 10-3. Peripheral Circuit of Secondary-side
Shunt Regulator (U51)
Margin tape
10.1.7 Transformer
Apply proper design margin to core temperature rise
by core loss and copper loss.
P1 S1 P2 S2 D
Because the switching currents contain high frequency
currents, the skin effect may become a consideration.
Choose a suitable wire gauge in consideration of the
RMS current and a current density of 4 to 6 A/mm2.
If measures to further reduce temperature are still
necessary, the following should be considered to
increase the total surface area of the wiring:
Margin tape
Winding structural example (a)
Margin tape
● Increase the number of wires in parallel.
● Use litz wires.
● Thicken the wire gauge.
P1 S1 D S2 S1 P2
Margin tape
In the following cases, the surge of VCC pin voltage
becomes high.
Winding structural example (b)
● The surge voltage of primary main winding, P, is high
(low output voltage and high output current power
supply designs)
Figure 10-4. Winding Structural Examples
● The winding structure of auxiliary winding, D, is
susceptible to the noise of winding P.
When the surge voltage of winding D is high, the
VCC pin voltage increases and the Overvoltage
Protection (OVP) may be activated. In transformer
design, the following should be considered;
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(4) ROCP Trace Layout
10.2 PCB Trace Layout and Component
Placement
ROCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should
be at a single point ground (point A in Figure 10-5)
Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should
be low impedance with small loop and wide trace. In
addition, the ground traces affect radiated EMI noise,
and wide, short traces should be taken into account.
Figure 10-5 shows the circuit design example.
which is close to the base of ROCP
.
(5) FB/OLP Trace Layout
The components connected to FB/OLP pin should be
as close to FB/OLP pin as possible. The trace
between the components and FB/OLP pin should be
as short as possible.
(1) Main Circuit Trace Layout
This is the main trace containing switching currents,
and thus it should be as wide trace and small loop as
possible.
If C1 and the IC are distant from each other, placing
a capacitor such as film capacitor (about 0.1 μF and
with proper voltage rating) close to the transformer
or the IC is recommended to reduce impedance of
the high frequency current loop.
(6) Secondary Rectifier Smoothing Circuit Trace
Layout:
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(2) Control Ground Trace Layout
Since the operation of the IC may be affected from
the large current of the main trace that flows in
control ground trace, the control ground trace should
be separated from main trace and connected at a
single point grounding of point A in Figure 10-5 as
close to the ROCP pin as possible.
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of RDS(ON), consider it in thermal design.
Since the copper area under the IC and the D/ST pin
trace act as a heatsink, its traces should be as wide as
possible.
(3) VCC Trace Layout:
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C2 and
the IC are distant from each other, placing a
capacitor such as film capacitor Cf (about 0.1 μF to
1.0 μF) close to the VCC pin and the GND pin is
recommended.
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(1)Main trace should be wide
trace and small loop
(6)Main trace of secondary side should
be wide trace and small loop
D51
T1
R1
C5
C1
P
C51
(7)Trace of D/ST pin should be
wide for heat release
D1
S
5
8
7
6
D2
R2
D/ST D/ST DN/CST D/ST
C4
U1
STR3A400HDL
C2
D
S/OCP VCC
FB/OLP
4
GND
3
1
2
(3) Loop of the power
supply should be small
ROCP
PC1
(5)The components connected to
FB/OLP pin should be as close
to FB/OLP pin as possible
C3
A
CY
(4)ROCP Should be as close to S/OCP pin as
possible.
(2) Control GND trace should be connected at a
single point as close to the ROCP as possible
Figure 10-5. Peripheral Circuit Example Around the IC
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11. Pattern Layout Example
The following show the two outputs PCB pattern layout example and the schematic of circuit using STR3A400HDL
series. The PCB pattern layout example is made usable to other ICs in common. The parts in Figure 11-2 are only used.
Figure 11-1. PCB Circuit Trace Layout Example
F1
1
L1
L51
CN51
VOUT1
C10
C11
D1
D4
D2
D3
TH1
T1
D51
C2
C1
R5
R54
R55
R51
C4
R1
C56 R62
3
C3
J1
P1
R52
C53
R4
D5
PC1
C51
R57
S1
JW52
R53
U51
C52
R56
6
5
8
7
GND
D/ST D/ST D/ST D/ST
JW51
R60
R59
U1
C8
JW53
STR3A400HDL
L52
R58
D52
D6
R2
GND
S/OCP VCC
FB/OLP
OUT2
GND
1
2
3
4
D
C5
C57 R63
C54
C55
R61
C7
R3
C6
PC1
CN52
C9
Figure 11-2. Circuit Schematic for PCB Circuit Trace Layout
STR3A400HDL-DSE Rev.1.0
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© SANKEN ELECTRIC CO.,LTD. 2016
STR3A400HDL Series
12. Reference Design of Power Supply
As an example, the following show the power supply specification, the circuit schematic, the bill of materials, and the
transformer specification.
● Power Supply Specification
STR3A463HDL
IC
85VAC to 265VAC
34.8 W (40.4 W peak)
8 V / 0.5 A
Input voltage
Maximum output power
Output 1
14 V / 2.2 A (2.6 A peak)
Output 2
● Circuit Schematic
See Figure 11-2
● Bill of Materials
Recommended
Sanken Parts
Recommended
Sanken Parts
Symbol
Part type
Ratings(1)
Symbol
L51
Part type
Ratings(1)
Short
F1
Fuse
250 VAC , 3 A
10 mH
Inductor
Inductor
Schottky
Schottky
Electrolytic
Ceramic
(2)
(2)
L1
CM inductor
L52
D51
D52
C51
C52
C53
C54
C55
C56
C57
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
JW51
JW52
Short
TH1
D1
D2
D3
D4
D5
D6
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
R1
R2
R3
R4
R5
PC1
U1
NTC thermistor Short
60 V, 1.5 A
100V, 10A
680 μF, 25 V
0.1 μF, 50 V
680 μF, 25 V
470 μF, 16 V
Open
EK16
General
600 V, 1 A
EM01A
EM01A
EM01A
EM01A
SARS01
SJPL-D2
FMEN-210A
(2)
(2)
(2)
General
600 V, 1 A
600 V, 1 A
600 V, 1 A
800 V, 1.2 A
200 V, 1 A
0.1 μF, 275 V
Open
General
General
Electrolytic
Electrolytic
Electrolytic
Ceramic
General
(2)
(2)
(2)
Fast recovery
Film, X2
Electrolytic
Electrolytic
Ceramic
(2)
(2)
Open
Ceramic
Open
150 μF, 400 V
1000 pF, 2 kV
22 μF, 50 V
0.01 μF
General
Open
General
1.5 kΩ
(2)
Electrolytic
Ceramic
General
100 kΩ
(2)
(2)
(2)
General, 1% Open
General, 1% Open
General, 1% 10 kΩ
Ceramic
Open
Ceramic
15 pF, 2 kV
2200 pF, 250 V
Open
Ceramic, Y1
Ceramic
General
General
General
Open
1 kΩ
(2)
(2)
(3)
(2)
(2)
(2)
(3)
(2)
Ceramic
Open
6.8 kΩ
Metal oxide
General
330 kΩ, 1 W
10 Ω
General, 1% 39 kΩ
General
General
General
Open
Open
Open
Short
Short
Short
(2)
(2)
General
0.56 Ω, 1 W
47 Ω, 1 W
Open
General
Metal oxide
Photo-coupler
IC
PC123 or equiv
－
STR3A463HDL JW53
Shunt
regulator
See
VREF = 2.5 V
TL431 or equiv
TL431or
equiv
T1
Transformer
U51
the specification
(1) Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
(2) It is necessary to be adjusted based on actual operation in the application.
(3) Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or
use combinations of resistors in series to reduce applied voltage to each of them, according to the requirement of the application.
STR3A400HDL-DSE Rev.1.0
Jul. 07, 2017
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http://www.sanken-ele.co.jp/en/
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© SANKEN ELECTRIC CO.,LTD. 2016
STR3A400HDL Series
● Transformer Specification
Primary inductance, LP: 460 μH
Core size: EER-28S
Al-value: 373 nH/N2 (Center gap of about 0.25 mm)
Winding specification
Number of
turns (T)
Wire diameter
(mm)
Winding
Primary winding
Primary winding
Symbol
P1
Construction
Single-layer, solenoid
winding
Single-layer, solenoid
winding
18
φ 0.30
φ 0.30
P2
18
Auxiliary winding
Output 1 winding
Output 1 winding
Output 2 winding
Output 2 winding
D
6
3
3
2
2
φ 0.20
Space winding
S1-1
S1-2
S2-1
S2-2
φ 0.4 × 2
φ 0.4 × 2
φ 0.4 × 2
φ 0.4 × 2
Solenoid winding
Solenoid winding
Solenoid winding
Solenoid winding
4mm
2mm
VDC
14V
P2
P1
P1
S2-1
S1-1
S2-2
S1-2
S2-2 S1-2
D
S1-1
S2-1
P2
Drain
VCC
8V
D
Bobbin
GND
Core
GND
Cross-section view
●: Start at this pin
STR3A400HDL-DSE Rev.1.0
Jul. 07, 2017
SANKEN ELECTRIC CO.,LTD.
http://www.sanken-ele.co.jp/en/
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© SANKEN ELECTRIC CO.,LTD. 2016
STR3A400HDL Series
Important Notes
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DSGN-CEZ-16003
STR3A400HDL-DSE Rev.1.0
Jul. 07, 2017
SANKEN ELECTRIC CO.,LTD.
http://www.sanken-ele.co.jp/en/
24
© SANKEN ELECTRIC CO.,LTD. 2016
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