STR6A169HVD [SANKEN]
Off-Line PWM Controllers with Integrated Power MOSFET;
| 型号： | STR6A169HVD |
| 厂家： | 
SANKEN ELECTRIC |
| 描述： | Off-Line PWM Controllers with Integrated Power MOSFET 开关 |
| 文件： | 总26页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Off-Line PWM Controllers with Integrated Power MOSFET
STR6A100MV/HVD Series
Data Sheet
Description
Package
The STR6A100MV/HVD series are power ICs for
switching power supplies, incorporating a MOSFET and
a current mode PWM controller IC.
DIP8
The operating mode of the IC automatically changes
to green-mode or burst oscillation mode according to
load in order to improve the all load efficiency. The
product achieves high cost-performance power supply
systems with few external components.
Not to Scale
STR6S100xV Series
Features
● Part Number
● Improving Circuit Efficiency
(Since the step drive control can keep VRM of
secondary rectification diodes low, the circuit
efficiency can be improved by low VF)
● Current Mode Type PWM Control
● Soft Start Function
● Adjustable Standby Operating Point
No Load Power Consumption < 15 mW
● Operation Mode
STR6A1××HVD
(1) (2)
(1) Frequency
M is 65 kHz.
H is 100 kHz.
(2) OVP and TSD operation
D is auto-restart.
None is latch shutdown.
Electrical Characteristics
MOSFET
Fixed Frequency: 65 kHz / 100 kHz
Green-Mode: 25 kHz to 65 kHz / 25 kHz to 100 kHz
Burst Oscillation Mode
Part Number
VDSS(min.)
RDS(ON)(max.)
fOSC(AVG) = 65 kHz
STR6A153MV
● Random Switching Function
650 V
1.9 Ω
● Slope Compensation Function
● Leading Edge Blanking Function
● Bias Assist Function
fOSC(AVG) = 100 kHz
STR6A163HVD
STR6A161HVD
STR6A169HVD
700 V
700 V
700 V
2.3 Ω
3.95 Ω
6.0 Ω
● Protections
● Two Types of Overcurrent Protection (OCP): Pulse-
by-Pulse, built-in compensation circuit to minimize
OCP point variation on AC input voltage
Overload Protection with Timer (OLP): Auto-restart
Overvoltage Protection (OVP): Latched shutdown or
auto-restart
Thermal Shutdown (TSD): Latched shutdown or auto-
restart*
*With hysteresis
● Output Power, POUT
*
Adapter
Open Frame
AC85
Part Number
AC85
~265V
AC230V
AC230V
~265V
fOSC(AVG) = 65 kHz
STR6A153MV
26 W
21 W
40 W
28 W
fOSC(AVG) = 100 kHz
STR6A163HVD
25 W
20 W
15 W
11 W
40 W
35 W
30 W
28 W
23.5 W
19.5 W
Typical Application
STR6A161HVD 20.5 W
STR6A169HVD 17 W
BR1
D51
VAC
T1
P
* The output power is actual continues power that is
measured at 50 °C ambient. The peak output power can
be 120 to 140 % of the value stated here. Core size, ON
Duty, and thermal design affect the output power. It may
be less than the value stated here.
C1
U1
ROCP
C51
1
8
7
S/OCP
BA
D/ST
D/ST
S
C4
2
3
4
RBA
GND
C3
D2
5
VCC
FB/OLP
Application
STR6A100×V
D
C2
● White Goods
PC1
● Office Automation Equipment
● Audio Visual Equipment
● Industrial Equipment
CY
TC_STR6A100xV_1_R2
● Other Switched-Mode Power Supply
STR6A100MV/HVD-DSJ Rev.2.0
Jul. 14, 2017
SANKEN ELECTRIC CO.,LTD.
http://www.sanken-ele.co.jp/en/
1
© SANKEN ELECTRIC CO.,LTD. 2014
STR6A100MV/HVD Series
Contents
Description--------------------------------------------------------------------------------------------------------------- 1
Contents------------------------------------------------------------------------------------------------------------------ 2
1. Absolute Maximum Ratings ------------------------------------------------------------------------------------ 3
2. Electrical Characteristics---------------------------------------------------------------------------------------- 4
3. Performance Curves---------------------------------------------------------------------------------------------- 6
3.1. Derating Curves--------------------------------------------------------------------------------------------- 6
3.2. MOSFET Safe Operating Area Curves---------------------------------------------------------------- 7
3.3. Transient Thermal Resistance Curves ----------------------------------------------------------------- 8
4. Block Diagram ----------------------------------------------------------------------------------------------------10
5. Pin Configuration Definitions ---------------------------------------------------------------------------------10
6. Typical Application----------------------------------------------------------------------------------------------11
7. Physical Dimensions ---------------------------------------------------------------------------------------------11
8. Marking Diagram------------------------------------------------------------------------------------------------12
9. Operational Description ----------------------------------------------------------------------------------------13
9.1. Startup Operation -----------------------------------------------------------------------------------------13
9.2. Undervoltage Lockout (UVLO)-------------------------------------------------------------------------13
9.3. Bias Assist Function---------------------------------------------------------------------------------------13
9.4. Soft Start Function ----------------------------------------------------------------------------------------14
9.5. Constant Output Voltage Control----------------------------------------------------------------------14
9.6. Leading Edge Blanking Function ----------------------------------------------------------------------15
9.7. Random Switching Function ----------------------------------------------------------------------------15
9.8. Step Drive Control-----------------------------------------------------------------------------------------15
9.9. Operation Mode--------------------------------------------------------------------------------------------16
9.10. Overcurrent Protection (OCP) -------------------------------------------------------------------------17
9.10.1. OCP Operation --------------------------------------------------------------------------------------17
9.10.2. OCP Input Compensation Function ------------------------------------------------------------17
9.11. Overload Protection (OLP)------------------------------------------------------------------------------18
9.12. Overvoltage Protection (OVP)--------------------------------------------------------------------------18
9.12.1. Latched Shutdown Type: STR6A153MV------------------------------------------------------19
9.12.2. Auto-restart Type: STR6A16xHVD ------------------------------------------------------------19
9.13. Thermal Shutdown (TSD) -------------------------------------------------------------------------------19
9.13.1. Latched Shutdown Type: STR6A153MV------------------------------------------------------19
9.13.2. Auto-restart Type: STR6A16xHVD ------------------------------------------------------------19
10. Design Notes-------------------------------------------------------------------------------------------------------20
10.1. External Components-------------------------------------------------------------------------------------20
10.1.1. Input and Output Electrolytic Capacitor ------------------------------------------------------20
10.1.2. S/OCP Pin Peripheral Circuit --------------------------------------------------------------------20
10.1.3. BA Pin Peripheral Circuit-------------------------------------------------------------------------20
10.1.4. FB/OLP Pin Peripheral Circuit ------------------------------------------------------------------20
10.1.5. VCC Pin Peripheral Circuit ----------------------------------------------------------------------20
10.1.6. Snubber Circuit--------------------------------------------------------------------------------------20
10.1.7. Phase Compensation--------------------------------------------------------------------------------21
10.1.8. Transformer ------------------------------------------------------------------------------------------21
10.2. PCB Trace Layout and Component Placement-----------------------------------------------------22
11. Pattern Layout Example----------------------------------------------------------------------------------------23
12. Reference Design of Power Supply---------------------------------------------------------------------------24
12.1. Circuit Specifications -------------------------------------------------------------------------------------24
12.2. Circuit Schematic------------------------------------------------------------------------------------------24
12.3. Transformer Specification-------------------------------------------------------------------------------24
12.4. Bill of Materials --------------------------------------------------------------------------------------------25
Important Notes -------------------------------------------------------------------------------------------------------26
STR6A100MV/HVD-DSJ Rev.2.0
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© SANKEN ELECTRIC CO.,LTD. 2014
STR6A100MV/HVD Series
1. Absolute Maximum Ratings
Current polarities are defined as follows: a current flow going into the IC (sinking) is positive current (+); and a
current flow coming out of the IC (sourcing) is negative current (−).
Unless otherwise specified, TA = 25 °C, 7 pin = 8 pin.
Parameter
Symbol
Conditions
Pins
Rating
4.0
Unit
A
Remarks
STR6A153MV
STR6A163HVD
Drain Peak Current (1)
IDPEAK
8 − 1
Single pulse
STR6A161HVD
STR6A169HVD
2.5
1.8
STR6A153MV
STR6A163HVD
4.0
Maximum Drain Current
Avalanche Energy(2)(3)
IDMAX
8 − 1
8 – 1
A
STR6A161HVD
STR6A169HVD
STR6A153MV
STR6A163HVD
STR6A161HVD
STR6A169HVD
2.5
1.8
ILPEAK = 2.2 A
ILPEAK = 2.15 A
ILPEAK = 1.78 A
ILPEAK = 1.8 A
57
53
EAS
mJ
36
24
S/OCP Pin Voltage
VS/OCP
VBA
IBA
1 − 3
2 − 3
2 − 3
4 − 3
4 − 3
5 − 3
8 − 3
8 − 1
5 − 3
—
−2 to 6
−0.3 to 7.5
1.0
V
V
BA Pin Voltage
BA Pin Sink Current
mA
V
FB/OLP Pin Voltage
FB/OLP Pin Sink Current
VCC Pin Voltage
VFB
IFB
−0.3 to 14
1.0
mA
V
VCC
VD/ST
PD1
−0.3 to 32
−1 to VDSS
1.35
D/ST Pin Voltage
V
MOSFET Power Dissipation(4)
Control Part Power Dissipation
Operating Ambient Temperature
Storage Temperature
Junction Temperature
W
W
°C
°C
°C
(5)
PD2
1.2
TOP
Tstg
Tj
−40 to 125
−40 to 125
150
—
—
(1) See Section 3.2, MOSFET Safe Operating Area Curves.
(2) See Figure 3-2. Avalanche Energy Derating Coefficient Curve
(3) Single pulse, VDD = 99 V, L = 20 mH.
(4) See Section Figure 3-3 TA-PD1Curve.
(5) When embedding this hybrid IC onto the printed circuit board (copper area in a 15 mm × 15 mm).
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
2. Electrical Characteristics
Current polarities are defined as follows: a current flow going into the IC (sinking) is positive current (+); and a
current flow coming out of the IC (sourcing) is negative current (−).
Unless otherwise specified, TA = 25 °C, VCC = 18 V, 7 pin = 8 pin.
Parameter
Symbol
Conditions
Pins
Min.
Typ.
Max.
Unit
Remarks
Power Supply Startup Operation
Operation Start Voltage
Operation Stop Voltage*
Circuit Current in Operation
VCC(ON)
VCC(OFF)
ICC(ON)
VST(ON)
ICC(ST)
5 − 3
5 − 3
5 − 3
13.8
7.6
—
15.0
8.5
16.2
9.2
V
V
VCC = 12 V
1.5
3.0
mA
Startup Circuit Operation
Voltage
8 – 3
40
47
55
V
mA
V
VCC = 13.5 V
Startup Current
5 − 3 −4.05 −2.50 −1.08
Startup Current Biasing
Threshold Voltage*
ICC = −500 µA
VCC(BIAS)
5 − 3
8.0
9.6
10.5
Normal Operation
STR6A153MV
STR6A16xHVD
STR6A153MV
STR6A16xHVD
58
90
—
—
65
100
5.4
72
110
—
Average Switching
Frequency
fOSC(AVG)
8 – 3
8 − 3
kHz
kHz
Switching Frequency
Modulation Deviation
Δf
8.4
—
VCC = 12 V
Maximum Feedback Current IFB(MAX)
4 − 3 −170
−130
− 13
−85
− 5
µA
µA
Minimum Feedback Current
IFB(MIN)
4 − 3
−21
Light Load Operation
FB/OLP Pin Starting
Voltage of Frequency
Decreasing
STR6A153MV
STR6A16xHVD
STR6A153MV
STR6A16xHVD
2.64
2.88
2.40
2.48
3.30
3.60
3.00
3.10
3.96
4.32
3.60
3.72
fOSC(AVG)
× 0.9
VFB(FDS)
1 − 8
V
FB/OLP Pin Ending Voltage
of Frequency Decreasing
fOSC(MIN)
× 1.1
VFB(FDE)
fOSC(MIN)
1 − 8
V
Minimum Switching
Frequency
5 − 8
18
25
32
kHz
Standby Operation
STR6A153MV
STR6A16xHVD
STR6A153MV
STR6A16xHVD
STR6A153MV
STR6A16xHVD
STR6A153MV
STR6A16xHVD
1.17
1.24
1.50
1.65
1.78
2.01
2.02
2.29
1.28
1.35
1.63
1.79
1.92
2.16
2.17
2.45
1.39
1.46
1.76
1.93
2.06
2.31
2.32
2.61
FB/OLP Pin Oscillation
Stop Threshold Voltage 1
RBA: Short
RBA: Open
RBA: 330 kΩ
RBA: 68 kΩ
VFB(OFF1)
VFB(OFF2)
VFB(OFF3)
VFB(OFF4)
4 − 3
4 − 3
4 − 3
4 − 3
V
V
V
V
FB/OLP Pin Oscillation
Stop Threshold Voltage 2
FB/OLP Pin Oscillation
Stop Threshold Voltage 3
FB/OLP Pin Oscillation
Stop Threshold Voltage 4
* VCC(BIAS) > VCC(OFF) always.
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
Parameter
Protection
Symbol
Conditions
Pins
Min.
Typ.
Max.
Unit
Remarks
Maximum ON Duty
DMAX
tBW
8 − 3
70
75
80
%
ns
Leading Edge Blanking
Time
—
—
330
—
STR6A153MV
STR6A16xHVD
—
—
17.3
25.8
—
—
OCP Compensation
Coefficient
DPC
—
—
mV/μs
OCP Compensation ON
Duty
OCP Threshold Voltage at
Zero ON Duty
OCP Threshold Voltage at
36% ON Duty
DDPC
—
36
—
%
V
V
VOCP(L)
VOCP(H)
1 − 3 0.735 0.795 0.855
1 − 3 0.843 0.888 0.933
OCP Threshold Voltage in
Leading Edge Blanking
Time
VOCP(LEB)
1 − 3
—
1.69
—
V
OLP Threshold Voltage
OLP Delay Time
VFB(OLP)
tOLP
4 − 3
4 − 3
5 − 3
4 − 3
5 − 3
6.8
55
7.3
75
7.8
90
V
ms
µA
V
OLP Operation Current
ICC(OLP)
—
260
11.8
29.1
—
FB/OLP Pin Clamp Voltage VFB(CLAMP)
10.5
27.0
13.5
31.2
OVP Threshold Voltage
VCC(OVP)
Tj(TSD)
V
Thermal Shutdown
Operating Temperature
Thermal Shutdown
Temperature Hysteresis
—
—
127
145
80
—
—
°C
°C
STR6A16xHVD
Tj(TSD)HYS
—
MOSFET
STR6A153MV
STR6A16xHVD
650
700
—
—
—
—
—
—
—
—
—
—
—
Drain-to-Source Breakdown
Voltage
IDS = 300 µA
VDS = VDSS
VDSS
IDSS
8 − 1
8 − 1
V
Drain Leakage Current
300
1.9
2.3
3.95
6.0
250
µA
STR6A153MV
STR6A163HVD
STR6A161HVD
STR6A169HVD
—
—
IDS = 0.4 A
On-Resistance
RDS(ON)
8 − 1
Ω
—
—
Switching Time
tf
8 − 1
—
ns
Thermal Resistance
Junction to Case
θj-C
—
—
—
22
°C/W
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
3. Performance Curves
3.1. Derating Curves
100
80
60
40
20
0
100
80
60
40
20
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Junction Temperature, TJ (°C)
Ambient Temperature, TA (°C )
Figure 3-1. SOA Temperature Derating Coefficient
Curve
Figure 3-2. Avalanche Energy Derating Coefficient
Curve
1.6
PD1=1.35W
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
Ambient Temperature, TA (°C )
Figure 3-3. Ambient Temperature versus Power
Dissipation Curve
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
3.2. MOSFET Safe Operating Area Curves
When the IC is used, the safe operating area curve should be multiplied by the temperature derating coefficient
derived from Figure 3-1.
The broken line in the safe operating area curve is the drain current curve limited by on-resistance.
Unless otherwise specified, TA = 25 °C and single pulse input.
10
1
10
1
0.1ms
0.1ms
1ms
1ms
0.1
0.01
0.1
0.01
1
10
100
1000
1
10
100
1000
Drain to Source Voltage (V)
Drain to Source Voltage (V)
Figure 3-4. STR6A153MV SOA Curve
Figure 3-5. STR6A163HVD SOA Curve
10
10
1
1
0.1
0.1
0.01
0.01
1
10
100
1000
1
10
100
1000
Drain-to-Source Voltage (V)
Drain-to-Source Voltage (V)
Figure 3-6. STR6A161HVD SOA Curve
Figure 3-7. STR6A169HVD SOA Curve
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
3.3. Transient Thermal Resistance Curves
100
10
1
0.1
0.01
1µ
10µ
100µ
1m
10m
100m
1s
Time (s)
Figure 3-8. STR6A153MV and STR6A163HVD Transient Thermal Resistance Curve
100
10
1
0.1
0.01
1µ
10µ
100µ
1m
10m
100m
1s
Time (s)
Figure 3-9. STR6A161HVD Transient Thermal Resistance Curve
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
100
10
1
0.1
0.01
1µ
10µ
100µ
1m
10m
100m
1s
Time (s)
Figure 3-10. STR6A169HVD Transient Thermal Resistance Curve
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
4. Block Diagram
VCC
5
D/ST
7, 8
Startup
UVLO
Reg.
VREG
OVP
TSD
BA
2
Auto Standby
Adjustment
Driver
PWM OSC
S
Q
R
OCP
VREG VCC
Drain Peak Current
Compensation
OLP
S/OCP
1
Feedback
Control
FB/OLP
4
LEB
GND
3
Slope
Compensation
BD_STR6A100xV_R1
5. Pin Configuration Definitions
Pin
1
Name
Descriptions
MOSFET source and Overcurrent Protection
(OCP) signal input
S/OCP
D/ST
D/ST
1
2
3
4
S/OCP
8
7
6
2
3
BA
Input of selectable standby operation point signal
Ground
BA
GND
GND
Constant voltage control signal input and
Overload Protection (OLP) signal input
Power supply voltage input for control part and
Overvoltage Protection (OVP) signal input
4
5
FB/OLP
FB/OLP
VCC
5
VCC
6
7
8
−
(Pin removed)
D/ST
MOSFET drain and startup current input
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
6. Typical Application
The PCB traces for D/ST pins should be as wide as possible, in order to improve thermal release capability.
In applications having a power supply specified such that D/ST pin has large transient surge voltages, a clamp
snubber circuit of a capacitor-resistor-diode (CRD) combination should be added on the primary winding P, or a
damper snubber circuit of a capacitor (C) or a resistor-capacitor (RC) combination should be added between the D/ST
pin and the S/OCP pin.
CRD clamp snubber
C（RC）
damper snubber
L51
BR1
C1
D51
VOUT
(+)
T1
VAC
R54
R51
R1
C6
PC1
R52
C5
P
R55
C51
D1
S
C53
U1
ROCP
1
8
7
S/OCP
D/ST
D/ST
C52 R53
RBA
2
3
4
R2
D2
C2
BA
U51
R56
C4
(-)
GND
D
5
VCC
FB/OLP
C3
PC1
STR6A100×V
CY
TC_STR6A100xV_2_R1
Figure 6-1. Typical Application
7. Physical Dimensions
● DIP8
NOTES
● Dimensions in millimeters
● Pb-free (RoHS compliant)
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
8. Marking Diagram
STR6A153MV
8
6 A 1 5 3 M
Part Number
S K Y M D V
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N or D)
D is a period of days,
1
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10-11 days of the month (21st to 31st)
Control Number
STR6A163HVD
8
6 A 1 6 x H
Part Number (6A161HVD, 6A163HVD, 6A169HVD)
S K Y M D V D
Lot Number:
Y is the last digit of the year of manufacture (0 to 9)
M is the month of the year (1 to 9, O, N or D)
D is a period of days,
1
1: the first 10 days of the month (1st to 10th)
2: the second 10 days of the month (11th to 20th)
3: the last 10-11 days of the month (21st to 31st)
Control Number
STR6A100MV/HVD-DSJ Rev.2.0
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STR6A100MV/HVD Series
VCC pin
voltage
VCC(ON)
9. Operational Description
All of the parameter values used in these descriptions
are typical values, unless they are specified as minimum
or maximum. Current polarities are defined as follows: a
current flow going into the IC (sinking) is positive
current (+); and a current flow coming out of the IC
(sourcing) is negative current (−).
tSTART
Drain current,
ID
9.1. Startup Operation
Figure 9-2. Startup Operation
Figure 9-1 shows the circuit around IC.
The IC incorporates the startup circuit. The circuit is
connected to D/ST pin. When D/ST pin voltage reaches
to Startup Circuit Operation Voltage VST(ON) = 47 V, the
startup circuit starts operation.
During the startup process, the constant current,
ICC(ST) = −2.50 mA, charges C2 at VCC pin. When VCC
pin voltage increases to VCC(ON) = 15.0 V, the control
circuit starts operation. During the IC operation, the
voltage rectified the auxiliary winding voltage, VD, of
Figure 9-1 becomes a power source to the VCC pin.
After switching operation begins, the startup circuit turns
off automatically so that its current consumption
becomes zero.
9.2. Undervoltage Lockout (UVLO)
Figure 9-3 shows the relationship of VCC pin voltage
and circuit current ICC. When VCC pin voltage decreases
to VCC(OFF) = 8.5 V, the control circuit stops operation by
Undervoltage Lockout (UVLO) circuit, and reverts to the
state before startup.
Circuit Current, ICC
Stop
Start
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ꢀꢀ ꢌꢍꢎ
(1)
⇒ ꢑꢒꢊꢓꢔꢁ ꢆ ꢋ ꢋ ꢕꢖꢊꢒꢔꢁ ꢆ
ꢀꢀ
VCC Pin
Voltage
VCC(OFF)
VCC(ON)
The startup time of IC is determined by C2 capacitor
value. The approximate startup time tSTART (shown in
Figure 9-2) is calculated as follows:
Figure 9-3. Relationship between
VCC Pin Voltage and ICC
ꢆ ꢞ
ꢁ
ꢀꢀ ꢃꢝꢘ
ꢁ
ꢆ
ꢀꢀ ꢌꢝ
ꢗꢅꢘꢄꢙꢘ ꢚ ꢛꢕ ꢜ
ꢟꢠꢀꢀꢁꢅꢘꢆ
ꢟ
(2)
9.3. Bias Assist Function
where,
By the Bias Assist Function, the startup failure is
prevented. The Bias Assist Function is activated, in both
of following condition:
tSTART is startup time of IC (s), and
VCC(INT) is initial voltage on VCC pin (V).
the FB pin voltage is FB/OLP Pin Oscillation Stop
Threshold Voltage, VFB(OFF) or less
and the VCC voltage decreases to the Startup Current
Biasing Threshold Voltage, VCC(BIAS) = 9.6 V.
When the Bias Assist Function is activated, the VCC
pin voltage is kept almost constant voltage, VCC(BIAS) by
providing the startup current, ICC(ST), from the startup
circuit. Thus, the VCC pin voltage is kept more than
BR1
T1
VAC
U1
C1
P
7, 8
D/ST
D2 R2
5
3
VCC
VCC(OFF)
.
Since the startup failure is prevented by the Bias Assist
Function, the value of C2 connected to VCC pin can be
small. Thus, the startup time and the response time of the
OVP become shorter.
D
C2
VD
GND
Figure 9-1. VCC pin Peripheral Circuit
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The operation of the Bias Assist Function in startup is
as follows. It is necessary to check and adjust the startup
process based on actual operation in the application, so
that poor starting conditions may be avoided.
Figure 9-4 shows VCC pin voltage behavior during the
startup period.
In case tLIM is longer than the OLP Delay Time, tOLP,
the output power is limited by the Overload Protection
(OLP).
Thus, it is necessary to adjust the value of output
capacitor and the turn ratio of auxiliary winding D so that
the tLIM is less than tOLP = 55 ms (min.).
After VCC pin voltage increases to VCC(ON) = 15.0 V at
startup, the IC starts the operation. Then circuit current
increases and VCC pin voltage decreases. At the same
time, the auxiliary winding voltage VD increases in
proportion to output voltage. These are all balanced to
produce VCC pin voltage.
When VCC pin voltage is decrease to VCC(OFF) = 8.5 V
in startup operation, the IC stops switching operation and
a startup failure occurs.
Startup of IC Startup of SMPS
VCC pin
voltage
Normal opertion
tSTART
VCC(ON)
VCC(OFF)
Time
Soft start period
When the output load is light at startup, the output
voltage may become more than the target voltage due to
the delay of feedback circuit. In this case, the FB pin
voltage is decreased by the feedback control. When the
FB pin voltage decreases to VFB(OFF) or less, the IC stops
switching operation and VCC pin voltage decreases.
When VCC pin voltage decreases to VCC(BIAS), the Bias
Assist Function is activated and the startup failure is
prevented.
approximately 8.75 ms (fixed)
D/ST pin
current, ID
Limited by OCP operation
tLIM < tOLP (min.)
Time
Figure 9-5. VCC and ID Waveforms during Startup
VCC Pin
Voltage
Startup success
Target operating
IC starts operation
9.5. Constant Output Voltage Control
voltage
Increase with rising of
output voltage
VCC(ON)
VCC(BIAS)
The IC achieves the constant voltage control of the
power supply output by using the current-mode control
method, which enhances the response speed and provides
the stable operation.
Bias assist period
VCC(OFF)
The FB/OLP pin voltage is internally added the slope
compensation at the feedback control (see Section
0.Block Diagram), and the target voltage, VSC, is
generated. The IC compares the voltage, VROCP, of a
current detection resistor with the target voltage, VSC, by
the internal FB comparator, and controls the peak value
of VROCP so that it gets close to VSC, as shown in Figure
9-6 and Figure 9-7.
Startup failure
Time
Figure 9-4. VCC pin Voltage during Startup Period
9.4. Soft Start Function
Light Load Conditions
Figure 9-5 shows the behavior of VCC pin voltage and
drain current during the startup period.
When load conditions become lighter, the output
voltage, VOUT, increases. Thus, the feedback current
from the error amplifier on the secondary-side also
increases. The feedback current is sunk at the FB/OLP
pin, transferred through a photo-coupler, PC1, and the
FB/OLP pin voltage decreases. Thus, VSC decreases,
and the peak value of VROCP is controlled to be low,
and the peak drain current of ID decreases.
The IC activates the soft start circuitry during the
startup period. Soft start time is fixed to around 8.75 ms.
during the soft start period, over current threshold is
increased step-wisely (7 steps). This function reduces the
voltage and the current stress of MOSFET and secondary
side rectifier diode.
Since the Leading Edge Blanking Function (see
Section 9.6) is deactivated during the soft start period,
there is the case that ON time is less than the leading
edge blanking time, tBW = 330 ns.
This control prevents the output voltage from
increasing.
Heavy Load Conditions
After the soft start period, D/ST pin current, ID, is
limited by the Overcurrent Protection (OCP), until the
output voltage increases to the target operating voltage.
When load conditions become greater, the IC performs
the inverse operation to that described above. Thus,
VSC increases and the peak drain current of ID
increases.
This period is given as tLIM
.
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STR6A100MV/HVD Series
This control prevents the output voltage from
decreasing.
Target voltage
without Slope Compensation
U1
S/OCP
1
GND FB/OLP
3
4
PC1
IFB
tON1
T
tON2
ROCP
C3
VROCP
T
T
Figure 9-8. Drain Current, ID, Waveform
in Subharmonic Oscillation
Figure 9-6. FB/OLP Pin Peripheral Circuit
Target voltage including
Slope compensation
9.6. Leading Edge Blanking Function
The constant voltage control of output of the IC uses
the peak-current-mode control method.
VSC
-
In peak-current-mode control method, there is a case
that the power MOSFET turns off due to unexpected
response of FB comparator or Overcurrent Protection
circuit (OCP) to the steep surge current in turning on a
power MOSFET.
+
VROCP
Voltage on both
sides of ROCP
FB Comparator
In order to prevent this response to the surge voltage in
turning-on the power MOSFET, the Leading Edge
Blanking, tBW = 330 ns is built-in. During tBW, the OCP
threshold voltage becomes VOCP(LEB) = 1.69 V which is
higher than the normal OCP threshold voltage (see
Section 9.10).
Drain Current,
ID
Figure 9-7. Drain Current, ID, and FB Comparator
Operation in Steady Operation
In the current mode control method, when the drain
current waveform becomes trapezoidal in continuous
operating mode, even if the peak current level set by the
target voltage is constant, the on-time fluctuates based on
the initial value of the drain current.
This results in the on-time fluctuating in multiples of
the fundamental operating frequency as shown in Figure
9-8. This is called the subharmonics phenomenon.
In order to avoid this, the IC incorporates the Slope
Compensation Function. Because the target voltage is
added a down-slope compensation signal, which reduces
the peak drain current as the on-duty gets wider relative
to the FB/OLP pin signal to compensate VSC, the
subharmonics phenomenon is suppressed.
9.7. Random Switching Function
The IC modulates its switching frequency randomly by
superposing the modulating frequency on fOSC(AVG) in
normal operation. This function reduces the conduction
noise compared to others without this function, and
simplifies noise filtering of the input lines of power
supply.
9.8. Step Drive Control
Figure 9-9 shows a flyback control circuit. The both
end of secondary rectification diode (D51) is generated
surge voltage when a power MOSFET turns on. Thus,
VRM of D51 should be set in consideration of the surge.
The IC optimally controls the gate drive of the internal
power MOSFET (Step drive control) depending on the
load condition. The step drive control reduces the surge
voltage of D51 when the power MOSFET turns on (see
Figure 9-10). Since VRM of D51 can be set to lower value
than usual, the price reduction and the increasing circuit
efficiency are achieved by using a diode of low VF.
Even if subharmonic oscillations occur when the IC
has some excess supply being out of feedback control,
such as during startup and load shorted, this does not
affect performance of normal operation.
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STR6A100MV/HVD Series
Switching
frequency
fOSC
VD51
D51
BR1
T1
VAC
fOSC(AVG)
Normal
operation
P1
S1
C1
C51
fOSC(MIN)
Green mode
Burst oscillation
ID
7, 8
D/ST
U1
Output power, PO
S/OCP
1
Figure 9-11. Relationship between PO and fOSC
ROCP
Switching period
Figure 9-9. Flyback Control Circuit
ID
Non-switching period
ID
Time
fOSC(MIN)
Time
Time
Reducing surge voltage
Figure 9-12. Switching Waveform at Burst Oscillation
VD51
Table 9-1. FB/OLP Pin Starting and Ending Voltage of
Frequency Decreasing
Time
Without step drive
Time
With step drive
control
STR6A153MV
STR6A16xHVD
(fOSC = 100 kHz)
control
(fOSC = 65 kHz)
VFB(FDS) (typ.)
VFB(FDE) (typ.)
3.30 V
3.00 V
3.60 V
3.10 V
Figure 9-10. ID and VD51 Waveforms
The standby operation point can be adjusted by the
external resistor, RBA (see Figure 9-13) according to the
power supply specification.
Table 9-2 shows the load ratio of the standby operation
point, where the load ratio at the Overcurrent Protection
operating point is 100 %.
9.9. Operation Mode
The operation of the IC automatically changes to green
mode or burst oscillation mode in order to reduce the
switching loss (see Figure 9-11).
When the output load becomes lower, FB/OLP pin
voltage decreases. When FB/OLP pin voltage decreases
to VFB(FDS) or less, the green mode is activated and the
oscillation frequency starts decreasing. When FB/OLP
pin voltage becomes VFB(FDE), the oscillation frequency
stops decreasing (see Table 9-1). At this point, the
oscillation frequency becomes fOSC(MIN) = 25 kHz.
When FB/OLP pin voltage further decreases and
becomes the standby operation point, the burst oscillation
mode is activated. As shown in Figure 9-12, the burst
oscillation mode consists of switching period and non-
switching period. The oscillation frequency during
switching period is the Minimum Frequency,
fOSC(MIN) = 25 kHz.
U1
BA
GND
3
FB/OLP
4
2
PC1
RBA
C3
C4
Figure 9-13. BA Pin Peripheral Circuit
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STR6A100MV/HVD Series
Table 9-2. Standby Operation Point
width of S/OCP pin should be less than tBW, as shown in
Figure 9-14. In order to prevent surge voltage, pay extra
attention to ROCP trace layout (See Section 10.2).
In addition, if a C (RC) damper snubber of Figure 9-15
is used, reduce the capacitor value of damper snubber.
FB/OLP Pin Oscillation Stop
Threshold Voltage
STR6A153MV STR6A16xHVD
(fOSC=65 kHz) (fOSC=100kHz)
Output Power Ratio
of the Standby
RBA
Operation Point
Short
Open
1.28 V
1.63 V
1.92 V
2.17 V
1.35 V
1.79 V
2.16 V
2.45 V
About 3 to 6 %
About 4 to 8 %
About 6 to 11 %
About 8 to 13 %
tBW
VOCP(LEB)
330 kΩ
68 kΩ
VOCP’
Generally, to improve efficiency under light load
conditions, the frequency of the burst mode becomes just
a few kilohertz. Because the IC suppresses the peak drain
current well during burst mode, audible noises can be
reduced.
The OCP detection usually has some detection delay
time. The higher the AC input voltage is, the steeper the
slope of ID is. Thus, the peak drain current at the burst
oscillation mode becomes high at a high AC input
voltage.
Surge pulse voltage width at turning-on
Figure 9-14. S/OCP Pin Voltage
C（RC）
Damper snubber
T1
It is necessary to consider that the burst frequency
becomes low at a high AC input.
D51
C51
If the VCC pin voltage decreases to VCC(BIAS) = 9.6 V
during the transition to the burst mode, the Bias Assist
function is activated and stabilizes the standby mode,
because the Startup Current, ICC(ST), is provided to the
VCC pin so that the VCC pin voltage does not decrease
to VCC(OFF). However, if the Bias Assist Function is
always activated during steady-state operation including
standby mode, the power loss increases. Therefore, the
VCC pin voltage should be more than VCC(BIAS), for
example, by adjusting the turns ratio of the auxiliary
winding and secondary-side winding and/or reducing the
value of R2 (See Section 10.1).
C1
U1
7, 8
D/ST
C（RC）
Damper snubber
S/OCP
1
ROCP
Figure 9-15. Damper Snubber
9.10.2. OCP Input Compensation Function
9.10. Overcurrent Protection (OCP)
9.10.1. OCP Operation
ICs with PWM control usually have some propagation
delay time. The steeper the slope of the actual drain
current at a high AC input voltage is, the larger the
detection voltage of actual drain peak current is,
compared to VOCP. Thus, the peak current has some
variation depending on the AC input voltage in OCP
state.
In order to reduce the variation of peak current in OCP
state, the IC incorporates a built-in Input Compensation
Function.
The Input Compensation Function is the function of
correction of OCP threshold voltage depending with AC
input voltage, as shown in Figure 9-16.
When AC input voltage is low (ON Duty is broad), the
OCP threshold voltage is controlled to become high. The
difference of peak drain current become small compared
with the case where the AC input voltage is high (ON
Duty is narrow).
Overcurrent Protection (OCP) detects each drain peak
current level of a power MOSFET on pulse-by-pulse
basis, and limits the output power when the current level
reaches to OCP threshold voltage.
During Leading Edge Blanking Time, the OCP
threshold voltage becomes VOCP(LEB) = 1.69 V which is
higher than the normal OCP threshold voltage as shown
in Figure 9-14. Changing to this threshold voltage
prevents the IC from responding to the surge voltage in
turning-on the power MOSFET. This function operates
as protection at the condition such as output windings
shorted or unusual withstand voltage of secondary-side
rectifier diodes.
When power MOSFET turns on, the surge voltage
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STR6A100MV/HVD Series
The compensation signal depends on ON Duty. The
relation between the ON Duty and the OCP threshold
voltage after compensation VOCP' is expressed as
Equation (3). When ON Duty is broader than 36 %, the
VOCP' becomes a constant value VOCP(H) = 0.888 V
When the OLP is activated, the IC stops switching
operation, and the VCC pin voltage decreases.
During OLP operation, the Bias Assist Function is
disabled. When the VCC pin voltage decreases to
VCC(OFF)SKP (about 9 V), the startup current flows, and the
VCC pin voltage increases. When the VCC pin voltage
increases to VCC(ON), the IC starts operation, and the
circuit current increases. After that, the VCC pin voltage
decreases. When the VCC pin voltage decreases to
VCC(OFF) = 8.5 V, the control circuit stops operation.
Skipping the UVLO operation of VCC(OFF) (see Section
9.2), the intermittent operation makes the non-switching
interval longer and restricts the temperature rise of the
power MOSFET.
ꢌꢀꢎꢡ ꢚ ꢌꢀꢎꢁꢢꢆ ꢣ ꢤꢥꢛ ꢜ ꢦꢧꢨꢏꢇꢩ
ꢦꢧꢤꢪꢗꢫ
ꢬꢌꢅꢀꢁꢄꢍꢭꢆ
ꢔꢔꢔꢔꢔꢔꢔꢔꢔꢔꢔꢚ ꢌꢀꢎꢁꢢꢆ ꢣ ꢤꢥꢛ ꢜ
(3)
where,
When the abnormal condition is removed, the IC
returns to normal operation automatically.
VOCP(L) is OCP Threshold Voltage at Zero ON Duty (V),
DPC is OCP Compensation Coefficient (mV/μs),
ONTime is on-time of power MOSFET (μs),
ONDuty is on duty of power MOSFET (%), and
fOSC(AVG) is Average PWM Switching Frequency (kHz).
U1
VCC
5
GND FB/OLP
1.0
4
3
D2 R2
PC1
VOCP(H)
VOCP(L)
C3
C2
D
Figure 9-17. FB/OLP Pin Peripheral Circuit
DDPC=36%
50
DMAX=75%
100
0.5
Non-switching
interval
Non-switching
interval
0
VCC Pin Voltage
VCC(ON)
On Duty (%)
Figure 9-16. Relationship between On Duty and Drain
Current Limit after Compensation
VCC(OFF)SKP
VCC(OFF)
tOLP
tOLP
tOLP
FB/OLP Pin Voltage
VFB(OLP)
9.11. Overload Protection (OLP)
Figure 9-17 shows the FB/OLP pin peripheral circuit,
and Figure 9-18 shows each waveform for OLP
operation.
Drain Current,
ID
When the peak drain current of ID is limited by OCP
operation, the output voltage, VOUT, decreases and the
feedback current from the secondary photo-coupler
becomes zero. Thus, the feedback current, IFB, charges
C3 connected to the FB/OLP pin and the FB/OLP pin
voltage increases. When the FB/OLP pin voltage
increases to VFB(OLP) = 7.3 V or more for the OLP delay
time, tOLP = 75 ms or more, the OLP is activated, the IC
stops switching operation.
During OLP operation, the intermittent operation by
VCC pin voltage repeats and reduces the stress of parts
such as the power MOSFET and secondary side rectifier
diode.
Figure 9-18. OLP Operational Waveforms
9.12. Overvoltage Protection (OVP)
When a voltage between VCC pin and GND terminal
increases to VCC(OVP) = 29.1 V or more, Overvoltage
Protection (OVP) is activated. The IC has two operation
types of OVP. One is the latched shutdown. The other is
auto-restart.
In case the VCC pin voltage is provided by using
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STR6A100MV/HVD Series
auxiliary winding of transformer, the overvoltage
conditions such as output voltage detection circuit open
can be detected because the VCC pin voltage is
proportional to output voltage. The approximate value of
output voltage VOUT(OVP) in OVP condition is calculated
by using Equation (4).
9.13. Thermal Shutdown (TSD)
When the temperature of control circuit increases to
Tj(TSD) = 145 °C or more, Thermal Shutdown (TSD) is
activated. The IC has two operation types of TSD. One is
latched shutdown, the other is auto-restart.
ꢚ
ꢌꢮꢘꢁꢝꢌꢙꢯꢄꢢꢆ ꢜ ꢕꢰꢊꢑꢔꢁ ꢆ
(4)
9.13.1. Latched Shutdown Type:
STR6A153MV
ꢌꢮꢘꢁꢌꢍꢎꢆ
ꢀꢀꢁꢝꢌꢙꢯꢄꢢꢆ
When the TSD is activated, the IC stops switching
operation at the latched state. In order to keep the latched
state, when VCC pin voltage decreases to VCC(BIAS), the
Bias Assist Function is activated and VCC pin voltage is
kept to over the VCC(OFF). Releasing the latched state is
done by turning off the input voltage and by dropping the
where,
VOUT(NORMAL) is output voltage in normal operation, and
VCC(NORMAL) is VCC pin voltage in normal operation.
9.12.1. Latched Shutdown Type:
STR6A153MV
VCC pin voltage below VCC(OFF)
.
When the OVP is activated, the IC stops switching
operation at the latched state. In order to keep the latched
state, when VCC pin voltage decreases to VCC(BIAS), the
Bias Assist Function is activated and VCC pin voltage is
9.13.2. Auto-restart Type: STR6A16xHVD
Figure 9-20 shows the TSD operational waveforms.
When TSD is activated, and the IC stops switching
operation. After that, VCC pin voltage decreases. When
the VCC pin voltage decreases VCC(BIAS), the Bias Assist
Function is activated and VCC pin voltage is kept to over
kept to over the VCC(OFF)
.
Releasing the latched state is done by turning off the
input voltage and by dropping the VCC pin voltage
below VCC(OFF)
.
the VCC(OFF)
.
When the temperature reduces to less than
Tj(TSD)−Tj(TSD)HYS, the Bias Assist Function is disabled
and the VCC pin voltage decreases to VCC(OFF). At that
time, the IC stops operation by the UVLO circuit and
reverts to the state before startup. After that, the startup
circuit is activated, the VCC pin voltage increases to
VCC(ON), and the IC starts switching operation again.
In this way, the intermittent operation by TSD and
UVLO is repeated while there is an excess thermal
condition.
9.12.2. Auto-restart Type: STR6A16xHVD
When the OVP is activated, the IC stops switching
operation. During OVP operation, the Bias Assist
Function is disabled, the intermittent operation by UVLO
is repeated. When the fault condition is removed, the IC
returns to normal operation automatically (see Figure
9-19).
When the fault condition is removed, the IC returns to
normal operation automatically.
VCC Pin Voltage
VCC(OVP)
Junction Temperature,
VCC(ON)
VCC(OFF)
Tj
Tj(TSD)
Tj(TSD)−Tj(TSD)HYS
Drain Current,
ID
Bias Assist
Function
ON
ON
OFF
OFF
VCC Pin Voltage
VCC(ON)
Figure 9-19. OVP Operational Waveforms
VCC(BIAS)
VCC(OFF)
Drain Current,
ID
Figure 9-20. TSD Operational Waveforms (Auto-
restart)
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STR6A100MV/HVD Series
10. Design Notes
10.1.4. FB/OLP Pin Peripheral Circuit
C3 is for high frequency noise reduction and phase
compensation, and should be connected close to these
pins. The value of C3 is recommended to be about 2200
pF to 0.01 µF, and should be selected based on actual
operation in the application.
10.1. External Components
Take care to use properly rated, including derating as
necessary and proper type of components.
CRD clamp snubber
C（RC）
damper snubber
BR1
C1
10.1.5. VCC Pin Peripheral Circuit
T1
VAC
R1
C6
The value of C2 is generally recommended to be 10 µF
to 47 μF (see Section 9.1 Startup Operation, because
the startup time is determined by the value of C2).
In actual power supply circuits, there are cases in
which the VCC pin voltage fluctuates in proportion to
the output current, IOUT (see Figure 10-1), and the
Overvoltage Protection (OVP) on the VCC pin may be
activated. This happens because C2 is charged to a
peak voltage on the auxiliary winding D, which is
caused by the transient surge voltage coupled from the
primary winding when the power MOSFET turns off.
For alleviating C2 peak charging, it is effective to add
some value R2, of several tenths of ohms to several
ohms, in series with D2 (see Figure 10-1). The optimal
value of R2 should be determined using a transformer
matching what will be used in the actual application,
because the variation of the auxiliary winding voltage
is affected by the transformer structural design.
C5
P
D1
U1
ROCP
1
8
S/OCP
D/ST
RBA
7
2
3
4
D2 R2
BA
D/ST
C4
GND
D
C2
5
VCC
FB/OLP
C3
PC1
Figure 10-1. The IC Peripheral Circuit
10.1.1. Input and Output Electrolytic
Capacitor
Apply proper derating to ripple current, voltage, and
temperature rise. Use of high ripple current and low
impedance types, designed for switch mode power
supplies, is recommended.
Without R2
VCC Pin Voltage
With R2
10.1.2. S/OCP Pin Peripheral Circuit
In Figure 10-1, ROCP is the resistor for the current
detection. A high frequency switching current flows to
ROCP, and may cause poor operation if a high
inductance resistor is used. Choose a low inductance and
high surge-tolerant type.
Output Current, IOUT
Figure 10-2. Variation of VCC Pin Voltage and Power
10.1.6. Snubber Circuit
10.1.3. BA Pin Peripheral Circuit
In case the surge voltage of VDS is large, the circuit
should be added as follows (see Figure 10-1);
The FB/OLP pin oscillation stop threshold voltage is
selected by the value of RBA connected to the BA pin (see
Section 9.9 Operation Mode).
The reference value of C4 is from 1000 pF to 2200 pF
for high frequency noise rejection
● A clamp snubber circuit of a capacitor-resistor- diode
(CRD) combination should be added on the primary
winding P.
● A damper snubber circuit of a capacitor (C) or a
resistor-capacitor (RC) combination should be added
between the D/ST pin and the S/GND pin.
In case the damper snubber circuit is added, this
components should be connected near D/ST pin and
S/OCP pin.
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STR6A100MV/HVD Series
output winding S should be maximized to reduce the
leakage inductance.
● The coupling of the winding D and the winding S
should be maximized.
10.1.7. Phase Compensation
A typical phase compensation circuit with a secondary
shunt regulator (U51) is shown in Figure 10-3.
C52 and R53 are for phase compensation. The value of
C52 and R53 are recommended to be around 0.047μF to
0.47μF and 4.7 kΩ to 470 kΩ, respectively. They should
be selected based on actual operation in the application.
● The coupling of the winding D and the winding P
should be minimized.
In the case of multi-output power supply, the coupling
of the secondary-side stabilized output winding, S1, and
the others (S2, S3…) should be maximized to improve
the line-regulation of those outputs.
Figure 10-4 shows the winding structural examples of
two outputs.
L51
T1
VOUT
(+)
D51
R54
R51
PC1
R52
R55
C51
Margin tape
S
C53
C52 R53
P1 S1 P2 S2 D
U51
R56
Margin tape
(-)
Winding Structural Example (a)
Figure 10-3. Peripheral Circuit Around Secondary
Shunt Regulator (U51)
Margin tape
10.1.8. Transformer
P1 S1 D S2 S1 P2
Apply proper design margin to core temperature rise
by core loss and copper loss.
Margin tape
Because the switching currents contain high frequency
currents, the skin effect may become a consideration.
Choose a suitable wire gauge in consideration of the
RMS current and a current density of 4 to 6 A/mm2.
If measures to further reduce temperature are still
necessary, the following should be considered to increase
the total surface area of the wiring:
Winding Structural Example (b)
Figure 10-4. Winding Structural Examples
● Winding Structural Example (a):
S1 is sandwiched between P1 and P2 to maximize the
coupling of them for surge reduction of P1 and P2.
D is placed far from P1 and P2 to minimize the
coupling to the primary for the surge reduction of D.
● Increase the number of wires in parallel.
● Use litz wires.
● Thicken the wire gauge.
In the following cases, the surge of VCC pin voltage
becomes high.
● Winding Structural Example (b)
P1 and P2 are placed close to S1 to maximize the
coupling of S1 for surge reduction of P1 and P2.
D and S2 are sandwiched by S1 to maximize the
coupling of D and S1, and that of S1 and S2. This
structure reduces the surge of D, and improves the
line-regulation of outputs.
● The surge voltage of primary main winding, P, is high
(low output voltage and high output current power
supply designs)
● The winding structure of auxiliary winding, D, is
susceptible to the noise of winding P.
When the surge voltage of winding D is high, the VCC
pin voltage increases and the Overvoltage Protection
(OVP) may be activated. In transformer design, the
following should be considered;
● The coupling of the winding P and the secondary
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STR6A100MV/HVD Series
such as film capacitor Cf (about 0.1 μF to 1.0 μF)
close to the VCC pin and the GND pin is
recommended.
10.2. PCB Trace Layout and Component
Placement
(4) ROCP Trace Layout
Since the PCB circuit trace design and the component
layout significantly affects operation, EMI noise, and
power dissipation, the high frequency PCB trace should be
low impedance with small loop and wide trace.
In addition, the ground traces affect radiated EMI noise,
and wide, short traces should be taken into account.
Figure 10-5 shows the circuit design example.
ROCP should be placed as close as possible to the
S/OCP pin. The connection between the power
ground of the main trace and the IC ground should be
at a single point ground (point A in Figure 10-5)
which is close to the base of ROCP
.
(5) Peripheral components of the IC
The components for control connected to the IC
should be placed as close as possible to the IC, and
should be connected as short as possible to the each
pin.
(1) Main Circuit Trace Layout
This is the main trace containing switching currents,
and thus it should be as wide trace and small loop as
possible.
If C1 and the IC are distant from each other, placing
a capacitor such as film capacitor (about 0.1 μF and
with proper voltage rating) close to the transformer or
the IC is recommended to reduce impedance of the
high frequency current loop.
(6) Secondary Rectifier Smoothing Circuit Trace Layout:
This is the trace of the rectifier smoothing loop,
carrying the switching current, and thus it should be
as wide trace and small loop as possible. If this trace
is thin and long, inductance resulting from the loop
may increase surge voltage at turning off the power
MOSFET. Proper rectifier smoothing trace layout
helps to increase margin against the power MOSFET
breakdown voltage, and reduces stress on the clamp
snubber circuit and losses in it.
(2) Control Ground Trace Layout
Since the operation of IC may be affected from the
large current of the main trace that flows in control
ground trace, the control ground trace should be
separated from main trace and connected at a single
point grounding of point A in Figure 10-5 as close to
the ROCP pin as possible.
(7) Thermal Considerations
Because the power MOSFET has a positive thermal
coefficient of RDS(ON), consider it in thermal design.
Since the copper area under the IC and the D/ST pin
trace act as a heatsink, its traces should be as wide as
possible.
(3) VCC Trace Layout:
This is the trace for supplying power to the IC, and
thus it should be as small loop as possible. If C2 and
the IC are distant from each other, placing a capacitor
(1)Main trace should be wide
trace and small loop
(6)Main trace of secondary side should
be wide trace and small loop
(4)ROCP should be as close to S/OCP pin
as possible.
T1
D51
(7)Trace of D/ST pin should be
wide for heat release
R1
C1
C6
P
C5
C51
S
A
D1
U1
ROCP
C4
1
8
7
S/OCP
D/ST
D/ST
2
3
4
BA
RBA
D2
R2
(2) Control GND trace
GND
should be connected at
a single point as close
to the ROCP as possible
5
D
VCC
FB/OLP
C2
PC1 C3
(5)The components
connected to the IC
should be as close to
the IC as possible, and
should be connected as
short as possible
CY
(3) Loop of the power supply should be small
Figure 10-5. Peripheral Circuit Example Around the IC
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STR6A100MV/HVD Series
11. Pattern Layout Example
The following show the PCB pattern layout example and the schematic of circuit using STR6A100MV/HVD series.
The PCB pattern layout example is made usable to other ICs in common. The parts in Figure 11-2 are only used.
Figure 11-1 PCB Circuit Trace Layout Example
L52
CN51
1
T1
D52
C57
OUT2(+)
OUT2(-)
R59
R60
R58
R61
C55
C56
L51
2
3
CN1
1
F1
L1
JW51
JW52
JW54
JW6
C12
L2
D1
D4
D2
D3
TH1
D51
C54
C1
C2
OUT1(+)
P1
C5
R54
R55
C13
C3
C4
R51
R1
3
PC1
C51
R52
R2
D7
C53 R57
S1
C52
U51
R53
R56
4
D2
D1
OUT1(-)
JW10
5
VCC
8
7
D8 R3
C8
JW4
JW31
CN31
1
D31
U1 D/ST D/ST
C9
OUT4(+)
OUT4(-)
STR6A100×V
C31
C32
R31
C10
2
BA
2
GND
S/OCP
1
FB/OLP
4
JW53
C11
JW21
3
CN21
1
U21
OUT
GND
JW8
3
D21
JW11
CP1
1
IN
OUT3(+)
OUT3(-)
JW3
JW7
JW9
2
C21
R5
R4
R21
C6
C7
C22
2
Figure 11-2 Circuit Schematic for PCB Circuit Trace Layout
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STR6A100MV/HVD Series
12. Reference Design of Power Supply
As an example, the following show the power supply specification, the circuit schematic, the bill of materials, and the
transformer specification.
12.1. Circuit Specifications
IC
STR6A163HVD
Input voltage
AC85V to AC265V
Maximum output power 21 W
Output voltage
Output current
14 V
1.5 A (max.)
12.2. Circuit Schematic
The circuit symbols correspond to these of Figure 11-1
F1
1
T1
L2
L51
R52
L1
D1
D4
D2
D3
TH1
D51
C54
3
OUT1(+)
C1
C2
R1
C5
R54
R55
C3
C4
P1
P2
R51
3
CN1
PC1
R2
D7
C53 R57
S1
JW10
C51
C52
U51
R53
R56
4
OUT1(-)
5
VCC
8
7
D8
R3
JW4
U1 D/ST
D/ST
D1
C9
C8
STR6A100×V
C10
BA
2
GND
S/OCP
1
FB/OLP
4
JW53
C11
3
JW11
CP1
JW3
R5
R4
C6
C7
12.3. Transformer Specification
Table 12-1. Transformer Specification
Primary Inductance, LP
Core Size
Al-value
Winding Specification
Winding Structure
700 μH
EI-22
231 nH/N2 (center gap is 0.23 mm)
See Table 12-2
See Figure 12-1
Table 12-2. Winding Specification
Winding
Symbol
P1
Number of Turns (T)
Wire Diameter (mm)
2UEW-φ0.23
2UEW-φ0.23
2UEW-φ0.23
TEX-φ0.26 × 2
TEX-φ0.26 × 2
Construction
Primary Winding 1
Primary Winding 2
Auxiliary Winding
Output Winding 1
Output Winding 2
30
25
10
9
Single-layer, solenoid winding
Single-layer, solenoid winding
Space winding
Single-layer, solenoid winding
Single-layer, solenoid winding
P2
D
S1
S2
9
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STR6A100MV/HVD Series
VDC
(+) 14V
P1
P2
P1
S2
D
VOUT
S1
S2
(-)
D/ST
VCC
S1
P2
D
Bobbin
GND
● Start at this pin
Cross-section view
Figure 12-1. Winding Structure
12.4. Bill of Materials
Recommended
Sanken Parts
Recommended
Sanken Parts
Symbol
Part Type
Film, X2
Ratings(1)
Symbol
Part Type
Ratings(1)
Short
(2)
(2)
C1
0.033 μF, 275 V
Open
L2
Inductor
Inductor
Photo-coupler
Metal oxide
General
(2)
C2
Electrolytic
Electrolytic
Electrolytic
Ceramic
L51
PC1
R1
Short
C3
82 μF, 400 V
Open
PC123 or equiv
470 kΩ, 1 W
Short
(3)
(2)
C4
C5
1000 pF, 630 V
1000 pF
R2
C6
Ceramic
R3
General
4.7 Ω
(2)
(2)
(2)
(2)
C7
Ceramic
0.01 μF
R4
General
1 Ω, 1 W
330 kΩ
2.2 kΩ
C8
Electrolytic
Ceramic
22 μF, 50 V
Open
R5
General
C9
R51
R52
R53
R54
R55
R56
R57
General
C10
C11
C51
C52
C53
C54
Ceramic
Open
General
1.5 kΩ
(2)
Ceramic, Y1
Electrolytic
Ceramic
2200 pF, 250 V
1000 μF, 25V
0.22 μF, 50V
Open
General
10 kΩ
General
6.8 kΩ
General, 1%
General, 1%
General
39 kΩ
Electrolytic
Ceramic
10 kΩ
Open
Open
See the
specification
D1
General
600 V, 1 A
EM01A
T1
Transformer
(2)
D2
D3
General
General
600 V, 1 A
600 V, 1 A
EM01A
EM01A
TH1
U1
NTC thermistor Short
STR6A163HVD
IC
－
VREF=2.5V
TL431or equiv
D4
General
600 V, 1 A
EM01A
U51
Shunt regulator
D7
D8
D51
F1
Fast recovery
Fast recovery
Schottky
1000V, 0.5A
200 V, 1 A
100 V, 10 A
AC250V, 2 A
3.3 mH
EG01C
AL01Z
JW3
JW4
Short
Short
Short
Short
Short
FMEN-210A JW10
Fuse
JW11
(2)
L1
CM inductor
JW53
(1) Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less.
(2) It is necessary to be adjusted based on actual operation in the application.
(3) Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration
or use combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application.
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STR6A100MV/HVD Series
Important Notes
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DSGN-CEZ-16003
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