ENA0929 [SANYO]
CMOS IC FROM 128K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller; CMOS集成电路从128K字节， RAM 4096字节的片上8位单芯片微控制器
| 型号： | ENA0929 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | CMOS IC FROM 128K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller |
| 文件： | 总25页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0929
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
LC87F5NC8A
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F5NC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 83.3ns, integrate on a single chip a number of hardware features such as 128K-byte flash ROM (onboard
rewritable), 4096byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, two synchronous SIO ports (with
automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full
duplex), four 12-bit PWM channels, an 8-bit 15-channel AD converter, a system clock frequency divider, and a 29-
source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
• Block-erase in 128 byte units
• 131072 × 8 bits
RAM
• 4096 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
• 125ns (8MHz)
• 500ns (2MHz)
V
DD
V
DD
V
DD
=2.8 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
Note: Bus cycle time indicates the speed to read ROM.
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
• 375ns (8MHz)
• 1.5µs (2MHz)
V
V
V
=2.8 to 5.5V
=2.5 to 5.5V
=2.2 to 5.5V
DD
DD
DD
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 64 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PBn, PCn,
S2Pn, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 2-bit units 16 (PEn, PFn)
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
• Reset pins
• Power pins
6 (V 1 to 4, V 1 to 4)
SS DD
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Ver.1.00
92607HKIM 20070810-S00009 No. A0929-1/25
LC87F5NC8A
Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) ×2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bit in continuous transmission mode)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 8 bits × 15 channels
PWM: Multifrequency 12-bit PWM × 4 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
No.A0929-2/25
LC87F5NC8A
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
2
0000BH
00013H
INT1
3
INT2/T0L/INT4
4
0001BH
00023H
INT3/INT5/base timer0/base timer1
T0H/INT6
5
6
0002BH
00033H
T1L/T1H/INT7
7
SIO0/UART1 receive/UART2 receive
SIO/UART1 transmit/UART2 transmit
ADC/T6/T7/PWM4, PWM5
Port 0/T4/T5/PWM2, PWM3
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels maximum (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits (5 tCYC execution time)
• 24-bits × 16-bits (12 tCYC execution time)
• 16-bits ÷ 8-bits (8 tCYC execution time)
• 24-bits ÷ 16-bits (12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal)
• CF oscillation circuit
• Crystal oscillation circuit
: For system clock
: For system clock, with internal Rf
: For low-speed system clock
• Multifrequency RC oscillation circuit (internal) : For system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0µs, 2.0µs, 4.0µs, 8.0µs, 16.0µs, 32.0µs, and
64.0µs (at a main clock rate of 12MHz).
No.A0929-3/25
LC87F5NC8A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Package Form
• QIP100E (14 × 20) : “Lead-free type”
Development Tools
• Evaluation (EVA) chip
• Emulator
: LC87EV690
: EVA62S + ECB876600D + SUB875C00 + POD100QFP
ICE-B877300 + SUB875C00 + POD100QFP
: TCB87-TypeB + LC87F5NC8A
• On-chip-debugger
Programming Boards
Package
Programming boards
W87F52256Q
QIP100E (14 × 20)
Flash ROM Programmer
Maker
Model
Support version(Note)
Device
Flash Support
Group, Inc.
AF9708/09/09B
Revision : After Rev.02.73
LC87F76C8A
(including product of Ando Electric Co.,Ltd)
(Single)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
Revision : After Rev.02.29
Revision : After Rev.01.88
Flash Support
LC87F5NC8A
LC87F5NC8A
Group, Inc.(Gang)
(including product of Ando Electric Co.,Ltd)
Application Version:
After 1.04
SKK/SKK Type-B/SKK DBG Type-B
(SANYO FWS)
SANYO
Chip Data Version:
After2.10
No.A0929-4/25
LC87F5NC8A
Package Dimensions
unit : mm (typ)
3151A
23.2
20.0
80
51
81
50
31
100
1
30
0.65
0.3
0.15
(0.58)
SANYO : QIP100E(14X20)
No.A0929-5/25
LC87F5NC8A
Pin Assignment
8079 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PB6
81
SI2P1/SI2/SB2
SI2P0/SO2
PF7
PF6
PF5
PF4
PF3
PF2
PF1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PB5
82
PB4
83
PB3
84
PB2
85
PB1
86
PB0
87
V
V
3
SS
88
89
90
91
92
93
94
95
96
97
98
99
3
DD
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PF0
LC87F5NC8A
V
V
4
4
DD
SS
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PC3
PC2
PC1
PC0
PA0
PA1
PA2
100
1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Top view
SANYO: QIP100E(14×20) “Lead-free Type”
No.A0929-6/25
LC87F5NC8A
System Block Diagram
IR
PLA
Interrupt control
Flash ROM
Standby control
CF
RC
PC
X’tal
MRC
Bus Interface
Port 0
ACC
SIO0
SIO1
B register
C register
SIO2
Port 1
Timer 0
Port 3
ALU
Timer 1
Timer 4
Port 7
Port 8
PSW
RAR
Timer 5
ADC
INT0 to 7
PWM0/1
PWM4/5
Base timer
Noise rejection filter
RAM
Port 2
Port A
Port B
Stack Pointer
Watchdog Timer
On-chip debugger
Timer 6
Timer 7
UART1
UART2
Port C
Port E
Port F
No.A0929-7/25
LC87F5NC8A
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
V
1, V
3, V
2
4
-
- Power supply pin
+ Power supply pin
SS
SS
DD
DD
SS
SS
1, V
3, V
2
-
No
DD
DD
4
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input, bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input, bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output, Beeper output
• 8-bit I/O port
Port 2
I/O
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
enable
enable
enable
enable
INT4
INT5
INT6
INT7
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
disable
disable
disable
disable
Port 3
I/O
• 7-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P36
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Continued on next page.
No.A0929-8/25
LC87F5NC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer
P71: INT1 input/HOLD release input/Timer 0H capture input
P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input
P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input
• Interrupt acknowledge type
Rising/
Rising
Falling
H level
L level
Falling
disable
disable
enable
enable
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
• AD converter input port: AN8 (P70), AN9 (P71)
Port 8
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
• Other functions
P80 to P87
P80 to P87: AD converter input port
• 6-bit I/O port
Port A
I/O
I/O
I/O
Yes
Yes
Yes
• I/O specifiable in 1-bit units
PA0 to PA5
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
Port B
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
PB0 to PB7
Port C
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PC0 to PC7
DBGP0 to DBGP2 (PC5 to PC7): On-chip Debugger
• 8-bit I/O port
Port E
I/O
I/O
I/O
No
No
No
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 8-bit I/O port
PE0 to PE7
Port F
• I/O specifiable in 2-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• 4-bit I/O port
PF0 to PF7
SIO2 Port
• I/O specifiable in 1-bit units
• Shared functions:
SI2P0 to SI2P3
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
PWM0, PWM1
O
• PWM0, PWM1 output port
No
• General-purpose I/O available
Reset pin
RES
XT1
I
I
No
No
• Input terminal for 32.768kHz X'tal oscillation
• Shared functions:
AN10: AD converter input port
General-purpose input port
Must be connected to V 1 if not to be used.
DD
XT2
I/O
• Output terminal for 32.768kHz X'tal oscillation
• Shared functions:
No
AN11: AD converter input port
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
Ceramic resonator input pin
CF1
CF2
I
No
No
O
Ceramic resonator output pin
No.A0929-9/25
LC87F5NC8A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Options Selected
Port
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
P00 to P07
1
2
CMOS
Programmable (Note 1)
No
N-channel open drain
CMOS
P10 to P17
P20 to P27
P30 to P36
1 bit
1 bit
1 bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
N-channel open drain
CMOS
1
2
N-channel open drain
CMOS
1
2
N-channel open drain
N-channel open drain
CMOS
P70
-
No
No
No
1
P71 to P73
P80 to P87
PA0 to PA5
-
-
N-channel open drain
CMOS
1 bit
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
N-channel open drain
CMOS
PB0 to PB7
PC0 to PC7
1 bit
1 bit
1
2
N-channel open drain
CMOS
1
2
N-channel open drain
CMOS
PE0 to PE7
PF0 to PF7
-
-
-
No
No
No
CMOS
SI2P0, SI2P2
SI2P3
CMOS
SI2P1
-
No
CMOS (when selected as ordinary port)
N-channel open drain (When SIO2 data is selected)
CMOS
No
PWM0, PWM1
-
-
-
No
No
No
No
No
No
XT1
XT2
Input only
Output for 32.768kHz quartz oscillator
N-channel open drain (when in general-purpose No
output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the V 1 pin and prolong the backup time.
DD
Be sure to electrically short the V 1, V 2, V 3 and V 4 pins.
SS SS SS SS
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Back-up
LSI
capacitor
V
1
DD
Power
Supply
V
2
DD
V
V
3
4
DD
DD
V
1
V
2
V
3
V
4
SS
SS
SS
SS
No.A0929-10/25
LC87F5NC8A
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up
capacitor
LSI
V
V
V
V
1
2
3
4
DD
DD
DD
DD
Power
Supply
V
1
V
2
V
3
V
4
SS
SS
SS
SS
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
DD
Maximum Supply
voltage
V
max
V
V
1, V 2,
V
1=V 2=V 3=V 4
DD
DD
DD
DD
DD DD DD DD
-0.3
+6.5
+0.3
3, V
DD
4
Input voltage
V (1)
XT1, CF1
-0.3
V
V
I
DD
Input/Output
Voltage
V
(1)
Ports 0, 1, 2
IO
V
Ports 3, 7, 8
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1,XT2
Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
-0.3
+0.3
DD
Peak output
current
IOPH(1)
CMOS output select per 1
application pin
-10
IOPH(2)
IOPH(3)
IOM(1)
Per 1 application pin.
Per 1 application pin.
-20
-5
P71 to P73
Average output
current
Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
CMOS output select per 1
application pin
-7.5
(Note1-1)
IOM(2)
Per 1 application pin.
-10
-3
IOM(3)
P71 to P73
P71 to P73
Per 1 application pin.
Total output
current
ΣIOAH(1)
ΣIOAH(2)
Total of all applicable pins
Total of all applicable pins
-10
PWM0, PWM1
SI2P0 to SI2P3
Port 0
mA
-25
-25
ΣIOAH(3)
ΣIOAH(4)
Total of all applicable pins
Total of all applicable pins
Port 0
PWM0, PWM1
SI2P0 to SI2P3
Ports 2, 3, B
-45
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
ΣIOAH(8)
ΣIOAH(9)
ΣIOAH(10)
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
-25
-25
-45
-25
-25
-45
Ports A, C
Ports 2, 3, A, B, C
Port F
Ports 1, E
Ports 1, E, F
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A0929-11/25
LC87F5NC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pins/Remarks
P02 to P07
Conditions
V
[V]
min
unit
DD
Peak output
current
IOPL(1)
Per 1 application pin.
Ports 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
P00, P01
20
IOPL(2)
IOPL(3)
IOML(1)
Per 1 application pin.
Per 1 application pin.
Per 1 application pin.
30
10
Ports 7, 8, XT2
Average output
current
P02 to P07
Ports 1, 2, 3
(Note1-1)
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1
P00, P01
15
IOML(2)
IOML(3)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Per 1 application pin.
20
7.5
15
Ports 7, 8, XT2
Port 7, XT2
Port 8
Per 1 application pin.
Total output
current
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
mA
15
Ports 7, 8, XT2
20
PWM0, PWM1
SI2P0 to SI2P3
Port 0
45
45
ΣIOAL(5)
ΣIOAL(6)
Total of all applicable pins
Total of all applicable pins
Port 0
PWM0, PWM1
SI2P0 to SI2P3
Ports 2, 3, B
80
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
ΣIOAL(10)
ΣIOAL(11)
ΣIOAL(12)
Pd max
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Total of all applicable pins
Ta=-40 to +85°C
45
45
80
45
45
80
Ports A, C
Ports 2, 3, A, B, C
Port F
Ports 1, E
Ports 1, E, F
QIP100E(14×20)
Maximum power
dissipation
320
+85
mW
Operating ambient
temperature
Topr
Tstg
-40
°C
Storage ambient
temperature
-55
+125
Note 1-1: Average output current is average of current in 100ms interval.
No.A0929-12/25
LC87F5NC8A
Recommended Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
Specification
SS
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
Operating
V
(1)
V
1=V
2
0.245µs≤ tCYC≤200µs
0.367µs≤ tCYC≤200µs
1.470µs≤ tCYC≤200µs
2.8
2.5
2.2
5.5
5.5
5.5
DD
DD DD
supply voltage
(Note2-1)
=V 3=V
DD
4
DD
Memory
VHD
V
1=V
2
RAM and register contents in
HOLD mode.
DD DD
sustaining
supply voltage
High level input
voltage
=V 3=V
DD
4
2.0
5.5
DD
V
(1)
Ports 1, 2, 3
IH
SI2P0 to SI2P3
P71 to P73
0.3V
V
V
DD
DD
2.2 to 5.5
2.2 to 5.5
+0.7
P70 port input/
interrupt side
Ports 0, 8
V
(2)
IH
0.3V
DD
DD
Ports A, B, C, E, F
PWM0, PWM1
P70 Watchdog timer
side
+0.7
V
V
V
(3)
(4)
V
V
V
IH
DD
2.2 to 5.5
2.2 to 5.5
0.9V
DD
XT1, XT2, CF1,
RES
IH
DD
0.75V
DD
Low level input
voltage
(1)
Ports 1, 2, 3
SI2P0 to SI2P3
P71 to P73
IL
0.1V
DD
4.0 to 5.5
2.2 to 4.0
V
V
SS
+0.4
P70 port input/
interrupt
0.2V
SS
DD
V
(2)
Ports 0, 8
0.15V
IL
DD
2.5 to 5.5
2.2 to 5.5
2.5 to 5.5
V
V
SS
Ports A, B, C, E, F
PWM0, PWM1
+0.4
0.2V
0.8V
SS
DD
V
V
(5)
(6)
Port 70 Watchdog
Timer
IL
DD
V
V
SS
-1.0
RES
XT1, XT2, CF1,
2.5 to 5.5
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.25V
DD
IL
SS
Instruction cycle
time
tCYC
0.245
0.367
1.470
200
(Note2-2)
µs
200
200
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.1
0.1
0.1
12
8
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
2
MHz
• CF2 pin open
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24.4
16
4
• System clock frequency
division rate=1/2
Oscillation
frequency
Range
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
12MHz ceramic oscillation
See Fig. 1.
2.8 to 5.5
2.5 to 5.5
12
8MHz ceramic oscillation
See Fig. 1.
8
4
(Note2-3)
4MHz ceramic oscillation
See Fig. 1.
MHz
2.2 to 5.5
FmRC
Internal RC oscillation
2.5 to 5.5
2.5 to 5.5
0.3
1.0
16
2.0
FmMRC
Frequency variable RC
oscillation source oscillation
32.768kHz crystal oscillation.
See Fig. 2.
FsX’tal
XT1, XT2
2.5 to 5.5
32.768
kHz
Note 2-1: V
DD
must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0929-13/25
LC87F5NC8A
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
High level input
current
I
1)
Ports 0, 1, 2
Ports 3, 7, 8
Ports A, B, C
SI2P0 to SI2P3
RES
Output disable
Pull-up resistor OFF
=V
IH(
V
IN DD
2.2 to 5.5
1
(including the off-leak current of the
output Tr.)
PWM0, PWM1
XT1, XT2
I
(2)
IH
Using as an input port
2.2 to 5.5
2.2 to 5.5
1
V
=V
IN DD
I
I
(3)
IH
CF1
V
=V
15
IN DD
µA
Low level input
current
(1)
IL
Ports 0, 1, 2
Ports 3, 7, 8
Ports A, B, C, E, F
SI2P0 to SI2P3
RES
Output disable
Pull-up resistor OFF
V
=V
IN SS
2.2 to 5.5
-1
(including the off-leak current of the
output Tr.)
PWM0, PWM1
XT1, XT2
I
I
(2)
IL
Using as an input port
2.2 to 5.5
-1
V
V
I
=V
IN SS
(3)
IL
CF1
=V
2.2 to 5.5
4.5 to 5.5
-15
-1
IN SS
High level output
voltage
V
(1)
Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P
=-1.0mA
V
OH
OH
OH
DD
V
(2)
I
I
I
I
I
I
I
=-0.4mA
=-0.2mA
=-0.4mA
=-0.2mA
=-10mA
=-1.6mA
=-1.0mA
V
OH
OH
OH
OH
OH
OH
OH
DD
-0.4
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
V
V
V
V
V
V
(3)
(4)
(5)
(6)
(7)
(8)
V
DD
-0.4
OH
OH
OH
OH
OH
OH
Ports 71, 72, 73
V
DD
-0.4
V
DD
-0.4
PWM0, PWM1
P30, P31(PWM4, 5
output mode)
V
DD
-1.5
V
DD
-0.4
V
V
DD
-0.4
Low level output
voltage
V
V
V
(1)
(2)
(3)
Ports 0, 1, 2, 3
Ports A, B, C, E, F
SI2P0 to SI2P3
PWM0, PWM1,
P00, P01
I
I
I
=10mA
=1.6mA
=1.0mA
4.5 to 5.5
3.0 to 5.5
1.5
0.4
OL
OL
OL
OL
OL
OL
2.2 to 5.5
0.4
V
V
V
V
V
(4)
(5)
(6)
(7)
(8)
I
I
I
I
I
=30mA
=5.0mA
=2.5mA
=1.6mA
=1.0mA
=0.9V
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
1.5
0.4
0.4
0.4
0.4
80
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
Ports 7, 8, XT2
Pull-up resistation
Hysteresis voltage
Pin capacitance
Rpu(1)
Rpu(2)
Ports 0, 1, 2, 3
Port 7
V
OH
15
15
35
DD
kΩ
2.2 to 5.5
35
120
Ports A, B, C, E, F
RES
VHYS
Ports 1, 2, 7
SI2P0 to SI2P3
All pins
2.2to 5.5
0.1V
V
DD
CP
• For pins other than that under
test: V =V
IN SS
• f=1MHz
2.2 to 5.5
10
pF
• Ta=25°C
No.A0929-14/25
LC87F5NC8A
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Pins
Parameter
Frequency
Symbol
tSCK(1)
Conditions
/Remarks
V
[V]
min
typ
max
unit
DD
SCK0(P12)
• See Fig. 6.
2
1
1
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
tSCKHA(1a)
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• See Fig. 6.
2.2 to 5.5
4
6
tCYC
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected.
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2a)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Continuous data
transmission/reception mode
• SIO2 is not in use simultaneous.
• CMOS output selected.
• See Fig. 6.
tSCKH(2)
+(10/3)
tCYC
2.2 to 5.5
tSCKH(2)
+2tCYC
tCYC
tSCKHA(2b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• CMOS output selected.
• See Fig. 6.
tSCKH(2)
+(16/3)
tCYC
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SI0(P11),
SB0(P11)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
0.03
0.03
2.2 to 5.5
Output
SO0(P10),
SB0(P11),
• Continuous data
(1/3)tCYC
+0.05
delay time
transmission/reception mode
• (Note 4-1-3)
µs
• Synchronous 8-bit mode.
• (Note 4-1-3)
1tCYC
+0.05
2.2 to 5.5
• (Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0929-15/25
LC87F5NC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Pins/
Parameter
Frequency
Symbol
Tsck(3)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK1(P15)
• See Fig. 6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected.
• See Fig. 6.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
0.03
0.03
Data hold time
thDI(2)
tdD0(4)
µs
Output delay
time
SO1(P13),
SB1(P14)
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
change in open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0929-16/25
LC87F5NC8A
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Specification
Pins/
Parameter
Frequency
Symbol
tSCK(5)
Conditions
Remarks
V
[V]
min.
typ
max.
unit
DD
SCK2
• See Fig. 6.
2
1
1
(SI2P2)
Low level
tSCKL(5)
pulse width
High level
pulse width
tSCKH(5)
tSCKHA(5a)
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
2.2 to 5.5
4
7
tCYC
• See Fig. 6.
• (Note 4-3-2)
tSCKHA(5b)
• Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
• See Fig. 6.
• (Note 4-3-2)
Frequency
tSCK(6)
SCK2
• CMOS output selected.
• See Fig. 6.
4/3
(SI2P2),
SCK2O
(SI2P3)
Low level
tSCKL(6)
tSCKH(6)
tSCKHA(6a)
1/2
1/2
pulse width
High level
pulse width
tSCK
• Continuous data transmission/
reception mode of SIO0 is not in
use simultaneous.
2.2 to 5.5
tSCKH(6)
tSCKH(6)
+(5/3)tCYC
+(10/3)tCYC
• CMOS output selected.
• See Fig. 6.
tCYC
tSCKHA(6b)
• Continuous data transmission/
reception mode of SIO0 is in use
simultaneous.
tSCKH(6)
tSCKH(6)
+(5/3)tCYC
+(19/3)tCYC
• CMOS output selected.
• See Fig. 6.
Data setup time
Data hold Time
tsDI(3)
thDI(3)
tdD0(5)
SI2(SI2P1),
SB2(SI2P1)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
0.03
0.03
2.2 to 5.5
µs
Output delay
time
SO2
• Must be specified with respect to
falling edge of SIOCLK
(SI2P0),
SB2(SI2P1)
• Must be specified as the time to
the beginning of output state
change in open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.2 to 5.5
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A0929-17/25
LC87F5NC8A
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
tCYC
µs
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are
enabled.
INT1(P71),
INT2(P72)
INT4(P20 to P23),
INT5(P24 to P27),
INT6(P20)
2.2 to 5.5
1
INT7(P24)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
INT3(P73) when noise filter
time constant is 1/1.
INT3(P73)(The noise rejection
clock is selected to 1/32.)
INT3(P73)(The noise rejection
clock is selected to 1/128.)
RES
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled.
Reset acceptable.
2.2 to 5.5
2.2 to 5.5
2
64
2.2 to 5.5
2.2 to 5.5
256
200
AD Converter Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
AN0(P80) to
AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1),
AN11(XT2),
AN12(PA3),
AN13(PA4),
AN14(PA5)
3.0 to 5.5
8
Absolute
ET
(Note 6-1)
3.0 to 5.5
1.5
LSB
accuracy
Conversion time
TCAD
AD conversion time=32×tCYC
(when ADCR2=0) (Note 6-2)
11.74
97.92
(tCYC=
3.06µs)
97.92
4.5 to 5.5
(tCYC=
0.367µs)
23.53
3.0 to 5.5
4.5 to 5.5
(tCYC=
0.735µs)
15.68
(tCYC=
3.06µs)
97.92
µs
AD conversion time=64×tCYC
(when ADCR2=1)
(Note 6-2)
(tCYC=
0.245µs)
23.49
(tCYC=
1.53µs)
97.92
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.367µs)
(tCYC=
1.53µs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
µA
VAIN=V
SS
-1
Note 6-1: The quantization error ( 1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0929-18/25
LC87F5NC8A
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
1
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
=V
=V
=V
2
3
4
DD
DD
DD
4.5 to 5.5
9.5
20.5
(Note 7-1)
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
2.8 to 4.5
4.5 to 5.5
2.5 to 4.5
4.5 to 5.5
2.2 to 4.5
5.5
8
14.8
15.5
11
IDDOP(2)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(3)
IDDOP(4)
4
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
2.8
1.5
6.6
mA
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(5)
IDDOP(6)
4.2
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.2 to 4.5
1
4.8
3.3
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
IDDOP(7)
IDDOP(8)
0.55
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
2.2 to 4.5
4.5 to 5.5
2.2 to 4.5
1.3
0.7
40
5.7
4.6
120
77
• System clock set to 1MHz with frequency
variable RC oscillation
IDDOP(9)
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
IDDOP(10)
µA
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
IDDOP(11)
20
HALT mode
consumption
current
IDDHALT(1)
V
1
DD
=V
=V
=V
2
3
4
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
DD
DD
4.5 to 5.5
2.8 to 5.5
4.5 to 5.5
2.5 to 4.5
3.6
2.1
2.7
1.4
8.3
4.4
5.8
3.1
(Note 7-1)
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• HALT mode
mA
IDDHALT(2)
IDDHALT(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A0929-19/25
LC87F5NC8A
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
unit
DD
HALT mode
consumption
current
IDDHALT(4)
V
1
• HALT mode
DD
=V
=V
=V
2
3
4
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
DD
DD
DD
4.5 to 5.5
2.2 to 4.5
1.1
2.6
(Note 7-1)
• System clock set to 4MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(5)
IDDHALT(6)
0.57
1.5
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
4.5 to 5.5
2.2 to 4.5
0.36
0.19
1.0
0.8
mA
IDDHALT(7)
IDDHALT(8)
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
4.5 to 5.5
2.2 to 4.5
4.5 to 5.5
2.2 to 4.5
1.15
0.57
20
4.2
3.0
77
• System clock set to 1MHz with frequency
variable RC oscillation
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
6
70
µA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
V
1
• HOLD mode
DD
4.5 to 5.5
2.2 to 4.5
0.04
0.02
20
15
• CF1=V
DD
or open (External clock mode)
Timer HOLD
mode
• Timer HOLD mode
• CF1=V or open (External clock mode)
4.5 to 5.5
2.2 to 4.5
17
4
70
55
DD
consumption
current
• FmX'tal=32.768kHz by crystal oscillation
mode
IDDHOLD(4)
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
SS
Specification
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ max
unit
mA
DD
Onboard
IDDFW(1)
V
1
• Without CPU current
DD
programming
current
2.70 to 5.5
5
10
Programming
time
tFW(1)
tFW(2)
• Erasing
2.7 to 5.5
2.7 to 5.5
20
40
30
60
ms
• programming
µs
No.A0929-20/25
LC87F5NC8A
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = V 4 = 0V
SS
SS
SS
Specification
SS
Parameter
Symbol
Pins/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
Transfer rate
UBR, UBR2
UTX1(P32),
RTX1(P33),
UTX2(P33),
RTX2(P34)
2.5 to 5.5
16/3
8192/3
tCYC
Data length : 7/8/9 bits (LSB first)
Stop bits : 1-bit (2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Stop bit
End of
transmission
Start bit
Start of
transmission
Transmit data (LSB first)
UBR
UBR2
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Stop bit
End of
reception
Start bit
Start of
reception
Receive data (LSB first)
UBR
UBR2
V 1, V 1 Terminal Condition
DD SS
It is necessary to place capacitors between V 1 and V 1 as describe below.
DD SS
• Place capacitors as close to V 1 and V 1 as possible.
DD SS
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1µF.
• Use thicker pattern for V 1 and V 1.
DD
SS
L2
L1
V
V
1
SS
C1
C2
1
DD
L1’
L2’
No.A0929-21/25
LC87F5NC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
12MHz
10MHz
CSTCE12M0G52-R0
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCE8M00G52-R0
CSTLS8M00G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(10)
(15)
(10)
(15)
(15)
(15)
(10)
(10)
(15)
(10)
(15)
(15)
(15)
Open
Open
Open
Open
Open
Open
Open
470
680
680
1k
2.5 to 5.5
2.4 to 5.5
2.5 to 5.5
2.3 to 5.5
2.5 to 5.5
2.2 to 5.5
2.2 to 5.5
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
Internal C1,C2
MURATA
8MHz
4MHz
1k
1.5k
1.5k
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Fig. 4).
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Circuit Constant
Operating Voltage
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Range
[V]
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
EPSON
Applicable
32.768kHz
MC-306
18
18
Open
560k
2.2 to 5.5
1.5
3.0
TOYOCOM
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf1
CF
Rd1
C2
Rf2
Rd2
C4
C1
C3
X’tal
Figure 1 Ceramic Oscillator Circuit
Figure 2 Crystal Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0929-22/25
LC87F5NC8A
V
V
DD
DD
limit
Power supply
GND
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Instruction execution
Unfixed
Reset Time and Oscillation Stabilization Time
HOLD reset
Signal absent
HOLD reset signal VALID
HOLD reset signal
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0929-23/25
LC87F5NC8A
V
DD
R
C
Note:
Select C
RES
and R value to assure that at least 200µs
RES
RES
reset time is generated after the V
the minimum operating voltage..
becomes higher than
DD
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0,2 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0,2 only)
tSCKLA
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0929-24/25
LC87F5NC8A
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
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Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
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semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
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product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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This catalog provides information as of August, 2007. Specifications and information herein are subject
to change without notice.
PS
No.A0929-25/25
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