FT-55U [SANYO]
256K (32768 words 8 bits) SRAM Control Pins: OE and CE; 256K （ 32768字8位） SRAM控制引脚： OE和CE
| 型号： | FT-55U |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 256K (32768 words 8 bits) SRAM Control Pins: OE and CE |
| 文件： | 总7页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6302
CMOS IC
LC35256FM, FT-55U/70U
256K (32768 words × 8 bits) SRAM
Control Pins: OE and CE
Preliminary
Overview
Package Dimensions
unit: mm
The LC35256FM and LC35256FT are asynchronous
silicon-gate CMOS SRAMs with a 32K-word by 8-bit
structure. These are full-CMOS devices with 6 transistors
per memory cell, and feature low-voltage operation, a low
operating current drain, and an ultralow standby current.
Control inputs include OE for fast memory access and CE
(chip enable) for power saving and device selection. This
makes these devices optimal for systems that require low
power or battery backup, and makes memory expansion
easy. The ultralow standby current allows these devices to
be used with capacitor backup as well.
3187A-SOP28D
[LC35256FM]
0.15
15
28
1
14
18.0
0.4
Features
• Supply voltage range: 4.5 to 5.5 V
• Access time at 5 V operation:
1.27
LC35256FM, FT-55U: 55 ns (maximum)
LC35256FM, FT-70U: 70 ns (maximum)
• Standby current: 3.0 µA (Ta ≤ 70°C)
5.0 µA (Ta ≤ 85°C)
• Operating temperature: –40 to +85°C
• Data retention voltage: 2.0 to 5.5 V
• All I/O levels: TTL compatible
SANYO: SOP28D
unit: mm
3221-TSOP28 (Type I)
[LC35256FT]
21
8
• Input/output shared function pins, 3-state output pins
• No clock required
• Package
28-pin SOP (450 mil) plastic package: LC35256FM
28-pin TSOP (8 × 13.4 mm) plastic package: LC35256FT
1
22
28
7
0.55
0.2
0.125
8.1
SANYO: TSOP28 (Type I)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
52600RM (OT) No. 6302-1/7
LC35256FM, FT-55U/70U
Pin Assignment (Top view)
SOP28D
TSOP28
OE
22
23
24
25
26
27
28
1
2
3
4
5
21
20
19
18
17
16
15
14
13
12
11
10
9
A
10
A
A
1
2
28
V
14
CC
A
CE
I/O
11
A
9
27 WE
8
12
A
8
I/O
I/O
I/O
I/O
7
6
5
4
A
A
A
A
A
A
A
A
3
26
25
24
23
A
A
A
A
A
WE
7
6
5
4
3
2
1
0
13
8
13
4
V
A
A
CC
14
12
GND
5
9
I/O
3
A
A
A
A
A
I/O
2
7
6
5
4
3
6
11
I/O
1
A
0
7
22 OE
21
6
7
A
1
8
A
2
8
A
10
9
20 CE
19 I/O
LC35256FT
10
8
I/O 11
1
18 I/O
17 I/O
16 I/O
15 I/O
7
6
5
4
I/O 12
2
I/O 13
3
GND 14
LC35256FM
Block Diagram
A
6
7
8
9
A
A
A
V
CC
Memory cell array
A
A
A
A
A
10
11
12
13
14
512 × 512
GND
Column I/O
circuit
I/O
I/O
Output
data
buffer
1
8
Column decoder
Address buffer
A
A A A A A
1 2 3 4 5
0
CE
WE
OE
No. 6302-2/7
LC35256FM, FT-55U/70U
Pin Functions
A0 to A14
WE
Address input
Read/write control input
Output enable input
Chip enable input
Data I/O
OE
CE
I/O1 to I/O8
VCC, GND
Power supply, ground
Function Table
Mode
Read cycle
Write cycle
CE
L
OE
L
WE
H
I/O
Supply current
Data output
ICCA
ICCA
ICCA
ICCS
L
X
L
Data input
Output disable
Unselected
L
H
H
High impedance
High impedance
H
X
X
Specifications
Absolute Maximum Ratings
Parameter
Maximum supply voltage
Input pin voltage
Symbol
Conditions
Ratings
Unit
V
VCC max
VIN
7.0
–0.3* to VCC + 0.3
–0.3 to VCC + 0.3
–40 to +85
V
I/O pin voltage
VI/O
V
Operating temperature
Storage temperature
Topr
Tstg
°C
°C
–55 to +125
Note: * The minimum value is –3.0 V for pulse widths under 30 ns.
I/O Capacitances at Ta = 25°C, f = 1 MHz
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
10
10
I/O pin capacitance
Input pin capacitance
CI/O
CI
VI/O = 0 V
VIN = 0 V
6
6
pF
pF
Note: All units are not tested; only samples are tested.
DC Allowable Operating Ranges at Ta = –40 to +85°C, V = 4.5 to 5.5 V
CC
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
4.5
max
Supply voltage
Input voltage
VCC
VIH
VIL
5.0
5.5
VCC + 0.3
+0.8
V
V
V
2.2
–0.3*
Note: * The minimum value is –3.0 V for pulse widths under 30 ns.
No. 6302-3/7
LC35256FM, FT-55U/70U
DC Electrical Characteristics at Ta = –40 to +85°C, V = 4.5 to 5.5 V
CC
Ratings
Parameter
Input leakage current
Symbol
ILI
Conditions
Unit
µA
min
–1.0
typ*
max
+1.0
VIN = 0 to VCC
VCE = VIH or VOE = VIH or VWE = VIL,
I/O = 0 to VCC
Output leakage current
ILO
–1.0
2.4
+1.0
µA
V
Output high-level voltage
Output low-level voltage
VOH
VOL
IOH = –1.0 mA
V
V
IOL = 2.0 mA
0.4
5.0
45
ICCA2
VCE = VIL, II/O = 0 mA, VIN = VIH or VIL
mA
LC35256FM, FT-55U
40
35
Min.
cycle
VCE = VIL, VIN = VIH
or VIL, II/O = 0 mA,
Duty 100 %
Operating current drain
TTL inputs
ICCA3
LC35256FM, FT-70U
40
mA
1 µs cycle
3.5
6.0
Ta ≤ 25°C
Ta ≤ 60°C
Ta ≤ 70°C
Ta ≤ 85°C
0.05
1.5
3.0
5.0
1.0
VCC – 0.2 V/
0.2 V inputs
V
V
CE ≥ VCC – 0.2 V,
IN = 0 to VCC
Standby mode
current drain
ICCS1
µA
ICCS2
VCE = VIH, VIN = 0 to VCC
mA
TTL inputs
Note: * Reference values when VCC = 5 V and Ta = 25°C.
AC Electrical Characteristics at Ta = –40 to +85°C, V = 4.5 to 5.5 V
CC
AC test conditions
Input pulse voltage levels: V = 2.4 V V = 0.6 V
IH
,
IL
Input rise and fall times: 5 ns
Input and output timing levels: 1.5 V
Output load: 30 pF + 1 TTL gate (including the jig capacitance)
Read Cycle
LC35256FM, FT
Parameter
Symbol
-55U
-70U
Unit
min
max
min
max
Read cycle time
tRC
tAA
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
CE access time
55
55
30
70
tCA
70
35
OE access time
tOA
Output hold time
tOH
10
5
10
10
5
CE output enable time
OE output enable time
CE output disable time
OE output disable time
tCOE
tOOE
tCOD
tOOD
5
20
20
30
25
Write Cycle
LC35256FM, FT
Parameter
Symbol
-55U
-70U
Unit
min
max
min
max
Write cycle time
tWC
tAS
55
0
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time
Write pulse width
CE setup time
tWP
40
50
0
50
60
0
tCW
tWR
tWR1
tDS
Write recovery time
CE write recovery time
Data setup time
0
0
25
0
30
0
Data hold time
tDH
CE data hold time
WE output enable time
WE output disable time
tDH1
tWOE
tWOD
0
0
5
5
20
30
No. 6302-4/7
LC35256FM, FT-55U/70U
Timing Charts
1
[Read cycle] *
t
RC
A
A
0 to 14
t
t
OH
AA
t
CA
CE
t
t
t
COD
OOD
COE
t
OA
OE
t
OOE
*5
Output data valid
D
1 to D
8
OUT
OUT
6
[Write cycle 1] (WE write) *
t
WC
A
to A
14
0
4
t
*
CW
CE
3
t
*
t
WR
t
WP
AS
WE
t
t
WOE
WOD
*5
*7
D
1 to D
OUT
8
OUT
t
t
DH
DS
D
1 to D
8
Data in stable
*2
*2
IN IN
6
[Write cycle 2] (CE write) *
t
WC
A
to A
14
0
4
t
*
t
CW
AS
CE
t
WR1
3
t
*
WP
WE
High impedance
*5
D
1 to D
OUT
8
OUT
t
t
DH1
DS
D
1 to D
8
Data in stable
IN IN
No. 6302-5/7
LC35256FM, FT-55U/70U
Notes:1. WE must be held at the high level during the read cycle.
2. Do not apply reverse phase signals to the DOUT pins when those pins are in the output state.
3. The time tWP is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs
first.
4. The time tCW is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first.
5. The DOUT pins will be in the high-impedance state if any one of the following hold: OE is at the high level, CE is at the high level, or WE is at the low
level.
6. The OE pin must be either held high or held low during the write cycle.
7. DOUT has the same phase as the write data during this write cycle.
Circuit Design Notes
When designing application circuits, always take the following into consideration and design the circuits so that the
absolute maximum ratings are never exceeded.
• Supply voltage fluctuations
• Sample-to-sample variations in the electrical characteristics of the electronic components used, including
semiconductor devices, resistors, and capacitors.
• Ambient temperature
• Variations in the input and clock signals
• The application of abnormal pulses
Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable
operating range is specified.
When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which
intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused
input pins as specified in the device documentation.
Data Retention Conditions at Ta = –40 to +85°C
Parameter
Symbol
VDR
Conditions
min
2.0
typ*
max
5.5
Unit
V
Data retention supply voltage
VCE ≥ VCC – 0.2 V
Ta ≤ 25°C
0.02
VCC = 3.0 V
Ta ≤ 60°C
Ta ≤ 70°C
Ta ≤ 85°C
1.0
2.0
3.5
Data retention supply current
ICCDR
µA
V
CE ≥ VCC – 0.2 V
Chip enable setup time
Chip enable hold time
tCDR
tR
0
ns
ns
t
RC**
Note: * Reference values for VCC = 3 V, Ta = 25°C.
** tRC: Read cycle time
Data Retention Waveforms
Data retention mode
t
t
CDR
R
V
CC
V
*
CCL
V
IH
V
DR
V
CE
GND
V
≥ V
– 0.2 V
CC
CE
Note: * VCCL 5 V operation: 4.5 V
No. 6302-6/7
LC35256FM, FT-55U/70U
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of May, 2000. Specifications and information herein are subject to
change without notice.
PS No. 6302-7/7
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