LB11870_07 [SANYO]
For Polygonal Mirror Motors Three-Phase Brushless Motor Driver; 对于多面反射镜电机三相无刷电机驱动器
| 型号： | LB11870_07 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | For Polygonal Mirror Motors Three-Phase Brushless Motor Driver |
| 文件： | 总14页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN7256A
Monolithic Digital IC
For Polygonal Mirror Motors
LB11870
Three-Phase Brushless Motor Driver
Overview
The LB11870 is a three-phase brushless motor driver developed for driving the motors used with the polygonal
mirror in laser printers and plain paper copiers. It can implement, with a single IC chip, all the circuits required
for polygonal mirror drive, including speed control and driver functions. The LB11870 can implement motor drive
with minimal power loss due to its use of direct PWM drive.
Functions
• Three-phase bipolar drive
• Direct PWM drive
• Includes six high and low side diodes on chip.
• Output current control circuit
• PLL speed control circuit
• Phase lock detection output (with masking function)
• Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip.
• Deceleration type switching circuit (free running or reverse torque)
• PWM oscillator
• Power saving circuit
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
62707 MS IM B8-9164 / 80102 AS (OT) No.7256-1/14
LB11870
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage
V
max
30
2.3
CC
Output current
I
max
T ≤ 500ms *1
A
O
Allowable power dissipation 1
Allowable power dissipation 2
Operating temperature
Storage temperature
Pd max1
Independent IC
0.85
W
W
°C
°C
Pd max2
Topr
Mounted on a circuit board *2
1.72
-20 to +80
-55 to +150
Tstg
Note *1: Be sure to perform derating from the standard value by 20% or more before use.
Note *2: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage range
V
9.5 to 28
0 to -20
0 to 28
0 to 15
0 to 28
0 to 10
CC
5V constant voltage output current
LD pin applied voltage
LD pin output current
IREG
VLD
ILD
mA
V
mA
V
FGS pin applied voltage
FGS pin output current
VFG
IFG
mA
Electrical Characteristics at Ta = 25°C, V
= VM = 24V
CC
Ratings
typ
Parameter
Symbol
Conditions
unit
min
max
21
Supply current 1
I
I
1
2
16
mA
mA
CC
Supply current 2
3.5
5.0
In stop mode
CC
[5V constant voltage output circuit]
Output voltage
VREG
4.65
5.0
80
10
0
5.35
130
60
V
Voltage regulation
ΔVREG1
ΔVREG2
ΔVREG3
mV
mV
V
=9.5 to 28V
CC
Load regulation
I
=-5 to -20mA
O
Temperature coefficient
mV/°C
Design target value*
[Output Block]
Output saturation voltage 1
Output saturation voltage 2
V
V
I
sat1
sat2
leak
1.9
2.6
2.4
3.2
100
1.3
1.8
1.6
2.4
V
I
I
=0.5A, V (SINK)+V (SOURCE)
O O
O
O
V
μA
V
=1.2A, V (SINK)+V (SOURCE)
O
O
O
O
Output leakage current
Lower diode forward voltage 1
Lower diode forward voltage 2
Upper diode forward voltage 1
Upper diode forward voltage 2
[Hall Amplifier Block]
O
VD1-1
VD1-2
VD2-1
VD2-2
1.0
1.4
1.2
1.9
ID=-0.5A
ID=-1.2A
ID=0.5A
ID=1.2A
V
V
V
IHB
-2
0
-0.5
μA
V
Input bias current
VICM
VREG-2.0
42
Common-mode input voltage range
Hall input sensitivity
80
15
mVp-p
mV
ΔV (HA)
24
12
Hysteresis width
IN
VSLH
VSHL
mV
Input voltage: Low to high
Input voltage: High to low
[FG Schmitt Block]
-12
mV
IB(FGS)
-2
0
-0.5
μA
V
Input bias current
VICM(FGS)
VREG-2.0
42
Common-mode input voltage range
Input sensitivity
V
(FGS)
80
15
mVp-p
mV
IN
ΔV (FGS)
24
12
Hysteresis width
IN
VSLH(FGS)
VSHL(FGS)
mV
Input voltage: Low to high
Input voltage: High to low
-12
mV
*: These value are design guarantee values, and are not tested.
Continued on next page.
No.7256-2/14
LB11870
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
unit
min
max
[PWM Oscillator]
V
(PWM)
2.65
0.9
2.95
3.25
1.5
V
V
High-level output voltage
Low-level output voltage
OH
V
(PWM)
1.2
-45
OL
External capacitor charge
current
ICHG
VPWM=2V
C=680pF
-60
-30
μA
f(PWM)
34
kHz
Oscillator frequency
Amplitude
V(PWM)
1.45
1.75
2.05
Vp-p
[FGS Output]
0.15
0.5
10
V
Output saturation voltage
Output leakage current
[CSD Oscillator Circuit]
High-level output voltage
Low-level output voltage
Amplitude
V
(FGS)
IFGS=7mA
OL
μA
IL(FGS)
V
=V
CC
O
V
(CSD)
3.2
0.9
3.5
1.1
3.8
1.3
V
V
OH
V
(CSD)
OL
V(CSD)
ICHG1
2.15
2.4
2.65
-5.5
Vp-p
μA
External capacitor charge
current
-13.5
-9.5
External capacitor charge
current
ICHG2
f(CSD)
6
10
29
14
μA
Hz
Oscillator frequency
[Phase Comparator Output]
High-level output voltage
Low-level output voltage
Output source current
Output sink current
[Lock Detection Output]
Output saturation voltage
Output leakage current
[Error Amplifier Block]
Input offset voltage
Input bias current
C=0.068μF
VPDH
VPDL
IPD+
IPD-
VREG-0.2
1.5
VREG-0.1
0.2
V
V
I
I
=-100μA
OH
0.3
=100μA
OL
-0.5
mA
mA
VPD=VREG/2
VPD=VREG/2
V
(LD)
0.15
0.5
10
V
ILD=10mA
OL
IL(LD)
μA
V
=V
CC
O
V
(ER)
-10
-1
10
1
mV
μA
V
Design target value*
IO
IB(ER)
(ER)
V
VREG-1.2
VREG-0.9
0.9
Output H level voltage
Output L level current
DC bias level
I
I
=-500μA
OH
OH
V
(ER)
1.2
5%
V
=500μA
OL
OL
VB(ER)
-5%
VREG/2
V
[Current limiter Circuit]
Drive gain 1
GDF1
GDF2
VRF
0.4
0.8
0.5
1.0
0.5
0.6
1.2
deg
deg
V
When the phase is locked
When not locked
Drive gain 2
0.45
0.55
Limiter voltage
V
-VM
CC
[Thermal Shutdown Operation]
Thermal shutdown operating
temperature
TSD
Design target value*
(junction temperature)
Design target value*
(junction temperature)
150
175
40
°C
°C
ΔTSD
Hysteresis width
[Low-Voltage Protection]
Operating voltage
VSD
8.1
0.2
8.45
0.35
8.9
0.5
V
V
ΔVSD
Hysteresis width
*: These value are design guarantee values, and are not tested.
Continued on next page.
No.7256-3/14
LB11870
Continued from preceding page.
Ratings
typ
Parameter
Symbol
ICLD
Conditions
unit
min
max
[CLD Circuit]
External capacitor charge
current
-6
-4.3
-3
μA
V
(CLD)
3.25
3.5
3.75
V
Operating voltage
H
[CLK Pin]
fI(CLK)
(CLK)
0.1
3.5
0
10
kHz
V
External input frequency
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
V
VREG
1.5
IH
V
V
(CLK)
(CLK)
V
IL
VREG-0.5
0.35
VREG
0.65
10
V
IO
V
(CLK)
0.5
0
V
IS
I
(CLK)
IH
-10
μA
μA
High-level input current
Low-level input current
[S/S Pin]
VCLK=VREG
VCLK=0V
I
(CLK)
IL
-280
-210
V
(SS)
(SS)
(SS)
3.5
0
VREG
1.5
V
V
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
IH
V
V
IL
VREG-0.5
0.35
VREG
0.65
10
V
IO
V
(SS)
0.5
0
V
IS
I
(SS)
IH
-10
μA
μA
High-level input current
Low-level input current
[BRSEL Pin]
VS/S=VREG
VS/S=0V
I
(SS)
-280
-210
IL
V
(BRSEL)
3.5
0
VREG
1.5
V
V
High-level input voltage
Low-level input voltage
Input open voltage
High-level input current
Low-level input current
IH
V
V
(BRSEL)
(BRSEL)
IL
VREG-0.5
-10
VREG
10
V
IO
I
(BRSEL)
IH
0
μA
μA
V
V
=VREG
BRSEL
I
(BRSEL)
IL
-220
-160
=0V
BRSEL
Package Dimensions
unit : mm (typ)
3278
Pd max - Ta
Mounted on a board
(114.3 × 76.1 × 1.6mm, glass epoxy)
17.8
2.0
1.6
1.2
0.8
(6.2)
1.72W
48
25
0.963W
Independent IC
0.85W
1
24
0.2
1.3
0.65
0.2
0.476W
(0.45)
0.4
0
-20
0
20
40
60
80
100
ILB01545
Ambient temperature, Ta - °C
1.5
SANYO : HSSOP48(375mil)
No.7256-4/14
LB11870
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37
36 35 34 33 32 31 30 29 28 27 26 25
LB11870
1
2
3
4
5
6
7
8
9
10
13 14 15 16 17 18 19 20 21 22
11 12
23 24
Three-Phase Logic Truth Table (IN = [H] indicates a condition in which: IN+ > IN–)
IN1
H
H
H
L
IN2
IN3
H
L
OUT1
OUT2
OUT3
L
L
L
H
M
L
M
H
H
M
L
L
H
H
H
L
L
M
H
H
M
L
L
L
H
H
M
H
L
L
No.7256-5/14
LB11870
Block Diagram and Application Circuit Example
VREG
VREG
FGFIL
FGS
LD
CLD
PD
FGIN–
FGIN+
LD
LDMASK
–
+
FG
FILTER
EI
VREG
–
EO
+
CLK
PLL
TOC
CLK
TSD
VREG
VREG
PWM
S/S
PWM
OSC
CONT
AMP
FC
PH
COMP
S/S
PEAK
HOLD
VCC
VCC2
VCC1
BRSEL
CSD
BRSEL
CURR
LIM
LOGIC
VM2
VM1
OUT1
Rf
CSD
OSC
COUNT
HALL LOGIC
DRIVER
OUT2
OUT3
HALL
HYS AMP
IN1+ IN1– IN2+ IN2– IN3+ IN3–
GND1 GND2
GND3
VREG
No.7256-6/14
LB11870
Pin Functions
Pin No.
Symbol
Pin Description
Motor drive output
Equivalent Circuit
3
1
OUT1
OUT2
OUT3
GND3
39
38
37
V
1
CC
46
44
300Ω
Output block ground
37
38
VM1
VM2
Output block power supply and current
detection.
Insert the resistor Rf between this pin and
1
3
46
V
1.
CC
The output current will be limited to the current
value
I
= VRF/Rf.
OUT
39
V
2
Upper diode cathode connection. Short this pin
CC
44
to V 1.
CC
11
12
9
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
Hall element inputs.
VREG
The high state is when IN+ is greater than IN-,
and the low state is the reverse.
10
6
An amplitude of at least 100mVp-p (differential)
is desirable for the Hall element signal inputs. If
noise on the Hall signals is a problem, insert
capacitors between the IN+ and IN- inputs.
8
300Ω
300Ω
6
9
11
8
10 12
13
14
FG
+
FG input.
IN
VREG
FG
-
If noise on the FG signal input is a problem,
connect a filter consisting of either a capacitor
or a capacitor and a resistor.
IN
300Ω
300Ω
13
14
15
16
17
GND1
GND2
PWM
Control circuit block ground
SUBGND pin
Sets the PWM oscillator frequency.
VREG
Insert a capacitor between this pin and ground.
The PWM oscillator frequency is set to about
34kHz when a 680pF capacitor is used.
200Ω
17
Continued on next page.
No.7256-7/14
LB11870
Continued from preceding page.
Pin No.
19
Symbol
FC
Pin Description
Equivalent Circuit
Frequency characteristics correction for the
current control circuit.
VREG
Insert a capacitor (about 0.01 to 0.1μF)
between this pin and ground.
The output duty is determined by comparing
the voltage on this pin to the PWM oscillator
waveform.
300Ω
19
21
PD
Phase comparator output.
VREG
The phase error is converted to a pulse duty
and output from this pin.
300Ω
21
22
EI
Error amplifier input.
VREG
300Ω
22
23
EO
Error amplifier output.
VREG
23
24
TOC
Torque command voltage input.
VREG
This pin is normally connected to the EO pin.
When the TOC voltage falls, the lower output
transistor on duty is increased.
300Ω
24
Continued on next page.
No.7256-8/14
LB11870
Continued from preceding page.
Pin No.
25
Symbol
FGFIL
Pin Description
FG filter connection.
Equivalent Circuit
VREG
If noise on the FG signal input is a problem,
insert a capacitor (up to about 2200pF)
between this pin and ground.
25
26
CSD
Sets the rotor constraint protection circuit
operating time and the initial reset pulse.
A protection operating time of about 8 seconds
can be set by insert a capacitor of about
0.068μF between this pin and ground. If the
rotor constraint protection circuit is not used,
insert a resistor and a capacitor in parallel
between this pin and ground. (Values: about
220kΩ and 4700pF)
VREG
300Ω
26
27
CLD
Sets the phase lock state signal mask time.
A mask time of about 90ms can be set by
inserting a capacitor of about 0.1μF between
this pin and ground.
VREG
Leave this pin open if masking is not required.
300Ω
27
28
29
28
FGS
FG Schmitt output.
VREG
29
LD
Phase lock state detection output.
This output goes to the on state (low level)
when the phase is locked.
VREG
Continued on next page.
No.7256-9/14
LB11870
Continued from preceding page.
Pin No.
32
Symbol
S/S
Pin Description
Start/stop control input.
Equivalent Circuit
VREG
VREG
VREG
Low: 0 to 1.5V
High: 3.5V to VREG
Hysteresis: 0.5V
Low: start.
This pin goes to the high level when open.
2kΩ
2kΩ
2kΩ
32
33
34
33
34
35
CLK
BRSEL
PH
Clock input.
Low: 0 to 1.5V
High: 3.5V to VREG
Hysteresis: 0.5V
f
= 10kHz (maximum)
CLK
If noise is a problem, use a capacitor to remove
that noise at this input.
Deceleration switching control input.
Low: 0 to 1.5V
High: 3.5V to VREG
This pin goes to the high level when open.
Low: reverse torque control, High: free running.
An external Schottky barrier diode is required
on the output low side if reverse torque control
is used.
RF waveform smoothing.
VREG
If noise on the RF waveform is a problem,
insert a capacitor between this pin and ground.
500Ω
35
Continued on next page.
No.7256-10/14
LB11870
Continued from preceding page.
Pin No.
36
Symbol
VREG
Pin Description
Equivalent Circuit
Stabilized power supply output (5V output).
Insert a capacitor of about 0.1μF between this
pin and ground for stabilization.
V
CC
36
40
V
1
Power supply.
CC
Insert a capacitor of at least 10µF between this
pin and ground to prevent noise from entering
the IC.
2, 4, 5
7, 18
NC
Since these pins are not connected to the IC
internally, they can be used for wiring
connections.
20, 30
31, 41
42, 43
45, 47
48
FRAME
Connect this pin to ground.
Overview of the LB11870
1. Speed Control Circuit
This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (falling edges
on the FGIN+ and FGS signals), and the IC uses the detected error to control motor speed.
During this control operation, the FG servo frequency will be the same as the CLK frequency.
f
(servo) = f
CLK
FG
2. Output Drive Circuit
To minimize power loss in the output circuits, this IC adopts a direct PWM drive technique. The output transistors
are always saturated when on, and the IC adjusts the motor drive output by changing the output on duty. The low side
output transistor is used for the output PWM switching.
Both the high and low side output diodes are integrated in the IC. However, if reverse torque control mode is selected
for use during deceleration, or if a large output current is used and problems occur (such as incorrect operation or
waveform disruption due to low side kickback), a Schottky diode should be inserted between OUT and ground. Also,
if it is necessary to reduce IC heating during steady-state (constant speed) operation, it may be effective to insert a
Schottky diode between V
and OUT. (This is effective because the load associated with the regenerative current
CC
during PWM switching is born not by the on-chip diode but by the external diode.)
3. Current Limiter Circuit
The current limiter circuit limits the peak level of the current to a level determined by I = VRF/Rf (where VRF =
0.5V (typical) and Rf is the value of the current detection resistor). The current limiter operates by reducing the
output on duty to suppress the current.
The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the
current limiting function does not malfunction, its operation has a delay of about 2μs. If the motor coils have a low
resistance or a low inductance, current fluctuations at startup (when there is no reactive power in the motor) will be
rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above
the set current. Designers must take this increase in the current due to the delay into account when setting the current
limiter value.
No.7256-11/14
LB11870
4. Power Saving Circuit
This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is
implemented by removing the bias current from most of the circuits in the IC. However, the 5V regulator output is
provided in the power saving state.
5. Reference Clock
Care must be taken to assure that no chattering or other noise is present on the externally input clock signal.
Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor.
If the IC is set to the start state when the reference clock signal is not present, if the rotor constraint protection circuit
is used, the motor will turn somewhat and then motor drive will be shut off. However, if the rotor constraint
protection circuit is not used, and furthermore reverse torque control mode is selected for deceleration, the motor will
be driven at ever increasing speed in the reverse direction. (This is because the rotor constraint protection circuit
oscillator signal is used for clock cutoff protection.) Applications must implement a workaround for this problem if
there is any possibility whatsoever for it to occur.
6. Notes on the PWM Frequency
The PWM frequency is determined by the value of the capacitor C (in F) connected to the PWM pin.
f
≈ 1 / (43000 × C)
PWM
If a 680pF capacitor is used, the circuit will oscillate at about 34kHz. If the PWM frequency is too low, the motor
will emit switching noise, and if it is too high, the power loss in the output will be excessive. A PWM frequency in
the range 15 to 50kHz is desirable. To minimize the influence of the output on this circuit, the ground lead of this
capacitor should be connected as close as possible to the IC control system ground (the GND1 pin).
7. Hall Input Signals
Signals with an amplitude in excess of the hysteresis (42mV maximum) must be provided as the Hall input signals.
However, an amplitude of over 100mV is desirable to minimize the influence of noise. If the output waveforms are
disturbed (at phase switching) due to noise on the Hall inputs, insert capacitors across these inputs.
8. FG Input Signal
Normally, one phase of the Hall signals is input as the FG signal. If noise is a problem the input must be filtered with
either a capacitor or an RC filter circuit. Although it is also possible to remove FG signal noise by inserting a
capacitor between the FGFIL pin and ground, the IC may not be able to operate correctly if this signal is damped
excessively. If this capacitor is used, its value must be less than about 2200pF. If the location of this capacitor's
ground lead is inappropriate, it may, inversely, make noise problems even more likely to occur. Thus the ground lead
location must be chosen carefully.
9. Rotor Constraint Protection Circuit
This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is
constrained. If the LD output is high (unlocked) for over a certain fixed period with the IC in the start state, the low
side transistor will be turned off. The time constant is determined by the capacitor connected to the CSD pin.
<time constant (in seconds)> ≈ 120 × C (μF)
If a 0.068μF capacitor is used, the protection time will be about 8 seconds. The set time must be selected to have an
adequate margin with respect to the motor startup time. This protection circuit will not operate during deceleration
when the clock frequency is switched. To clear the rotor constraint protection state, the IC must be set to the stopped
state or the power must be turned off and reapplied.
Since the CSD pin also functions as the initial reset pulse generation pin at startup, the logic circuit will go to the
reset state and the IC will not be able to function if this pin is connected to ground. Therefore, both a 220kΩ resistor
and a 4700pF capacitor must be inserted between this pin and ground if the rotor constraint protection circuit is not
used.
No.7256-12/14
LB11870
10. Phase Lock Signal
(1) Phase lock range
Since this IC does not include a counter or similar functionality in the speed control system, the speed error range
in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of
the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the
motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in
states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in
at startup and when unlocked due to switching clock frequencies.
(2) Masking function for the phase lock state signal
A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock
pullin. However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CLD pin and ground.
<masking time (seconds)> ≈ 0.9 × C (μF)
When a 0.1μF capacitor is used, the masking time will be about 90ms. In cases where complete masking is
required, a masking time with fully adequate margin must be used. If no masking is required, leave the CLD pin
open.
11. Power Supply Stabilization
Since this IC provides a large output current and adopts a switching drive technique, the power supply line level can
be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the
V
pins and ground. The ground leads of these capacitors must be connected to the three pins that are the power
CC
grounds, and they must be connected as close as possible to the pins themselves. If these capacitors (electrolytic
capacitors) cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1μF must be
connected near these pins.
If reverse torque control mode is selected for use during deceleration, since there are states where power is returned
to the power supply system, the power supply line levels will be particularly easily disrupted. Since the power line
level is most easily disrupted during lock pull-in at high motor speeds, this state needs extra attention; in particular,
capacitors that are adequately large to handle this situation must be selected.
If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected
with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors
must be used.
12. VREG Stabilization
A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply.
The ground lead of that capacitor must be connected as close as possible to the IC control system ground (GND1).
13. Error Amplifier External Component Values
To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC
as possible. In particular, they must be located as far from the motor as possible.
14. FRAME Pin and the IC Metallic Rear Surface
The FRAME pin must be connected to the GND1 and GND2 pins, and the ground side of the electrolytic capacitor
must be connected to GND3. The IC's metallic rear surface is connected to the FRAME pin internally to the IC.
Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC
package to the PCB with, for example, a solder with good thermal conductivity.
No.7256-13/14
LB11870
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of June, 2007. Specifications and information herein are subject
to change without notice.
No.7256-14/14
PS
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