LC35W256EM-10W [SANYO]

256K (32K words x 8 bits) SRAM Control pins: OE and CE; 256K ( 32K字× 8位) SRAM控制引脚: OE和CE
LC35W256EM-10W
型号: LC35W256EM-10W
厂家: SANYO SEMICON DEVICE    SANYO SEMICON DEVICE
描述:

256K (32K words x 8 bits) SRAM Control pins: OE and CE
256K ( 32K字× 8位) SRAM控制引脚: OE和CE

静态存储器
文件: 总6页 (文件大小:49K)
中文:  中文翻译
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Ordering number : ENN6304  
CMOS IC  
LC35W256EM, ET-10W  
256K (32K words × 8 bits) SRAM  
Control pins: OE and CE  
Overview  
Package Dimensions  
unit: mm  
The LC35W256EM-10W and LC35W256ET-10W are  
asynchronous silicon-gate CMOS SRAMs with a 32768-  
word by 8-bit structure. These are full-CMOS devices  
with 6 transistors per memory cell, and feature ultralow-  
voltage operation, a low operating current drain, and an  
ultralow standby current. Control inputs include OE for  
fast memory access and CE for power saving and device  
selection. This makes these devices optimal for systems  
that require low power or battery backup, and makes  
memory expansion easy. The ultralow standby current  
allows these devices to be used with capacitor backup as  
well.  
3187A-SOP28D  
[LC35W256EM-10W]  
0.15  
15  
28  
1
14  
18.0  
0.4  
Features  
1.27  
• Supply voltage range: 2.7 to 3.6 V  
• Access time: 100 ns (maximum)  
• Standby current: 0.8 µA (Ta 60°C)  
4.0 µA (Ta 70°C)  
• Operating temperature: –10 to +70°C  
• Data retention voltage: 2.0 to 3.6 V  
SANYO: SOP28D  
unit: mm  
3221-TSOP28 (Type I)  
[LC35W256ET-10W]  
• All I/O levels: CMOS compatible (0.8 V , 0.2 V  
)
CC  
CC  
• Input/output shared function pins, 3-state output pins  
• No clock required (fully static circuits)  
• Package  
21  
8
28-pin SOP (450 mil) plastic package:  
LC35W256EM-10W  
28-pin TSOP (8 × 13.4 mm) plastic package:  
LC35W256ET-10W  
1
22  
28  
7
0.55  
0.2  
0.125  
8.1  
SANYO: TSOP28 (Type I)  
Any and all SANYO products described or contained herein do not have specifications that can handle  
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s  
control systems, or other applications whose failure can be reasonably expected to result in serious  
physical and/or material damage. Consult with your SANYO representative nearest you before using  
any SANYO products described or contained herein in such applications.  
SANYO assumes no responsibility for equipment failures that result from using products at values that  
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other  
parameters) listed in products specifications of any and all SANYO products described or contained  
herein.  
SANYO Electric Co.,Ltd. Semiconductor Company  
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN  
12800RM (OT) No. 6304-1/6  
LC35W256EM, ET10W  
Pin Assignment (Top view)  
SOP28  
TSOP28  
OE  
22  
23  
24  
25  
26  
27  
28  
1
2
3
4
5
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
A
10  
A
A
1
2
28 V  
14  
12  
CC  
A
CE  
I/O  
11  
A
9
27 WE  
8
A
8
I/O  
I/O  
I/O  
I/O  
7
6
5
4
A
A
A
A
A
A
A
A
3
26 A  
13  
A
WE  
7
6
5
4
3
2
1
0
13  
4
25 A  
24 A  
23 A  
8
V
A
A
CC  
14  
12  
GND  
5
9
I/O  
3
A
A
A
A
A
I/O  
2
7
6
5
4
3
6
11  
I/O  
1
A
0
7
22 OE  
21 A  
6
7
A
1
8
A
2
8
10  
9
20 CE  
LC35W256ET-10W  
10  
19 I/O  
18 I/O  
17 I/O  
16 I/O  
15 I/O  
8
7
6
5
4
I/O 11  
1
I/O 12  
2
I/O 13  
3
GND 14  
LC35W256EM-10W  
Block Diagram  
A
A
A
A
6
7
8
9
V
CC  
Memory cell array  
A
10  
11  
12  
13  
14  
512 × 512  
GND  
A
A
A
A
Column I/O  
circuit  
I/O  
I/O  
Output  
data  
buffer  
1
8
Column decoder  
Address buffer  
A
A A A A A  
1 2 3 4 5  
0
CE  
WE  
OE  
No. 6304-2/6  
LC35W256EM, ET10W  
Pin Functions  
A0 to A14  
WE  
Address input  
Read/write control input  
Output enable input  
Chip enable input  
Data I/O  
OE  
CE  
I/O1 to I/O8  
VCC, GND  
Power supply, ground  
Function Table  
Mode  
CE  
L
OE  
L
WE  
H
I/O  
Supply current  
Read cycle  
Write cycle  
Output disable  
Unselected  
Data output  
ICCA  
ICCA  
ICCA  
ICCS  
L
X
L
Data input  
L
H
H
High impedance  
High impedance  
H
X
X
Specifications  
Absolute Maximum Ratings  
Parameter  
Maximum supply voltage  
Input pin voltage  
Symbol  
Conditions  
Ratings  
Unit  
V
VCC max  
VIN  
4.6  
–0.3* to VCC + 0.3  
–0.3 to VCC + 0.3  
–10 to +70  
V
I/O pin voltage  
VI/O  
V
Operating temperature  
Storage temperature  
Topr  
Tstg  
°C  
°C  
–55 to +125  
Note: * The minimum value is –2.0 V for pulse widths under 30 ns.  
I/O Capacitances at Ta = 25°C, f = 1 MHz  
Ratings  
Parameter  
Symbol  
Conditions  
Unit  
min  
typ  
max  
10  
10  
I/O pin capacitance  
Input pin capacitance  
CI/O  
CI  
VI/O = 0 V  
VIN = 0 V  
6
6
pF  
pF  
Note: All units are not tested; only samples are tested.  
DC Allowable Operating Ranges at Ta = –10 to +70°C, V = 2.7 to 3.6 V  
CC  
Ratings  
typ  
Parameter  
Symbol  
Conditions  
Unit  
min  
2.7  
max  
Supply voltage  
Input voltage  
VCC  
VIH  
VIL  
3.0  
3.6  
VCC + 0.3  
0.2VCC  
V
V
V
0.8VCC  
–0.3*  
Note: * The minimum value is –2.0 V for pulse widths under 30 ns.  
No. 6304-3/6  
LC35W256EM, ET10W  
DC Electrical Characteristics at Ta = –10 to +70°C, V = 2.7 to 3.6 V  
CC  
Ratings  
typ  
Parameter  
Input leakage current  
Symbol  
ILI  
Conditions  
Unit  
µA  
min  
–1.0  
max  
+1.0  
VIN = 0 to VCC  
VCE = VIH or VOE = VIH or VWE = VIL  
I/O = 0 to VCC  
Output leakage current  
Output high-level voltage  
ILO  
–1.0  
+1.0  
µA  
V
VOH1  
VOH2  
VOL1  
VOL2  
ICCA2  
IOH1 = –2.0 mA  
V
V
– 0.4  
– 0.1  
V
V
CC  
IOH2 = –100 µA  
CC  
IOL1 = 2.0 mA  
0.4  
0.4  
1.2  
18  
V
Output low-level voltage  
Operating current drain  
IOL2 = 100 µA  
V
VCE = VIL, II/O = 0 mA, VIN = VIH or VIL  
mA  
mA  
mA  
µA  
µA  
µA  
mA  
CMOS inputs  
min cycle  
15  
1.5  
VCE = VIL, VIN = VIH or VIL  
II/O = 0 mA, DUTY 100 %  
ICCA3  
1 µs cycle  
Ta 25°C  
Ta 60°C  
Ta 70°C  
2.5  
0.01  
V
V
CE VCC – 0.2 V,  
VCC – 0.2 V/  
0.2 V inputs  
Standby mode  
current drain  
ICCS1  
0.8  
4.0  
0.4  
IN = 0 to VCC  
ICCS2  
VCE = VIH, VIN = 0 to VCC  
CMOS inputs  
Note: * Reference values when VCC = 3 V and Ta = 25°C.  
AC Electrical Characteristics at Ta = –10 to +70°C, V = 2.7 to 3.6 V  
CC  
AC test conditions  
Input pulse voltage levels: 0.2 V to 0.8 V  
CC  
CC  
Input rise and fall times: 5 ns  
Input and output timing levels: 1/2 V  
CC  
Output load: 30 pF (including the jig capacitance)  
Read Cycle  
Parameter  
Symbol  
tRC  
min  
100  
max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Read cycle time  
Address access time  
CE access time  
tAA  
100  
tCA  
100  
50  
OE access time  
tOA  
Output hold time  
tOH  
10  
10  
5
CE output enable time  
OE output enable time  
CE output disable time  
OE output disable time  
tCOE  
tOOE  
tCOD  
tOOD  
35  
30  
Write Cycle  
Parameter  
Symbol  
tWC  
min  
max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write cycle time  
100  
0
Address setup time  
Write pulse width  
CE setup time  
tAS  
tWP  
80  
90  
0
tCW  
Write recovery time  
CE write recovery time  
Data setup time  
tWR  
tWR1  
tDS  
0
50  
0
Data hold time  
tDH  
CE data hold time  
WE output enable time  
WE output disable time  
tDH1  
tWOE  
tWOD  
0
5
35  
No. 6304-4/6  
LC35W256EM, ET10W  
Timing Charts  
1
[Read cycle] *  
t
RC  
A
A
0 to 14  
t
t
OH  
AA  
t
CA  
CE  
OE  
t
t
t
COD  
OOD  
COE  
t
OA  
t
OOE  
5
*
Output data valid  
D
1 to 8  
OUT  
6
[Write cycle 1] (WE write) *  
t
WC  
A
A
0 to 14  
4
t
*
CW  
CE  
3
t
*
t
t
WP  
WR  
AS  
WE  
t
t
WOE  
WOD  
5
*
*7  
D
1to 8  
OUT  
t
t
DH  
DS  
D
1 to 8  
Data in stable  
*2  
*2  
IN  
6
[Write cycle 2] (CE write) *  
t
WC  
A
A
0 to 14  
4
*
t
t
CW  
AS  
CE  
t
WR1  
3
t
*
WP  
WE  
High impedance  
5
*
D
1to 8  
OUT  
t
t
DH1  
DS  
D
1 to 8  
Data in stable  
IN  
No. 6304-5/6  
LC35W256EM, ET-10W  
Notes:1. WE must be held at the high level during the read cycle.  
2. Do not apply reverse phase signals to the DOUT pins when those pins are in the output state.  
3. The time tWP is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs  
first.  
4. The time tCW is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first.  
5. The DOUT pins will be in the high-impedance state if any one of the following is held: OE is at the high level, CE is at the high level, or WE is at the  
low level.  
6. The OE pin must be either held high or held low during the write cycle.  
7. DOUT has the same phase as the write data during this write cycle.  
Data Retention Characteristics at Ta = –10 to +70°C  
Parameter  
Data retention supply voltage  
Chip enable setup time  
Symbol  
VDR  
Conditions  
min  
2.0  
max  
3.6  
Unit  
V
V
CE VCC – 0.2 V  
tCDR  
tR  
0
ns  
ns  
Chip enable hold time  
tRC*  
Note: * tRC: Read cycle time  
Data Retention Waveforms (CE control)  
Data retention mode  
t
t
R
CDR  
V
CC  
2.7 V  
V
IH  
V
DR  
V
CE  
V
V  
– 0.2 V  
CC  
CE  
GND  
Specifications of any and all SANYO products described or contained herein stipulate the performance,  
characteristics, and functions of the described products in the independent state, and are not guarantees  
of the performance, characteristics, and functions of the described products as mounted in the customer’s  
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,  
the customer should always evaluate and test devices mounted in the customer’s products or equipment.  
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all  
semiconductor products fail with some probability. It is possible that these probabilistic failures could  
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,  
or that could cause damage to other property. When designing equipment, adopt safety measures so  
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective  
circuits and error prevention circuits for safe design, redundant design, and structural design.  
In the event that any or all SANYO products (including technical data, services) described or contained  
herein are controlled under any of applicable local export control laws and regulations, such products must  
not be exported without obtaining the export license from the authorities concerned in accordance with the  
above law.  
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or  
mechanical, including photocopying and recording, or any information storage or retrieval system,  
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.  
Any and all information described or contained herein are subject to change without notice due to  
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”  
for the SANYO product that you intend to use.  
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not  
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but  
no guarantees are made or implied regarding its use or any infringements of intellectual property rights  
or other rights of third parties.  
This catalog provides information as of Januarly, 2000. Specifications and information herein are subject  
to change without notice.  
PS No. 6304-6/6  

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