LC651154N [SANYO]
Four-Bit CMOS Microcontrollers for Small-Scale Control Applications; 四位CMOS微控制器为小规模控制中的应用
| 型号： | LC651154N |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Four-Bit CMOS Microcontrollers for Small-Scale Control Applications |
| 文件： | 总39页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6728
CMOS IC
LC651154N, 651154F, 651154L, LC651152N, 651152F, 651152L
Four-Bit CMOS Microcontrollers for
Small-Scale Control Applications
Preliminary
Overview
— All ports:
· Are I/O ports
The LC651154N/F/L and the LC651152N/F/L are the
small-scale control application versions of Sanyo’s
LC6500 series of 4-bit single-chip CMOS
microcontrollers, and feature the same basic architecture
and instruction set. These microcontrollers include an 8-
input 8-bit A/D converter and are appropriate for use in a
wide range of applications, from applications with a small
number of circuits and controls that were previously
implemented in standard logic to applications with a larger
scale such as home appliances, automotive equipment,
communications equipment, office equipment, and audio
equipment such as decks and players. Also note that since
these ICs provide the same basic functions (certain
functions and specifications do differ) as, and are pin
compatible with the earlier LC651104N/F/L and
LC651102N/F/L, they can replace those ICs in most cases.
· I/O voltage handling capacity: 15 V (maximum)
(Open-drain specification C, D, E, and F ports
only)
· Output current: 20 mA (maximum) sink current
(Are capable of directly driving an LED.)
— Support options to match application system
specifications
A. Open-drain output, internal pull-up resistor
specification: All ports, in bit units
B. Output level at reset specification: Ports C and D
can be specified to go to the high or low level in
4-bit units.
• Interrupt function
— Timer interrupts through an interrupt vector (Can be
tested under program control)
— INT pin and serial I/O full/empty interrupts through
an interrupt vector (Can be tested under program
control)
• Stack levels: 8 (Shared with the interrupt system.)
• Timers: 4-bit variable prescaler and 8-bit programmable
timers
• Clock oscillator options that match a wide range of
system specifications
— Oscillator circuit options:
Two-pin RC oscillator (N and L versions)
Two-pin ceramic oscillator (N, F, and L versions)
— Clock divider circuit options:
No divider, built-in divide-by-3, built-in divide-by-4
(N and L versions)
• Continuous square wave output (with a period 64 times
the cycle time)
• A/D converter (successive approximation)
— 8-bit precision with 8 input channels
• Watchdog timer
Features
• Fabricated in a CMOS process for low power (A
standby function that can be invoked under program
control is also provided.)
• ROM/RAM
LC651154N/F/L — ROM: 4K × 8 bits,
RAM: 256 × 4 bits
LC651152N/F/L — ROM: 2K × 8 bits,
RAM: 256 × 4 bits
• Instruction set: The 80-instruction set common to the
LC6500 family
• Wide operating supply voltage range: 2.2 to 6.0 V
(L versions)
• Instruction cycle time: 0.92 µs (F versions)
• On-chip serial I/O function
• Flexible I/O ports
— Number of ports: 6 ports with a total of 22 pins
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91799RM (OT) No. 6278-1/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
— RC circuit time constant
— Optional watchdog timer reset function from an
external pin
Function Table
Parameter
ROM
LC651154N/1152N
LC651154F/1152F
LC651154L/1152L
4096 × 8 bits (1154N)
2048 × 8 bits (1152N)
4096 × 8 bits (1154F)
2048 × 8 bits (1152F)
4096 × 8 bits (1154L)
2048 × 8 bits (1152L)
Memory
RAM
256 × 4 bits (1154/1152N)
80
256 × 4 bits (1154/1152F)
80
256 × 4 bits (1154/1152L)
80
Instruction set
Table reference
Interrupts
Instructions
Supported
Supported
Supported
1 external, 1 internal
1 external, 1 internal
1 external, 1 internal
4-bit variable prescaler
+ 8-bit timers
4-bit variable prescaler
+ 8-bit timers
4-bit variable prescaler
+ 8-bit timers
Timers
On-chip functions
Stack levels
Standby function
8
8
8
Standby mode entered by the
HALT instruction supported
Standby mode entered by the
HALT instruction supported
Standby mode entered by the
HALT instruction supported
Number of ports
Serial port
22 I/O port pins
Input and output in 4 or 8 bit units
15 V max.
22 I/O port pins
Input and output in 4 or 8 bit units
15 V max.
22 I/O port pins
Input and output in 4 or 8 bit units
15 V max.
I/O voltage handling capability
Output current
I/O ports
10 mA typ. 20 mA max.
10 mA typ. 20 mA max.
10 mA typ. 20 mA max.
I/O circuit types
Open drain (n-channel) and pull-up resistor output options can be specified in 1-bit units
A high or low level output can be selected in port units (ports C and D only)
Output level at reset
Square wave output
Minimum cycle time
Supply voltage
Supported
2.77 µs (VDD ≥ 3 V)
3 to 6 V
Supported
0.92 µs (VDD ≥ 2.5 V)
2.5 to 6 V
Supported
3.84 µs (VDD ≥ 2.2 V)
2.2 to 6 V
Characteristics
Current drain
1.5 mA typ.
2 mA typ.
1.5 mA typ.
RC (800/400 kHz typ.)
Ceramic (400 k, 800 k, 1 MHz, 4 MHz)
RC (400 kHz typ.)
Ceramic (400 k, 800 k, 1 MHz, 4 MHz)
Oscillator element
Ceramic 4 MHz
Oscillator
Divider circuit option
Package
1/1, 1/3, 1/4
1/1
1/1, 1/3, 1/4
Other items
DIP30S-D, MFP30S, SSOP30
DIP30S-D, MFP30S, SSOP30
DIP30S-D, MFP30S, SSOP30
Note: Recommendations for oscillator elements and oscillator circuit constants will be announced as the recommended circuits for these ICs are determined.
Verify the progress of these developments periodically.
No. 6278-2/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Differences between the LC651154N/1152N and the LC651104N/1102N.
The table below lists the points that require care when converting an existing product that uses the LC651104N/1102N to
use the LC651154N/1152N.
Parameter
LC651154N/1152N
LC651104N/1102N
250 mW
Pdmax (1) : DIP
Pdmax (2) : MFP
Pdmax (3) : SSOP
310 mW
Allowable power dissipation
220 mW
160 mW
150 mW
(No corresponding package)
Oscillator frequency precision: within ±2%
fCFOSC
Oscillator frequency precision: within ±4%
Changes in the recommended oscillator
constants (See table 1.)
[OSC1, OSC2]
Oscillator characteristics
Ceramic oscillator
800 kHz typ. (VDD = 3 to 6 V)
900 kHz typ. (VDD = 4 to 6 V)
Constants changed: Rext = 5.6 kΩ ±1 %
Constants changed: Rext = 4.7 kΩ ±1 %
Oscillator frequency
2-pin RC oscillator
Oscillator frequency
Frequency variability (sample to sample):
587 to 1298 kHz
Frequency variability (sample to sample):
634 to 1278 kHz
fMOSC
[OSC1, OSC2]
400 kHz typ. (VDD = 3 to 6 V)
400 kHz typ. (VDD = 3 to 6 V)
Frequency variability (sample to sample):
290 to 616 kHz
Frequency variability (sample to sample):
276 to 742 kHz
Pull-up resistors
Ru [RES]
200 to 800 kΩ (500 kΩ typ.)
min. 2.0 µs
300 to 700 kΩ (500 kΩ typ.)
min. 3.0 µs
Serial clock input clock cycle time
A/D converter characteristics
AV+ = VDD
tCKCY (1) [ SCK]
Operating voltage
Reference input current
IRIF [AV+, AV–]
VDD = 3 to 6 V
VDD = 4 to 6 V
200 to 800 µA (500 µA typ.)
VDD = 3 to 6 V
75 to 300 µA (150 µA typ.)
AV– = VSS
Watchdog timer
Cw = 0.047 ±5% µF
Rw = 680 ±1% kΩ
RI = 100 ±1% Ω
VDD = 4 to 6 V
DIP30S-D, MFP30S
An SSOP30 version was added.
Package
DIP30S-D, MFP30S
Differences between the LC651154F/1152F and the LC651104F/1102F.
The table below lists the points that require care when converting an existing product that uses the LC651104F/1102F to
use the LC651154F/1152F.
Parameter
LC651154F/1152F
310 mW
LC651104F/1102F
250 mW
Pdmax (1) : DIP
Pdmax (2) : MFP
Pdmax (3) : SSOP
VDD
Allowable power dissipation
220 mW
150 mW
160 mW
(No corresponding package)
4 to 6 V
Operating supply voltage
Low-level input voltage
2.5 to 6 V
Specifications for VDD = 4 to 6 V
The specifications for VDD = 2.5 to 6 V
were added.
VIL(n)
Specifications for VDD = 4 to 6 V
Oscillator characteristics
Ceramic oscillator
Oscillator frequency
Pull-up resistors
fCFOSC
Oscillator frequency precision: within ±2 % Oscillator frequency precision: within ±4 %
[OSC1, OSC2]
Ru [RES]
200 to 800 kΩ (500 kΩ typ.)
AD speed 1/1 : VDD = 3.5 to 6 V
AD speed 1/2 : VDD = 3 to 6 V
300 to 700 kΩ (500 kΩ typ.)
AD speed 1/1 : VDD = 4.5 to 6 V
AD speed 1/2 : VDD = 4 to 6 V
A/D converter characteristics
AV+ = VDD
Operating voltage
Reference input current
IRIF [AV+, AV–]
AV– = VSS
200 to 800 µA (500 µA typ.)
75 to 300 µA (150 µA typ.)
DIP30S-D, MFP30S
DIP30S-D, MFP30S
An SSOP30 version was added.
Package
No. 6278-3/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Differences between the LC651154L/1152L and the LC651104L/1102L.
The table below lists the points that require care when converting an existing product that uses the LC651104L/1102L to
use the LC651154L/1152L.
Parameter
LC651154L/1152L
LC651104L/1102L
250 mW
Pdmax (1) : DIP
Pdmax (2) : MFP
Pdmax (3) : SSOP
VDD
310 mW
Allowable power dissipation
220 mW
160 mW
150 mW
(No corresponding package)
2.5 to 6 V
Operating supply voltage
2.2 to 6 V
Oscillator frequency precision: within ±2%
Oscillator characteristics
Ceramic oscillator
fCFOSC
Oscillator frequency precision: within ±4%
400 kHz typ. (VDD = 2.5 to 6 V)
Changes in the recommended oscillator
constants (See table 1.)
[OSC1, OSC2]
Oscillator frequency
2-pin RC oscillator
Oscillator frequency
400 kHz typ. (VDD = 2.2 to 6 V)
fMOSC
Frequency variability (sample to sample):
290 to 841 kHz
Frequency variability (sample to sample):
276 to 742 kHz
[OSC1, OSC2]
Pull-up resistors
Ru [RES]
200 to 800 kΩ (500 kΩ typ.)
min. 2.0 µs
300 to 700 kΩ (500 kΩ typ.)
min. 6.0 µs
Serial clock input clock cycle time
A/D converter characteristics
AV+ = VDD
tCKCY (1) [ SCK]
Operating voltage
Reference input current
IRIF [AV+, AV–]
VDD = 3 to 6 V
VDD = 4 to 6 V
200 to 800 µA (500 µA typ.)
75 to 300 µA (150 µA typ.)
VDD = 2.5 to 6.0 V
AV– = VSS
Watchdog timer
VDD = 2.2 to 6.0 V
DIP30S-D, MFP30S
An SSOP30 version was added.
Package
DIP30S-D, MFP30S
Caution: Perform a full system evaluation and inspection after replacing the microcontroller.
No. 6278-4/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Pin Assignment
The pin assignment is the same for the DIP, MFP, and SSOP packages.
No. 6278-5/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Pin Functions
OSC1, OSC2: Connections for the oscillator capacitor and resistor or ceramic element
RES: Reset
TEST:
INT:
SI:
IC testing.
Interrupt request input
Serial input
PA0 to PA3: Common I/O ports A0 to A3
PC0 to PC3: Common I/O ports C0 to C3
PD0 to PD3: Common I/O ports D0 to D3
PE0 to PE3: Common I/O ports E0 to E3
SO:
Serial output
SCK:
Serial clock input output
AD0 to AD7: A/D converter analog inputs
PF0 to PF3:
Common I/O ports F0 to F3
AV+, AV–:
WDR:
A/D converter reference voltage inputs
Watchdog timer reset input
PG0 to PG3: Common I/O ports G0 to G3
Note: Pins SI, SO, SCK, and INT are shared function pins also used as PF0:3.
System Block Diagram
RAM:
F:
Data memory
Flag
ROM:
PC:
Program memory
Program counter
WR:
AC:
Working register
Accumulator
Arithmetic and logic unit
Data pointer
E register
INT:
Interrupt control
IR:
Instruction register
ALU:
DP:
I.DEC:
CF, CSF:
ZF, ZSF:
EXTF:
TMF:
Instruction decoder
Carry flag and carry save flag
Zero flag and zero save flag
External interrupt request flag
Internal interrupt request flag
E:
CTL:
OSC:
TM:
STS:
Control register
Oscillator circuit
Timer
Status register
No. 6278-6/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Development Support
The following are provided for development with the LC651154 and LC651152.
• User’s manual
See the “LC651104/1102 User’s Manual.”
• Development tools manual
See the “Four-Bit Microcontroller EVA86000 Development Tools Manual.”
• Software manual
“LC65/66 Series Software Manual”
• Development tools
— Program development (EVA86000 System)
— On-chip EPROM microcontroller <LC65E1104> for program evaluation
Pin Functions
Number
of pins
Handling when
unused
Symbol
I/O
Function
Option
At reset
VDD
VSS
—
—
1
Power supply
—
—
—
—
(1) Two-pin RC oscillator or
external clock
(2) Two-pin ceramic oscillator
(3) Divider option
1. No divider
OSC1
OSC2
1
1
Input
• Connection for the RC circuit or ceramic oscillator
element used for the system clock oscillator
• Leave OSC2 open when an external clock input is
used.
—
Output
2. Divide-by-3
3. Divide-by-4
• I/O port A0 to A3
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
Testing in 1-bit units (BP and BNP instructions)
Set and reset in 1-bit units (SPB and RPB
instructions)
• PA3 is used for standby mode control
• Application must assure that chattering does not
occur on the PA3 input during HALT instruction
execution.
• All four pins have shared functions
PA0/AD0 - A/D converter input AD0
PA1/AD1 - A/D converter input AD1
PA2/AD2 - A/D converter input AD2
PA3/AD3 - A/D converter input AD3
High-level
output (The
output n-
channel
transistors in
the off state.)
Select the
PA0 to
PA3/
(1) Open-drain output
(2) Pull-up resistor
open-drain
output option
and connect
4
I/O
Options (1) and (2) can be
specified in bit units
AD0 to
AD3
to VSS
.
(1) Open-drain output
(2) Pull-up resistor
(3) High-level output during reset
(4) Low-level output during reset
• Options (1) and (2) can be
specified in bit units
• High-level
output
• I/O port C0 to C3
The port functions are identical to those of PA0 to
PA3. (See note.)
• The output during a reset can be selected to be
either high or low as an option.
Note: This port has no standby mode control
function.
• Low-level
output
The same as
for PA0 to
PA3
PC0 to
PC3
4
4
I/O
I/O
(Depending
on option
selected.)
• Options (3) and (4) are
specified 4 bits at a time
• I/O port D0 to D3
The port functions and options are identical to
those of PC0 to PC3.
The same as
for PA0 to
PA3
PD0 to
PD3
The same as
PC0 to PC3
The same as PC0 to PC3
Continued on next page.
No. 6278-7/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Number
of pins
Handling when
unused
Symbol
I/O
Function
Option
At reset
• I/O port E0 to E1
(1) Open-drain output
(2) Pull-up resistor
Input in 4-bit units (IP instruction)
Output in 4-bit units (OP instruction)
High-level
output (The
output n-
• Options (1) and (2) can be
specified in bit units
Set and reset in 1-bit units (SPB and RPB
instructions)
Identical to
those for PA0
to PA3
PE0-PE1/
WDR
2
I/O
channel
transistors in
the off state.)
(3) Normal port PE1
Testing in 1-bit units (BP and BNP instructions)
(4) Watchdog reset WDR
• PE0 also has a continuous pulse (64·Tcyc) output
function.
• Either options (3) and (4)
may be specified.
• PE1 becomes the watchdog reset pin WDR when
selected for such as an option.
• I/O port F0 to F3
The port functions and options are identical to
those of PE0 to PE1 (See note.)
• PF0 to PF3 have shared functions as the serial
interface pins and the INT input.
Identical to
those for PA0
to PA3
PF0/SI
The function can be selected under program
control.
The serial port Identical to
PF1/SO
PF2/SCK
PF3/INT
4
I/O
Identical to those for PA0 to PA3
functions are
disabled.
those for PA0
to PA3
SI ... Serial input pin
SO ... Serial output pin
The interrupt
source is set
to INT.
SCK ... Input and output of the serial clock signal
INT ... Interrupt request input
The serial I/O function can be switched between 4-
bit and 8-bit transfers under program control.
Note: There is no continuous pulse output function.
• I/O port G0 to G3
The port functions and options are identical to
those of PE0 to PE1 (See note.)
Note: There is no continuous pulse output function.
• All four pins have shared functions.
PG0/AD4 - A/D converter input AD4
PG1/AD5 - A/D converter input AD5
PG2/AD6 - A/D converter input AD6
PG3/AD7 - A/D converter input AD7
Identical to
those for PA0 those for PA0
to PA3
Identical to
PG0-PG3/
AD4-AD7
4
I/O
Identical to those for PA0 to PA3
to PA3
AV+
AV–
1
1
—
—
Connect to
A/D converter reference voltage input
• System reset input
—
—
—
—
VSS
.
• Applications must provide an external capacitor for
the power-on reset.
RES
1
1
Input
Input
—
• Apply a low level to this pin for 4 clock cycles to
effect and reset start.
• IC test pin
This pin must
be connected
TEST
—
—
This pin must be connected to VSS during normal
operation.
to VSS
.
No. 6278-8/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Oscillator Circuit Options
Option
Circuit
Conditions and other notes
External clock
The OSC2 pin must be left open.
Two-pin RC oscillator
Ceramic oscillator
Ceramic
oscillator element
Divider Circuit Options
Option
Circuit
Conditions and other notes
• This option can be used with any of the three oscillator
options.
• The oscillator frequency or external clock frequency must
not exceed 1444 kHz. (LC651154N, LC651152N)
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz. (LC651154F, LC651152F)
• The oscillator frequency or external clock frequency must
not exceed 1040 kHz. (LC651154L, LC651152L)
No divider
• This option can only be used with the external clock and the
ceramic oscillator options.
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz.
Built-in divide-by-three circuit
Divide-by-3
• This option can only be used with the external clock and the
ceramic oscillator options.
• The oscillator frequency or external clock frequency must
not exceed 4330 kHz.
Divide-by-4
Built-in divide-by-four circuit
Caution: The following tables summarize the oscillator and divider circuit options. Use care when selecting these options.
No. 6278-9/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Oscillator Options
LC651154N, LC651152N
Divider option
(cycle time)
Circuit type
Frequency
400 kHz
VDD range
3 to 6 V
Notes
Cannot be used with the divide-by-three
and divide-by-four options.
1/1 (10 µs)
1/1 (5 µs)
1/3 (15 µs)
1/4 (20 µs)
1/1 (4 µs)
1/3 (12 µs)
1/4 (16 µs)
1/3 (3 µs)
1/4 (4 µs)
3 to 6 V
3 to 6 V
3 to 6 V
3 to 6 V
3 to 6 V
3 to 6 V
3 to 6 V
3 to 6 V
800 kHz
Ceramic oscillator
1 MHz
4 MHz
Cannot be used with the no divider circuit
option.
200 k to 1444 kHz
600 k to 4330 kHz
800 k to 4330 kHz
1/1 (20 to 2.77 µs) 3 to 6 V
1/3 (20 to 2.77 µs) 3 to 6 V
1/4 (20 to 3.70 µs) 3 to 6 V
External clock used with the 2-pin RC oscillator circuit
Use the no divider circuit option and the 3 to 6 V
recommended circuit constants. If using other circuit
constants is unavoidable, the application must use a
frequency identical to the external clock and observe
the VDD range specification.
Two-pin RC
External clock used with the ceramic oscillator option
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
LC651154F, LC651152F
Divider option
(cycle time)
1/1 (1 µs)
Circuit type
Frequency
4 MHz
VDD range
2.5 to 6 V
Notes
Ceramic oscillator
External clock used with the 2-pin RC oscillator circuit 200 k to 4330 kHz
1/1 (20 to 0.92 µs) 2.5 to 6 V
External clock used with the ceramic oscillator option
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
No. 6278-10/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154L, LC651152L
Divider option
(cycle time)
Circuit type
Frequency
400 kHz
VDD range
2.2 to 6 V
Notes
Cannot be used with the divide-by-three
and divide-by-four options.
1/1 (10 µs)
1/1 (5 µs)
1/3 (15 µs)
1/4 (20 µs)
1/1 (4 µs)
1/3 (12 µs)
1/4 (16 µs)
2.2 to 6 V
2.2 to 6 V
2.2 to 6 V
2.2 to 6 V
2.2 to 6 V
2.2 to 6 V
800 kHz
Ceramic oscillator
1 MHz
4 MHz
Cannot be used with either the no divider
1/4 (4 µs)
2.2 to 6 V circuit option or the divide-by-three circuit
option.
200 k to 1040 kHz
600 k to 3120 kHz
800 k to 4160 kHz
1/1 (20 to 3.84 µs) 2.2 to 6 V
1/3 (20 to 3.84 µs) 2.2 to 6 V
1/4 (20 to 3.84 µs) 2.2 to 6 V
External clock used with the 2-pin RC oscillator circuit
Use the no divider circuit option and the 2.2 to 6 V
recommended circuit constants. If using other circuit
constants is unavoidable, the application must use a
frequency identical to the external clock and observe
the VDD range specification.
Two-pin RC
External clock used with the ceramic oscillator option
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
Port C and D Output Level During Reset Option
The output level during a reset can be selected from the two options below in 4-bit units for the C and D ports.
Option
Conditions and other notes
Ports C and D in 4-bit units
Ports C and D in 4-bit units
High-level output during reset
Low-level output during reset
Port Output Type Option
The following two options may be selected for the I/O ports individually (bit units).
Option
Circuit
Applicable ports
1. Open-drain output
Ports A, C, D, E, F, and G
2. Built-in pull-up resistor
Watchdog Reset Option
This option allows the PE1/WDR pin to be selected either to be used as the normal port PE1 or to be used as the
watchdog reset pin WDR.
No. 6278-11/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154N, 651152N
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Ratings
Unit
Maximum supply voltage
VDD max
–0.3 to +7.0
Allowed up to the
generated voltage.
Output voltage
Input voltage
VO
OSC2
1
VI (1)
VI (2)
VIO (1)
VIO (2)
VIO (3)
IOP
OSC1 *
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +15
V
TEST, RES, AV+, AV–
PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3
PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3
PC0 to 3, PG0 to 3
Open-drain specification ports
Pull-up resistor specification ports
I/O voltage
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–2 to +20
Peak output current
I/O ports
I/O ports
PC0 to 3
PD0 to 3
PE0 to 1
PF0 to 3
PG0 to 3
PA0 to 3
IOA
Per single pin, averaged over 100 ms
The total current for PC0 to PC3,
–2 to +20
∑IOA (1)
∑IOA (2)
–15 to +100
–15 to +100
2
PD0 to PD3, and PE0 to PE1 *
mA
Average output current
The total current for PF0 to PF3,
2
PG0 to PG3, and PA0 to PA3 (See note 2.) *
Pd max (1) Ta = –40 to +85°C (DIP package)
310
220
Allowable power dissipation Pd max (2) Ta = –40 to +85°C (MFP package)
Pd max (3) Ta = –40 to +85°C (SSOP package)
mW
°C
160
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V, V = 3.0 to 6.0 V (Unless otherwise specified.)
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Unit
min
3.0
max
6.0
Operating supply voltage
Standby supply voltage
VDD
VST
3
RAM and register values retained* VDD
1.8
6.0
Ports C, D, E, and F with
open-drain specifications
V
IH (1)
Output n-channel transistors off
0.7 VDD
13.5
Ports C, D, E, and F with
pull-up resistor specifications
VIH (2)
VIH (3)
Output n-channel transistors off
Output n-channel transistors off
0.7 VDD
0.7 VDD
VDD
VDD
Port A, G
V
The INT, SCK, and SI
pins with open-drain
specifications
High-level input voltage
VIH (4)
Output n-channel transistors off
Output n-channel transistors off
0.8 VDD
0.8 VDD
13.5
VDD
The INT, SCK, and SI
pins with pull-up resistor
specifications
V
IH (5)
VIH (6)
VIH (7)
VDD = 1.8 to 6.0 V
RES
0.8 VDD
0.8 VDD
VDD
VDD
External clock specifications
OSC1
Continued on next page.
No. 6278-12/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Applicable pins
and notes
Parameter
Symbol
IL (1)
Conditions
Unit
min
VSS
max
V
Output n-channel transistors off VDD = 4 to 6 V
Output n-channel transistors off VDD = 3 to 6 V
Output n-channel transistors off VDD = 4 to 6 V
Output n-channel transistors off VDD = 3 to 6 V
External clock specifications VDD = 4 to 6 V
External clock specifications VDD = 3 to 6 V
VDD = 4 to 6 V
Port
0.3 VDD
0.25 VDD
0.25 VDD
0.2 VDD
0.25 VDD
0.2 VDD
0.3 VDD
0.25 VDD
0.25 VDD
0.2 VDD
VIL (2)
VIL (3)
VIL (4)
VIL (5)
VIL (6)
VIL (7)
VIL (8)
VIL (9)
VIL (10)
Port
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
INT, SCK, SI
INT, SCK, SI
OSC1
V
Low-level input voltage
OSC1
TEST
VDD = 3 to 6 V
TEST
VDD = 4 to 6 V
RES
VDD = 3 to 6 V
RES
The clock may have a
frequency up to 4.33 MHz
when either the divide-by-
three or divide-by-four
internal divider circuit option
is used.
Operating frequency
(cycle time)
200
(20)
1444
(2.77)
fop (Tcyc)
V
DD = 3 to 6 V
kHz (µs)
External clock conditions
Frequency
Figure 1.
text
V
DD = 3 to 6 V
OSC1
200
69
4330
50
kHz
ns
Either the divide-by-
three or divide-by-four
internal divider circuit
must be used if the
clock frequency
Pulse width
textH, textL
textR, textF
VDD = 3 to 6 V
VDD = 3 to 6 V
OSC1
OSC1
Rise and fall times
exceeds 1.444 MHz.
Recommended oscillator
circuit constants
Cext
Rext
270 ±5%
12 ±1%
pF
Figure 2
VDD = 3 to 6 V
VDD = 3 to 6 V
OSC1, OSC2
OSC1, OSC2
kΩ
Two-pin RC oscillator
Cext
Rext
270 ±5%
5.6 ±1%
pF
Figure 2
Figure 3
kΩ
4
Ceramic oscillator *
See table 1.
No. 6278-13/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Electrical Characteristics at Ta = –40 to +85°C, V = 0 V, V = 3.0 to 6.0 V (Unless otherwise specified.)
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
Unit
min
max
• Output n-channel transistors off
(Including the n-channel transistor
off leakage current.)
Ports C, D, E and F with
the open-drain
specifications
IIH (1)
5.0
• VIN = 13.5 V
• Output n-channel transistors off
(Including the n-channel transistor Ports A and G with the
off leakage current.)
• VIN = VDD
High-level input current
µA
IIH (2)
1.0
1.0
open-drain specifications
When an external clock is used,
IIH (3)
IIL (1)
OSC1
VIN = VDD
• Output n-channel transistors off
• VIN = VSS
Ports with the open-drain
specifications
–1.0
• Output n-channel transistors off
• VIN = VSS
Ports with the pull-up
resistor specifications
IIL (2)
IIL (3)
IIL (4)
–1.3
–0.35
–10
mA
µA
Low-level input current
High-level output voltage
VIN = VSS
RES
–45
When an external clock is used,
OSC1
–1.0
VIN = VSS
• IOH = –50 µA
• VDD = 4.0 to 6.0 V
Ports with the pull-up
resistor specifications
VOH (1)
VOH (2)
VOL (1)
VDD – 1.2
VDD – 0.5
Ports with the pull-up
resistor specifications
IOH = –10 µA
• IOL = 10 mA
• VDD = 4.0 to 6.0 V
Port
Port
1.5
0.5
Low-level output voltage
Hysteresis voltage
When IOL = 1 mA and the IOL for
each port is 1 mA or less.
V
V
OL (2)
VHIS
VtH
VtL
0.1 VDD
RES, INT, SCK, SI, and
OSC1 with Schmitt
High-level threshold
voltage
0.4 VDD
0.2 VDD
0.8 VDD
0.6 VDD
5
specifications*
Low-level threshold
voltage
6
Current drain *
• Operating, with the output
n-channel transistors off
• With the ports at VDD
IDDOP (1)
VDD
1.5
4
Two-pin RC oscillator
Ceramic oscillator
• Figure 2, fosc = 800 kHz (typical)
IDDOP (2)
IDDOP (3)
•
•
Figure 3, 4 MHz, divide-by-three circuit used VDD
Figure 3, 4 MHz, divide-by-four circuit used VDD
1.5
1.5
1.0
1.5
5
4
IDDOP (4) • Figure 3, 400 kHz
IDDOP (5) • Figure 3, 800 kHz
VDD
VDD
2.5
4
mA
• 200 kHz to 1444 kHz, no divider
circuit
• 600 kHz to 4330 kHz, divide-by-
three circuit used
• 800 kHz to 4330 kHz, divide-by-
four circuit used
VDD
1.5
5
External clock
Standby mode
IDDOP (6)
IDDst
Output n-channel transistors off,
VDD
VDD
0.05
10
5
VDD = 6 V
µA
Ports at VDD, VDD = 3 V
0.025
Continued on next page.
No. 6278-14/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
Unit
kHz
min
max
408
816
1020
4080
Oscillator characteristics
• Figure 3, fo = 400 kHz
• Figure 3, fo = 800 kHz
• Figure 3, fo = 1 MHz
• Figure 3, fo = 4 MHz, with the
divide-by-three or divide-by-four
circuit used.
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
392
784
980
400
800
1000
4000
Ceramic oscillator
Oscillator frequency
7
fCFOSC*
3920
Oscillator stabilization time
(note 8)
• Figure 4, fo = 400 kHz
10
10
• Figure 4, fo = 800 kHz, 1 MHz, or
4 MHz, with the divide-by-three or
divide-by-four circuit used.
tCFS
ms
Two-pin RC oscillator
Oscillator frequency
• Figure 2, Cext = 270 pF ±5%
• Figure 2, Rext = 5.6 kΩ ±1%
OSC1, OSC2
OSC1, OSC2
587
290
800
400
1298
818
fMOSC
kHz
• Figure 2, Cext = 270 pF ±5%
• Figure 2, Rext = 12 kΩ ±1%
Pull-up resistor
I/O ports
• Output n-channel transistors off
• VIN = VSS, VDD = 5 V
Pull-up resistor
specification ports
RPP
Ru
8
14
500
30
kΩ
RES
VIN = VSS, VDD = 5 V
RES
200
800
External reset characteristics
Reset time
tRST
See figure 5.
• f = 1 MHz
Pin capacitances
Cp
• With all pins other than the pin
10
pF
being tested at VIN = VSS
.
Serial clock
tCKCY (1) Figure 6
tCKCY (2) Figure 6
SCK
SCK
SCK
2.0
1.0
Input clock cycle time
Output clock cycle time
9
64 × TCYC*
Input clock low-level pulse
width
tCKL (1)
CKL (2)
Figure 6
Figure 6
Figure 6
Figure 6
Output clock low-level pulse
width
t
SCK
SCK
SCK
32 × TCYC
32 × TCYC
Input clock high-level pulse
width
t
CKH (1)
CKH (2)
1.0
Output clock high-level
pulse width
t
µs
Serial input
• Stipulated with respect to the
rising edge of SCK.
• Figure 6
SI
SI
0.4
0.4
Data setup time
tICK
Data hold time
Serial output
tCKI
• Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
Output delay time
tCKO
and an external capacitor of 50 pF SO
0.6
on only the n-channel open-drain
pins.
• Figure 6
Continued on next page.
No. 6278-15/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Applicable pins
and notes
Parameter
Symbol
tPCY
Conditions
Unit
min
max
Pulse output function
Period
• Figure 7
• TCYC = 4 × system clock
period
PE0
64 × TCYC
• With an external resistor of
1 kΩ and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
32 × TCYC
High-level pulse width
tPH
PE0
PE0
µs
±10%
32 × TCYC
Low-level pulse width
Resolution
tPL
±10%
8
bit
AV+ = VDD
AV– = VSS
Absolute precision
±1
±2 LSB
When the A/D converter
speed is normal (1:1),
namely 26 × TCYC
72
(TCYC
2.77 µs)
312
(TCYC =
12 µs)
=
Conversion time
TCAD
µs
When the A/D converter
speed is one half (1:2),
namely 51 × TCYC
141
612
(TCYC
=
(TCYC
=
2.77 µs)
12 µs)
AV+
AV–
AV+
AV–
AV–
VDD
AV+
Input reference voltage
V
VSS
VDD = 3 to 6 V
Input reference current
range
IRIF
VAIN
AV+ = VDD, AV– = VSS
AV+, AV–
200
AV–
500
800
µA
V
Analog input voltage
range
AD0 to AD7
AV+
1
Including the output off
leakage current.
AD0 to AD7
(The I/O
VAIN = VDD
shared
Analog port input current
IAIN
function ports
have open-
drain
µA
VAIN = VSS
–1
specifications.)
When PE1 has the
open-drain specifications.
Cw
Rw
RI
WDR
WDR
WDR
0.1 ±5%
680 ±1%
100 ±1%
µF
kΩ
Ω
Recommended
When PE1 has the
open-drain specifications.
10
constants*
VDD = 3 to 6 V
When PE1 has the
open-drain specifications.
Clear time (discharge)
Clear period (charge)
tWCT
Figure 8
Figure 8
WDR
WDR
100
36
µs
tWCCY
ms
When PE1 has the
open-drain specifications.
Cw
Rw
RI
WDR
WDR
WDR
0.047 ±5%
680 ±1%
100 ±1%
µF
kΩ
Ω
Recommended
When PE1 has the
open-drain specifications.
10
constants*
V
DD = 3 to 6 V
When PE1 has the
open-drain specifications.
Clear time (discharge)
Clear period (charge)
tWCT
Figure 8
Figure 8
WDR
WDR
40
18
µs
tWCCY
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range.
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-16/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
open
External clock
Figure 1 External Clock Input Waveform
Ceramic oscillator
element
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6278-17/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation
Oscillation
stabilization
time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.)
CSA4.00MG
C1
C2
R
33 pF ±10%
33 pF ±10%
0 Ω
CST4.00MGW (Internal capacitor)
4 MHz (Kyocera Corporation)
KBR4.0MSA
C1
C2
R
33 pF ±10%
33 pF ±10%
0 Ω
KBR4.0MKS (Internal capacitor)
1 MHz (Murata Mfg. Co., Ltd.)
CSB1000J
C1
C2
R
100 pF ±10%
100 pF ±10%
3.3 kΩ
800 kHz (Murata Mfg. Co., Ltd.)
CSB800J
C1
C2
R
100 pF ±10%
100 pF ±10%
3.3 kΩ
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
400 kHz (Murata Mfg. Co., Ltd.)
CSB400P
C1
C2
R
220 pF ±10%
220 pF ±10%
3.3 kΩ
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
No. 6278-18/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 6 Serial I/O Timing
The load conditions are the same
as those in figure 5.
Figure 7 Port PE0 Pulse Output Timing
tWCCY
:
The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
tWCT
:
The discharge time due to software processing.
Figure 8 Watchdog Timer Waveform
No. 6278-19/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
RC Oscillator Characteristics for the LC651154N and LC651152N
Figure 9 shows the RC oscillator characteristics for the LC651154N and LC651152N.
However, the sample-to-sample variation in the LC651154N and LC651152N RC oscillator frequency described below
does occur.
1) When:
V
DD
= 3.0 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 12.0 kΩ
f
will be:
MOSC
290 kHz ≤ f
≤ 818 kHz
MOSC
2) When:
= 3.0 to 6.0 V, Ta = –40 to +85°C
V
DD
External constants: Cext = 270 pF
Rext = 5.6 kΩ
f
will be:
MOSC
587 kHz ≤ f
≤ 1298 kHz
MOSC
Therefore, only the above circuit constants are recommended.
If use of circuit constants other than the above is unavoidable, they must be in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 9.)
Notes • The oscillator frequency must be in the range 350 to 850 kHz when V = 5.0 V and Ta = 25°C.
DD
• Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating
clock frequency range (see the oscillator divider option table) for the voltage range V = 3.0 to 6.0 V and for
DD
the temperature range Ta = –40 to +85°C.
These characteristics curves are for
reference purposes only and are not
guaranteed.
Figure 9 RC Oscillator Frequency Data (Representative Values)
No. 6278-20/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154F, 651152F
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Ratings
Unit
Maximum supply voltage
VDD max
–0.3 to +7.0
Allowed up to the
generated voltage.
Output voltage
Input voltage
VO
OSC2
1
VI (1)
VI (2)
VIO (1)
VIO (2)
VIO (3)
IOP
OSC1 *
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +15
V
TEST, RES, AV+, AV–
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports
PA0 to PA3, PG0 to PG3
I/O voltage
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–2 to +20
Peak output current
I/O ports
IOA
Per single pin, averaged over 100 ms
The total current for PC0 to PC3,
I/O ports
–2 to +20
PC0 to PC3
PD0 to PD3
PE0 and PE1
PF0 to PF3
PG0 to PG3
PA0 to PA3
∑IOA (1)
∑IOA (2)
–15 to +100
–15 to +100
2
PD0 to PD3, and PE0 and PE1 *
mA
Average output current
The total current for PF0 to PF3, PG0 to PG3,
2
and PA0 to PA3 (See note 2.) *
Pd max (1) Ta = –40 to +85°C (DIP package)
310
220
Allowable power dissipation Pd max (2) Ta = –40 to +85°C (MFP package)
Pd max (3) Ta = –40 to +85°C (SSOP package)
mW
°C
160
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V, V = 2.5 to 6.0 V (Unless otherwise specified.)
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Unit
min
2.5
max
6.0
Operating supply voltage
Standby supply voltage
VDD
VST
3
RAM and register values retained* VDD
1.8
6.0
Ports C, D, E, and F with
open-drain specifications
VIH (1)
Output n-channel transistors off
0.7 VDD
13.5
Ports C, D, E, and F with
pull-up resistor specifications
VIH (2)
VIH (3)
Output n-channel transistors off
Output n-channel transistors off
0.7 VDD
0.7 VDD
VDD
VDD
Port A, G
V
The INT, SCK, and SI
pins with open-drain
specifications
High-level input voltage
VIH (4)
Output n-channel transistors off
Output n-channel transistors off
0.8 VDD
0.8 VDD
13.5
VDD
The INT, SCK, and SI
pins with pull-up resistor
specifications
V
IH (5)
VIH (6)
VIH (7)
VDD = 1.8 to 6.0 V
RES
0.8 VDD
0.8 VDD
VDD
VDD
External clock specifications
OSC1
Continued on next page.
No. 6278-21/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Applicable pins
and notes
Parameter
Symbol
IL (1)
Conditions
Unit
min
VSS
max
V
Output n-channel transistors off VDD = 4 to 6 V
Port
0.3 VDD
0.2 VDD
0.25 VDD
0.15 VDD
0.25 VDD
0.15 VDD
0.3 VDD
0.2 VDD
0.25 VDD
0.15 VDD
VIL (2)
VIL (3)
VIL (4)
VIL (5)
VIL (6)
VIL (7)
VIL (8)
VIL (9)
VIL (10)
Output n-channel transistors off VDD = 2.5 to 6 V Port
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Output n-channel transistors off VDD = 4 to 6 V
INT, SCK, SI
Output n-channel transistors off VDD = 2.5 to 6 V INT, SCK, SI
External clock specifications VDD = 4 to 6 V
External clock specifications VDD = 2.5 to 6 V OSC1
VDD = 4 to 6 V TEST
VDD = 2.5 to 6 V TEST
VDD = 4 to 6 V RES
OSC1
V
Low-level input voltage
VDD = 2.5 to 6 V RES
Operating frequency
(cycle time)
200
(20)
4330
(0.92)
fop (Tcyc)
kHz (µs)
External clock conditions
Frequency
text
OSC1
OSC1
OSC1
200
69
4330
50
kHz
ns
Pulse width
textH, textL Figure 1.
textR, textF
Rise and fall times
ns
Recommended oscillator
circuit constants
Figure 2
See table 1.
4
Ceramic oscillator *
Electrical Characteristics at Ta = –40 to +85°C, V = 0 V, V = 2.5 to 6.0 V (Unless otherwise specified.)
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
Unit
min
max
• Output n-channel transistors off
(Including the n-channel transistor
off leakage current.)
Ports C, D, E and F with
the open-drain
specifications
IIH (1)
5.0
• VIN = 13.5 V
• Output n-channel transistors off
(Including the n-channel transistor Ports A and G with the
High-level input current
µA
IIH (2)
IIH (3)
IIL (1)
1.0
1.0
off leakage current.)
• VIN = VDD
open-drain specifications
When an external clock is used,
OSC1
VIN = VDD
• Output n-channel transistors off
• VIN = VSS
Ports with the open-drain
specifications
–1.0
• Output n-channel transistors off
• VIN = VSS
Ports with the pull-up
resistor specifications
IIL (2)
IIL (3)
IIL (4)
–1.3
–45
–0.35
–10
mA
µA
Low-level input current
High-level output voltage
VIN = VSS
RES
When an external clock is used,
OSC1
–1.0
VIN = VSS
• IOH = –50 µA
• VDD = 4.0 to 6.0 V
Ports with the pull-up
resistor specifications
VOH (1)
VOH (2)
VOL (1)
VDD – 1.2
VDD – 0.5
Ports with the pull-up
resistor specifications
IOH = –10 µA
• IOL = 10 mA
• VDD = 4.0 to 6.0 V
Port
Port
1.5
0.5
Low-level output voltage
Hysteresis voltage
When IOL = 1 mA and the IOL for
each port is 1 mA or less.
V
V
OL (2)
VHIS
VtH
VtL
0.1 VDD
RES, INT, SCK, SI, and
OSC1 with Schmitt
High-level threshold
voltage
0.4 VDD
0.8 VDD
0.6 VDD
5
specifications*
Low-level threshold
voltage
0.25 VDD
Continued on next page.
No. 6278-22/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Unit
mA
µA
min
max
6
Current drain*
IDDOP (1) • Figure 2, 4 MHz
• 200 kHz to 4330 kHz
2
2
6
6
Ceramic oscillator
• Operating, with the output
IDDOP (2)
n-channel transistors off and the VDD
ports at VDD
.
• Output n-channel transistors off
VDD = 6 V
• Ports at VDD, VDD = 2.5 V
VDD
VDD
0.05
10
5
Standby mode
IDDst
0.025
Oscillator characteristics
Ceramic oscillator
7
fCFOSC
tCFS
RPP
Ru
*
• Figure 2, fo = 4 MHz
OSC1, OSC2
3920
4000
4080
10
kHz
ms
Oscillator frequency*8
• Figure 3, fo = 4 MHz
Pull-up resistor
I/O ports
• Output n-channel transistors off
• VIN = VSS, VDD = 5 V
Pull-up resistor
specification ports
8
14
500
30
kΩ
RES
VIN = VSS, VDD = 5 V
RES
200
800
External reset characteristics
Reset time
tRST
See figure 4.
• f = 1 MHz
Pin capacitances
Cp
• With all pins other than the pin
10
pF
being tested at VIN = VSS
tCKCY (1) Figure 5
CKCY (2) Figure 5
.
Serial clock
SCK
SCK
SCK
2.0
0.6
Input clock cycle time
Output clock cycle time
9
t
64 × TCYC
*
Input clock low-level pulse
width
tCKL (1)
CKL (2)
tCKH (1)
CKH (2)
Figure 5
Figure 5
Figure 5
Figure 5
Output clock low-level pulse
width
t
SCK
SCK
SCK
32 × T
CYC
Input clock high-level pulse
width
0.6
Output clock high-level
pulse width
t
32 × T
CYC
Serial input
Data setup time
tICK
• Stipulated with respect to the
rising edge of SCK.
• Figure 5
SI
SI
0.2
0.2
µs
Data hold time
Serial output
tCKI
• Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
SO
0.4
Output delay time
tCKO
• Figure 5
Pulse output function
Period
tPCY
• Figure 6
• TCYC = 4 × system clock
period
• With an external resistor of
1 kΩ and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
PE0
PE0
64 × TCYC
High-level pulse width
Low-level pulse width
tPH
32 × TCYC
±10%
32 × TCYC
tPL
PE0
±10%
Continued on next page.
No. 6278-23/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Applicable pins
and notes
Parameter
Resolution
Symbol
Conditions
Unit
bit
min
max
VDD = 3 to 6 V
8
AV+ = VDD A/D converter speed 1/1 VDD = 3.5 to 6 V
AV– = VSS A/D converter speed 1/2 VDD = 3.5 to 6 V
When the A/D converter
±1
±1
±2
±2
Absolute precision
LSB
24
(TCYC
312
(TCYC =
speed is normal (1/1),
VDD = 3.5 to 6 V
=
namely 26 × TCYC
0.92 µs)
12 µs)
Conversion time
TCAD
µs
V
When the A/D converter
speed is one half (1/2),
namely 51 × TCYC
47
612
VDD = 3 to 6 V
(TCYC
=
(TCYC
=
0.92 µs)
12 µs)
AV+
AV–
AV+
AV–
VDD
AV+
Input reference voltage
AV–
VSS
Input reference current
range
IRIF
AV+ = VDD, AV– = VSS
AV+, AV–
200
AV–
500
800
AV+
µA
V
Analog input voltage
range
VAIN
AD0 to AD7
VDD = 3 to 6 V
Including the output off
leakage current.
AD0 to AD7
(The I/O
1
VAIN = VDD
shared
Analog port input current
IAIN
function ports
have open-
drain
µA
VAIN = VSS
–1
specifications.)
When PE1 has the
open drain specifications.
Cw
Rw
RI
WDR
WDR
WDR
0.01 ±5%
680 ±1%
100 ±1%
µF
kΩ
Ω
Recommended
When PE1 has the
open drain specifications.
10
constants*
When PE1 has the
open drain specifications.
Clear time (discharge)
Clear period (charge)
tWCT
Figure 7
Figure 7
WDR
WDR
10
µs
tWCCY
4.2
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 2 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 3).
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-24/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
open
External clock
Figure 1 External Clock Input Waveform
Ceramic oscillator
element
Figure 2 Ceramic Oscillator Circuit
No. 6278-25/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation
Oscillation
stabilization
time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.)
CSA4.00MG
C1
C2
R
33 pF ±10%
33 pF ±10%
0 Ω
CST4.00MGW (Internal capacitor)
4 MHz (Kyocera Corporation)
KBR4.0MSA
C1
C2
R
33 pF ±10%
33 pF ±10%
0 Ω
KBR4.0MKS (Internal capacitor)
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
No. 6278-26/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 5 Serial I/O Timing
The load conditions are the same
as those in figure 4.
Figure 6 Port PE0 Pulse Output Timing
tWCCY
:
The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
tWCT
:
The discharge time due to software processing.
Figure 7 Watchdog Timer Waveform
No. 6278-27/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
LC651154L, 651152L
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Ratings
Unit
Maximum supply voltage
VDD max
–0.3 to +7.0
Allowed up to the
generated voltage.
Output voltage
Input voltage
VO
OSC2
1
VI (1)
VI (2)
VIO (1)
VIO (2)
VIO (3)
IOP
OSC1 *
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +15
V
TEST, RES, AV+, AV–
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports
PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports
PA0 to PA3, PG0 to PG3
I/O voltage
–0.3 to VDD + 0.3
–0.3 VDD + 0.3
–2 to +20
Peak output current
I/O ports
IOA
Per single pin, averaged over 100 ms
The total current for PC0 to PC3,
I/O ports
–2 to +20
PC0 to PC3
PD0 to PD3
PE0 to PE1
PF0 to PF3
PG0 to PG3
PA0 to PA3
∑IOA (1)
∑IOA (2)
–15 to +100
–15 to +100
2
PD0 to PD3, and PE0 to PE1 *
mA
Average output current
The total current for PF0 to PF3, PG0 to PG3,
2
and PA0 to PA3 (See note 2.) *
Pd max (1) Ta = –40 to +85°C (DIP package)
310
220
Allowable power dissipation Pd max (2) Ta = –40 to +85°C (MFP package)
Pd max (3) Ta = –40 to +85°C (SSOP package)
mW
°C
160
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V, V = 2.2 to 6.0 V (Unless otherwise specified.)
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
VDD
Unit
min
2.2
max
6.0
Operating supply voltage
Standby supply voltage
VDD
VST
3
RAM and register values retained* VDD
1.8
6.0
Ports C, D, E, and F with
open-drain specifications
V
IH (1)
Output n-channel transistors off
0.7 VDD
13.5
Ports C, D, E, and F with
pull-up resistor specifications
VIH (2)
VIH (3)
Output n-channel transistors off
Output n-channel transistors off
0.7 VDD
0.7 VDD
VDD
VDD
Port A, G
The INT, SCK, and SI
pins with open-drain
specifications
High-level input voltage
V
IH (4)
IH (5)
Output n-channel transistors off
Output n-channel transistors off
0.8 VDD
0.8 VDD
13.5
VDD
The INT, SCK, and SI
pins with pull-up resistor
specifications
V
V
VIH (6)
VIH (7)
VIL (1)
VIL (2)
VIL (3)
VIL (4)
VIL (5)
VDD = 1.8 to 6.0 V
RES
0.8 VDD
0.8 VDD
VSS
VDD
VDD
External clock specifications
Output n-channel transistors off
Output n-channel transistors off
Output n-channel transistors off
OSC1
Port
0.2 VDD
0.15 VDD
0.15 VDD
0.2 VDD
0.15 VDD
INT, SCK, SI
OSC1
TEST
RES
VSS
Low-level input voltage
VSS
VSS
VSS
Continued on next page.
No. 6278-28/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Applicable pins
and notes
Parameter
Symbol
Conditions
Unit
min
200
max
1040
The clock may have a frequency up to
Operating frequency
(cycle time)
fop (Tcyc) 4.16 MHz when the divide-by-four internal
divider circuit option is used.
kHz (µs)
(20)
(3.84)
External clock conditions
Frequency
Figure 1.
text
OSC1
200
100
4160
100
kHz
ns
Either the divide-by-three or divide-by-
four internal divider circuit must be used if
the clock frequency exceeds 1.040 MHz.
Pulse width
textH, textL
OSC1
OSC1
Rise and fall times
textR, textF
ns
Recommended oscillator
circuit constants
Two-pin RC oscillator
Cext
Rext
Figure 2
OSC1, OSC2
270 ±5%
12 ±1%
pF
kΩ
4
Ceramic oscillator *
Figure 3
See table 1.
No. 6278-29/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Electrical Characteristics at Ta = –40 to +85°C, V = 0 V, V = 2.2 to 6.0 V (Unless otherwise specified.)
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
Unit
min
max
• Output n-channel transistors off
(Including the n-channel transistor
off leakage current.)
Ports C, D, E and F with
the open-drain
specifications
IIH (1)
5.0
• VIN = 13.5 V
• Output n-channel transistors off
(Including the n-channel transistor Ports A and G with the
High-level input current
µA
IIH (2)
IIH (3)
IIL (1)
1.0
1.0
off leakage current.)
• VIN = VDD
open-drain specifications
When an external clock is used,
OSC1
VIN = VDD
• Output n-channel transistors off
• VIN = VSS
Ports with the open-drain
specifications
–1.0
• Output n-channel transistors off
• VIN = VSS
Ports with the pull-up
resistor specifications
IIL (2)
IIL (3)
IIL (4)
–1.3
–0.35
–10
mA
µA
Low-level input current
VIN = VSS
RES
–45
When an external clock is used,
OSC1
–1.0
VIN = VSS
Ports with the pull-up
resistor specifications
High-level output voltage
Low-level output voltage
Hysteresis voltage
VOH
• IOH = –10 µA
VDD – 0.5
V
OL (1)
• IOL = 3 mA
Port
1.5
0.4
When IOL = 1 mA and the IOL for
each port is 1 mA or less.
V
VOL (2)
Port
VHIS
VtH
VtL
0.1 VDD
RES, INT, SCK, SI, and
OSC1 with Schmitt
High-level threshold
voltage
0.4 VDD
0.2 VDD
0.8 VDD
0.6 VDD
5
specifications*
Low-level threshold
voltage
6
Current drain *
• Operating, with the output
n-channel transistors off
• With the ports at VDD
Two-pin RC oscillator
Ceramic oscillator
IDDOP (1)
VDD
1.0
4
• Figure 2, fosc = 800 kHz (typical)
IDDOP (2)
IDDOP (3)
•
•
Figure 3, 4 MHz, divide-by-four circuit used VDD
1.5
0.5
4
1
Figure 3, 4 MHz, divide-by-four circuit used
VDD
V
DD = 2.2 V
IDDOP (4) • Figure 3, 400 kHz
IDDOP (5) • Figure 3, 800 kHz
VDD
VDD
1.0
1.5
2.5
4
mA
• 200 kHz to 1024 kHz, no divider
circuit
• 600 kHz to 3120 kHz, divide-by-
three circuit used
• 800 kHz to 4160 kHz, divide-by-
four circuit used
VDD
1.5
4
External clock
Standby mode
IDDOP (6)
IDDst
Output n-channel transistors off,
VDD
VDD
0.05
10
4
VDD = 6 V
µA
Ports at VDD, VDD = 2.2 V
0.020
Continued on next page.
No. 6278-30/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins and notes
Unit
kHz
min
max
408
816
1020
4080
Oscillator characteristics
• Figure 3, fo = 400 kHz
• Figure 3, fo = 800 kHz
• Figure 3, fo = 1 MHz
• Figure 3, fo = 4 MHz, with the
divide-by-four
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
392
784
980
400
800
1000
4000
Ceramic oscillator
Oscillator frequency
7
fCFOSC*
3920
circuit used.
• Figure 4, fo = 400 kHz
• Figure 4, fo = 800 kHz, 1 MHz, or
4 MHz, with the divide-by-four
circuit used.
10
10
8
Oscillator stabilization time *
tCFS
ms
Two-pin RC oscillator
Oscillator frequency
• Figure 2, Cext = 270 pF ±5%
• Figure 2, Rext = 5.6 kΩ ±1%
fMOSC
OSC1, OSC2
290
400
841
kHz
Pull-up resistor
I/O ports
• Output n-channel transistors off
• VIN = VSS, VDD = 5 V
Pull-up resistor
specification ports
RPP
Ru
8
14
500
30
kΩ
RES
VIN = VSS, VDD = 5 V
RES
200
800
External reset characteristics
Reset time
tRST
See figure 5.
• f = 1 MHz
Pin capacitances
Serial clock
Cp
• With all pins other than the pin
10
pF
being tested at VIN = VSS
.
t
CKCY (1) Figure 6
CKCY (2) Figure 6
SCK
2.0
2.0
Input clock cycle time
9
Output clock cycle time
t
SCK
SCK
64 × TCYC
*
Input clock low-level pulse
width
t
t
CKL (1)
CKL (2)
Figure 6
Figure 6
Figure 6
Figure 6
Output clock low-level pulse
width
SCK
SCK
SCK
32 × T
CYC
Input clock high-level pulse
width
t
CKH (1)
CKH (2)
2.0
Output clock high-level
pulse width
t
32 × T
CYC
Serial input
• Stipulated with respect to the
rising edge of SCK.
• Figure 6
Data setup time
tICK
SI
SI
0.5
0.5
µs
Data hold time
Serial output
tCKI
• Stipulated with respect to the
falling edge of SCK.
• With an external resistor of 1 kΩ
and an external capacitor of 50 pF
on only the n-channel open-drain
pins.
SO
1.0
Output delay time
tCKO
• Figure 6
Pulse output function
Period
• Figure 7
• TCYC = 4 × system clock
period
• With an external resistor of
1 kΩ and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.
tPCY
PE0
PE0
PE0
64 × TCYC
32 × TCYC
High-level pulse width
Low-level pulse width
tPH
tPL
±10%
32 × TCYC
±10%
Continued on next page.
No. 6278-31/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Ratings
typ
Applicable pins
and notes
Parameter
Resolution
Symbol
Conditions
Unit
min
max
8
bit
AV+ = VDD
AV– = VSS
±1
±2 LSB
Absolute precision
When the A/D converter
speed is normal (1/1),
namely 26 × TCYC
99
(TCYC
3.84 µs)
312
(TCYC =
12 µs)
µs
=
Conversion time
TCAD
When the A/D converter
speed is one half (1/2),
namely 51 × TCYC
195
612
(TCYC
=
(TCYC
=
3.84 µs)
12 µs)
AV+
AV–
AV+
AV–
VDD
AV+
Input reference voltage
V
AV–
VSS
VDD = 3 to 6 V
Input reference current
range
AV+ = VDD
AV– = VSS
IRIF
AV+, AV–
200
AV–
500
800
AV+
µA
V
Analog input voltage
range
VAIN
AD0 to AD7
Including the output off
leakage current.
AD0 to AD7
(The I/O
1
VAIN = VDD
shared
Analog port input current
IAIN
function ports
have open-
drain
µA
VAIN = VSS
–1
specifications.)
When PE1 has the
open-drain specifications.
Cw
Rw
RI
WDR
WDR
WDR
0.1 ±5%
680 ±1%
100 ±1%
µF
kΩ
Ω
Recommended
When PE1 has the
open-drain specifications.
10
constants*
VDD = 2.2 to 6 V
When PE1 has the
open-drain specifications.
Clear time (discharge)
Clear period (charge)
tWCT
Figure 8
Figure 8
WDR
WDR
100
31
µs
tWCCY
ms
When PE1 has the
open-drain specifications.
Cw
Rw
RI
WDR
WDR
WDR
0.047 ±5%
680 ±1%
100 ±1%
µF
kΩ
Ω
Recommended
When PE1 has the
open-drain specifications.
10
constants*
V
DD = 2.2 to 6 V
When PE1 has the
open-drain specifications.
Clear time (discharge)
Clear period (charge)
tWCT
Figure 8
Figure 8
WDR
WDR
40
14
µs
tWCCY
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 4).
9. TCYC = 4 × the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-32/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
open
External clock
0.15 VDD
Figure 1 External Clock Input Waveform
Ceramic oscillator
element
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6278-33/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation
Oscillation
stabilization
time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.)
CSA4.00MG
C1
C2
R
33 pF ±10%
33 pF ±10%
0 Ω
CST4.00MGW (Internal capacitor)
4 MHz (Kyocera Corporation)
KBR4.0MSA
C1
C2
R
33 pF ±10%
33 pF ±10%
0 Ω
KBR4.0MKS (Internal capacitor)
1 MHz (Murata Mfg. Co., Ltd.)
CSB1000J
C1
C2
R
100 pF ±10%
100 pF ±10%
3.3 kΩ
800 kHz (Murata Mfg. Co., Ltd.)
CSB800J
C1
C2
R
100 pF ±10%
100 pF ±10%
3.3 kΩ
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 µF
will be between 10 and 100 ms.
400 kHz (Murata Mfg. Co., Ltd.)
CSB400P
C1
C2
R
220 pF ±10%
220 pF ±10%
3.3 kΩ
If the power supply rise time is long, increase the value of CRES so that
the reset time is at least 10 ms.
No. 6278-34/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 6 Serial I/O Timing
The load conditions are the same
as those in figure 5.
Figure 7 Port PE0 Pulse Output Timing
tWCCY
:
The charge time due to the time constant of the circuit consisting of
the external components Cw, Rw, and Rl.
tWCT
:
The discharge time due to software processing.
Figure 8 Watchdog Timer Waveform
No. 6278-35/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
RC Oscillator Characteristics for the LC651154L and LC651152L
Figure 9 shows the RC oscillator characteristics for the LC651154L and LC651152L.
However, the sample-to-sample variation in the LC651154L and LC651152L RC oscillator frequency described below
does occur.
1) When:
V
DD
= 2.2 to 6.0 V, Ta = –40 to +85°C
External constants: Cext = 270 pF
Rext = 12.0 kΩ
f
will be:
MOSC
290 kHz ≤ f
≤ 841 kHz
MOSC
Therefore, only the above circuit constants are recommended.
If use of circuit constants other than the above is unavoidable, they must be in the following ranges.
Cext = 150 to 390 pF
Rext = 3 to 20 kΩ
(See figure 9.)
Note 8. The oscillator frequency must be in the range 350 to 850 kHz when V = 5.0 V and Ta = 25°C.
DD
Note 9. Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating
clock frequency range (see the oscillator divider option table) for the voltage range V = 2.2 to 6.0 V and for
DD
the temperature range Ta = –40 to 85°C.
These characteristics curves are for
reference purposes only and are not
guaranteed.
Figure 9 RC Oscillator Frequency Data (Representative Values)
No. 6278-36/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Notes on Printed Circuit Board Design
This section describes points that require care concerning noise from the point of view of the microcontroller and
presents means of preventing associated problems when designing a printed circuit board to use with these products in a
mass produced end product. The ideas presented in this section are effective design techniques for preventing and
avoiding problems (such as incorrect microcontroller operation and program failures) due to noise.
1. The V and V power supply pins
DD
SS
Insert capacitors that meet the following conditions between the V and V power supply pins.
DD
SS
• The lengths of the lines between the V and V pins and the capacitors C1 and C2 should be as close to exactly
DD
SS
equal as possible (L1 = L1’, L2 = L2’). Furthermore, these distances should be as short as possible.
• Insert two capacitors, C1 and C2 in parallel, with C1 having a large capacitance and C2 having a small capacitance.
• The V and V lines in the printed circuit board pattern should be wider than any other lines in the pattern.
DD
SS
2. The OSC1 and OSC2 clock I/O pins
— If the ceramic oscillator option is selected (See figure 2-1.)
• Keep the lines between the clock I/O pins (input: OSC1, output:
OSC2) and the external components as short as possible (the
distance Losc in the figure).
• Make the length of the lines (Lvss + L1 and Lvss + L2) from
the microcontroller V pin to the V side of the capacitors
SS
SS
connected to the oscillator element as short as possible.
• V line for the oscillator circuit and other V line should
SS
SS
branch from a point nearest to the V pin.
SS
• Due to the capacitances of the wiring on the printed circuit
board, it may be necessary to modify the values of the oscillator
circuit constants (including the values of the capacitors C1 and
C2 and the limiting resistor Rd) from the values presented in
this catalog. We recommend consulting the manufacturer of the
oscillator element with regard to these circuit constants.
Figure 2-1 Sample Oscillator Circuit 1
(Ceramic oscillator)
— If the 2-pin RC oscillator option is selected (Figure 2-2)
• Keep the lines between the clock I/O pins (input: OSC1, output:
OSC2) and the external components (the capacitor Cext and the
resistor Rext) as short as possible (the distance Losc in the figure).
• Make the length of the lines (Lvss + Lc) from the
microcontroller V pin to the V side of the capacitor
SS
SS
functioning as the oscillator element as short as possible.
• Take the V used by the oscillator circuit (as well as other V
SS
SS
usages) from a point as close as possible to the V pin.
— If the external oscillator option is selected (Figure 2-3)
• Keep the line between the clock input pin (OSC1) and the external
oscillator circuit as short as possible (the distance Losc in the figure).
• Leave the clock output pin (OSC2) open.
SS
Figure 2-2 Sample Oscillator Circuit 2
(2-pin RC oscillator)
• Make the length (Losc) of the lines to the V
and V pins
DD
SS
used by the external oscillator as short as possible.
— Other points that apply to all oscillator circuits:
External
oscillator
• Keep all lines that carry signals that change rapidly, signals that
have large amplitudes due to being connected to the medium-
voltage handling capacity ports, or signals that carry large
currents as far away from the oscillator circuit as possible. Also,
do not allow such signal lines to cross any clock-signal related
lines.
Figure 2-3 Sample Oscillator Circuit 3
(External oscillator)
No. 6278-37/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
3. RES: Reset pin
• Keep the length of lines (Lres in the figure) from the RES pin to external circuits as short as possible.
• Keep the length of the lines (L1 and L2) to the capacitor (Cres) inserted between RES and V as short as possible.
SS
External
circuit
Figure 3 RES Pin Wiring
4. TEST: Test pin
• Keep the length of the line (L) from the TEST pin to the V pin as short as possible.
SS
• Run the line from the TEST pin to the V pin as close to the V pin as possible.
SS
SS
Figure 4 TEST Pin Wiring
5. AD0 to AD7: Analog input pins
Analog input pin lines, such as those used to connect to an A/D converter input pin or a comparator input pin should
be connected so as to meet the following conditions.
• Keep the line (L1) between the limiting resistor (Rl) and the analog input pin as short as possible.
• Locate the capacitor inserted between the analog input pins and the AV- pin (the A/D converter reference voltage
input pin) as close as possible to the AV- input pin. That is, make the line length L1 + L2 as short as possible.
Analog
input pin
External circuit
(sensor block)
Figure 5 Analog Input Pin Wiring
6. I/O pins
All of the pins on these products function as both input and output pins.
• When used as an input pin, insert a limiting resistor, and keep the length of the line to that pin as short as possible.
Supplement: This is not only useful in printed circuit board design, but is also useful in preventing and avoiding
problems (such as incorrect microcontroller operation and program failures) by taking the program specifications
and microcontroller option selections described below into consideration.
• If signals are input from external sources when the microcontroller power supply is unstable, select the medium-
voltage handling capacity (n-channel open drain) output as the output type option for that input pin, and also insert
a limiting resistor in the input circuit.
• Always implement key chattering exclusion measures for external signals applied to microcontroller input pins.
• The pin output data should be re-output periodically with an output instruction (OP or SPB).
No. 6278-38/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
• When reading data input to a pin that can function as either input or output, set the output value for that pin to 1
every time the input is read using an output instruction (OP or SPB).
7. Unused pins
• See the users manual for the product or refer to the pin functions as described in the semiconductor report for the
device.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of September, 1999. Specifications and information herein are
subject to change without notice.
PS No. 6278-39/39
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