LC66308A [SANYO]
Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM; 四位单片微控制器有4个，6个和8 KB的片上ROM
| 型号： | LC66308A |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Four-Bit Single-Chip Microcontrollers with 4, 6, and 8 KB of On-Chip ROM |
| 文件： | 总13页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN5996
CMOS IC
LC662104A, 662106A, 662108A
Four-Bit Single-Chip Microcontrollers
with 4, 6, and 8 KB of On-Chip ROM
• Instruction cycle time: 0.95 to 10 µs (at 3.0 to 5.5 V)
• Powerful timer functions and prescalers
— Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
— Time base function using a 12-bit prescaler.
• Powerful interrupt system with 6 interrupt factors and 6
interrupt vector locations.
— External interrupts: 3 factors/3 vector locations
— Internal interrupts: 3 factors/3 vector locations
• Flexible I/O functions
Selectable options include 20-mA drive outputs, pull-up
and open drain circuits.
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
• Power saving functions using halt and hold modes.
• Packages: DIP30SD, MFP30S
• Evaluation ICs: LC665099 (evaluation chip) + EVA86K
- ECB662500
Overview
The LC662104A, LC662106A, and LC662108A are 4-bit
CMOS microcontrollers that integrate on a single chip all
the functions required in a special-purpose telephone
controller, including ROM, RAM, I/O ports, a serial
interface, a DTMF generator, timers, and interrupt
functions. These microcontrollers are available in a 30-pin
package.
Features and Functions
• On-chip ROM capacities of 4, 6, and 8 kilobytes, and an
on-chip RAM capacity of 384 × 4 bits.
• Fully supports the LC66000 Series common instruction
set (128 instructions). (The special-purpose instructions
for TM1 and SI/01 are disabled.)
• I/O ports: 24 pins
• DTMF generator
This microcontroller incorporates a circuit that can
generate two sine wave outputs, DTMF output.
• 8-bit serial interface: one circuit
LC66E2108(on-chip EPROM microcontroller)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
101698RM (OT) No. 5966-1/13
LC662104A, 662106A, 662108A
Package Dimensions
unit: mm
unit: mm
3196-DIP30SD
[LC662104A]
3216-MFP30S
[LC662106A]
SANYO: DIP30SD
SANYO: MFP30S
No. of
RAM
capacity
Type No.
pins
ROM capacity
Package
QFP48E
Features
LC66304A/306A/308A
LC66404A/406A/408A
LC66506B/508B/512B/516B
LC66354A/356A/358A
LC66354S/356S/358S
LC66556A/558A/562A/566A
LC66354B/356B/358B
LC66556B/558B/562B/566B
LC66354C/356C/358C
LC662104A/06A/08A
42
42
64
42
42
64
42
64
42
30
42
64
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
DIP42S
DIP42S
DIP64S
DIP42S
Normal versions
4.0 to 6.0 V/0.92 µs
512 W
QFP48E
QFP64A
QFP48E
QFP44M
QFP64E
QFP48E
QFP64E
QFP48E
MFP30S
QFP48E
QFP64E
6 K/8 K/12 K/16 KB 512 W
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
512 W
Low-voltage versions
2.2 to 5.5 V/3.92 µs
6 K/8 K/12 K/16 KB 512 W
4 K/6 K/8 KB 512 W
6 K/8 K/12 K/16 KB 512 W
DIP64S
DIP42S
DIP64S
DIP42S
DIP30SD
DIP42S
DIP64S
Low-voltage high-speed versions
3.0 to 5.5 V/0.92 µs
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
384 W
2.5 to 5.5 V/0.92 µs
On-chip DTMF generator versions
3.0 to 5.5 V/0.95 µs
LC662304A/06A/08A/12A/16A
LC662508A/12A/16A
4 K/6 K/8 K/12 K/16 KB 512 W
8 K/12 K/16 KB 512 W
Dual oscillator support
3.0 to 5.5 V/0.95 µs
LC665304A/06A/08A/12A/16A
48
4 K/6 K/8 K/12 K/16 KB 512 W
DIP48S
QFP48E
DIC42S
with window
QFC48
with window
LC66E308
LC66P308
LC66E408
LC66P408
LC66E516
42
42
42
42
64
EPROM 8 KB
OTPROM 8 KB
EPROM 8 KB
OTPROM 8 KB
EPROM 16 KB
512 W
512 W
512 W
512 W
512 W
DIP42S
QFP48E
DIC42S
with window
QFC48
with window
Window and OTP evaluation versions
4.5 to 5.5 V/0.92 µs
DIP42S
QFP48E
DIC64S
with window
QFC64
with window
LC66P516
64
30
OTPROM 16 KB
EPROM 8 KB
512 W
384 W
DIP64S
QFP64E
LC66E2108
DIC42S
with window
QFC48
with window
LC66E2316
LC66E2516
LC66E5316
42
64
EPROM 16 KB
EPROM 16 KB
EPROM 16 KB
512 W
512 W
512 W
Window evaluation versions
4.5 to 5.5 V/0.95 µs
DIC64S
with window
QFC64
with window
DIC52S
with window
QFC48
with window
52/48
LC66P2108
LC66P2316
LC66P2516
LC66P5316
30
42
64
48
OTPROM 8 KB
OTPROM 16 KB
OTPROM 16 KB
OTPROM 16 KB
384 W
512 W
512 W
512 W
DIP30SD
DIP42S
DIP64S
DIP48S
MFP30S
QFP48E
QFP64E
QFP48E
OTP
4.0 to 5.5 V/0.95 µs
No. 5996-2/13
LC662104A, 662106A, 662108A
We recommend the use of reflow-soldering techniques to solder-mount MFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly
immersed in a dip-soldering bath (dip-soldering techniques).
No. 5996-3/13
LC662104A, 662106A, 662108A
System Block Diagram
Differences between the LC663XX Series and the LC6621XX Series
LC6630X Series
(Including the LC66599 evaluation chip)
Item
System differences
• Hardware wait time (number of
cycles) when hold mode is cleared
LC6635XB Series
LC6621XX Series
16384 cycles
65536 cycles
16384 cycles
About 64 ms at 4 MHz (Tcyc = 1 µs) About 16 ms at 4 MHz (Tcyc = 1 µs) About 16 ms at 4 MHz (Tcyc = 1 µs)
• Value of timer 0 after a reset
(Including the value after hold mode Set to FF0.
is cleared)
Set to FFC.
None
Set to FFC.
Yes
None (Tools are handled with
• DTMF generator
external devices.)
None (Tools are handled with
external devices.)
• Inverter array
• SIO1
None
Yes
None
None
None
Yes
• Three-value inputs/comparator
inputs
Yes
Yes
• Three-state output from P31
and P32
None
None
Yes
• Using P0 to clear halt mode
In 4-bit groups
In 4-bit groups
Can be specified for each bit.
None for INT3, INT4, and INT5.
(Tools are handled with external
devices.)
INT3, INT4, and INT5 can be used
with the internal functions.
• External extended interrupts
None for INT3, INT4, and INT5.
Shared with INT2
Shared with INT2
(Tools are handled with external
devices.)
• Other P53 functions
Shared with INT2
• LC66304A/306A/308A
4.0 to 6.0 V/0.92 to 10 µs
• LC66E308/P308
• 3.0 to 5.5 V/0.92 to 10 µs
• LC6635XA
2.2 to 5.5 V/3.92 to 10 µs
3.0 to 5.5 V/1.96 to 10 µs
Differences in main characteristics
• Operating power-supply voltage
and operating speed (cycle time)
3.0 to 5.5 V/0.95 to 10 µs
4.5 to 5.5 V/0.92 to 10 µs
• Pull-up resistors
P0, P1, P4, and P5: about 3 to 10 kΩ
P0, P1, P4, and P5: about 3 to 10 kΩ P0, P1, P4, and P5: about 100 kΩ
• P2 to P6 and PC: 15V handling
• P0, P1, PD, PE: Normal voltage
handling
• P2 to P6 and PC: 15V handling
• P0, P1, PD, PE: Normal voltage
handling
P2 to P4, P51, and P53: 15V voltage
handling Others: normal voltage
handling
• Port voltage handling
No. 5996-4/13
LC662104A, 662106A, 662108A
Pin Function Overview
State after a
reset
Pin
I/O
Overview
Output driver type
Options
I/O ports P00 to P03
P00
P01
P02
P03
• Input or output in 4-bit or 1-bit units
• P00 to P03 support the halt mode
control function (This function can be
specified in bit units.)
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pull-up MOS or Nch
OD output
• Output level on reset
I/O
High or low (option)
P10
P11
P12
P13
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Pull-up MOS or Nch
OD output
• Output level on reset
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
I/O
High or low (option)
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0
pin.
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• P23 is also used as the INT0 interrupt
request pin, and also as the timer 0
event counting and pulse width
measurement input.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15V handling when OD
option selected
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
CMOS or Nch OD
output
I/O
H
I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt
request.
• P31 is also used for the square wave
output from timer 0.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• Nch: +15V handling when OD
option selected
P30/INT1
P31/POUT0
P32
CMOS or Nch OD
output
I/O
H
• P31 and P32 also support 3-state
outputs.
Hold mode control input
• Hold mode is set up by the HOLD
instruction when HOLD is low.
• In hold mode, the CPU is restarted by
setting HOLD to the high level.
• This pin can be used as input port P33
along with P30 to P32.
P33/HOLD
I
• When the P33/HOLD pin is at the low
level, the CPU will not be reset by a
low level on the RES pin. Therefore,
applications must not set P33/HOLD
low when power is first applied.
I/O ports P40 to P43
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used • Nch: Intermediate sink current • Pull-up MOS or Nch
in conjunction with P50 to P53.
• Can be used for output of 8-bit ROM
data when used in conjunction with
P50 to P53.
• Pch: Pull-up MOS type
P40
P41
P42
P43
I/O
type
OD output
• Output level on reset
High or low (option)
• Nch: +15V handkling when
OD option selected
Continued on next page.
No. 5996-5/13
LC662104A, 662106A, 662108A
Continued from preceding page.
State after a
reset
Pin
I/O
Overview
Output driver type
Options
• Pull-up MOS or Nch
OD output
• Output level on reset
• Output level after a
reset
(An external pull-up
resistor must be
supplied when used
for DT output.)
I/O ports P50 to P53
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
• Nch: +15-V handling when
OD option selected (P51 and
P53 only)
P50
• Input or output in 4-bit or 1-bit units
• P51 is also used for dial pulse output
• P52 is also used for DTMF output
• P53 is also used as the INT2 interrupt
request.
P51/DP
P52/DT
P53/INT2
I/O
High or low (option)
OSC1
OSC2
I
System clock oscillator connections
When an external clock is used, leave
OSC2 open and connect the clock signal
to OSC1.
Ceramic oscillator or
external clock selection
Option selection
O
System reset input
When the P33/HOLD pin is at the high
level, a low level input to the RES pin will
initialize the CPU.
RES
I
I
CPU test pin
This pin must be connected to VSS
during normal operation.
TEST
VDD
VSS
Power supply pins
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD
.
CMOS output: Complementary output.
OD output: Open-drain output.
No. 5996-6/13
LC662104A, 662106A, 662108A
User Options
1. Port 0, 1, 4, and 5 output level options a reset
The output levels at reset for I/O ports 0, 1, 4, and 5 in independent 4-bit groups, can be selected from the following
two options.
Option
Output high at reset
Output low at reset
Conditions and notes
The four bits of ports 0, 1, 4, or 5 are set in a group
The four bits of ports 0, 1, 4, or 5 are set in a group
2. Oscillator circuit options
• Main clock
Option
Circuit
Conditions and notes
OSC1
External clock
The input has Schmitt characteristics
C1
OSC1
OSC2
Ceramic oscillator
Ceramic oscillator
C2
Note: There is no RC oscillator option.
3. Watchdog timer option
A runaway detection function (watchdog timer) can be selected as an option.
4. Port output type options
• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, and P5 can be selected
individually from the following two options.
Option
Circuit
Conditions and notes
Output data
Input data
The port P2, P3, P5, and P6 inputs have Schmitt
characteristics.
Open-drain output
DSB
Output data
Input data
The port P2, P3, and P5 inputs have Schmitt
characteristics.
Output with built-in pull-up
resistor
The CMOS outputs (ports P2 and P3) and the
pull-up MOS outputs (P0, P1, P4, and P5) are
distinguished by the drive capacity of the p-
channel transistor.
DSB
No. 5996-7/13
LC662104A, 662106A, 662108A
LC662108 Series Option Data Area and Definitions
ROM area
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Option specified
Output level at reset
Option/data relationship
0 = high level, 1 = low level
P5
P4
Unused
This bit must be set to 0.
Oscillator option
Unused
0 = (RC oscillator) external clock, 1 = ceramic oscillator
This bit must be set to 0.
2000H
P1
Output level at reset
0 = low level, 1 = high level
0 = none, 1 = yes
P0
Watchdog timer option
P13
P12
Output type
P11
0 = OD, 1 = PU
0 = OD, 1 = PU
P10
P03
2001H
2002H
2003H
P02
Output type
P01
P00
Unused
P32
This bit must be set to 0.
0 = OD, 1 = PU
P31
P30
P23
P22
P21
P20
P53
P52
P51
P50
P43
P42
P41
P40
Output type
Output type
0 = OD, 1 = PU
0 = OD, 1 = PU
0 = OD, 1 = PU
Output type
Output type
2004H
to
This bit must be set to 0.
Unused
*: Location 2008H must be set to 7F.
200CH
This data is generated by the assmbler (21).
If the assembler is not used, set this data to 00.
200DH
Reserved. Must be set to predefined values.
This data is generated by the assmbler (0x).
If the assembler is not used, set this data to 00.
200EH
Reserved. Must be set to predefined values.
Continued on next page.
No. 5996-8/13
LC662104A, 662106A, 662108A
Continued from preceding page.
ROM area
Bit
7
Option specified
Option/data relationship
6
5
4
This data is generated by the assmbler (00).
200FH
Reserved. Must be set to predefined values.
3
If the assembler is not used, set this data to (00).
2
1
0
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Note
1
Maximum supply voltage
VDD max
VDD
–0.3 to +7.0
V
P2, P3 (except for the P33/HOLD pin),
P4, P51, and P53
VIN1
–0.3 to +15.0
V
Input voltage
V
IN2
All other inputs
–0.3 to VDD + 0.3
–0.3 to +15.0
V
V
V
2
1
2
V
OUT1
OUT2
P2 and P3 (except for the P33/HOLD pin)
All other inputs
Output voltage
V
–0.3 to VDD + 0.3
P0, P1, P2, P3 (except for the P33/HOLD pin),
P4, P5
ION1
20
mA
3
Output current per pin
Total pin current
–IOP1
–IOP2
Σ ION1
Σ ION2
Σ IOP1
Σ IOP2
Pd max
Topr
P0, P1, P4, P5
2
mA
mA
mA
mA
mA
mA
mW
°C
4
4
3
3
4
4
5
P2, P3 (except for the P33/HOLD pin)
P1, P2, P3 (except for the P33/HOLD pin)
P0, P4, P5
4
75
75
P1, P2, P3 (except for the P33/HOLD pin)
P0, P4, P5
25
25
Allowable power dissipation
Operating temperature
Storage temperature
Ta = –30 to +70°C: DIP30S (MFP30S)
340 (200)
–30 to +70
–55 to +125
Tstg
°C
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that
pin apply.
2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed.
3. Sink current
4. Source current
5. We recommend the use of reflow soldering techniques to solder mount MFP packages.
Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering
bath (dip-soldering techniques).
No. 5996-9/13
LC662104A, 662106A, 662108A
Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified.
Ratings
typ
Parameter
Symbol
VDD
Conditions
Unit
Note
min
3.0
max
Operating supply voltage
VDD
5.5
5.5
V
V
Memory retention supply voltage
V
DDH
VDD: During hold mode
1.8
P2, P3 (except for the P33/HOLD pin),
P4, P51, and P53: N-channel output transistor off
VIH1
VIH2
VIH3
0.8 VDD
13.5
VDD
VDD
V
V
V
1
P33/HOLD, RES, OSC1:
N-channel output transistor off
Input high-level voltage
Input low-level voltage
0.8 VDD
0.8 VDD
P0, P1, P50, P52:
N-channel output transistor off
P2, P3 (except for the P33/HOLD pin),
RES, and OSC1: N-channel output transistor off
VIL1
VIL2
VIL3
VSS
VSS
VSS
0.2 VDD
0.2 VDD
0.2 VDD
V
V
V
2
P33/HOLD: VDD = 1.8 to 5.5 V
P0, P1, P4, P5, TEST:
N-channel output transistor off
Operating frequency
(instruction cycle time)
fop
(Tcyc)
0.4
(10)
4.20
(0.95)
MHz
(µs)
[External clock input conditions]
Frequency
fext
0.4
4.20
MHz
ns
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Pulse width
t
extH, textL
100
Rise and fall times
textR, textF
30
ns
Note: 1. Applies to pins with open-drain specifications. However, VIH2 is applied to the P33/HOLD pin.
When ports P2 and P3 have CMOS output specifications they cannot be used as input pins.
2. Applies to pins with open-drain specifications.
No. 5996-10/13
LC662104A, 662106A, 662108A
Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.
Ratings
typ
Parameter
Symbol
Conditions
Unit
µA
Note
1
min
max
5.0
P2, P3 (except for the P33/HOLD pin), P4,
P51, and P53: VIN = 13.5 V, with the output
Nch transistor off
IIH1
Input high-level current
Input low-level current
P0, P1, P50, P52, OSC1, RES, and P33/HOLD:
IIH2
1.0
µA
µA
1
2
3
V
IN = VDD, with the output Nch transistor off
P0, P1, P2, P3, P4, and P5:
IN = VSS, with the output Nch transistor off
IIL1
–1.0
V
P2, P3 (except for the
P33/HOLD pin)
IOH = –1 mA
OH = –0.1 mA
VDD – 1.0
VDD – 0.5
30
Output high-level voltage
V
OH1
V
kΩ
V
I
Value of the output pull-up resistor
RPO
P0, P1, P4, P5
100
150
0.4
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): IOL = 1.6 mA
VOL
VOL
1
2
5
Output low-level voltage
P0, P1, P2, P3, P4, and P5
(except for the P33/HOLD pin): IOL = 8 mA
1.5
5.0
1.0
V
I
I
OFF1
OFF2
P2, P3, P4, P51, and P53: VIN = 13.5 V
µA
µA
6
6
Output off leakage current
Does not apply to P2, P3, P4, P51, and P53:
V
IN = VDD
[Schmitt characteristics]
Hysteresis voltage
VHYS
VtH
0.1 VDD
High-level threshold voltage
Low-level threshold voltage
[Ceramic oscillator]
P2, P3, P4, P5, and RES
0.5 VDD
0.2 VDD
0.8 VDD
0.5 VDD
V
V
VtL
Oscillator frequency
fCF
OSC1, OSC2: See Figure 2. 4 MHz
See Figure 3. 4 MHz
4.0
MHz
ms
Oscillator stabilization time
[Serial clock]
fCFS
10.0
Input
0.9
2.0
0.4
1.0
µs
Tcyc
µs
Cycle time
Output
tCKCY
SCK0: With the timing of Figure 4 and the test
load of Figure 5.
Input
tCKL
tCKH
Low-level and high-level
pulse widths
Output
Output
Tcyc
µs
Rise an fall times
[Serial input]
t
CKR, tCKF
0.1
Data setup time
tICK
tCKI
0.3
0.3
µs
µs
SI0: With the timing of Figure 4.
Stipulated with respect to the rising edge (↑) of
SCK0.
Data hold time
[Serial output]
SO0: With the timing of Figure 4 and the test
load of Figure 5. Stipulated with respect to the
falling edge (↓) of SCK0.
Output delay time
[Pulse conditions]
tCKO
0.3
µs
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT0 high and low-level
tIOH, tIOL
2
Tcyc
High and low-level pulse widths
for interrupt inputs other than INT0
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
t
IIH, tIIL
2
3
Tcyc
Tcyc
RES high and low-level
pulse widths
RES: Figure 6, conditions under which reset
can be applied.
t
RSH, tRSL
VDD: 4-MHz ceramic oscillator
4.5
4.5
8.0
8.0
5.5
5.5
10
mA
mA
mA
mA
µA
Operating current drain
IDD OP
8
V
DD: 4-MHz external clock
VDD: 4-MHz ceramic oscillator
DD: 4-MHz external clock
VDD: VDD = 1.8 to 5.5 V
2.5
Halt mode current drain
Hold mode current drain
IDDHALT
IDDHOLD
V
2.5
0.01
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins.
4. With the output Nch transistor off for pull-up output specification pins.
6. With the output Pch transistor off for open-drain output specification pins.
7. Reset state
No. 5996-11/13
LC662104A, 662106A, 662108A
Tone (DTMF) Output Characteristics
DC Characteristics at Ta = –30 to +70°C, VSS = 0 V
Ratings
typ
Parameter
Symbol
VT1
Conditions
DT: Single tone, VDD = 3.5 to 5.5 V*
DT: Dual tones, VDD = 3.5 to 5.5 V*
Unit
Vp-p
dB
min
0.9
max
2.0
Tone output voltage
1.3
Row/column tone output
voltage ratio
DBCR1
1.0
2.0
3.0
Note*: See Figure 7.
VDD
0.8 VDD
0.2 VDD
VSS
OSC1
(OSC2)
t
t
extH
extL
External clock
Open
t
t
extR
extF
1/f
ext
Figure 1 External Clock Input Waveform
Operating VDD lower limit
0 V
OSC1
OSC2
Ceramic
oscillator
C1
C2
Stable oscillation
Oscillator unstable
period tCFS
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
Table 1 Recomended Ceramic Oscillator Constants
External capacitor type
Built-in capacitor type
4 MHz
(Murata Mfg. Co., Ltd.)
CSA4.00MG
4 MHz
(Murata Mfg. Co., Ltd.)
CST4.00MG
C1 = 33 pF
C2 = 33 pF
C1 = 33 pF
C2 = 33 pF
4 MHz
(Kyocera Corporation)
KBR4.0MSB
4 MHz
(Kyocera Corporation)
KBR4.0MKC
t
CKCY
t
CKR
t
t
t
CKH
CKF
CKL
SCK0
0.8 V
V
DD (input)
– 1
0.2 V
0.4 V
DD (input)
DD (output)
DD
(output)
t
t
ICK CKI
SI0
0.8 V
0.2 V
DD
DD
t
CK0
SO0
V
DD
0.4 V
– 1
DD
Figure 4 Serial I/O Timing Figure 5
Timing Load
No. 5996-12/13
LC662104A, 662106A, 662108A
t
t
I0H
I1H
t
RSH
0.8 V
DD
0.2 V
DD
t
t
I0L
I1L
t
t
PINL
RSL
Figure 6 Input Timing for the INT0, INT1, INT2, and RES pins
Figure 7 Tone Output Pin Load
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject
to change without notice.
PS No. 5996-13/13
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