LC66E5316 [SANYO]
Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip EPROM; 四位单芯片微控制器的片上EPROM 16 KB
| 型号： | LC66E5316 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Four-Bit Single-Chip Microcontroller with 16 KB of On-Chip EPROM |
| 文件： | 总27页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS LSI
LC66E5316
No. 5488
Four-Bit Single-Chip Microcontroller
with 16 KB of On-Chip EPROM
Preliminary
Overview
The LC66E5316 is an on-chip EPROM version of the
LC6653XX Series CMOS 4-bit single-chip
microcontrollers. The LC66E5316 provides the same
functions as the LC665316A, and is pin compatible with
that product. Since the LC66E5316 is provided in a
window package, it can be reprogrammed repeatedly and is
thus optimal for program development.
Package Dimensions
unit: mm
3225-DIC52S
[LC66E5316]
46.74
52
1
27
26
Features and Functions
• On-chip EPROM capacity of 16 kilobytes, and an on-
chip RAM capacity of 512 × 4 bits.
41.94
• Fully supports the LC66000 Series common instruction
set (128 instructions).
• I/O ports: 42 pins
• A sub-oscillator circuit can be used (option)
This circuit allows power dissipation to be reduced by
operating at lower speeds.
0.9
0.46
44.45
1.778
1.145
SANYO: DIC52S
• 8-bit serial interface: two circuits (can be connected in
cascade to form a 16-bit interface)
unit: mm
3157-QFC48
• Instruction cycle time: 0.95 to 10 µs (at 4.5 to 5.5 V)
• Powerful timer functions and prescalers
— Time limit timer, event counter, pulse width
measurement, and square wave output using a 12-bit
timer.
[LC66E5316]
20.0
14.0
1.0
3.0
0.35
— Time limit timer, event counter, PWM output, and
square wave output using an 8-bit timer.
— Time base function using a 12-bit prescaler.
• Powerful interrupt system with 8 interrupt factors and 8
interrupt vector locations.
1.5
0.15
25
36
37
24
— External interrupts: 3 factors/3 vector locations
— Internal interrupts: 5 factors/5 vector locations
• Flexible I/O functions
13
48
16-value comparator inputs, 20-mA drive outputs,
inverter circuits, pull-up and open-drain circuits
selectable as options.
• Optional runaway detection function (watchdog timer)
• 8-bit I/O functions
1
12
2.2
4.2
4.77max
SANYO: QFC48
• Power saving functions using halt and hold modes.
• Packages: DIC52S (window), QFC48 (window)
• Evaluation LSIs: LC66599 (evaluation chip) +
EVA800/850 - TB662YXX2
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
21097HA (OT) No. 5488-1/27
LC66E5316
Series Organization
No. of
pins
RAM
capacity
Type No.
ROM capacity
Package
QFP48E
Features
LC66304A/306A/308A
LC66404A/406A/408A
LC66506B/508B/512B/516B
LC66354A/356A/358A
LC66354S/356S/358S
LC66556A/558A/562A/566A
LC66354B/356B/358B
LC66556B/558B/562B/566B
LC66354C/356C/358C
LC662104A/06A/08A
42
42
64
42
42
64
42
64
42
30
42
64
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
512 W
DIP42S
Normal versions
4.0 to 6.0 V/0.92 µs
DIP42S
DIP64S
DIP42S
QFP48E
QFP64A
QFP48E
QFP44M
QFP64E
QFP48E
QFP64E
QFP48E
MFP30S
QFP48E
QFP64E
6 K/8 K/12 K/16 KB 512 W
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
512 W
Low-voltage versions
2.2 to 5.5 V/3.92 µs
6 K/8 K/12 K/16 KB 512 W
4 K/6 K/8 KB 512 W
6 K/8 K/12 K/16 KB 512 W
DIP64S
DIP42S
DIP64S
DIP42S
DIP30SD
DIP42S
DIP64S
Low-voltage high-speed versions
3.0 to 5.5 V/0.92 µs
4 K/6 K/8 KB
4 K/6 K/8 KB
512 W
384 W
2.5 to 5.5 V/0.92 µs
On-chip DTMF generator versions
3.0 to 5.5 V/0.95 µs
LC662304A/06A/08A/12A/16A
LC662508A/12A/16A
4 K/6 K/8 K/12 K/16 KB 512 W
8 K/12 K/16 KB 512 W
Dual oscillator support
3.0 to 5.5 V/0.95 µs
LC665304A/06A/08A/12A/16A
48
4 K/6 K/8 K/12 K/16 KB 512 W
DIP48S
QFP48E
DIC42S
with window
QFC48
with window
LC66E308
LC66P308
LC66E408
LC66P408
LC66E516
42
42
42
42
64
EPROM 8 KB
OTPROM 8 KB
EPROM 8 KB
OTPROM 8 KB
EPROM 16 KB
512 W
512 W
512 W
512 W
512 W
DIP42S
QFP48E
DIC42S
with window
QFC48
with window
Window and OTP evaluation versions
4.5 to 5.5 V/0.92 µs
DIP42S
QFP48E
DIC64S
with window
QFC64
with window
LC66P516
64
30
OTPROM 16 KB
EPROM 8 KB
512 W
384 W
DIP64S
QFP64E
LC66E2108*
DIC42S
with window
QFC48
with window
LC66E2316
LC66E2516
LC66E5316
42
64
EPROM 16 KB
EPROM 16 KB
EPROM 16 KB
512 W
512 W
512 W
Window evaluation versions
4.5 to 5.5 V/0.92 µs
DIC64S
with window
QFC64
with window
DIC52S
with window
QFC48
with window
52/48
LC66P2108*
30
42
64
48
OTPROM 8 KB
OTPROM 16 KB
OTPROM 16 KB
OTPROM 16 KB
384 W
512 W
512 W
512 W
DIP30SD
DIP42S
DIP64S
DIP48S
MFP30S
QFP48E
QFP64E
QFP48E
LC66P2316*
OTP
4.0 to 5.5 V/0.95 µs
LC66P2516
LC66P5316
Note: * Under development
No. 5488-2/27
LC66E5316
Pin Assignments
DIC52S
P20/SI0/A0
P21/SO0/A1
1
2
52 P13/D7
51 P12/D6
3
4
5
6
50 P11/D5
49 P10/D4
48 P03/D3
47 P02/D2
P22/SCK0/A2
P23/INT0/A3
P30/INT1/A4
P31/POUT0/A5
P32/POUT1/A6
7
46 P01/D1
8
9
45 P00/D0
V
SS
44 PD3/AN4/INV4O
43 PD2/AN3/INV4I
42 PD1/AN2/INV3O
41 PD0/AN1/INV3I
40 PC3/INV2O/DASEC
39 PC2/INV2I/CE
38 PC1
37 PC0
36 P83
35 P82
34 P81/DS1
33 P80/DS0
32 P63/PIN1
31 P62/SCK1
30 P61/SO1
29 P60/SI1
OSC1
OSC2
LC66E5316
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
V
DD
RES/V /OE
PP
PE0/XT1
PE1/XT2
TEST/EPMOD
P33/HOLD
P40/INV0I/A7
P41/INV0O/A8
P42/INV1I/A9
P43/INV1O/A10
P50/A11
P51/A12
P52/A13
P53/INT2/TA
N. C.
28 N. C.
27 N. C.
N. C.
QFC48
36 35 34 33 32 31 30 29 28 27 26 25
P02/D2 37
P03/D3 38
24 P81/DS1
23 P80/DS0
22 P63/PIN1
21 P62/SCK1
20 P61/SO1
19 P60/SI1
P10/D4 39
P11/D5 40
LC66E5316
P12/D6 41
P13/D7 42
P20/SI0/A0 43
P21/SO0/A1 44
P22/SCK0/A2 45
P23/INT0/A3 46
P30/INT1/A4 47
P31/POUT0/A5 48
18 P53/INT2/TA
17 P52/A13
16 P51/A12
15 P50/A11
14 P43/INV1O/A10
13 P42/INV1I/A9
1
2 3 4 5 6 7 8 9 10 11 12
Top view
No. 5488-3/27
LC66E5316
Usage Notes
The LC66E5316 was created for program development, product evaluation, and prototype development for products
based on the LC6653XX Series microcontrollers. Keep the following points in mind when using this product.
1. After a reset
The RES pin must be held low for an additional 3 instruction cycles after the oscillator stabilization period has
elapsed. Also, the port output circuit types are set up during the 9 instruction cycles immediately after RES is set
high. Only then is the program counter set to 0 and program execution started from that location. (The port output
circuits all revert to the open-drain type during periods when RES is low.)
V
min
DD
V
DD
OSC
RES
At least 3
instruction
At least 10 ms
Oscillator
stabilization
Location Location
Program execution (PC)
Port output type
0
1
Option switching
period
Option specification
Open drain
9 instruction
cycles
2. Notes on LC6653XX evaluation
The high end of the EPROM area (locations 3FF0H to 3FFFH) are the option specification area. Option specification
data must be programmed for and loaded into this area. The Sanyo specified cross assembler for this product is the
program LC66S.EXE. Also, insert JMP instructions so that user programs do not attempt to execute addresses that
exceed the capacity of the mask ROM, and write zeros (00H) to areas (other than 3FF0H to 3FFFH) that exceed the
actual capacity of the mask ROM.
3. Always apply an opaque seal to the window on the LC66E5316 package when actually using the device.
Main differences between the LC66E5316, LC66P5316, and LC6653XX Series
Item
LC6653XX Series (mask version)
–30 to +70°C
LC66E5316
+10 to +40°C
LC66P5316
–30 to +70°C
Differences in the main
characteristics
• Operating temperature range
3.0 to 5.5 V/0.95 to 10 µs
(When the main oscillator is
operating)
4.5 to 5.5 V/0.95 to 10 µs
(When the main oscillator is
operating)
4.0 to 5.5 V/0.95 to 10 µs
(When the main oscillator is
operating)
• Operating supply voltage/operating
frequency (cycle time)
3.0 to 5.5 V/25 to 127 µs
4.5 to 5.5 V/25 to 127 µs
4.0 to 5.5 V/25 to 127 µs
(When the sub-oscillator is operating) (When the sub-oscillator is operating) (When the sub-oscillator is operating)
Typical: 10 µA
Typical: 10 µA
• Input high-level current (RES)
• Input low-level current (RES)
Maximum: 1 µA
Maximum: 1 µA
(normal operation and halt mode)
Hold mode: 1 µA maximum
(normal operation and halt mode)
Hold mode: 1 µA maximum
Typical: 100 µA
Typical: 100 µA
• Current drain
(Operating at 4 MHz)
(Operating at 32 kHz)
(Halt mode at 4 MHz)
(Halt mode at 32 kHz)
(Hold mode)
Larger than that for the mask versions Larger than that for the mask versions
Typical: 10 nA, maximum: 10 µA
Typical: 10 nA, maximum: 10 µA*
Typical: 10 nA, maximum: 10 µA*
The output type specified in
the options
Port output types at reset
Package
Open-drain outputs
Open-drain outputs
• DIP48S
• QFP48E
• DIC52S window package
• QFC48 window package
• DIP48S
• QFP48E
Note: * Although the microcontroller will remain in hold mode if the RES pin is set low while it is in hold mode, always use the reset start sequence (after
switching HOLD from low to high, switch RES from low to high) when clearing hold mode. Also a current of about 100 µA flows from the RES pin
when it is low. This increases the hold mode current drain by about 100 µA.
See the data sheets for the individual products for details on other differences.
No. 5488-4/27
LC66E5316
System Block Diagram
RAM STACK
(512W)
EPROM
EPROM
control
A0 to A
D0 to D
(16KB)
RES
C
Z
TEST
FLAG
SYSTEM
CONTROL
CE
DASEC
/OE
OSC1
OSC2
HOLD
V
PP
E
M
R
DD DD
P P P P
H L X Y
ALU
EPMOD
TA
PC
SP
E
A
XT1
XT2
POUT0
SI0
MPX
TIMER0
SERIAL I/O 0
SO0
PRESCALER
MPX
AN1 to 4
ADC
PE
SCK0
INT0
INT1, INT2
INTERRUPT
CONTROL
SI1
PD
MPX
TIMER1
P5
SERIAL I/O 1
SO1
SCK1
PIN1, POUT1
PC
INVxO
DS1
INVxI
(x=0 to 4)
P0
P1
P2
P3
P4
P6
P8
DS0
Pin Function Overview
State after a Standby mode
Pin
I/O
Overview
Output driver type
Options
reset
operation
I/O ports P00 to P03
Hold mode:
Output off
P00/D0
P01/D1
P02/D2
P03/D3
• Input or output in 4-bit or 1-bit units
• P00 to P03 support the halt mode
control function (This function can be
specified in bit units.)
• Pull-up MOS or
Nch OD output
• Output level on
reset
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
High or low
(option)
I/O
Halt mode:
Output
retained
• Used as data pins in EPROM mode
Hold mode:
Output off
P10/D4
P11/D5
P12/D6
P13/D7
• Pull-up MOS or
Nch OD output
• Output level on
reset
I/O ports P10 to P13
• Input or output in 4-bit or 1-bit units
• Used as data pins in EPROM mode
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
High or low
(option)
I/O
Halt mode:
Output
retained
I/O ports P20 to P23
• Input or output in 4-bit or 1-bit units
• P20 is also used as the serial input SI0
pin.
Hold mode:
Output off
P20/SI0/A0
P21/SO0/A1
P22/SCK0/
A2
• P21 is also used as the serial output
SO0 pin.
• P22 is also used as the serial clock
SCK0 pin.
• Pch: CMOS type
• Nch: Intermediate sink current
type
CMOS or Nch OD
output
I/O
H
P23/INT0/A3
• P23 is also used as the INT0 interrupt
request pin, and also as the timer 0
event counting and pulse width
measurement input.
Hold mode:
Output off
• Used as address pins in EPROM mode
Continued on next page.
No. 5488-5/27
LC66E5316
Continued from preceding page.
State after a Standby mode
Pin
I/O
Overview
Output driver type
Options
reset
operation
I/O ports P30 to P32
• Input or output in 3-bit or 1-bit units
• P30 is also used as the INT1 interrupt
request.
• P31 is also used for the square wave
output from timer 0.
• P32 is also used for the square wave
and PWM output from timer 1.
• P31 and P32 also support 3-state
outputs.
Hold mode:
Output off
P30/INT1/A4
P31/POUT0/
A5
P32/POUT1/
A6
• Pch: CMOS type
• Nch: Intermediate sink current
type
CMOS or Nch OD
output
I/O
H
Halt mode:
Output
retained
• Used as address pins in EPROM mode
Hold mode control input
• Hold mode is set up by the HOLD
instruction when HOLD is low.
• In hold mode, the CPU is restarted by
setting HOLD to the high level.
• This pin can be used as input port P33
along with P30 to P32.
P33/HOLD
I
• When the P33/HOLD pin is at the low
level, the CPU will not be reset by a
low level on the RES pin. Therefore,
applications must not set P33/HOLD
low when power is first applied.
Hold mode:
Port output
off, inverter
output off
I/O ports P40 to P43
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used • Pch: Pull-up MOS type
in conjunction with P50 to P53.
• Can be used for output of 8-bit ROM
data when used in conjunction with
P50 to P53.
• Dedicated inverter circuit (option)
• Used as address pins in EPROM mode
P40/INV0I/
A7
P41/INV0O/
A8
P42/INV1I/
A9
P43/INV1O/
A10
• High or
low
(option)
• Inverter
I/O is set
to the
• Pull-up MOS or
Nch OD output
• Output level on
reset
• CMOS type when the inverter
circuit option is selected
• Nch: Intermediate sink current
type
I/O
Halt mode:
Port output
retained,
inverter
• Inverter circuit
output off
state.
output
continues
I/O ports P50 to P53
Hold mode:
Output off
• Input or output in 4-bit or 1-bit units
• Input or output in 8-bit units when used
in conjunction with P40 to P43.
• Can be used for output of 8-bit ROM
data when used in conjunction with
P40 to P43.
• P53 is also used as the INT2 interrupt
request.
• Used as address pins in EPROM mode
P50/A11
P51/A12
P52/A13
• Pull-up MOS or
Nch OD output
• Output level on
reset
• Pch: Pull-up MOS type
• Nch: Intermediate sink current
type
High or low
(option)
I/O
P53/INT2/TA
Halt mode:
Output
retained
I/O ports P60 to P63
Hold mode:
Output off
• Input or output in 4-bit or 1-bit units
• P60 is also used as the serial input SI1
pin.
• P61 is also used as the serial output
SO1 pin.
• P62 is also used as the serial clock
SCK1 pin.
• P63 is also used for the event count
input to timer 1.
P60/SI1
P61/SO1
P62/SCK1
P63/PIN1
• Pch: CMOS type
• Nch: Intermediate sink current
type
• CMOS or Nch OD
output
I/O
H
Halt mode:
Output
retained
Continued on next page.
No. 5488-6/27
LC66E5316
Continued from preceding page.
State after a Standby mode
Pin
I/O
Overview
Output driver type
Options
reset
operation
Hold mode:
Output off
Dedicated output ports P80 to P83
• Output in 4-bit or 1-bit units
• The contents of the output latch are
input using input instructions.
• P80 is a data shaper input (options)
• P81 is a data shaper output (options)
• CMOS or Pch OD
output
• Output level at
reset
• Data shaper
circuit
P80/DS0
P81/DS1
P82
• Pch: CMOS type
• Nch: Intermediate sink current
type
High or low
(option)
O
Halt mode:
Output
retained
P83
Hold mode:
Output off
PC0
PC1
PC2/INV2I/
CE
PC3/INV2O/
DASEC
I/O ports PC0 to PC3
• Output in 4-bit or 1-bit units
• Dedicated inverter circuits (option)
• Used as the control CE and DASEC
pin in EPROM mode.
• Pch: CMOS type
• Nch: Intermediate sink current
type
• CMOS or Nch OD
output
• Inverter circuits
I/O
H
Halt mode:
Output
retained
PD0/AN1/
INV3I
PD1/AN2/
INV3O
PD2/AN3/
INV4I
PD3/AN4/
INV4O
Inverter
• Only when the inverter circuit
option is selected:
• Pch: CMOS type
• Nch: Intermediate sink current
type
Dedicated input ports PD0 to PD3
• Can be switched in software to function
as 16-value analog inputs.
• Hold mode:
Output off
• Halt mode:
Output
Normal
input
I
Inverter circuits
• Dedicated inverter circuits (option)
continues
PE0/XT1
PE1/XT2
Dedicated input ports and sub-oscillator
connections
Sub-oscillator/port
PE selection
Option
selection
I
I
Hold
OSC stop
OSC1
OSC2
System clock oscillator connections
Ceramic oscillator
or external clock
selection
Option
selection
When an external clock is used, leave
OSC2 open and connect the clock signal
to OSC1.
Halt
OSC cont
O
System reset input
• When the P33/HOLD pin is at the high
level, a low level input to the RES pin
will initialize the CPU.
• Used as the VPP/OE pin in EPROM
mode.
RES/V
OE
/
PP
I
I
CPU test pin
TEST/
EPMOD
This pin must be connected to V
SS
during normal operation.
Power supply pins
V
DD
V
SS
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to V
CMOS output: Complementary output.
.
DD
OD output: Open-drain output.
Continued on next page.
No. 5488-7/27
LC66E5316
User Options
1. Port 0, 1, 4, 5, and 8 output level at reset option
The output levels at reset for I/O ports 0, 1, 4, 5, and 8, in independent 4-bit groups, can be selected from the
following two options.
Option
Conditions and notes
1. Output high at reset
2. Output low at reset
The four bits of ports 0, 1, 4, 5, or 8 are set in a group
The four bits of ports 0, 1, 4, 5, or 8 are set in a group
2. Oscillator circuit options
• Main clock
Option
Circuit
Conditions and notes
OSC1
1. External clock
The input has Schmitt characteristics
C1
OSC1
OSC2
Ceramic oscillator
C2
2. Ceramic oscillator
Note: There is no RC oscillator option.
• Sub-clock
Option
Circuit
Conditions and notes
DSB
1. Ports PE0 and PE1
Input data
C1
XT1
2 Sub-oscillator
(crystal oscillator)
Crystal oscillator
C2
XT2
3. Watchdog timer option
A runaway detection function (watchdog timer) can be selected as an option.
4. Port output type options
• The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, and PC can be
selected individually from the following two options.
Option
Circuit
Conditions and notes
Output data
Input data
The port P2, P3, P5, and P6 inputs have Schmitt
characteristics.
1. Open-drain output
DSB
Output data
Input data
The port P2, P3, P5, and P6 inputs have Schmitt
characteristics.
2. Output with built-in pull-up
resistor
The CMOS outputs (ports P2, P3, P6, and PC)
and the pull-up MOS outputs (P0, P1, P4, and
P5) are distinguished by the drive capacity of the
p-channel transistor.
DSB
No. 5488-8/27
LC66E5316
• One of the following two options can be selected for P8, in bit units.
Option
Circuit
Conditions and notes
Output data
Output data
1. Open-drain output
DSB
2. Output with built-in pull-
down resistor
(CMOS output)
DSB
5. Inverter array circuit option
One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PC2/PC3,
PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to inputs)
Option
Circuit
Conditions and notes
Output data
Input data
When the open-drain output type is selected
DSB
1. Normal port I/O circuit
Output data
Input data
When the built-in pull-up resistor output type is
selected.
The CMOS outputs (PC) and the pull-up MOS
outputs (P4) are distinguished by the drive
capacity of the p-channel transistor.
DSB
Input
Output data
high
Input data
If this option is selected, the I/O circuit is disabled
by the DSB signal.
DSB
2. Inverter I/O circuit
Also note that the open-drain port output type
option and the high level at reset option must be
selected.
Output
Output data
high
Input data
DSB
No. 5488-9/27
LC66E5316
6. Buffer array circuit option
In addition to normal port output, one of the following two options may also be selected for P80 and P81.
Option
Circuit
Conditions and notes
Output data
Output data
When the open-drain output type is selected
DSB
1. Normal port output
When the built-in pull-down resistor output type is
selected (CMOS output)
DSB
Output data
low
P80
If this option is selected, the I/O circuit is disabled
by the DSB signal.
Also note that the open-drain port output type
option and the low level at reset option must be
selected.
2. Buffer input (P80) and
buffer output (P81) circuits
Output data
low
DSB
P81
P80
Output data
low
If this option is selected, the I/O circuit is disabled
by the DSB signal.
Also note that the open-drain port output type
option and the low level at reset option must be
selected.
3. Buffer input (P80) and
buffer output (P81) circuits
with built-in zero-cross
detection circuits
Output data
low
DSB
P81
No. 5488-10/27
LC66E5316
LC665316 Series Option Data Area and Definitions
ROM area
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Option specified
Output level at reset
Option/data relationship
0 = high level, 1 = low level
P5
P4
Sub-oscillator option
Oscillator option
P8
0 = port PE, 1 = crystal oscillator
0 = external clock, 1 = ceramic oscillator
3FF0H
P1
Output level at reset
0 = low level, 1 = high level
0 = none, 1 = yes (present)
P0
Watchdog timer option
P13
P12
Output type
P11
0 = OD, 1 = PU
0 = OD, 1 = PU
P10
P03
3FF1H
3FF2H
3FF3H
3FF4H
3FF5H
3FF6H
P02
Output type
P01
P00
Unused
P32
This bit must be set to 0.
0 = OD, 1 = PU
P31
P30
P23
P22
P21
P20
P53
P52
P51
P50
P43
P42
P41
P40
Output type
Output type
0 = OD, 1 = PU
Output type
Output type
0 = OD, 1 = PU
0 = OD, 1 = PU
Unused
This bit must be set to 0.
P63
P62
P61
P60
Output type
0 = OD, 1 = PU
Unused
This bit must be set to 0.
P83
P82
P81
P80
Output type
0 = OD, 1 = PD
Unused
Unused
This bit must be set to 0.
This bit must be set to 0.
Continued on next page.
LC66E5316
Continued from preceding page.
ROM area
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Option specified
Option/data relationship
Unused
This bit must be set to 0.
3FF7H
PC3
PC2
Output type
0 = OD, 1 = PU
PC1
PC0
Unused
This bit must be set to 1.
0 = used, 1 = none
Buffer output
Buffer output with zero-cross bias input
0 = used, 1 = none
PD3
PD1
3FF8H
3FF9H
3FFAH
3FFBH
3FFCH
3FFDH
PC3
P43
P41
Inverter output
0 = inverter output, 1 = none
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
This bit must be set to 0.
This bit must be set to 0.
This bit must be set to 0.
This bit must be set to 0.
This bit must be set to 0.
This bit must be set to 0.
This bit must be set to 0.
This bit must be set to 0.
This data is generated by the assembler.
If the assembler is not used, set this data to ‘00’.
Reserved. Must be set to predefined data values.
Continued on next page.
No. 5488-12/27
LC66E5316
Continued from preceding page.
ROM area
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Option specified
Option/data relationship
This data is generated by the assembler.
If the assembler is not used, set this data to ‘00’.
3FFEH
Reserved. Must be set to predefined data values.
This data is generated by the assembler.
If the assembler is not used, set this data to ‘00’.
3FFFH
Reserved. Must be set to predefined data values.
Usage Notes
1. Option specification
When using a Sanyo cross assembler with the LC66E5316, use the version called “LC66S.EXE” and specify the
actual microcontroller to be evaluated with the CPU pseudo instruction in the source file. The port options must be
specified in the source file. The cross assembler will create an option code list in the option specification area
(locations 3FF0H to 3FFFH). It is also possible to directly set up data in the option specification area. If this is done,
the options must be specified according to the option code creation table shown on the following page.
2. Writing the EPROM
Use a special-purpose writing conversion board (the W66EP5316D for the DIP package, and the W66EP5316Q for
the QFP package) to allow the EPROM programmers listed below to be used when writing the data created by the
cross assembler to the LC66E5316.
• The EPROM programmers listed below can be used.
Manufacturer
Models that can be used
Advantest
Ando
R4945, R4944A, R4943, or equivalent products
AF9704
AVAL
—
Minato Electronics
MODEL1890A
• The “27512 (V 12.5 V) Intel high-speed write” technique must be used to write the EPROM. Set the address
PP
range to location 0 to 3FFFH. The DASEC jumper must be off.
3. Using the data security function
The data security function sets up the microcontroller in advance so that data that was written to the microcontroller
EPROM cannot be read out.
Use the following procedure to enable the LC66E5316 data security function.
• Set the write conversion board DASEC jumper to the on position.
• Write the data to the EPROM once again.
At this time, since this function will operate, the EPROM programmer will issue an error. However, this error does
not indicate that there was a problem in either the programmer or the LSI.
Notes: 1. If the data at all addresses was “FF” at step 2, the data security function will not be activated.
Notes: 2. The data security function will not be activated at step 2 if the “blank → program → verify” operation
sequence is used.
Notes: 3. Always return the jumper to the off position after the data security function has been activated.
No. 5488-13/27
LC66E5316
4. Erase procedure
Use a general-purpose EPROM eraser to erase data written to the EPROM.
LC66E5316 (DIC)
LC66E5316 (QFC)
Cut corner
Pin 1
SW
DASEC
Pin 1
Aligned to the top
SW DASEC
Pin 1
Write board (W66EP5316D)
Write board (W66EP5316Q)
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
V
Note
V
max
V
–0.3 to +7.0
DD
DD
P2, P3 (except for the P33/HOLD pin),
P61, and P63
V
1
–0.3 to +7.0
V
V
1
2
1
2
3
4
4
IN
Input voltage
V
2
All other inputs
–0.3 to V
+ 0.3
IN
DD
P2, P3 (except for the P33/HOLD pin),
P61, and P63
V
V
1
–0.3 to +7.0
V
OUT
Output voltage
2
All other inputs
–0.3 to V
+ 0.3
20
2
V
OUT
DD
P0, P1, P2, P3 (except for the P33/HOLD pin),
P4, P5, P6, P8, PC, PD1, PD3
I
1
mA
mA
mA
ON
–I
–I
–I
1
P0, P1, P4, P5
OP
Output current per pin
P2, P3 (except for the P33/HOLD pin),
P6,P8, and PC
2
3
4
OP
OP
P41, P43, PC3, PD1, PD3, P81
P4, P5, P6, P8, PC
10
75
mA
mA
4
3
Σ I
Σ I
Σ I
Σ I
1
ON
P0, P1, P2, P3 (except for the P33/HOLD pin),
PD1, PD3
2
1
2
75
25
25
mA
mA
mA
3
4
4
ON
Total pin current
P4, P5, P6, P8, PC
OP
P0, P1, P2, P3 (except for the P33/HOLD pin),
PD1, PD3
OP
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = –30 to +70°C: DIC42S (QFC48)
600 (430)
+10 to +40
–55 to +125
mW
°C
Tstg
°C
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that
pin apply.
2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed.
3. Sink current (Applies to P8 and PD when either the CMOS output specifications or the inverter array specifications have been selected.)
4. Source current (Applies to all pins except P8 and PD for which the pull-up output specifications, the CMOS output specifications, or the inverter
array specifications have been selected. Applies to PD pins for which the inverter array specifications have been selected.) Contact your Sanyo
representative for the electrical characteristics when the inverter array or buffer array options are specified
No. 5488-14/27
LC66E5316
Allowable Operating Ranges at Ta = +10 to +40°C, V = 0 V, V = 4.5 to 5.5 V, unless otherwise specified.
SS
DD
Parameter
Symbol
Conditions
min
4.5
1.8
typ
max
Unit
V
Note
Operating supply voltage
Memory retention supply voltage
V
V
V
5.5
5.5
DD
DD
DD
V
H
: During hold mode
V
DD
P2, P3 (except for the P33/HOLD pin),
P61, and P63: N-channel output transistor off
V
1
2
3
0.8 V
+7.0
V
V
V
1
2
IH
IH
IH
DD
DD
DD
P33/HOLD, RES, OSC1:
N-channel output transistor off
Input high-level voltage
Input low-level voltage
V
V
0.8 V
0.8 V
V
DD
P0, P1, P4, P5, PC, PD, PE:
N-channel output transistor off
V
DD
P2, P3 (except for the P33/HOLD pin), P6,
RES, and OSC1: N-channel output transistor off
V
V
V
1
2
3
V
V
V
0.2 V
V
V
V
IL
SS
DD
P33/HOLD: V
= 1.8 to 5.5 V
0.2 V
0.2 V
IL
DD
SS
DD
P0, P1, P4, P5, PC, PD, PE, TEST:
N-channel output transistor off
2
IL
SS
DD
0.4
(10)
4.2
(0.95)
MHz
(µs )
When the main oscillator is operating
When the sub-oscillator is operating
Operating frequency
(instruction cycle time)
fop
(Tcyc)
30
(133.2)
32.768
(122)
100
(40)
kHz
(µs)
[External clock input conditions]
Frequency
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
f
0.4
4.20
MHz
ns
ext
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Pulse width
t
t
, t
100
extH extL
OSC1: Defined by Figure 1. Input the clock
signal to OSC1 and leave OSC2 open.
(External clock input must be selected as the
oscillator circuit option.)
Rise and fall times
, t
30
ns
extR extF
Note: 1. Applies to pins with open-drain specifications. However, V 2 applies to the P33/HOLD pin.
IH
When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins.
2. PC port pins with CMOS output specifications cannot be used as input pins.
Contact your Sanyo representative for the allowable operating ranges for P4, PC, and PD when the inverter array is used, and for P8 when the
buffer array is used.
3. Applies to pins with open-drain specifications. However, V 2 applies to the P33/HOLD pin.
IL
P2, P3, and P6 port pins with CMOS output specifications cannot be used as input pins.
No. 5488-15/27
LC66E5316
Electrical Characteristics at Ta = +10 to +40°C, V = 0 V, V = 4.5 to 5.5 V unless otherwise specified.
SS
DD
Parameter
Symbol
Conditions
min
typ
max
5.0
Unit
µA
Note
1
P2, P3 (except for the P33/HOLD pin),
P61, and P63: V = +10.0 V, with the output
I
I
1
IH
IH
IN
Nch transistor off
P0, P1, P4, P5, P6, PC, OSC1, and P33/HOLD
(Does not apply to PD, PE, PC2, and PC3):
2
1.0
1.0
µA
µA
1
1
V
= V , with the output Nch transistor off
DD
IN
PD, PC2, PC3, PE0 (When used as a port; does
not apply when the sub-oscillator option is
selected.): V = V , with the output Nch
Input high-level current
I
3
IH
IN
DD
transistor off
I
I
4
5
RES: V = V , operating, halt mode
10
µA
µA
1
1
IH
IN
DD
RES: V = V , hold mode
1.0
1.0
IH
IN
DD
PE1 (When used as a port; does not apply when
the sub-oscillator option is selected.) V = V
I
6
µA
µA
1
2
IH
IN
DD
Input ports other than PD, PE, PC2, and PC3:
= V , with the output Nch transistor off
I
1
2
–1.0
IL
V
IN
SS
PD, PC2, PC3, PE0 (When used as a port; does
not apply when the sub-oscillator option is
selected.): V = V , with the output Nch
I
–1.0
µA
2
IL
Input low-level current
IN
SS
transistor off
RES: V = V
SS
I
I
3
4
100
20
µA
µA
1
1
IL
IN
PE1 (When used as a port; does not apply when
the sub-oscillator option is selected.): V = V
IL
IN
SS
P2, P3 (except for the P33/HOLD pin),
P6, P8, and PC: I = –1 mA
V
V
– 1.0
DD
DD
OH
Output high-level voltage
Value of the output pull-up resistor
Output low-level voltage
V
V
1
V
3
OH
P2, P3 (except for the P33/HOLD pin),
– 0.5
30
P6, P8, and PC: I
= –0.1 mA
OH
R
P0, P1, P4, P5
100
150
0.4
k
4
5
PO
P0, P1, P2, P3, P4, P5, P6, P8, and PC
(except for the P33/HOLD pin): I = 1.6 mA
OL
1
V
OL
OL
P0, P1, P2, P3, P4, P5, P6, P8, and PC
(except for the P33/HOLD pin): I = 8 mA
OL
V
I
2
1
1.5
5.0
1.0
V
P2, P3, P61, P63: V = +7.0 V
IN
µA
µA
µA
6
6
7
OFF
Does not apply to P2, P3, P61, P63, and P8.:
Output off leakage current
I
I
2
3
OFF
V
= V
DD
IN
P8: V = V
–1.0
OFF
IN
SS
[Schmitt characteristics]
Hysteresis voltage
V
0.1 V
V
V
V
HYS
DD
High-level threshold voltage
Low-level threshold voltage
[Ceramic oscillator]
Vt
P2, P3, P5, P6, OSC1 (EXT), RES
0.5 V
0.2 V
0.8 V
H
L
DD
DD
Vt
0.5 V
DD
DD
Oscillator frequency
f
OSC1, OSC2: Figure 2, 4 MHz
Figure 3, 4 MHz
4.0
MHz
ms
CF
Oscillator stabilization time
[Crystal oscillator]
f
10.0
5.0
CFS
XT1, XT2: Figure 2, when the sub-oscillator
option is selected, 32 kHz
Oscillator frequency
f
32.768
1.0
kHz
s
XT
Figure 3, when the sub-oscillator option is
selected, 32 kHz
Oscillator stabilization time
[Serial clock]
f
XTS
Input
0.9
2.0
0.4
1.0
µs
Tcyc
µs
Cycle time
Output
t
CKCY
SCK0, SCK1: With the timing of Figure 4 and
the test load of Figure 5.
Input
t
Low-level and high-level
pulse widths
CKL
Output
Output
t
Tcyc
µs
CKH
Rise an fall times
[Serial input]
t
, t
0.1
CKR CKF
Data setup time
Data hold time
t
0.3
0.3
µs
µs
SI0, SI1: With the timing of Figure 4.
Stipulated with respect to the rising edge (↑) of
SCK0 or SCK1.
ICK
t
CKI
Continued on next page.
No. 5488-16/27
LC66E5316
Continued from preceding page.
Parameter
Symbol
Conditions
min
typ
max
Unit
µs
Note
[Serial output]
SO0, SO1: With the timing of Figure 5 and
the test load of Figure 5. Stipulated with respect
to the falling edge (↓) of SCK0 or SCK1.
Output delay time
[Pulse conditions]
t
0.3
CKO
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT0 high and low-level
t
, t
2
Tcyc
IOH IOL
High and low-level pulse widths
for interrupt inputs other than INT0
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
t
, t
2
2
3
Tcyc
Tcyc
Tcyc
IIH IIL
PIN1 high and low-level
pulse widths
PIN1: Figure 6, conditions under which the
timer 1 event counter input can be accepted
t
, t
PINH PINL
RES high and low-level
pulse widths
RES: Figure 6, conditions under which reset
can be applied.
t
, t
RSH RSL
V
V
V
V
: 4-MHz ceramic oscillator
: 4-MHz external clock
6.0
6.0
4
12
12
mA
mA
mA
µA
DD
DD
DD
DD
Operating current drain
I
8
DD OP
: 4-MHz ceramic clock
8
Halt mode current drain
Hold mode current drain
I
: 32 kHz (main oscillator stopped),
100
500
DDHALT
sub-oscillator: crystal
I
V
: V = 1.8 to 5.5 V
0.01
10
µA
DDHOLD
DD DD
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins. (Also applies when the Pch open-drain option is selected for P8.)
4. With the output Nch transistor off for pull-up output specification pins.
5. When CMOS output specifications are selected for P8.
6. With the output Nch transistor off for pull-up output specification pins.
7. With the output Pch transistor off for open-drain output specification pins.
8. Reset state
Comparator Characteristics at Ta = –30 to +70°C, V = 0 V
SS
Parameter
Absolute precision
Symbol
Conditions
min
typ
max
±1
Unit
LSB
V
Note
1
V
AN1 to AN4: V
= 4.5 to 5.5 V
±1/2
CECM
DD
Threshold voltage
Input voltage
V
V
= 4.5 to 5.5 V
V
V
THCM
DD
SS
DD
V
AN1 to AN4: V
= 4.5 to 5.5 V
V
V
V
INCM
DD
SS
DD
Conversion time
T
V
= 4.5 to 5.5 V
DD
30
µs
CCM
Note: 1. Does not include the quantization error.
V
DD
0.8V
DD
0.2V
DD
OSC1
(OSC2)
OPEN
V
SS
t
t
extH
extL
External clock
t
t
extF
extR
1/fext
Figure 1 External Clock Input Waveform
No. 5488-17/27
LC66E5316
V
DD
Operating V
minimum value
DD
0V
OSC1
XT1
OSC2
Rd
XT2
OSC
Rd
C2
Stable oscillation
Ceramic
oscillator
Crystal
oscillatorI
C1
C2
C1
Oscillator
unstable period
t
CFS
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
Table 1 Guaranteed Ceramic Oscillator Constants External capacitor type
External capacitor type
C1 = 33 pF ± 10%
Built-in capacitor type
4 MHz
4 MHz
(Murata Mfg. Co., Ltd.)
CSA4.00MG
C2 = 33 pF ± 10%
Rd = 220 ± 5%
C1 = 33 pF ± 10%
C2 = 33 pF ± 10%
Rd = 0
(Murata Mfg. Co., Ltd.)
CST4.00MG
Rd = 220 ± 5%
4 MHz
(Kyocera Corporation)
KBR4.0MS
4 MHz
(Kyocera Corporation)
KBR4.0MES
Table 2 Guaranteed Crystal Oscillator Constants
C1 = 18 pF ± 10%
32 kHz
(Seiko Epson)
C-002RX
C2 = 18 pF ± 10%
Rd = 470 k ± 5%
t
CKCY
t
CKR
t
t
t
CKH
CKF
CKL
SCK0
0.8V
V
DD (input)
-1
SCK1
0.2V
DD (output)
DD (input)
0.4V
DD (output)
t
t
ICK CKI
SI0
0.8V
0.2V
DD
DD
SI1
R=1kΩ
t
CK0
TEST
point
SO0
SO1
V
DD
0.4V
-1
DD
C=50pF
Figure 4 Serial I/O Timing
Figure 5 Timing Load
t
t
I0H
I1H
t
t
PINH
RSH
0.8V
DD
0.2V
DD
t
t
I0L
I1L
t
t
PINL
RSL
Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins
No. 5488-18/27
LC66E5316
LC66XXXX Series Instruction Table (by function)
Abbreviations:
AC:
E:
Accumulator
E register
CF:
ZF:
HL:
XY:
M:
Carry flag
Zero flag
Data pointer DPH, DPL
Data pointer DPX, DPY
Data memory
M (HL): Data memory pointed to by the DPH, DPL data pointer
M (XY): Data memory pointed to by the DPX, DPY auxiliary data pointer
M2 (HL): Two words of data memory (starting on an even address) pointed to by the DPH, DPL data pointer
SP:
Stack pointer
M2 (SP): Two words of data memory pointed to by the stack pointer
M4 (SP): Four words of data memory pointed to by the stack pointer
in:
t2:
n bits of immediate data
Bit specification
t2
11
10
01
00
3
2
1
0
Bit
2
2
2
2
PCh:
PCm:
PCl:
Fn:
Bits 8 to 11 in the PC
Bits 4 to 7 in the PC
Bits 0 to 3 in the PC
User flag, n = 0 to 15
TIMER0: Timer 0
TIMER1: Timer 1
SIO:
P:
Serial register
Port
P (i4):
INT:
Port indicated by 4 bits of immediate data
Interrupt enable flag
( ), [ ]: Indicates the contents of a location
←:
:
Transfer direction, result
Exclusive or
:
Logical and
:
Logical or
+:
–:
—:
Addition
Subtraction
Taking the one's complement
No. 5488-19/27
LC66E5316
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D D D D
4 3 2 1 0
7
6
5
[Accumulator manipulation instructions]
AC ← 0
(Equivalent to LAI 0.)
Has a vertical
skip function.
CLA
DAA
Clear AC
1
0
0
0
0
0
0
0
1
2
1
2
Clear AC to 0.
ZF
ZF
Decimal adjust AC
in addition
1
0
1
0
0
1
0
0
1
0
1
1
1
1
1
0
AC ← (AC) + 6
(Equivalent to ADI 6.)
Add six to AC.
Add 10 to AC.
AC ← (AC) + 10
(Equivalent to
ADI 0AH.)
Decimal adjust AC
in subtraction
1
0
1
0
0
1
0
0
1
1
1
0
1
1
1
0
DAS
2
2
ZF
CLC
STC
Clear CF
Set CF
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
CF ← 0
CF ← 1
Clear CF to 0.
Set CF to 1.
CF
CF
Take the one’s complement
of AC.
CMA
Complement AC
0
0
0
1
1
0
0
0
1
1
AC ← (AC)
ZF
IA
Increment AC
Decrement AC
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
0
1
1
1
1
AC ← (AC) + 1
AC ← (AC) – 1
Increment AC.
Decrement AC.
ZF, CF
ZF, CF
DA
AC ← (CF),
ACn ← (ACn + 1),
3
Rotate AC right
through CF
RAR
RAL
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
Shift AC (including CF) right. CF
CF ← (AC )
0
AC ← (CF),
0
Rotate AC left
through CF
ACn + 1 ← (ACn),
Shift AC (including CF) left.
CF, ZF
CF ← (AC )
3
TAE
TEA
Transfer AC to E
Transfer E to AC
0
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
1
E ← (AC)
AC ← (E)
Transfer the contents of AC to E.
Transfer the contents of E to AC. ZF
Exchange the contents of
AC and E.
XAE
Exchange AC with E
0
1
0
0
0
1
0
0
1
1
(AC) ↔ (E)
[Memory manipulation instructions]
M (HL) ←
[M (HL)] + 1
IM
Increment M
Decrement M
0
0
0
1
0
0
1
0
1
1
2
2
1
1
1
1
2
2
1
1
Increment M (HL).
Decrement M (HL).
ZF, CF
M (HL) ←
[M (HL)] – 1
DM
0
1
0
1
1
0
0
0
0
0
0
1
1
1
0
1
ZF, CF
ZF, CF
ZF, CF
IMDR i8 Increment M direct
DMDR i8 Decrement M direct
SMB t2 Set M data bit
M (i8) ← [M (i8)] + 1 Increment M (i8).
M (i8) ← [M (i8)] – 1 Decrement M (i8).
I
I
I
I
I
I
I
I
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
1
I
I
I
I
I
I
I
I
7
6
5
4
3
2
1
0
Set the bit in M (HL) specified
by t0 and t1 to 1.
0
0
0
0
1
1
t
t
t
[M (HL), t2] ← 1
[M (HL), t2] ← 0
1
0
Clear the bit in M (HL)
specified by t0 and t1 to 0.
RMB t2 Reset M data bit
0
0
1
0
1
1
t
ZF
1
0
[Arithmetic, logic and comparison instructions]
Add the contents of AC and
M (HL) as two’s complement
values and store the result
in AC.
AC ← (AC) +
[M (HL)]
AD
Add M to AC
0
0
0
0
0
1
1
0
1
0
0
1
1
2
1
2
1
1
2
1
2
1
ZF, CF
ZF, CF
ZF, CF
ZF
Add the contents of AC and
M (i8) as two’s complement
values and store the result
in AC.
1
1
0
0
ADDR i8 Add M direct to AC
AC ← (AC) + [M (i8)]
I
I
I
I
I
I
I
I
7
6
5
4
3
2
1
0
Add the contents of AC,
M (HL) and C as two’s
complement values and
store the result in AC.
AC ← (AC) +
[M (HL)] + (CF)
ADC
Add M to AC with CF
0
0
0
0
0
0
1
0
Add the contents of AC and
the immediate data as two’s
complement values and store
the result in AC.
Add immediate data
to AC
1
0
1
0
0
1
0
0
1
1
1
1
AC ← (AC) +
I , I , I , I
3 2 1 0
ADI i4
SUBC
I
I
I
I
3
2
1
0
Subtract the contents of AC
and CF from M (HL) as two’s
complement values and store
the result in AC.
CF will be zero if
there was a
borrow and one
otherwise.
Subtract AC from M
with CF
AC ← [M (HL)] –
(AC) – (CF)
0
0
0
1
0
1
1
1
ZF, CF
Take the logical and of AC
and M (HL) and store the
result in AC.
And M with AC then
store AC
AC ← (AC)
[M (HL)]
ANDA
ORA
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
ZF
ZF
Take the logical or of AC and
M (HL) and store the result
in AC.
Or M with AC then
store AC
AC ← (AC)
[M (HL)]
Continued on next page.
No. 5488-20/27
LC66E5316
Continued from preceding page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D D D D
4 3 2 1 0
7
6
5
[Arithmetic, logic and comparison instructions]
Take the logical exclusive or
of AC and M (HL) and store
the result in AC.
Exclusive or M with
AC then store AC
AC ← (AC)
[M (HL)]
EXL
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
1
ZF
ZF
ZF
Take the logical and of AC
and M (HL) and store the
result in M (HL).
And M with AC then
store M
M (HL) ← (AC)
[M (HL)]
ANDM
ORM
0
0
0
1
1
0
1
0
Take the logical or of AC and
M (HL) and store the result
in M (HL).
Or M with AC then
store M
M (HL) ← (AC)
[M (HL)]
Compare the contents of AC
and M (HL) and set or clear CF
and ZF according to the result.
Magnitude
CF ZF
CM
Compare AC with M
0
0
0
1
0
1
1
0
1
1
[M (HL)] + (AC) + 1
ZF, CF
comparison
[M (HL)] > (AC)
[M (HL)] = (AC)
[M (HL)] < (AC)
0
1
1
0
1
0
Compare the contents of AC
and the immediate data
I
I I I and set or clear CF
3
2 1 0
and ZF according to the result.
Magnitude
CF ZF
Compare AC with
immediate data
1
1
1
0
0
1
0
0
1 1 1 1
CI i4
2
2
I
I
I I + (AC) + 1
2 1 0
ZF, CF
3
comparison
I
I
I
I
3
2
1
0
I
I
I
I
I
I
I
I
I
I
I
I
> AC
= AC
< AC
0
1
1
0
1
0
3
3
3
2
2
2
1
1
1
0
0
0
ZF ← 1
Compare the contents of DP
with the immediate data.
Set ZF if identical and clear
ZF if not.
L
Compare DP with
L
immediate data
1
1
1
0
0
1
0
1
1
1
1
1
if (DP ) = I
I
I
I
I
I
I
L
3
2
1
0
CLI i4
2
2
2
2
ZF
ZF
I
I
I
I
ZF ← 0
3
2
1
0
if (DP ) - I
L
3
2
1
0
ZF ← 1
if (AC, t2) = [M (HL), Compare the corresponding
t2]
ZF← 0
Compare AC bit with
M data bit
1
1
1
1
0
0
0
1
1
0
1
0
1
1
bits specified by t0 and t1 in
AC and M (HL). Set ZF if
CMB t2
t
t
1
0
if (AC, t2) - [M (HL), identical and clear ZF if not.
t2]
[Load and store instructions]
Load AC and E from
M2 (HL)
AC ← M (HL),
E ← M (HL + 1)
Load the contents of M2 (HL)
into AC, E.
LAE
0
1
0
1
1
1
0
0
1
1
2
1
1
1
1
2
1
1
Load AC with
LAI i4
Load the immediate data
into AC.
Has a vertical
skip function
1
1
0
1
0
0
0
0
I
I
I
I
AC ← I I I I
3 2 1 0
ZF
ZF
3
2
1
0
immediate data
Load AC from M
0
0
0
1
Load the contents of M (i8)
into AC.
LADR i8
direct
AC ← [M (i8)]
I
I
I
I
I
I
I
I
7
6
5
4
3
2
1
0
Store the contents of AC into
M (HL).
S
Store AC to M
0
1
0
0
0
1
1
1
M (HL) ← (AC)
Store AC and E to
M2 (HL)
M (HL) ← (AC)
M (HL + 1) ← (E)
Store the contents of AC, E
into M2 (HL).
SAE
0
0
1
1
0
0
1
0
1
1
1
0
1
0
0
Load the contents of M (reg)
into AC.
The reg is either HL or XY
depending on t .
0
Load AC from
M (reg)
LA reg
t
1
1
AC ← [M (reg)]
ZF
0
reg
T
0
HL
XY
0
1
Continued on next page.
No. 5488-21/27
LC66E5316
Continued from preceding page.
Instruction code
D D
1 0
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D
D
7
6
5
4
3
2
[Load and store instructions]
Load the contents of M (reg)
into AC. (The reg is either HL
or XY.) Then increment the
ZF is set
according to the
result of
AC ← [M (reg)]
Load AC from M (reg)
LA reg, I
0
1
0
0
1
0
t
1
1
1
2
2
DP ← (DP ) + 1
contents of either DP or DP . ZF
0
L
L
L Y
then increment reg
or DP ← (DP ) + 1 The relationship between t
incrementing
DP or DP .
Y
Y
0
and reg is the same as that
for the LA reg instruction.
L
Y
Load the contents of M (reg)
into AC. (The reg is either HL
or XY.) Then decrement the
contents of either DP or DP . ZF
ZF is set
according to the
result of
AC ← [M (reg)]
Load AC from M (reg)
LA reg, D
0
1
0
1
1
0
t
1
DP ← (DP ) – 1
0
L
L
L
Y
then decrement reg
or DP ← (DP ) – 1 The relationship between t
decrementing
DP or DP .
Y
Y
0
and reg is the same as that
L
Y
for the LA reg instruction.
Exchange the contents of
M (reg) and AC.
The reg is either HL or XY
depending on t .
0
Exchange AC with
XA reg
M (reg)
0
1
0
0
1
1
t
0
1
1
(AC) ↔ [M (reg)]
0
reg
T
0
HL
XY
0
1
Exchange the contents of
M (reg) and AC. (The reg is
either HL or XY.) Then
increment the contents of
either DP or DP . The
ZF is set
according to the
result of
Exchange AC with
XA reg, I M (reg) then
increment reg
(AC) ↔ [M (reg)]
DP ← (DP ) + 1
0
1
0
0
1
1
t
1
1
2
ZF
0
L
L
L
Y
or DP ← (DP ) + 1
incrementing
DP or DP .
Y
Y
relationship between t and
0
L
Y
reg is the same as that for
the XA reg instruction.
Exchange the contents of
M (reg) and AC. (The reg is
either HL or XY.) Then
ZF is set
according to the
result of
Exchange AC with
XA reg, D M (reg) then
decrement reg
(AC) ↔ [ [M (reg)]
DP ← (DP ) – 1
decrement the contents of
either DP or DP . The
0
1
1
1
0
0
1
0
1
1
1
0
t
1
0
1
2
ZF
0
L
L
L
Y
or DP ← (DP ) – 1
decrementing
DP or DP .
Y
Y
relationship between t and
0
L
Y
reg is the same as that for
the XA reg instruction.
Exchange AC with
XADR i8
0
I
Exchange the contents of AC
and M (i8).
2
2
2
2
(AC) ↔ [ [M (i8)]
E ← I
M direct
I
I
I
I
I
I
I
7
6
5
4
3
2
1
0
Load E & AC with
LEAI i8
1
1
0
0
0
1
1
I
0
I
I I
Load the immediate data i8
into E, AC.
7
6 5 4
immediate data
I
I
I
I
I
I
I
AC ← I I I I
7
6
5
4
3
2
1
0
3 2 1 0
Load into E, AC the ROM data
at the location determined by
[ROM (PCh, E, AC)] replacing the lower 8 bits of
the PC with E, AC.
Read table data from
RTBL
E, AC ←
0
1
0
1
1
0
1
0
1
1
2
2
program ROM
Output from ports 4 and 5 the
ROM data at the location
Read table data from
RTBLP program ROM then
output to P4, 5
Port 4, 5 ←
0
1
0
1
1
0
1
0
0
0
determined by replacing the
[ROM (PCh, E, AC)]
lower 8 bits of the PC with
E, AC.
[Data pointer manipulation instructions]
Load DP with zero
H
and DP with
immediate data
respectively
DP ← 0
Load zero into DP and the
H
L
H
LDZ i4
0
1
I
I
I
I
1
1
3
2
1
0
DPL ← I
I
I I
2 1 0
immediate data i4 into DP .
3
L
Load DP with
H
immediate data
1
0
1
0
0
0
0
0
1
1
1
1
Load the immediate data i4
into DP .
H
LHI i4
LLI i4
2
2
2
2
2
2
2
2
DP ← I
I I I
3 2 1 0
H
I
I
I
I
3
2
1
0
Load DP with
L
immediate data
1
0
1
0
0
0
0
1
1
1
1
1
Load the immediate data i4
into DP .
L
DP ← I
I I I
2 1 0
L
3
I
I
I
I
3
2
1
0
Load DP , DP with
1
1
0
0
0
0
0
0
DP ← I
I I I
6 5 4
Load the immediate data into
DL , DP .
H
L
H
7
LHLI i8
LXYI i8
immediate data
I
I
I
I
I
I
I
I
DP ← I
I
I
I
7
6
5
4
3
2
1
0
L
3
2
1
0
H
L
Load DP , DP with
1
1
0
0
0
0
0
0
DP ← I
I
I
I
I
I
I
Load the immediate data into
DL , DP .
X
Y
X
7
3
6
2
5
1
4
0
immediate data
I
I
I
I
I
I
I
I
DP ← I
7
6
5
4
3
2
1
0
Y
X
Y
Continued on next page.
No. 5488-22/27
LC66E5316
Continued from preceding page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D D D D
4 3 2 1 0
7
6
5
[Data pointer manipulation instructions]
Increment the contents
of DP .
L
IL
Increment DP
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
2
2
1
2
2
1
2
2
1
2
2
1
1
1
1
1
2
2
1
2
2
1
2
2
1
2
2
1
DP ← (DP ) + 1
ZF
ZF
ZF
ZF
L
L
L
Decrement the contents
of DP .
L
DL
Decrement DP
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
DP ← (DP ) – 1
L L
L
Increment the contents
of DP .
Y
IY
Increment DP
DP ← (DP ) + 1
Y Y
Y
Decrement the contents
of DP .
Y
DY
Decrement DP
DP ← (DP ) – 1
Y Y
Y
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
Transfer the contents of AC
to DP .
H
TAH
THA
XAH
TAL
TLA
XAL
TAX
TXA
XAX
TAY
TYA
XAY
Transfer AC to DP
DP ← (AC)
H
H
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
Transfer the contents of DP
to AC.
H
Transfer DP to AC
H
AC ← (DP )
ZF
ZF
ZF
ZF
H
Exchange AC
with DP
H
Exchange the contents of AC
and DP .
H
0
1
0
0
0
0
0
0
(AC) ↔ (DP )
H
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
1
Transfer the contents of AC
to DP .
L
Transfer AC to DP
L
DP ← (AC)
L
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
1
Transfer the contents of DP
L
to AC.
Transfer DP to AC
L
AC ← (DP )
L
Exchange AC
with DP
L
Exchange the contents of AC
and DP .
L
0
1
0
0
0
0
0
1
(AC) ↔ (DP )
L
1
1
1
1
0
1
0
1
1
0
1
0
1
1
1
0
Transfer the contents of AC
to DP .
X
Transfer AC to DP
X
DP ← (AC)
X
1
1
1
1
0
1
0
0
1
0
1
0
1
1
1
0
Transfer the contents of DP
X
to AC.
Transfer DP to AC
X
AC ← (DP )
X
Exchange AC
with DP
X
Exchange the contents of AC
and DP .
X
0
1
0
0
0
0
1
0
(AC) ↔ (DP )
X
1
1
1
1
0
1
0
1
1
0
1
0
1
1
1
1
Transfer the contents of AC
to DP .
Y
Transfer AC to DP
Y
DP ← (AC)
Y
1
1
1
1
0
1
0
0
1
0
1
0
1
1
1
1
Transfer the contents of DP
Y
to AC.
Transfer DP to AC
Y
AC ← (DP )
Y
Exchange AC
with DP
Y
Exchange the contents of AC
and DP .
Y
0
1
0
0
0
0
1
1
(AC) ↔ (DP )
Y
[Flag manipulation instructions]
SFB n4 Set flag bit
Set the flag specified
by n4 to 1.
0
0
1
0
1
1
1
1
n
n
n
n
1
1
1
1
Fn ← 1
Fn ← 0
3
3
2
2
1
1
0
0
Reset the flag specified
by n4 to 0.
RFB n4 Reset flag bit
n
n
n
n
ZF
[Jump and subroutine instructions]
This becomes
PC12 + (PC12)
immediately
following a BANK
instruction.
PC13, 12 ←
PC13, 12
PC11 to 0 ←
Jump to the location in the
same bank specified by the
immediate data P12.
JMP
addr
Jump in the current
bank
1
1
1
0
P
P
P
P
P P
11 10
9
8
0
2
1
2
1
P
P
P
P
P P
7
6
5
4
3
2
1
P
to P
8
11
PC13 to 8 ←
PC13 to 8,
PC7 to 4 ← (E),
PC3 to 0 ← (AC)
Jump to the location
determined by replacing the
lower 8 bits of the PC
by E, AC.
Jump to the address
stored at E and AC
in the current page
JPEA
0
0
1
0
0 1 1 1
PC13 to 11 ← 0,
PC10 to 0 ←
CAL
addr
0
1
0
1
0 P
P
P
P
P
P
to P ,
10
9
1
8
0
10 0
Call subroutine
2
2
Call a subroutine.
P
P
P
P
P
P
M4 (SP) ←
7
6
5
4
3
2
(CF, ZF, PC13 to 0),
SP ← (SP)-4
PC13 to 6,
PC10 ← 0,
CZP
addr
Call subroutine in the
zero page
PC5 to 2 ← P to P , Call a subroutine on page 0
3 0
1
0
0
0
1
0
0
1
P
P
P
P
1
1
2
1
3
2
1
0
M4 (SP) ←
in bank 0.
(CF, ZF, PC12 to 0),
SP ← SP-4
Change the memory bank
and register bank.
BANK
Change bank
1 0 1 1
Continued on next page.
No. 5488-23/27
LC66E5316
Continued from preceding page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D D D D
4 3 2 1 0
7
6
5
[Jump and subroutine instructions]
Store the contents of reg in
M2 (SP). Subtract 2 from SP
after the store.
reg
i
i
0
1
PUSH
reg
1
1
1
1
0
1
0
1
1
1
1
1
1
0
M2 (SP) ← (reg)
SP ← (SP) – 2
Push reg on M2 (SP)
2
2
2
2
i
i
HL
XY
AE
0
0
1
1
0
1
0
1
1
0
Illegal value
Add 2 to SP and then load the
contents of M2(SP) into reg.
The relation between i1i0 and
reg is the same as that for the
PUSH reg instruction.
POP
reg
1
1
1
1
0
1
0
0
1
1
1
1
1
0
SP ← (SP) + 2
reg ← [M2 (SP)]
Pop reg off M2 (SP)
i
i
1
0
Return from a subroutine or
interrupt handling routine. ZF
and CF are not restored.
Return from
subroutine
SP ← (SP) + 4
PC ← [M4 (SP)]
RT
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
2
2
SP ← (SP) + 4
PC ← [M4 (SP)]
Return from a subroutine or
interrupt handling routine. ZF ZF, CF
CF, ZF ← [M4 (SP)] and CF are restored.
Return from interrupt
routine
RTI
[Branch instructions]
PC7 to 0 ←
Branch to the location in the
same page specified by P to
BAt2
addr
1
1
0
1
0
0
t
P
t
P
P
P
P
P
P
P
P
P
1
0
7
3
6
2
5
4
7
Branch on AC bit
2
2
2
2
P
P
P
P
P
P
P if the bit in AC specified by
7
6
5
4
3
2
1
0
1
0
0
if (AC, t2) = 1
the immediate data t t is one.
1 0
PC7 to 0 ←
Branch to the location in the
BNAt2
addr
1
0
0
1
0
0
t
P
t
P
P
P
P
P
P
P
P
same page specified by P to
P if the bit in AC specified by
0
1
0
7
3
6
2
5
4
7
Branch on no AC bit
Branch on M bit
P
P
P
P
P
P
P
7
6
5
4
3
2
1
0
1
0
if (AC, t2) = 0
the immediate data t t is zero.
1 0
PC7 to 0 ←
Branch to the location in the
P
P
P
P
P
P
P
P
same page specified by P to
P if the bit in M (HL) specified
0
7
3
6
2
5
4
7
BMt2
addr
1
1
0
1
0 1
t
P
t
1
0
2
2
2
2
1
0
P
P
P
P
P
P
P
7
6
5
4
3
2
1
0
if [M (HL),t2]
by the immediate data t
t
1 0
= 1
is one.
PC7 to 0 ←
Branch to the location in the
P
P
P
P
P
P
P
P
same page specified by P to
P if the bit in M (HL) specified
0
7
3
6
2
5
4
7
BNMt2
addr
1
0
0
1
0 1
t
t
1
0
Branch on no M bit
1
0
P
P
P
P
P
P P
P
7
6
5
4
3
2
1
0
if [M (HL),t2]
by the immediate data t
t
1 0
= 0
is zero.
Internal control
registers can also
be tested by
executing this
instruction
immediately after
a BANK
instruction.
PC7 to 0 ←
Branch to the location in the
P
P
P
P
P
P
P
P
same page specified by P to
7
3
6
2
5
4
7
BPt2
addr
1
1
0
1
1
0
t
t
1
0
Branch on Port bit
2
2
P if the bit in port (DP )
0 L
specified by the immediate
1
0
P
P
P
P
P P P P
7
6
5
4 3 2 1 0
if [P (DP ), t2]
= 1
L
data t is one.
t
0
1
However, this is
limited to
registers that can
be read out.
Internal control
registers can also
be tested by
executing this
instruction
immediately after
a BANK
instruction.
PC7 to 0 ←
Branch to the location in the
same page specified by P to
P if the bit in port (DP )
0 L
P
P
P
P
P
P
P
P
7
7
6
2
5
4
BNPt2
addr
1
0
0
1
1
0
t
t
1
0
Branch on no Port bit
2
2
3
1
0
P
P
P
P
P P P P
7
6
5
4 3 2 1 0
if [P (DP ), t2]
= 0
specified by the immediate
data t is zero.
L
t
0
1
However, this is
limited to
registers that can
be read out.
Continued on next page.
No. 5488-24/27
LC66E5316
Continued from preceding page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
[Branch instructions]
PC7 to 0 ←
Branch to the location in the
1
1
0
1
1
1
0
0
P
P
P
P
P
P
P
P
7
3
6
2
5
4
0
BC addr Branch on CF
2
2
2
2
2
2
2
2
same page specified by P to
7
P
P
P
P
P P P P
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
1
P
if CF is one.
0
if (CF) = 1
PC7 to 0 ←
Branch to the location in the
BNC
1
0
0
1
1
P
1
0
0
P
P
P
P
P
P
P
P
7
3
6
2
5
4
0
Branch on no CF
addr
same page specified by P to
7
P
P
P
P
P
P
P
1
P
if CF is zero.
0
if (CF) = 0
PC7 to 0 ←
Branch to the location in the
1
1
0
1
1
P
1
0
1
P
P
P
P
P
P
P
P
7
3
6
2
5
4
0
BZ addr Branch on ZF
same page specified by P to
7
P
P
P
P
P
P
P
1
P
if ZF is one.
0
if (ZF) = 1
PC7 to 0 ←
Branch to the location in the
BNZ
1
0
0
1
1
P
1
0
1
P
P
P
P
P
P
P
P
7
3
6
2
5
4
0
Branch on no ZF
addr
same page specified by P to
7
P
P
P
P
P
P
P
1
P
if ZF is zero.
0
if (ZF) = 0
Branch to the location in the
PC7 to 0 ←
same page specified by P to
0
BFn4
1
1
1
1
n
P
n
P
n
P
n
P
P
P
P
P
P
P
P
P
3
2
1
0
7
3
6
2
5
4
0
Branch on flag bit
addr
2
2
2
2
P if the flag (of the 16 user
7
P
P
P
P
7
6
5
4
3
2
1
0
1
flags) specified by n
n n n
3
2 1 0
if (Fn) = 1
is one.
Branch to the location in the
same page specified by P to
PC7 to 0 ←
0
BNFn4
1
0
1
1
n
n
n
n
P
P
P
P
P
P
P
P
3
2
1
0
7
3
6
2
5
4
0
Branch on no flag bit
addr
P if the flag (of the 16 user
7
P
P
P
P
P P P P
3 2 1 0
7
6
5
4
1
flags) specified by n
is zero.
n n n
2 1 0
3
if (Fn) = 0
[I/O instructions]
Input the contents of port
0 to AC.
IP0
IP
Input port 0 to AC
Input port to AC
Input port to M
0
0
1
0
0
0
0
0
1
1
1
1
AC ← (P0)
AC ← [P (DP )]
ZF
ZF
Input the contents of port
P (DP ) to AC.
L
0
0
0
0
1
0
0
1
0
1
1
0
L
Input the contents of port
P (DP ) to M (HL).
L
IPM
1
1
0
1
0
1
1
1
1
2
1
2
M (HL) ← [P (DP )]
L
Input port to
AC direct
1
0
1
1
0
1
0
0
Input the contents of
P (i4) to AC.
IPDR i4
AC ← [P (i4)]
ZF
I
I
I
I
3
2
1
0
Input the contents of ports
P (4) and P (5) to E and AC
respectively.
Input port 4, 5 to
E, AC respectively
1
1
1
1
0
0
0
1
1
0
1
1
1
0
1
0
E ← [P (4)]
AC ← [P (5)]
IP45
2
2
Output the contents of AC to
port P (DP ).
L
OP
Output AC to port
Output M to port
0
0
0
0
1
0
0
1
0
1
0
1
1
1
2
1
1
2
P (DP ) ← (AC)
L
Output the contents of M (HL)
to port P (DP ).
L
OPM
1
1
0
1
1
1
0
1
P (DP ) ← [M (HL)]
L
Output AC to
port direct
1
0
1
1
0
1
0
1
Output the contents of AC
to P (i4).
OPDR i4
P (i4) ← (AC)
I
I
I
I
3
2
1
0
Output the contents of E and
AC to ports P (4) and P (5)
respectively.
Output E, AC to port
4, 5 respectively
1
1
1
1
0
0
0
1
1
0
1
1
1
0
1
1
P (4) ← (E)
P (5) ← (AC)
OP45
2
1
1
2
1
1
Set to one the bit in port
SPB t2
RPB t2
Set port bit
0
0
1
0
0
1
0
1
0
0
0
0
1
1
0
0
0
1
t
t
[P (DP ), t2] ← 1
P (DP ) specified by the
1
1
0
L
L
immediate data t t .
1
0
Clear to zero the bit in port
Reset port bit
t
t
[P (DP ), t2] ← 0
P (DP ) specified by the
ZF
ZF
0
L
L
immediate data t t .
1
0
Take the logical AND of P (P
3
And port with
immediate data then
output
P (P to P ) ←
3
0
ANDPDR
i4, p4
0
1
to P ) and the immediate data
0
2
2
2
2
[P (P to P )]
3 0
I
I
I
I
P
P
P
P
I I I I and output the result
3 2 1 0
3
2
1
0
3
2
1
0
I
to I
0
3
to P (P to P ).
3
0
Take the logical OR of P (P
3
Or port with
immediate data then
output
P (P to P ) ←
3 0
ORPDR
i4, p4
1
1
0
0
0
1
0
0
to P ) and the immediate data ZF
0
[P (P to P )]
3
0
I
I
I
I
P
P
P
P
I I I I and output the result
3 2 1 0
3
2
1
0
3
2
1
0
I
to I
3
0
to P (P to P ).
3
0
Continued on next page.
No. 5488-25/27
LC66E5316
Continued from preceding page.
Instruction code
Affected
status
bits
Mnemonic
Operation
Description
Note
D
D
D
D
D D D D
4 3 2 1 0
7
6
5
[Timer control instructions]
WTTM0 Write timer 0
Write the contents of M2 (HL),
AC into the timer 0 reload
register.
TIMER0 ← [M2 (HL)],
(AC)
1
1
0
0
1
0
1
0
1
2
1
2
2
2
Write the contents of E, AC
TIMER1 ← (E), (AC) into the timer 1 reload
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
WTTM1 Write timer 1
register A.
Read out the contents of the
timer 0 counter into M2 (HL),
AC.
M2 (HL),
AC ← (TIMER0)
RTIM0
RTIM1
Read timer 0
Read timer 1
1
1
0
0
1
0
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
1
Read out the contents of the
E, AC ← (TIMER1)
2
2
2
2
2
2
2
2
2
2
timer 1 counter into E, AC.
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
0
START0 Start timer 0
START1 Start timer 1
STOP0 Stop timer 0
Start timer 0 counter Start the timer 0 counter.
Start timer 1 counter Start the timer 1 counter.
Stop timer 0 counter Stop the timer 0 counter.
Stop timer 1 counter Stop the timer 1 counter.
1
1
1
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
1
STOP1 Stop timer 1
[Interrupt control instructions]
Set interrupt master
enable flag
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
Set the interrupt master
MSE ← 1
MSET
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
enable flag to one.
Reset interrupt
MRESET
1
1
1
0
0
0
0
1
1
0
1
0
0
0
1
0
Clear the interrupt master
MSE ← 0
master enable flag
enable flag to zero.
1
0
1
1
0
0
0
1
1
1
0
1
Set the interrupt enable flag
to one.
EIH i4
EIL i4
DIH i4
DIL i4
WTSP
RSP
Enable interrupt high
Enable interrupt low
Disable interrupt high
Disable interrupt low
Write SP
EDIH ← (EDIH) i4
I
I
I
I
3
2
1
0
1
0
1
1
0
0
0
0
1
1
0
1
Set the interrupt enable flag
to one.
EDIL ← (EDIL) i4
I
I
I
I
3
2
1
0
1
1
1
0
0
0
0
1
1
1
0
1
Clear the interrupt enable
EDIH ← (EDIH) i4
ZF
ZF
I
I
I
I
flag to zero.
3
2
1
0
1
1
1
0
0
0
0
0
1
1
0
1
Clear the interrupt enable
EDIL ← (EDIL) i4
I
I
I
I
flag to zero.
3
1
1
2
1
0
1
1
1
0
1
0
1
1
1
1
0
0
0
1
Transfer the contents of E,
AC to SP.
SP ← (E), (AC)
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
Transfer the contents of SP
to E, AC.
Read SP
E, AC ← (SP)
[Standby control instructions]
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
HALT
HOLD
HALT
HOLD
2
2
2
2
HALT
HOLD
Enter halt mode.
Enter hold mode.
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
[Serial I/O control instructions]
STARTS Start serial I O
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
0
2
2
2
2
2
2
START SI O
Start SIO operation.
1
1
1
1
0
1
0
0
1
1
1
1
1
1
1
1
Write the contents of E,
AC to SIO.
WTSIO Write serial I O
SIO ← (E), (AC)
E, AC ← (SIO)
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
Read out the contents of SIO
into E, AC.
RSIO
Read serial I O
[Other instructions]
Consume one machine cycle
without performing any
operation.
NOP
No operation
0
0
0
0
0
0
0
1
0
1
1
2
1
2
No operation
1
1
1
1
0
0
0
0
1
0
1
0
SB i2
Select bank
PC13, PC12 ← I
I
Specify the memory bank.
1
0
I
I
0
1
No. 5488-26/27
LC66E5316
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 5488-27/27
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