LC723784 [SANYO]
CMOS IC Electronic tuning system for car audio ETR Microcontrollers; CMOS IC电子调谐系统，汽车音响ETR微控制器
| 型号： | LC723784 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | CMOS IC Electronic tuning system for car audio ETR Microcontrollers |
| 文件： | 总14页 (文件大小：475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN8011A
LC723781N
LC723782N
LC723783N
LC723784
LC723785
CMOS IC
Electronic tuning system for car audio
ETR Microcontrollers
Overview
The LC723780 Series are large-capacity ETR microcontrollers that can support up to 128KB of ROM and up to 8KB of
RAM. In addition to the expanded table reference instruction to support large-capacity program ROM, the LC723780
Series provide enhanced interrupt capability to directly control CD mechanism and CD-DSP, and the capability to
support the RDS models. They also have a built-in serial I/O port and an 8-input 8-bit A/D converter for communicating
with the internal and external devices, and for minimizing the connecting wire between the front panel board and the
main board, particularly for car audio systems.
The on-chip high-performance PLL circuit provides a high-speed lock circuit used to search for alternative frequencies of
RDS in a short time, the ability to control the C/N characteristics of a local oscillator, and the high S/N through the direct
PLL configuration.
Functions
• ROM
: Up to 64K steps (65,535×16-bits)
The subroutine area holds 4K steps (4,096×16-bits)
: Up to 16K×4-bits (In banks 00 through FF)
LC723781N-ROM : 40KB, RAM : 2KB
LC723782N-ROM : 48KB, RAM : 2KB
LC723783N-ROM : 64KB, RAM : 4KB
LC723784-ROM : 96KB, RAM : 6KB
LC723785-ROM : 128KB, RAM : 8KB
: 32levels
• RAM
• Stack
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
92706 / 80505HKIM B8-9065,9068,9069,8420,8219 / 91004JOIM No.8011-1/14
LC723781N/723782N/723783N/723784/723785
• Serial I/O
: Three channels. These circuits can support both 2-wire and 3-wire 8-bit communication
techniques, and can be switched between MSB first and LSB first operation.
One of six internally generated serial transfer clock rates can be selected: 12.5kHz,
37.5kHz, 187.5kHz, 281.25kHz, 375kHz, and 450kHz
• External interrupts
• Internal interrupts
: Seven interrupt inputs (pins INT0 through INT5, and the HOLD pin)
These interrupts can be set to switch between rising and falling edges, although the
HOLD pin only supports falling edge detection.
: Seven interrupts ; four internal timer interrupts, and three serial I/O interrupts.
Functions (Continued)
• Interrupt nesting levels : 16 levels
Interrupts are prioritized in hardware as follows :
HOLD pin>INT0 pin>INT1 pin>INT2 pin>INT3 pin>INT4 pin>INT5 pin>
S-I/O0>S-I/O1>S-I/O2>Internal TMR0>Internal TMR1>Internal TMR2>
Internal TMR3
• A/D Converter
• General-purpose ports
: 8-bit resolution and 8 inputs
: Input ports : 13
Output ports : 4
I/O ports : 62 (These pins can be switched between input and output in 1-bit units.)
: Includes a sub-charge pump for high-speed locking.
Supports dead zone control.
• PLL block
Built-in unlock detection circuit
Twelve reference frequencies : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz,
10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz
: This 20-bit counter can be used for either frequency or period measurement and
supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms
: Two fixed timers and two programmable timers (8-bit counters)
• Universal counter
• Timers
TMR0
TMR1
: Supports four periods : 10µs, 100µs, 1ms, and 5ms
: Supports four periods : 10µs, 100µs, 1ms, and 10ms
TMR2 and TMR3 : Programmable 8-bit counters.
Input clocks with 10µs, 100µs, and 1ms
One 125-ms timer flip-flop provided
• Beep circuit
: Provides 12 fixed beep tones :
500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3kHz, 3.125kHz, 3.33kHz,
3.75kHz, 4.17kHz, and 7.03kHz
Programmable 8-bit beep tone generator.
Reference clocks with frequencies of 50kHz, 15kHz, and 5kHz.
: Built-in voltage detection reset circuit
External reset pin
• Reset
• Cycle time
• Halt mode
: 1.33µs/833ns (All instructions are one word), X’tal : 4.5MHz/7.2MHz
Supports software switching (Initial cycle time is 1.33µs)
: The microcontroller operating clock is stopped in Halt mode.
There are four conditions that can clear Halt mode : Interrupt requests,
timer flip-flop overflows, port PA inputs, and HOLD pin inputs.
• Operating supply voltage : 4.5 to 5.5V (Microcontroller block only : 3.5 to 5.5V)
• Package
• OTP version
• Development tools
: QIP100E
: LC72F3781
: Emulator
: RE128V
Evaluation chip
Evaluation board
: LC72EV3780
: EB-72EV3780
No.8011-2/14
LC723781N/723782N/723783N/723784/723785
Specifications
Absolute Maximum Ratings at Ta = 25°C V = 0V
SS
Parameter
Maximum supply voltage
Input voltage
Symbol
Conditions
Ratings
-0.3 to +6.5
Unit
V
V
V
V
V
V
V
I
max
DD
1
PC-PORT
-0.3 to +8
V
IN
IN
2
All input pins other than V
PJ-PORT
1
-0.3 to V +0.3
DD
V
IN
Output voltage
Output current
1
2
3
-0.3 to +14
-0.3 to +8
V
OUT
OUT
OUT
PC-PORT
V
All input pins other than V 1 and V 2
OUT OUT
-0.3 to V +0.3
DD
V
1
PC, PJ-PORT
0 to +5
mA
OUT
I
2
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ,
PR, PS, PT-PORT, EO1, EO2, SUBPD
Ta = -40 to +85 °C
OUT
0 to +3
mA
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
400
-40 to +85
-40 to +125
mW
°C
Tstg
°C
Allowable Operating Range at Ta = -40 to +85°C, V
= 3.5 to 5.5V
DD
Ratings
typ
5.0
Parameter
Symbol
Pins
uit
V
min
mx
Supply voltage
V
1
2
3
CPU and PLL operation
CPU operation
4.5
3.5
1.1
5.5
5.5
5.5
DD
DD
DD
V
V
V
Memory retention
Input high-level
voltage
1
PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS,
PT-PORT, HCTR, LCTR, INEO, SUBPD
(with the I/O ports set to input mode)
IH
0.7V
0.8V
V
V
V
V
DD
DD
V
2
PD, PE, PF, PG, PK-PORT, LCTR
IH
DD
2.5
DD
DD
(in period measurement mode),
,
HOLD RESET
V
V
V
3
4
SNS
V
V
V
V
IH
DD
PA-PORT
0.6V
IH
DD
Input low-level voltage
1
PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS,
PT-PORT, HCTR, LCTR, INEO, SUBPD
(with the I/O ports set to input mode)
IL
0
0.3V
0.2V
V
DD
V
2
PA, PD, PE, PF, PG, PK-PORT, LCTR
IL
0
V
DD
1.1
(in period measurement mode),
SNS
RESET
V
V
F
3
4
1
0
0
V
IL
HOLD
XIN
0.4V
V
IL
DD
8.0
Input frequency
4.0
10
10
2.0
0.5
0.4
4.5
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Hz
IN
IN
IN
IN
IN
IN
IN
IN
F
F
F
F
F
F
F
2
3
4
5
6
7
8
1
FMIN : V 2, V
IN
1
1
150
130
40
DD
FMIN : V 3, V
IN
DD
AMIN(H) : V 3, V
IN
1
DD
AMIN(L) : V 3, V
1
10
IN
DD
1
HCTR : V 3, V
IN
12
DD
LCTR : V 3, V
1
100
1
500
20×103
1.5
IN
DD
LCTR (in period measurement) : V 2, V 2, V
IH IL
1
DD
Input amplitude
V
V
V
V
XIN
0.5
0.07
0.04
0
Vrms
Vrms
Vrms
V
IN
2
3
6
FMIN
1.5
IN
IN
IN
FMIN, AMIN, HCTR, LCTR
ADI0 to ADI7
1.5
Input voltage range
V
DD
No.8011-3/14
LC723781N/723782N/723783N/723784/723785
Electrical Characteristics in the allowable operating ranges
Ratings
typ
Parameter
Symbol
Pins
unit
min
max
15
Input high-level current
I
I
I
1
XIN : V = V = 5.0V
DD
2.0
4.0
5.0
µA
µA
IH
I
2
FMIN, AMIN, HCTR, LCTR : V = V = 5.0V
DD
10
30
IH
I
3
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
SNS HOLD RESET
IH
PP, PQ, PR, PS, PT-PORT,
LCTR, INEO, SUBPD : V = V
,
,
, HCTR,
= 5.0V
DD
3
µA
I
(with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN,
PP, PO, PQ, PR, PS, and PT-PORT set to input mode)
Input low-level current
I
I
I
1
XIN : V = V
DD
= V
SS
2.0
4.0
5.0
10
15
30
µA
µA
IL
I
2
FMIN, AMIN, HCTR, LCTR : V = V
DD
= V
SS
IL
I
3
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
SNS HOLD RESET
IL
PP, PQ, PR, PS, PT-PORT,
LCTR, INEO, SUBPD : V = V
,
,
, HCTR,
3
µA
I
SS
(with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN,
PP, PO, PQ, PR, PS, and PT-PORT set to input mode)
RESET
, LCTR
Hysteresis
VH
V
PD, PE, PF, PG, PK-PORT,
(in period measurement)
0.1V
0.2V
V
V
DD
DD
Output high-level voltage
1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
OH
V
-1.0
DD
PS, PT-PORT : I = -1mA
O
V
V
V
2
3
EO1, EO2, SUBPD : I = -500µA
V
V
-1.0
-1.0
V
V
OH
O
DD
XOUT : I = -200µA
OH
O
DD
Output low-level voltage
1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ, PR,
OL
1.0
V
PS, PT-PORT : I = -1mA
O
V
V
V
I
2
EO1, EO2, SUBPD : I = -500µA
1.0
1.5
2.0
V
V
V
OL
OL
OL
O
3
4
XOUT : I = -200µA
O
PC, PJ-PORT : I = -5mA
O
Output off leakage
current
1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
PS, PT-PORT
OFF
-3
3
µA
I
I
2
3
EO1, EO2, SUBPD
-100
-5
100
5
nA
µA
OFF
PC, PJ-PORT
ADI0 to ADI7
SNS
OFF
A/D conversion error
Rejected pulse width
-1.5
+1.5
50
LSB
µs
PREJ1
VDET
Power down detection
voltage
2.7
3.0
3.3
V
Power supply current
I
I
I
I
I
1
2
3
4
5
V
V
V
V
1 : F 2 = 130MHz Ta = 25°C, X’tal : 4.5MHz
5
10
11
mA
mA
mA
mA
DD
DD
DD
DD
DD
DD
DD
DD
DD
IN
1 : F 2 = 130MHz Ta = 25°C, X’tal : 7.2MHz
5.5
IN
2 : Halt mode Ta = 25°C, X’tal : 4.5 MHz
2 : Halt mode Ta = 25°C, X’tal : 7.2MHz
*1 (Fig. 1)
0.45
0.55
Backup mode (OSC stopped)
= 5.5V, Ta = 25°C
5
1
µA
µA
V
*2 (Fig. 2)
*2 (Fig. 2)
DD
Backup mode (OSC stopped)
= 2.5V, Ta = 25°C
I
6
DD
V
DD
*1 : Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
No.8011-4/14
LC723781N/723782N/723783N/723784/723785
Test Circuits
Figure 1. I 2 in Halt Mode
DD
Figure 2. I 3 and I 4 in Backup Mode
DD DD
Package Dimensions
unit : mm
3151A
No.8011-5/14
LC723781N/723782N/723783N/723784/723785
Pin Assignment
No.8011-6/14
LC723781N/723782N/723783N/723784/723785
Block Diagram
No.8011-7/14
LC723781N/723782N/723783N/723784/723785
Pin Description
Pin name
Pin No.
I/O
Pin explanation
Equivalent circuit
PA0
PA1
PA2
PA3
32
31
30
29
I
Dedicated input ports.
These ports are designed with a low threshold voltage.
Input is disabled in Backup mode.
PB0
PB1
PB2
PB3
28
27
26
25
I/O
General-purpose I/O ports.
The mode (input or output) is set using the IOS2 instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PC0
PC1
PC2
PC3
24
23
22
21
I/O
General-purpose I/O ports (middle-voltage input and output).
The mode (input or output) is set using the IOS2 instruction.
External pull-up resistors are required since the output circuits are
open drain.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PD0/INT4
PD1/INT5
PD2
20
19
18
17
I/O
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
The external interrupt function is enabled when the external interrupt
enable flag is set.
PD3
• When used as general-purpose I/O ports :
The mode (input or output) is set in 1-bit units using the IOS2
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT4EN or INT5EN).
In this case, the pins must be set to input mode in advance.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.8011-8/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
Pin No.
I/O
Pin explanation
Equivalent circuit
PE0
16
15
14
13
12
11
10
9
I/O
General-purpose I/O ports with shared functions as serial I/O ports.
The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2
pins can be switched to function as open drain outputs.
The IOS1 instruction is used to switch between the general-purpose
I/O port and serial I/O port functions.
PE1/SCK2
PE2/SO2
PE3/SI2
PF0
PF1/SCK1
PF2/SO1
PF3/SI1
PG0
• When used as general-purpose I/O ports :
The pins are set to the general-purpose I/O port function using the
IOS1 instruction.
8
The mode (input or output) is set in 1-bit units using the IOS1
instruction
PG1/SCK0
PG2/SO0
PG3/SI0
7
6
• When used serial I/O ports :
5
The pins are set to the serial I/O port function using the IOS1
instruction.
[Pin states when set to the serial I/O port function]
PE0, PF0, PG0 … General-purpose I/O
PE1, PF1, PG1 … SCK input or output
PE2, PF2, PG2 … SO output
PE3, PF3, PG3 … SI input
The PE1/SCK2 and PE2/SO2 pins can be switched to function as
open drain outputs with the IOS2 instruction. When using this circuit
type, the external pull-up resistors must be connected to the same
power supply as that used by the IC.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
XIN
1
I
Connections for 4.5MHz/7.2MHz crystal oscillator element
XOUT
100
O
EO1
EO2
98
97
O
Main charge pump outputs.
These pins output a high level when the frequency of the local
oscillator divided by n is higher than that of the reference frequency,
and they output a low level when that frequency is lower.
They go to the high-impedance state when the frequencies match.
These pins go to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
V
PORT
PLL
39
93
4
-
Power supply connections.
DD
V
The V PORT and V PORT pins are mainly supply power for the
DD
DD
SS
V
CPU
peripheral I/O blocks.
SS
V
PORT
ADC
40
81
96
The V PLL and V PLL pins are mainly for the PLL circuits and
DD SS
the regulator.
SS
V
V
SS
PLL
The V CPU pin is mainly used by the CPU block.
SS
SS
The V ADC pin is mainly used by the ADC block.
SS
Since all the V
DD
and V pins are independent, all must be
SS
connected to the same power supply.
VREG
3
O
Internal low voltage output.
Connect a bypass capacitor to this pin.
Continued on next page.
No.8011-9/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
FMIN
Pin No.
95
I/O
Pin explanation
FM VCO (local oscillator) input.
Equivalent circuit
I
This pin is selected with CW1 in the PLL instruction.
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
AMIN
94
I
AM VCO (local oscillator) input.
This pin is selected and the band set with CW1 (b1, b0) in the PLL
instruction.
b1
1
b0
0
Band
2 to 40MHz (SW, AM upconversion)
0.5 to 10MHz (MW, LW)
1
1
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
SUBPD
92
I/O
Sub-charge pump output and general-purpose input shared function
port.
The IOS2 instruction is used for switching between the sub-charge
pump output and general-purpose input functions.
• When used as the sub-charge pump output :
The sub-charge pump output function is set up with the IOS2
instruction.
A high-speed locking circuit can be formed by using this pin in
conjunction with the main charge pump.
The sub-charge pump is controlled using the DZC instruction.
b3
0
b2
0
Operation
High impedance
Only operates when the PLL is unlocked
(450kHz)
0
1
Only operates when the PLL is unlocked
(900kHz)
1
1
0
1
Normal operation
• When used as a general-purpose input :
The general-purpose input function is set up with the IOS2
instruction.
Data is read from the port using the INR instruction.
This pin goes to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
Dedicated input port.
INEO
91
I
Data is read from the port using the INR instruction
Input is disabled in Backup mode.
Continued on next page.
No.8011-10/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
HCTR
Pin No.
90
I/O
I
Pin explanation
Equivalent circuit
Universal counter and general-purpose input shared function input port.
The IOS1 instruction is used for switching between the universal
counter and general- purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
The counter is controlled using UCS and UCC instructions.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used as a general-purpose input pin :
The general-purpose input function is set up with the IOS1
instruction.
Data is read from the port using the INR (b0) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function is selected after a power on reset.
Universal counter (frequency or period measurement) and general-
purpose input shared function input port.
LCTR
89
I
The IOS1 instruction is used for switching between the universal
counter and general-purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used for period measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since the bias feedback resistor is disconnected in this mode, the
input signal must be input with DC coupling.
• When used as a general-purpose input pin :
The general-purpose input port function is set up with the IOS1
instruction.
Data is read from the port using the INR (b1) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function (HCTR frequency measurement mode)
is selected after a power on reset.
SNS
88
I
Voltage sense and general-purpose input shared function port.
This input circuit is designed with a low input threshold voltage.
• When used as a voltage sense input :
The pin is used to test for power failures on the return from Backup
mode.
Application can test this condition using the internal SNS flip-flop.
The SNS flip-flop can be tested with the TST instruction.
(This usage requires external components, capacitors and resistors.
For the sample application circuit, see the user’s manual.)
• When used as a general-purpose input port :
When used as a general-purpose input port the pin state can be
tested with the TST instruction.
Unlike the other input ports, input to this pin is not disabled in Backup
mode and after a power on reset. As a result, through currents must
be taken into account when designing applications that use this pin as
a general-purpose input.
HOLD
87
I
Power supply monitor (with interrupt function)
This is designed with a high input threshold voltage.
This pin is normally connected to the ACC line and used for power off
detection.
When a power off state is detected, the HOLDON flag and the hold
interrupt request flag will be set.
To enter Backup mode, execute a CKSTP instruction when the HOLD
pin is low. Set this pin high to clear Backup mode.
Continued on next page.
No.8011-11/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
RESET
Pin No.
86
I/O
Pin explanation
Equivalent circuit
I
System reset pin.
When the CPU is operating or in Halt mode, the system is reset when
this pin is held low for at least one machine cycle. Execution starts
with the PC pointing to location 0. At this time the SNS flip-flop is set.
A low level must be applied for at least 50ms when power is first
applied.
PH0/ADI0
PH1/ADI1
PH2/ADI2
PH3/ADI3
PI0/ADI4
PI1/ADI5
PI2/ADI6
PI3/ADI7
85
84
83
82
81
80
79
78
I
General-purpose input and A/D converter input shared function ports.
The IOS1 instruction is used to switch between the general-purpose
input and the A/D converter input functions.
• When used as general-purpose input ports :
The general-purpose input port function is set up with the IOS1
instruction. (In bit units)
• When used as A/D converter input pins :
The A/D converter input port function is set up with the IOS1
instruction. (In bit units)
The pin whose voltage is to be converted is specified with the IOS1
instruction, and the conversion is started with UCC instruction.
Note : Since input is disabled for ports specified for the ADI function,
executing an input instruction for such a port will always return
a low level.
Input is disabled in Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PJ0
PJ1
PJ2
PJ3
76
75
74
73
O
General-purpose output ports (high-voltage output)
Since these are open-drain output circuits, external pull-up resistors
are required.
The internal transistors are turned off (resulting in a high-level output)
in Backup mode and after a power on reset.
PK0/INT0
PK1/INT1
PK2/INT2
PK3/INT3
72
71
70
69
I/O
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
The external interrupt function is enabled when the external interrupt
enable flag is set.
• When used as general-purpose I/O ports :
The mode (input or output) is set in 1-bit units using the IOS1
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT0EN through
INT3EN). Here, the pins must be set to input mode in advance.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.8011-12/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
Pin No.
I/O
I/O
Pin explanation
Equivalent circuit
PL0 to 3
PM0 to 3
68 to 61
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PN0/BEEP
PN1
60
59
58
57
I/O
General-purpose I/O port and beep tone output shared function ports.
The IOS2 instruction is used to switch between the general-purpose
I/O port and the beep tone output functions.
• When used as general-purpose I/O ports :
The general-purpose I/O port function is set up with the IOS2
instruction.
PN2
PN3
(Pins PN1 through PN3 are dedicated general-purpose output pins.)
• When used as the beep tone output pin :
The beep tone output function is set up with the IOS2 instruction.
The frequency is set up with the BEEP instruction.
When this pin is used as the beep tone output pin, executing an
output instruction for this pin only sets the internal latch and has no
influence on the output.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PO0 to 3
PP0 to 3
56 to 49
I/O
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PQ0 to 3
PR0 to 3
PS0 to 3
PT0 to 3
48 to 41
38 to 33
I/O
General-purpose I/O ports.
The mode is switched between input and output with the IOS
instruction, and data is input with the INR instruction and output with
the OUTR instruction.
The SPB, RPB, TPT, and TPF instruction cannot be used with these
ports.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
TEST1
TEST2
99
2
LSI test pins.
These pins must be connected to GND.
No.8011-13/14
LC723781N/723782N/723783N/723784/723785
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performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
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for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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This catalog provides information as of February, 2006. Specifications and information herein are subject
to change without notice.
PS No.8011-14/14
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