LC74735NW [SANYO]
On-Screen Display Controller; 屏幕显示控制器
| 型号： | LC74735NW |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | On-Screen Display Controller |
| 文件： | 总52页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7545
CMOS IC
LC74735NW
On-Screen Display Controller
12 dots (horizontal) × 16 dots (vertical): Graphic
glyph display (1 pixel: 2 × 2 dots)
— Character display clock:
Overview
The LC74735NW is an on-screen display CMOS IC that
displays characters and patterns on a TV screen.
For QVGA display, the LC74735NW supports the use of
both a 12 × 18 dot character font and a 12 × 18 dot
graphics font with 16 colors with a total of 512 characters
and glyphs.
For WVGA display, the LC74735NW supports the use of
both a 24 × 32 dot character font and a 12 × 16 dot
graphics font with 16 colors with a total of 512 characters
and glyphs.
About 9 MHz — QVGA with an LC oscillator
33.2 MHz (maximum: 40 MHz) WVGA with an
external clock signal input
*: The ROM image is known when QVGA or WVGA
mode is specified.
• Number of characters: 512 (internal)
Up to 2048 characters when an external 16-bit 4M ROM
is used.
• Character sizes: Four horizontal sizes (1×, 2×, 3×, and
4×)
The LC74735NW can also implement extremely varied
displays by the use of an external ROM.
The LC74735NW supports both QVGA (480 × 234) and
WVGA (800 × 480).
Four vertical sizes (1×, 2×, 3×, and 4×)
(The character size is specified in line
units.)
• Display start positions: 512 positions in the horizontal
direction and 256 positions in the vertical direction.
QVGA mode WVGA mode
Features
• Screen structure
— Main:
QVGA mode: 40 characters × 13 lines (up to 520
characters) on a QVGA panel
WVGA mode: 33 characters × 15 lines (up to 495
characters) on a WVGA panel
— Wallpaper display screen: Permanent repetition of a
2 × 2 (horizontal × vertical) character pattern
• Character structure
Setting units: Horizontal: 1 dot
2 dots (In
screen units)
2 dots (In
Vertical: 1 dot
screen units)
• Display functions
— Blinking specification (in character units)
Period: 1/64, 1/32, and 1/16 of the vertical sync
signal (in screen units)
Duty: Fixed at 50%
— Box (raised or recessed) display
— QVGA mode:
12 dots (horizontal) × 18 dots (vertical): Character
display
12 dots (horizontal) × 18 dots (vertical): Graphic
glyph display
Raised/recessed specification (in character units)
Left: Off/on specification (in character units)
Right: Off/on specification (in character units)
Top: Off/on specification (in character units)
Bottom: Off/on specification (in character units)
— WVGA mode:
24 dots (horizontal) × 32 dots (vertical): Character
display
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1003TN (OT) No. 7545-1/52
LC74735NW
— Border specification (in line units): Only valid with
glyphs from the character font.
• Color specification
Package Dimensions
unit: mm
3220-SQFP80
Character
— Character color (in character units): 1 of 16 colors
can be specified.
— Character background color (in character units): 1 of
16 colors can be specified.
— Border color (in line units): 1 of 16 colors can be
specified.
[LC74735NW]
14.0
12.0
0.135
1.25
1.25
0.5
60
41
61
40
• Graphic
— 16 types can be specified by ROM data
• Box color (line units) : 1/16 colors
• Background color (screen units) : 1/16 colors
• Color table (palette)
21
80
— Sixteen colors can be selected from a set of 512
colors (One of which is specified to be transparent.)
— Number of color tables: 2. This allows up to 32
colors to be displayed at the same time.
• Wallpaper screen (Graphics glyphs only)
Wallpaper display: Repeated display under the main
screen (2 characters horizontally by 2 characters
vertically).
1
20
0.2
0.5
0.5
SANYO: SQFP80
Sprite character display: Displayed above the main
screen (2 characters horizontally by 2 characters
vertically)
• Output
— QVGA
Analog RGB output
BLK (OSD display period signal)
— WVGA
Digital RGB output (3 bits per color)
BLK (OSD display period signal)
• Package: SQFP80
• Voltage: 3.3 V
No. 7545-2/52
LC74735NW
Pin Assignments
78
65
80
79
77
76
75
74
73
72
71
70
69
68
67
66
64
63
62
61
VSS1
OSCin
OSCout
CTRL1
SCLK
SIN
1
2
3
4
5
6
7
8
9
60 A16
59 A17
58 CE
57 OE
56 VDD3
55 VSS3
54 D0
CS
VDD1
VSYNC
53 D1
52 D2
VBLK 10
HSYNC 11
HBLK 12
TEST1 13
TEST2 14
RST 15
51 D3
50 D4
49 D5
48 D6
47 D7
46 VDD1
45 VSS1
44 D8
VSS1 16
VDD1 17
CLKOUT 18
VSS1 19
VDD1 20
43 D9
42 D10
41 D11
23
36
21
22
24
25
26
27
28
29
30
31
32
33
34
35
37
38
39
40
Top view
No. 7545-3/52
LC74735NW
Pin Functions
Pin No.
Symbol
SS1
Type
Functional description
1
2
3
V
Ground
Connect a ground to this pin. (Digital system ground)
OSCin
Connect to the character output dot clock generator oscillator coil and capacitor.
May also be used for external clock input.
LC oscillator
OSCout
Switches between external clock input mode and LC oscillator mode.
Low: LC oscillator, high: external clock input MORE+
4
5
6
CTRL1
SCLK
SIN
OSCin oscillator input control
Clock input
Clock input for the serial data input system
MORE+ (This input has hysteresis characteristics.)
Serial data input
MORE+ (This input has hysteresis characteristics.)
Data input
Enable input for the serial data input system. Serial data input is enabled when this pin is set low.
MORE+ (This input has hysteresis characteristics.)
7
8
9
CS
Enable input
VDD1
Power supply (+3.3 V)
Vertical sync signal input
Digital system power supply: +3.3 V
Vertical sync signal input
MORE+ (This input has hysteresis characteristics.)
VSYNC
VBLK
Vertical blanking signal input
MORE+ (This input has hysteresis characteristics.)
10
11
12
13
14
15
Vertical blanking signal input
Horizontal sync signal input
Horizontal blanking signal input
Test mode control 1
Horizontal sync signal input
MORE+ (This input has hysteresis characteristics.)
HSYNC
HBLK
Horizontal blanking signal input
MORE+ (This input has hysteresis characteristics.)
Test mode control 1
Low: normal operation, high: test mode MORE+
TEST1
TEST2
RST
Test mode control 2
Low: normal operation, high: test mode (scan mode) MORE+
Test mode control 2
System reset input
MORE+ (This input has hysteresis characteristics.)
Reset input
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
DD1
CLKOUT
SS1
DD1
1
Ground
Connect a ground to this pin. (Digital system ground)
Power supply: (+3.3 V: Digital system)
Clock output
V
Power supply (+3.3 V)
Clock output
V
Ground
Connect a ground to this pin. (Digital system ground)
Power supply: (+3.3 V: Digital system)
V
Power supply (+3.3 V)
Rout output: bit 2
Rout output: bit 1
Rout output: bit 0
Gout output: bit 2
Gout output: bit 1
Gout output: bit 0
Bout output: bit 2
Bout output: bit 1
Bout output: bit 0
Blanking signal output
Ground
RD2
RD1
RD0
GD2
GD1
GD0
BD2
BD1
BD0
BLK
Rout output
This is a 3-bit digital output with values from 000 to 111.
Gout output
This is a 3-bit digital output with values from 000 to 111.
Bout output
This is a 3-bit digital output with values from 000 to 111.
This signal indicates the OSD display period.
VSS1
Connect a ground to this pin. (Digital system ground)
Power supply: (+3.3 V: D/A converter)
VDD2
Power supply (+3.3 V)
Outr output: analog
Rout output: analog
Gout output: analog
Bout output: analog
OUTR
Rout
Output. Connect a resistor Ro (68 Ω) to this pin.
D/A converter (3 bits) output. Connect a resistor Ro to this pin.
D/A converter (3 bits) output. Connect a resistor Ro to this pin.
D/A converter (3 bits) output. Connect a resistor Ro to this pin.
Gout
Bout
CCOMP
CVREF
RREF
Phase correction capacitor connection Capacitor connection: 1.5 µF
Reference voltage output Capacitor connection: 0.1 µF
Reference resistor connection Connect a reference register to this pin.
Ground Connect a ground to this pin. (D/A converter ground)
V
SS2
Continued on next page.
No. 7545-4/52
LC74735NW
Continued from preceding page.
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
D11
D10
D9
Type
Data input 11
Functional description
ROM data input 11. MORE+
ROM data input 10. MORE+
ROM data input 9. MORE+
ROM data input 8. MORE+
Data input 10
Data input 9
Data input 8
Ground
D8
VSS1
Connect a ground to this pin. (Digital system ground)
Power supply: (+3.3 V: Digital system)
ROM data input 7. MORE+
VDD1
Power supply (+3.3 V)
Data input 7
Data input 6
Data input 5
Data input 4
Data input 3
Data input 2
Data input 1
Data input 0
Ground
D7
D6
D5
D4
D3
D2
D1
D0
ROM data input 6. MORE+
ROM data input 5. MORE+
ROM data input 4. MORE+
ROM data input 3. MORE+
ROM data input 2. MORE+
ROM data input 1. MORE+
ROM data input 0. MORE+
VSS3
Connect a ground to this pin. (External ROM output system ground)
VDD3
Power supply (+3.3 or +5.5 V) Power supply (External ROM output system power supply)
OE
CE
Output enable
ROM output enable output. This is an active low output.
ROM chip enable output. This is an active low output.
ROM address output 17
Chip enable
A17
A16
A15
A14
A13
A12
A11
A10
A9
Address output 17
Address output 16
Address output 15
Address output 14
Address output 13
Address output 12
Address output 11
Address output 10
Address output 9
Address output 8
Ground
ROM address output 16
ROM address output 15
ROM address output 14
ROM address output 13
ROM address output 12
ROM address output 11
ROM address output 10
ROM address output 9
A8
ROM address output 8
V
SS3
Connect a ground to this pin. (External ROM output system ground)
VDD3
Power supply (+3.3 or +5.5 V) Power supply (External ROM output system power supply)
A7
A6
A5
A4
A3
A2
A1
A0
Address output 7
Address output 6
Address output 5
Address output 4
Address output 3
Address output 2
Address output 1
Address output 0
Ground
ROM address output 7
ROM address output 6
ROM address output 5
ROM address output 4
ROM address output 3
ROM address output 2
ROM address output 1
ROM address output 0
VSS3
Connect a ground to this pin. (External ROM output system ground)
VDD3
Power supply (+3.3 or +5.5 V) Power supply (External ROM output system power supply)
No. 7545-5/52
LC74735NW
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
V
V
DD1
DD3
VDD1, VDD
2
VSS – 0.3 to VSS + 4.6
VSS – 0.3 to VSS + 6.0
VSS – 0.3 to VDD1 + 0.3
VSS – 0.3 to VDD1 + 0.3
VSS – 0.3 to VDD1 + 0.3
230
Supply voltage
Input voltage
Output voltage
VDD3
V
VIN
All input pins
V
V
V
OUT1
OUT2
RD2 to 0, GD2 to 0, BD2 to 0, and BLK outputs
A0 to A17, CE, OE outputs
V
V
Maximum power dissipation
Operating temperature
Storage temperature
Pdmax
Topg
Tstg
mW
°C
°C
–30 to +70
–40 to +125
Recommended Operating Conditions
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
V
DD1
DD3
VDD1, VDD
2
3.0
3.0
3.3
3.3
—
—
—
—
—
—
10
33
—
1.1
—
—
—
3.6
5.5
5.5
5.5
5.5
V
V
Supply voltage
V
VDD3
V
IH1
IH2
IH3
CTRL1, TEST1, TEST2
0.7 VDD
0.8 VDD
0.7 VDD
1
1
1
V
Input high-level voltage
Input low-level voltage
V
SCLK, SIN, CS, VSYNC, HSYNC, RST
D0 to D11
V
V
V
V
IL1
VIL
IL3
FOSC1
FOSC2
IN1
CTRL1, TEST1, TEST2
VSS – 0.3
VSS – 0.3
VSS – 0.3
—
0.3 VDD
0.2 VDD
0.3 VDD
1
1
1
V
2
SCLK, SIN, CS, VSYNC, HSYNC, RST
D0 to D11
V
V
V
Oscillator frequency
External clock input
OSCin and OSCout oscillator pins (LC oscillator)
OSCin, VDD1 = 3.3 V
—
MHz
—
40 MHz
3.3 Vp-p
V
VDD1 = 3.3 V, CTRL1 = high
Reference voltage
0.5
Vrefda
Rfda
—
—
225
75
V
Ω
Ω
Ω
D/A converter (3 bit, 3 ch)
When maximum output voltage =
0.7 V
Output load resistance ROUT, GOUT, and BOUT
Output load resistance OUTR
Reference load resistance, RREF
120
Rfbda
Rref
40
1232
2310
No. 7545-6/52
LC74735NW
Electrical Characteristics at Ta = –30 to +70°C, V = 3.3 V unless otherwise specified.
DD
Ratings
typ
Parameter
Symbol
Pin
Conditions
Unit
min
max
RD2 to 0, GD2 to 0, BD2 to 0, VDD1 = 3.0 V
VOH
VOH
VOH
1
2
3
V
V
V
1 – 0.8
—
—
—
—
V
V
V
V
V
V
DD
DD
DD
and BLK outputs
I
OH1 = –8 mA
VDD3 = 3.0 V
OH2 = –8 mA
VDD3 = 4.5 V
OH3 = –8 mA
Output high-level voltage
A0 to 17, CE, and OE
3 – 0.8
3 – 0.8
—
—
—
—
—
—
I
A0 to 17, CE, and OE
I
RD2 to 0, GD2 to 0, BD2 to 0, VDD1 = 3.0 V
VOL
VOL
VOL
1
2
3
0.4
0.4
0.4
and BLK outputs
I
OL1 = 8 mA
VDD3 = 3.0 V
OL2 = 8 mA
VDD3 = 4.5 V
OL3 = 8 mA
Output low-level voltage
A0 to 17, CE, and OE
—
I
A0 to 17, CE, and OE
—
I
CTRL1, TEST1, TEST2,
SCLK, SIN, CS, VSYNC,
HSYNC, RST
IIH
IIH
IIL
IL2
IDD
1
VIN = VDD
VIN = VDD
VIN = VSS
VIN = VSS
1
—
—
—
—
—
10
10
—
µA
µA
µA
2
D0 to 11
3
Input current
CTRL1, TEST1, TEST2,
SCLK, SIN, CS, VSYNC,
HSYNC
1
–10
I
D0 to 11
–10
—
—
—
—
µA
All outputs open
OSCin: 40 MHz
1
VDD1
37
mA
Operating current drain
D/A converter
I
DD2
DD3
VDD
2
3
D/A on
—
—
—
—
—
—
0
22
20
20
1.5
—
mA
mA
MHz
V
I
VDD
CLK
Vmax
Vmin
Clock frequency
—
Maximum output voltage
Minimum output voltage
V
DD2 = 3.3 V
DD2 = 3.3 V
0.25
—
V
V
No. 7545-7/52
LC74735NW
Timing Characteristics
OSD Write (See figure 1.) at Ta = –30 to +70°C, V 1 = 3.3 ± 0.3 V
DD
Ratings
typ
—
Parameter
Minimum input pulse width
Data setup time
Symbol
Conditions
Unit
min
200
max
t
w (sclk) SCLK
w (cs) CS (The period CS is high)
su (cs) CS
su (sin) SIN
—
ns
µs
ns
ns
µs
ns
µs
µs
t
1
200
200
2
—
—
—
—
—
—
—
—
t
—
t
—
t
h (cs)
CS
—
Data hold time
t
h (sin)
tword
twt
SIN
200
4.2
1
—
The time to write 8 bits of data
RAM data write time
—
One word write time
—
Supplementary Materials
t (cs)
w
CS
t
(cs)
su
t (sclk)
t (sclk)
t (cs)
h
w
w
SCLK
t
(sin)
t (sin)
h
su
SIN
CS
t
word
t
wt
SCLK
0
1
5
6
7
0
1
4
5
6
7
Figure 1 OSD Serial Data Input Timing
No. 7545-8/52
LC74735NW
System Block Diagram
VDD1, VDD2,VDD3
VSS1,VSS2,VSS3
CS
16-bits
latch
+
command
decoder
Serial-to-
parallel
converter
SIN
SCLK
RST
Horizontal
direction
control register
Address
control circuit
Horizontal
direction
counter
HSYNC
HBLK
VRAM
Vertical
direction
control register
OE, CE
A0-17
Address
control circuit
External ROM
control circuit
Vertical
direction
counter
HSYNC
HBLK
RAM and ROM
read and write
control
D0-11
FROM
RD2-0
GD2-0
BD2-0
BLK
Output control circuit
Character
size control
OUTR
ROUT
GOUT
BOUT
CCOMP
CVREF
RREF
OSCin
Timing
generator
OSCout
D/A
CTRL1
No. 7545-9/52
LC74735NW
Display Control Commands
The display control commands have serial input format that consists of 8-bit units transmitted LSB first. A commands
consists of a command identification code in the first byte and data in the second and following bytes. Both a first byte
and a second byte (16 bits) must be transmitted for each command. Commands 10, 11, and 71 set the IC to continuous
write mode. (Continuous write mode is cleared by setting the CS pin high.)
Display Control Command Table
First byte
Command identification code
Second byte
Data
Command
Data
7
6
5
4
3
2
0
1
0
7
6
5
4
3
2
1
0
Command00 (Write address)
Main
1
0
0
0
0
V3
V2
V1
V0
H5
H4
H3
H2
H1
H0
Command01 (Write address)
Sub (Wallpaper)
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
SV0
0
0
0
0
0
0
SH0
RM2 RM1(1)
at
BXS BXL BXR BXU BXD
(2) CB3 CB2 CB1 CB0 CC3 CC2 CC1 CC0
Command 10 (Character write)
Main
(3)
0
0
C6
0
CT0
C5
0
I/E
C4
0
M/G C10
C9
C1
0
C8
C0
0
(4) C7
C3
0
C2
0
1
0
0
1
0
1
RM2 RM1(1)
0
0
0
(2)
(3)
0
0
0
0
0
0
0
Command 11 (Character write)
Sub (Wallpaper)
0
CT0
C5
I/E
C4
M/G C10
C3 C2
C9
C1
C8
C0
(4) C7
C6
Command20 (System control)
Command21 (Display control)
Command22 (I/O polarity control 1)
Command23 (Screen background color)
Command24 (I/O polarity control 2)
Command25 (Output control)
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
TSTMD2 TSTMD1 Q/W2 Q/W1 SYSRST CTERS SRMERS MRMERS
LCSOFF BK1 BK0 SBG1 SBG0 DSPBG DSPGS DSPGM
BLD1 BLO0 BLOP BLO1 BLO0 CKP VIP
HIP
0
0
BGCT1 BGCT0 BGC3 BGC2 BGC1 BGC0
DSPMD1 DSPMD0 DASEL VBLKON HBLKON CKOP VBP HBP
CEHSL TOKSL VIPSL OTM2 OTM1 OTM0 QRM1 QRM0
Command30
(Vertical display start position: main)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
VPM7 VPM6 VPM5 VPM4 VPM3 VPM2 VPM1 VPM0
Command31
(Horizontal display start position: main)
HPM8 HPM7 HPM6 HPM5 HPM4 HPM3 HPM2 HPM1 HPM0
VPS7 VPS6 VPS5 VPS4 VPS3 VPS2 VPS1 VPS0
HPS8 HPS7 HPS6 HPS5 HPS4 HPS3 HPS2 HPS1 HPS0
VPG7 VPG6 VPG5 VPG4 VPG3 VPG2 VPG1 VPG0
HPG8 HPG7 HPG6 HPG5 HPG4 HPG3 HPG2 HPG1 HPG0
Command32
(Vertical display start position: sub)
0
Command33
(Horizontal display start position: sub)
Command34
(Vertical display start position: screen)
0
Command35
(Horizontal display start position: screen)
Command40
(Character size control)
0
0
0
0
0
0
0
0
0
0
0
SZV1 SZV0 SZH1 SZH0
Command41
(Character size control: line setting U)
LSZ7 LSZ6 LSZ5 LSZ4 LSZ3 LSZ2 LSZ1 LSZ0
LSZ15 LSZ14 LSZ13 LSZ12 LSZ11 LSZ10 LSZ9 LSZ8
Command42
(Character size control: line setting D)
Command50
(Box control U)
BXUW BXLW
BXDW BXRW
0
0
BXUCT0 BXUC3 BXUC2 BXUC1 BXUC0
BXDCT0 BXDC3 BXDC2 BXDC1 BXDC0
Command51
(Box control D)
Command52
(Box control: line setting U)
LBX7 LBX6 LBX5 LBX4 LBX3 LBX2 LBX1 LBX0
LBX15 LBX14 LBX13 LBX12 LBX11 LBX10 LBX9 LBX8
Command53
(Box control: line setting D)
Command60
(Border control)
BLK1 BLK0
0
0
0
EGCT0 EGC3 EGC2 EGC1 EGC0
Command61
(Border control: line setting U)
0
0
0
0
0
LFC7 LFC6 LFC5 LFC4 LFC3 LFC2 LFC1 LFC0
LFC15 LFC14 LFC13 LFC12 LFC11 LFC10 LFC9 LFC8
Command62
(Border control: line setting D)
Command70 (Write address)
Color table
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
CTN1 CTA3 CTA2 CTA1 CTA0
RMB(1)
(2)
0
0
0
0
0
0
TCK
TG0
TB2
TR2
TB1
TR1
TB0
TR0
Command71 (Data write)
Color table
TG2
TG1
No. 7545-10/52
LC74735NW
Command 00 (Main screen write address set command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
—
—
—
—
—
—
1
0
0
0
0
0
0
1
0
1
Command 0 identification code
Main screen write address setting
Sub-identification code: 0
V3
<MSB>
1
0
V2
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Main screen memory line address
(0 to E, hexadecimal)
QVGA mode: 13 lines
WVGA mode: 15 lines
7
6
5
4
3
2
1
0
V1
1
0
V0
<LSB>
1
0
H5
<MSB>
1
0
H4
H3
H2
H1
1
0
Main screen memory character position address
(00 to 27, hexadecimal)
1
0
QVGA mode: 40 characters
1
WVGA mode: 33 characters
0
1
0
H0
<LSB>
1
No. 7545-11/52
LC74735NW
Command 01 (Subscreen write address set command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
0
0
0
0
1
0
0
Command 0 identification code
Subscreen memory write address setting
Sub-identification code: 1
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
0
0
1
0
0
0
0
0
0
1
Subscreen memory line address
(0 to 1, hexadecimal) 2 lines
V0
5
4
3
2
1
—
—
—
—
—
Subscreen memory character address
(0 to 1, hexadecimal) 2 characters
H0
<LSB>
0
No. 7545-12/52
LC74735NW
Command 10 (Main screen display character data write setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
—
—
—
—
—
—
1
0
0
1
0
0
When this command has been issued, the IC
remains in display character data write mode until
the CS pin is set high.
Command 1 identification code
Display character data write setting
Sub-identification code 0
0
1
0
1
RM2
RM1
Mode
End
1
0
RM2
RM1
0
0
1
1
0
1
0
1
(1)(2)(3)(4)
(1)(2)(3)(4)
(3)(4)
Continuous
Continuous
Continuous
Continuous write mode selection
(2)(3)(4)
• Second byte (1)
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Blinking off
Blinking on
Raised
5
4
3
2
1
0
at
Blinking specification
BXS
BXL
BXR
BXU
BXD
Box specification: raised/recessed
Box specification: left side
Box specification: right side
Box specification: upper
Box specification: lower
Recessed
None
Box displayed
None
Box displayed
None
Box displayed
None
Box displayed
• Second byte (2)
Content
Function
DA0 to 7
Register
Notes
State
0
CB3
7
6
5
4
3
2
1
0
[MSB]
1
0
CB2
CB1
Character background color specification
When a character glyph is specified, 1 of 16 colors
may be selected.
1
Character background color specification
0000 to 1111, or 0 to F (hexadecimal)
0
1
0
CB0
[LSB]
1
0
CC3
[MSB]
1
0
CC2
CC1
Character color specification
When a character glyph is specified, 1 of 16 colors
may be selected.
1
Character color specification
0000 to 1111, or 0 to F (hexadecimal)
0
1
0
CC0
<LSB>
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-13/52
LC74735NW
• Second byte (3)
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Color table number 1
Color table number 2
Internal ROM
External ROM
Character
5
4
3
2
1
0
CT0
I/E
Color table selection
ROM selection
M/G
Character/graphic specification
Graphic
C10
[MSB]
C9
C8
Character code specification
• Second byte (4)
Content
Function
DA0 to 7
Register
C7
Notes
State
0
7
6
5
4
3
2
1
0
1
0
C6
Character code
1
Internal ROM: 512 characters
000 to 1FF (hexadecimal)
0 to 511
0
C5
1
0
C4
External ROM: 2048 characters
000 to 7FF (hexadecimal)
0 to 2047
1
Character code specification
0
C3
1
* Transparent character specification
I/E = 0 (Internal ROM)
M/G = 0 (Character)
0
C2
1
Code = 1FF (hexadecimal)
0
C1
1
0
C0
[LSB]
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-14/52
LC74735NW
Command 11 (Subscreen display character data write setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
—
—
—
—
—
—
1
0
0
1
0
1
When this command has been issued, the IC
remains in display character data write mode until
the CS pin is set high.
Command 1 identification code
Display character data write setting
Sub-identification code 1
0
1
0
1
RM2
RM1
Mode
End
1
0
RM2
RM1
0
0
1
1
0
1
0
1
[1][2][3][4]
[1][2][3][4]
[3][4]
Continuous write mode selection
Continuous
Continuous
Continuous
[2][3][4]
• Second byte (1)
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
0
0
0
0
0
0
0
0
• Second byte (2)
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-15/52
LC74735NW
• Second byte (3)
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Color table number 1
Color table number 2
Internal ROM
5
4
3
2
1
0
CT0
I/E
Color table selection
ROM selection
Graphic only
External ROM
Only when transparent is selected
Graphic only
M/G
C10
[MSB]
C9
C8
Character code specification
• Second byte (4)
Content
Function
DA0 to 7
Register
C7
Notes
State
0
7
6
5
4
3
2
1
0
1
0
C6
Character code
1
Internal ROM: 512 characters
000 to 1FF (hexadecimal)
0 to 511
0
C5
1
0
C4
External ROM: 2048 characters
000 to 7FF (hexadecimal)
0 to 2047
1
Character code specification
0
C3
1
* Transparent character specification
I/E = 0 (Internal ROM)
M/G = 0 (Character)
0
C2
1
Code = 1FF (hexadecimal)
0
C1
1
0
C0
[LSB]
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-16/52
LC74735NW
Command 20 (System control setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
1
0
1
0
0
0
0
0
Command 2 identification code
System control settings
Sub-identification code 0
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
1
0
1
0
1
0
1
0
1
0
1
0
Normal operation
Do not use test mode. This bit must always be set
to 0.
7
6
5
4
3
2
TSTMD2
TSTMD1
Q/W2
Test mode 2
Normal operation
Do not use test mode. This bit must always be set
to 0.
Test mode 1
Normal mode
Normal / Independent
QVGA / WVGA
Independent mode Specified by COM24.
QVGA mode
WVGA mode
D/A converter on, 40 characters × 13 lines
D/A converter off, 33 characters × 15 lines
Q/W1
The registers are reset when the CS pin is low.
The reset state is cleared when the CS pin goes high.
SYSRST
CTERS
Reset all registers (All bits set to 0.)
Applications must provide a wait time of about 1ms.
Use DSPOFF to execute this operation.
Erase the color table. (Sets all values to 00.)
Applications must provide a wait time of about 1ms.
Use DSPOFF to execute this operation.
1
0
SRMERS
MRMERS
Erase main RAM. (Sets all values to 00.)
Wallpaper
1
0
1
Applications must provide a wait time of about 1ms.
Use DSPOFF to execute this operation.
Erase sub-RAM. (Sets all values to 00.)
Main screen
No. 7545-17/52
LC74735NW
Command 21 (Display control setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
1
0
1
0
0
0
0
1
Command 2 identification code
Display control
Extended command 1 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
LC oscillator on/off control
State
0
Enables stopping the LC oscillator
Disables stopping the LC oscillator
7
6
5
4
3
2
1
0
LCSOFF
BK1
1
Valid when the display is off.
0
BK1
0
0
BK0
0
1
Blinking period
1/16
Blinking period
1
1/32
1/64
Specified for screen units.
0
BK0
1
0
1
0
Display after the main screen
SBG1
Subscreen display specification
Subscreen display specification
Screen background color
Subscreen (wallpaper)
Main screen
1
Display before the main screen
0
Iterated display (wallpaper)
SBG0
1
Horizontal 2-character x vertical 2-character display (sprite)
0
Display off
Display on
Display off
Display on
Display off
Display on
DSPBG
DSPGS
DSPGM
1
0
1
0
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-18/52
LC74735NW
Command 22 (I/O polarity control setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
1
0
1
0
0
0
1
0
Command 2 identification code
I/O polarity control 1
Extended command 2 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
BLD1
BLD0 BLY output delay
7
6
5
4
3
2
1
0
BLD1
BLD0
BLOP
BLO1
BLO0
CKP
0
0
1
1
0
1
0
1
±0
+1
+2
+3
BLK output delay setting
1
In dot clock units
0
1
0
BLK output: positive polarity
BLK output: negative polarity
BLK output polarity selection
1
0
BLO1 BLO0
BLK output
0
0
1
1
0
1
0
1
Text + character background + wallpaper + screen background
Text + character background + wallpaper
Text + character background
Text
1
BLK output control
0
1
0
Clock input: positive polarity
Clock input: negative polarity
VSYNC input: negative polarity
VSYNC input: positive polarity
HSYNC input: negative polarity
HSYNC input: positive polarity
Clock input polarity selection
VSYNC input polarity selection
HSYNC input polarity selection
1
0
VIP
1
0
HIP
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-19/52
LC74735NW
Command 23 (Screen background color setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
1
0
1
0
0
0
1
1
Command 2 identification code
Screen background color
Extended command 3 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
T1
0
0
T0
0
1
Color table setting
Color table No. 2
Invalid setting
5
4
3
2
1
0
BGCT1
BGCT0
BGC3
BGC2
BGC1
BGC0
Screen background color
Color table setting
1
X
Color table No. 1
Screen background color
0000 to 1111
Screen background color
Selects 1 of 16 values.
0 to F (hexadecimal)
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-20/52
LC74735NW
Command 24 (I/O polarity control setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
1
0
1
0
0
1
0
0
Command 2 identification code
I/O polarity control 2
Extended command 4 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Main screen display area selection
Only valid in independent mode.
COM20 to COM2
*: In WVGA mode: fixed 33-character × 15-line
display
MD1
MD0 Main screen display area
7
6
5
4
3
2
1
0
DSPMD1
DSPMD0
D/ASEL
VBLKON
HBLKON
CKOP
1
0
0
1
0
1
0
40 characters × 13 lines
33 characters × 15 lines
40 characters × 16 lines
0
1
0
On
D/A converter used/unused selection
Only valid in independent mode. COM20 to COM2
1
Off
0
Disabled
Enabled
Disabled
Enabled
VBLK input selection
1
0
HBLK input selection
1
0
Clock output positive polarity
Clock output negative polarity
VBLK input negative polarity
VBLK input positive polarity
HBLK input negative polarity
HBLK input positive polarity
Clock output polarity selection
VBLK input polarity selection
HBLK input polarity selection
1
0
VBP
1
0
HBP
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-21/52
LC74735NW
Command 25 (Output control 3 setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
1
0
1
0
0
1
0
1
Command 2 identification code
Output control
Extended command 5 identification code
• Second byte
Content
Function
DA0 to 7
7
Register
Notes
State
0
1
0
Normal operation
CEHSL
TOKSL
CE pin
CE pin held fixed at the high level
Normal mode
Transmissive mode
Transmissive mode specification
6
1
The color specified at address 0 in color table No. 1 is displayed
in the transmissive state.
0
1
0
1
0
1
0
Falling edge detection
Rising edge detection
Output off state (always low)
Normal output
5
4
3
VIPSL
OTMD2
OTMD1
Selects the detection polarity for the VSYNC signal.
CLKOUT pin (pin 18)
Output control
OTMD2 OTMD1 OTMD0
Output
0
0
0
0
0
0
1
1
0
1
0
1
Normal
A0 to 17 output selection
RGB No. 1
RGB No. 2
High-impedance state
2
1
0
OTMD0
QRM1
QRM0
1
0
1
0
QRM1
QRM0
ROM selection
ROM1
0
0
1
1
0
1
0
1
ROM selection when character output is specified
in QVGA mode
ROM2
ROM3
ROM4
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
• When RGB No. 1 or RGB No. 2 is selected:
The A17 to 9 output is set to the RD2 to BD0 three-value output. (Supported by connecting external resistors.)
* It will not be possible to use external ROM in this case. (Only internal ROM can be used.)
No. 1: RGB = 000 = Black only. Here the output will go to the high-impedance state giving the middle level due to the external resistor.
For areas other than the display area, the output will be at the low level.
No. 2: When any individual color is zero, the output will go to the high-impedance state giving the middle level due to the external resistor.
For areas other than the display area, the output will be at the low level.
No. 7545-22/52
LC74735NW
Command 30 (Main screen: vertical display start position setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
0
1
1
0
0
0
0
Command 3 identification code
Main screen: vertical display start position setting
Extended command 0 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
VPM7
(MSB)
7
6
5
4
3
2
1
0
1
The vertical display start position, VSM, is given by:
7
0
VSM = 1H × (∑ 2 n V P M n )
VPM6
VPM5
VPM4
VPM3
VPM2
VPM1
n=0
1
0
Main screen
HSYNC
1
The vertical display start position is specified by the
8 bits VPM7 to 0.
0
1
VSM
The weight of the LSB is 1H in QVGA mode, and
the weight of the LSB is 2H in WVGA mode
0
1
HSM
Main screen display area
0
This setting applies in screen units.
1
0
1
0
VPM0
(LSB)
1
No. 7545-23/52
LC74735NW
Command 31 (Main screen: horizontal display start position setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
0
1
1
0
0
1
0
1
Command 3 identification code
Main screen: horizontal display start position setting
Extended command 1 identification code
HPM8
(MSB)
0
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
5
4
3
2
1
0
HPM7
HPM6
HPM5
HPM4
HPM3
HPM2
HPM1
1
0
The horizontal display start position, HSM, is given by:
1
8
HSM = 1Tc × ( ∑ 2n H P M n ) + α
0
n=0
Main screen
1
α = 57 Tc
The horizontal display start position is specified by
the 9 bits HPM8:0.
0
Tc: The input clock frequency in operating mode.
1
The weight of the LSB is 1TC in QVGA mode, and
the weight of the LSB is 2TC in WVGA mode
0
1
0
• Setting disable range
This setting applies in screen units.
1
QVGA : 00 to 07 HEX
WVGA : 00 to 07 HEX
0
1
0
HPM0
(LSB)
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-24/52
LC74735NW
Command 32 (Subscreen: vertical display start position setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
0
1
1
0
1
0
0
Command 3 identification code
Subscreen: vertical display start position setting
Extended command 2 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
VPS7
7
6
5
4
3
2
1
0
(MSB)
1
The vertical display start position, VSS, is given by:
7
0
VSS = 1H × (∑ 2n V P S n )
VPS6
VPS5
VPS4
VPS3
VPS2
VPS1
n=0
1
0
Subscreen (wallpaper)
HSYNC
1
The vertical display start position is specified by the
8 bits VPS7 to 0.
0
VSS
1
The weight of the LSB is 1H in QVGA mode, and
the weight of the LSB is 2H in WVGA mode
0
1
HSS
Subscreen display area
0
This setting applies in screen units.
1
0
1
0
VPS0
(LSB)
1
No. 7545-25/52
LC74735NW
Command 33 (Subscreen: horizontal display start position setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
—
—
—
—
—
—
1
0
1
1
0
1
1
0
1
Command 3 identification code
Subscreen: horizontal display start position setting
Extended command 3 identification code
HPS8
(MSB)
0
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
5
4
3
2
1
0
HPS7
HPS6
HPS5
HPS4
HPS3
HPS2
HPS1
1
0
The horizontal display start position, HSS, is given by:
1
8
HSS = 1Tc × ( ∑ 2n H P S n ) + α
0
n=0
Subscreen (wallpaper)
1
α = 14 Tc
The horizontal display start position is specified by
the 9 bits HPS8 to 0.
0
Tc: The input clock frequency in operating mode.
1
The weight of the LSB is 1TC in QVGA mode, and
the weight of the LSB is 2TC in WVGA mode
0
1
0
This setting applies in screen units.
1
• Setting disable range
0
QVGA : 00 to 2F HEX
WVGA : 00 to 17 HEX
1
0
HPS0
(LSB)
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-26/52
LC74735NW
Command 34 (Screen background color: vertical display start position setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
0
1
1
1
0
0
0
Command 3 identification code
Screen background color: vertical display start position setting
Extended command 4 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
VPG7
(MSB)
7
6
5
4
3
2
1
0
1
The vertical display start position, VSG, is given by:
7
0
VSG = 1H × ( ∑ 2 nV P G n )
VPG6
VPG5
VPG4
VPG3
VPG2
VPG1
n=0
1
0
Screen background color
HSYNC
1
The vertical display start position is specified by
the 8 bits VPG7 to 0.
0
VSG
1
The weight of the LSB is 1H in QVGA mode, and
the weight of the LSB is 2H in WVGA mode
0
1
Screen background
color display area
HSG
0
This setting applies in screen units.
1
0
1
0
VPG0
(LSB)
1
No. 7545-27/52
LC74735NW
Command 35 (Screen background color: horizontal display start position setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
—
—
—
—
—
—
1
0
1
1
1
0
1
0
1
Command 3 identification code
Screen background color: horizontal display start position setting
Extended command 5 identification code
HPS8
(MSB)
0
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
7
6
5
4
3
2
1
0
HPG7
HPG6
HPG5
HPG4
HPG3
HPG2
HPG1
1
0
The horizontal display start position, HSG, is given by:
1
8
HSG = 1Tc × (∑ 2 n H P G n )
0
n=0
1
Screen background color
Tc: The input clock frequency in operating mode.
0
The horizontal display start position is specified by
the 9 bits HPG8 to 0.
1
The weight of the LSB is 1TC in QVGA mode, and
the weight of the LSB is 2TC in WVGA mode
This setting applies in screen units.
0
1
0
1
0
1
0
HPG0
(LSB)
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-28/52
LC74735NW
Command 40 (Character size control setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
1
1
0
0
0
0
0
0
Command 4 identification code
Display character data write settings
Extended command 0 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
—
—
—
—
0
0
0
0
0
1
0
3
2
1
0
SZV1
SZV0
SZH1
SZH0
SZV1
SZV0
Character size
0
0
1
1
0
1
0
1
1×
2×
3×
4×
Specifies the character size in the vertical direction.
This setting applies in line units.
1
0
1
0
SZH1
SZH0
Character size
Specifies the character size in the horizontal
direction.
This setting applies in line units.
0
0
1
1
0
1
0
1
1×
2×
3×
4×
1
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-29/52
LC74735NW
Command 41 (Character size line U control setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
0
0
0
1
0
0
Command 4 identification code
Character size line U control
Extended command 1 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Do not set for line 8.
Set for line 8.
7
6
5
4
3
2
1
0
LSZ7
LSZ6
LSZ5
LSZ4
LSZ3
LSZ2
LSZ1
LSZ0
1
0
Do not set for line 7.
Set for line 7.
1
0
Do not set for line 6.
Set for line 6.
1
0
Do not set for line 5.
Set for line 5.
1
Character size line setting control
Upper lines
0
Do not set for line 4.
Set for line 4.
1
0
Do not set for line 3.
Set for line 3.
1
0
Do not set for line 2.
Set for line 2.
1
0
Do not set for line 1.
Set for line 1.
1
No. 7545-30/52
LC74735NW
Command 42 (Character size line D control setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
0
0
1
0
0
0
Command 4 identification code
Character size line D control
Extended command 2 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Do not set for line 16.
Set for line 16.
7
6
5
4
3
2
1
0
LSZ15
LSZ14
LSZ13
LSZ12
LSZ11
LSZ10
LSZ9
1
0
Do not set for line 15.
Set for line 15.
1
0
Do not set for line 14.
Set for line 14.
1
0
Do not set for line 13.
Set for line 13.
1
Character size line setting control
Lower lines
0
Do not set for line 12.
Set for line 12.
1
0
Do not set for line 11.
Set for line 11.
1
0
Do not set for line 10.
Set for line 10.
1
0
Do not set for line 9.
Set for line 9.
LSZ8
1
No. 7545-31/52
LC74735NW
Command 50 (Box control: U setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
0
1
0
0
0
0
Command 5 identification code
Box control U settings
Extended command 0 identification code
• Second byte
Content
Function
DA0 to 7
7
Register
Notes
Box display: upper side
State
0
1
0
1
0
Box display: upper side is 1 dot.
Box display: upper side is 2 dots.
Box display: left side is 1 dot.
Box display: left side is 2 dots.
BXUW
Dot width. This setting applies in line units.
Box display: left side
Dot width. This setting applies in line units.
6
5
BXLW
—
Box display: upper side
Color table specification
This setting applies in line units.
0
1
Color table No. 1
Color table No. 2
4
BXUCT0
0
1
0
1
0
1
0
1
3
2
1
0
BXUC3
BXUC2
BXUC1
BXUC0
Box display: upper side
Color specification
This setting applies in line units.
Box display: upper side color specification
0000 to 1111
0 to F (hexadecimal)
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-32/52
LC74735NW
Command 51 (Box control: D setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
0
1
0
1
0
0
Command 5 identification code
Box control D settings
Extended command 1 identification code
• Second byte
Content
Function
DA0 to 7
7
Register
Notes
Box display: lower side
State
0
1
0
1
0
Box display: lower side is 1 dot.
Box display: lower side is 2 dots.
Box display: right side is 1 dot.
Box display: right side is 2 dots.
BXDW
Dot width. This setting applies in line units.
Box display: right side
Dot width. This setting applies in line units.
6
5
BXRW
—
Box display: lower side
Color table specification
This setting applies in line units.
0
1
Color table No. 1
Color table No. 2
4
BXDCT0
0
1
0
1
0
1
0
1
3
2
1
0
BXDC3
BXDC2
BXDC1
BXDC0
Box display: lower side
Color specification
This setting applies in line units.
Box display: lower side color specification
0000 to 1111
0 to F (hexadecimal)
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-33/52
LC74735NW
Command 52 (Box control: U line setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
0
1
1
0
0
0
Command 5 identification code
Box control U line setting
Extended command 2 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Do not set for line 8.
Set for line 8.
7
6
5
4
3
2
1
0
LBX7
LBX6
LBX5
LBX4
LBX3
LBX2
LBX1
LBX0
1
0
Do not set for line 7.
Set for line 7.
1
0
Do not set for line 6.
Set for line 6.
1
0
Do not set for line 5.
Set for line 5.
1
Box control line setting control
Upper lines
0
Do not set for line 4.
Set for line 4.
1
0
Do not set for line 3.
Set for line 3.
1
0
Do not set for line 2.
Set for line 2.
1
0
Do not set for line 1.
Set for line 1.
1
No. 7545-34/52
LC74735NW
Command 53 (Box control: D line control setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
0
0
1
1
0
0
Command 4 identification code
Box control D line setting
Extended command 3 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Do not set for line 16.
Set for line 16.
7
6
5
4
3
2
1
0
LBX15
LBX14
LBX13
LBX12
LBX11
LBX10
LBX9
1
0
Do not set for line 15.
Set for line 15.
1
0
Do not set for line 14.
Set for line 14.
1
0
Do not set for line 13.
Set for line 13.
1
Box control line setting control
Lower lines
0
Do not set for line 12.
Set for line 12.
1
0
Do not set for line 11.
Set for line 11.
1
0
Do not set for line 10.
Set for line 10.
1
0
Do not set for line 9.
Set for line 9.
LBX8
1
No. 7545-35/52
LC74735NW
Command 60 (Border control setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
—
—
—
—
—
—
1
1
1
0
0
0
0
1
0
1
Command 6 identification code
Border control setting
Extended command 0 identification code
BLK1
BLK0
Border mode specification
Normal display
Border
Shadow 1 (lower side)
Shadow 2 (lower and right sides)
1
0
BLK1
BLK0
0
0
1
1
0
1
0
1
Border mode specification
This setting applies in line units.
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
—
—
—
0
0
0
Border display
Color table specification
This setting applies in line units.
0
1
Color table No. 1
Color table No. 2
4
EGCT0
0
1
0
1
0
1
0
1
3
2
1
0
EGC3
EGC2
EGC1
EGC0
Border display
color specification
This setting applies in line units.
Border display: color specification
0000 to 1111
0 to F (hexadecimal)
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
No. 7545-36/52
LC74735NW
Command 61 (Border control U line setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
1
0
0
1
0
0
Command 6 identification code
Border control U line setting
Extended command 1 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Do not set for line 8.
Set for line 8.
7
6
5
4
3
2
1
0
LFC7
LFC6
LFC5
LFC4
LFC3
LFC2
LFC1
LFC0
1
0
Do not set for line 7.
Set for line 7.
1
0
Do not set for line 6.
Set for line 6.
1
0
Do not set for line 5.
Set for line 5.
1
Border control line settings control
Upper lines
0
Do not set for line 4.
Set for line 4.
1
0
Do not set for line 3.
Set for line 3.
1
0
Do not set for line 2.
Set for line 2.
1
0
Do not set for line 1.
Set for line 1.
1
No. 7545-37/52
LC74735NW
Command 62 (Border control D line setting command)
• First byte
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
1
0
1
0
0
0
Command 6 identification code
Border control D line setting
Extended command 2 identification code
• Second byte
Content
Function
DA0 to 7
Register
Notes
State
0
Do not set for line 16.
Set for line 16.
7
6
5
4
3
2
1
0
LFC15
LFC14
LFC13
LFC12
LFC11
LFC10
LFC9
1
0
Do not set for line 15.
Set for line 15.
1
0
Do not set for line 14.
Set for line 14.
1
0
Do not set for line 13.
Set for line 13.
1
Border control line settings control
Lower lines
0
Do not set for line 12.
Set for line 12.
1
0
Do not set for line 11.
Set for line 11.
1
0
Do not set for line 10.
Set for line 10.
1
0
Do not set for line 9.
Set for line 9.
LFC8
1
No. 7545-38/52
LC74735NW
Command 70 (Color table write address setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
1
1
1
1
0
0
0
0
Command 7 identification code
Color table write address setting
Sub-identifier code 0
• Second byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
—
—
—
0
1
0
1
0
1
0
1
0
1
Color table No. 1 selected
Color table No. 2 selected
Color table selection
No. 1 or No. 2
4
3
2
1
0
CTN1
CTA3
<MSB>
CTA2
CTA1
Color table address
0 to 15
Addresses of the color tables
0 to F (hexadecimal) 16 values
CTA0
<LSB>
No. 7545-39/52
LC74735NW
Command 71 (Color table data write setting command)
• First byte
Content
DA0 to 7
Register
Notes
State
Function
7
6
5
4
3
2
1
—
—
—
—
—
—
—
1
1
1
1
0
1
0
When this command has been issued, the IC
remains in display character data write mode until
the CS pin is set high.
Command 7 identification code
Display character data write setting
Sub-identifier code 1
0
1
RM3
0
1
Mode
End
Continuous
Continuous write mode selection
0
RM3
[1][2]
[1][2]
• Second byte (1)
Content
Function
DA0 to 7
Register
Notes
State
7
6
5
4
—
—
—
—
0
0
0
0
0
1
0
1
0
1
0
1
Color
3
2
1
0
TOK
TB2
TB1
TB0
Transparent (BLK output: low)
Color table
B output
000 to 111
Color table setting B
0 to 7 (hexadecimal)
• Second byte (2)
Content
DA0 to 7
Register
Notes
State
Function
7
6
—
—
0
0
0
1
0
1
0
1
0
1
0
1
0
1
5
4
3
2
1
0
TG2
TG1
TG0
TR2
TR1
TR0
Color table
G output
Color table setting G
000 to 111
0 to 7 (hexadecimal)
Color table
R output
Color table setting R
000 to 111
0 to 7 (hexadecimal)
*: This register is set to the all bits zero state when the IC is reset by the RST pin.
When transparent is selected, the BLK output is set to the low level. (Transparent state)
The RGB outputs are values from the color table.
The transparent specification is best for color table 1, address 0000.
Since the data is set to all zeros by a RAM clear operation,
the RGB output will be 000 (black) and the BLK output will be 1.
Transparent is specified by setting the TOK bit to 1. (The BLK output will go to the low level.)
No. 7545-40/52
LC74735NW
Display Structure
The display screen consists of a 40-character × 15-line grid.
QVGA mode (12 × 18 dot characters)
40-character × 13-line QVGA panel (480 × 234)
WVGA mode (12 × 16 dot characters)
33-character × 15-line WVGA panel (800 × 480)
Up to a maximum of 600 characters can be displayed.
If the character size is increased, the number of characters that can be displayed will decrease to be fewer than 600
characters.
Display memory is addressed by specifying a line address (0 to 14 (decimal) and a character position address (0 to 39
(decimal)).
40 characters
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
0
1
2
3
4
5
6
7
15 rows
8
9
A
B
C
D
E HEX
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27HEX
Display Structure (Display memory address)
No. 7545-41/52
LC74735NW
Sample Application Circuits
• QVGA mode (analog output)
3.3VDC
+
GND GND
60
59
58
57
1
2
V
1
A16
A17
CE
SS
GND
OSCin
OSCout
CTRL1
SCLK
SIN
3
4
GND
OE
5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
3
SCLK
SIN
DD
6
V
3
SS
GND
7
CS
D0
D1
D2
D3
D4
D5
D6
D7
1
CS
8
V
1
DD
9
VSYNC
HSYNC
VSYNC
VBLK
10
11
12
13
14
15
16
LC74735NW
HSYNC
HBLK
TEST1
TEST2
RST
V
DD
+
V
V
1
1
V
1
SS
SS
GND
17
18
D8
D9
DD
GND
CLKOUT
19
20
V
V
1
1
D10
D11
SS
DD
GND
+
+
GND
GND_A
GND_A
+
+
GND_A
GND_A
+
GND_A
+
+
GND_A GND_A
TR3
A1392
GND_A
No. 7545-42/52
LC74735NW
• WVGA mode (digital output)
3.3VDC
CLK
+
GND GND
60
59
58
57
1
V
1
A16
A17
CE
SS
2
3
OSCin
OSCout
CTRL1
SCLK
SIN
4
5
OE
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
3
SCLK
SIN
DD
6
V
3
SS
GND
7
CS
D0
D1
D2
D3
D4
D5
D6
D7
1
CS
8
V
1
DD
9
VSYNC
VBLK
VSYNC
HSYNC
10
11
12
13
14
15
16
LC74735NW
HSYNC
HBLK
TEST1
TEST2
RST
V
DD
+
V
V
1
1
V
1
SS
SS
17
18
GND
D8
D9
DD
GND
CLKOUT
19
20
V
1
D10
D11
SS
V
1
DD
GND
GND
GND
GND_A
No. 7545-43/52
LC74735NW
Operational Description
Command transfer method
Overview
• Commands are transferred in 8-bit units, LSB first.
Always send a first byte and a second byte (16 bits).
• Command 10 (Main RAM write)
Command 11 (Wallpaper write)
Command 71 (Color table write)
When these commands specify continuous mode (RM2, 1 RM3), the IC is locked in continuous write mode.
(Continuous write mode is cleared by setting the CS pin high.)
Writing Data to VRAM
• Write start address specification
Use command 00 to set the write start address.
V3:0: Vertical direction, H5:0: Horizontal direction
• Data write
Continuous write mode differs depending on the write mode specification. (RM1, RM2)
1 Normal (RM2 = 0, RM1 = 0: initial state) *Continuous mode not used*
-- COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 command wait state --
2 Write continuous (RM2 = 0, RM1 = 1): Mode 2
COM10-1 10-2-1 10-2-2 10-2-3 10-2-4
3 Write continuous (RM2 = 1, RM1 = 0): Mode 3
COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-3 10-2-4
4 Write continuous (RM2 = 1, RM1 = 1): Mode 4
COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-2 10-2-3 10-2-4
*: In modes 2, 3, and 4, the IC remains locked in continuous write mode until the CS pin is set high.
• The write address is automatically incremented.
• The write address is retained unless the IC is reset or a new write address is issued.
No. 7545-44/52
LC74735NW
Color Table write
• Write start address specification
Use command 70 to set the color table write start address.
CTN1: Color table specification (No.1, No.2), CTA3 to 0: Address specification
No.1
No.2
R
G
B
R
G
B
0000
0001
0010
XXX
XXX
XXX
0000
0001
0010
XXX
XXX
XXX
Address
1110
1111
1110
1111
• Data write
Continuous write mode differs depending on the write mode specification. (RM3)
1 Normal (RM3 = 0: initial state) *Continuous mode not used*
-- COM71-1 71-2-1 71-2-2 command wait state ---
2 Write continuous (RM3 = 1) mode
COM71-1 71-2-1 71-2-2
*: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high.
• The write address is automatically incremented.
• The write address is retained unless the IC is reset or a new write address is issued.
No. 7545-45/52
LC74735NW
Display format
Color Specification Related Items
• When a character is specified
Specify color with the character color (character area) and character background color (outside the character area)
Character color: One of 16 colors
Character background color: One of 16 colors
Color tables: Table No. 1 or No. 2 specified by CT1 to CT0. (COM1-2-3: VRAM)
→ One of 32 types
Character background color
Character color
Specified by CB0 to CB3: One of 16 colors
Specified by CC0 to CC3: One of 16 colors
(COM1-2-2: VRAM)
(COM1-2-2: VRAM)
• When a graphic is specified
Specify color is in dot units (12 × 18 or 12 × 16)
One of 16 colors (FROM)
Color tables: Table No. 1 or No. 2 specified by CT1 to CT0. (COM1-2-3: VRAM)
→ One of 32 types
Specified by FROM: One of 16 types
No. 7545-46/52
LC74735NW
Display Control Related Items
• Blinking: In character units
Normal at1 = 0 (COM1-2-1: VRAM)
Blinking at1 = 1
Display alternates between normal and transparent with the blinking period. (COM21-2: BK1, 0)
• Border display: Only valid for font specified characters
Border color: One of 16 colors (COM60-2 EGC3 to 0)
Color table specification (COM60-2 EGCT0)
→ One of 32 types
Border mode control (COM60-1 BLK1, 0)
Border
Shadow 1: lower
Shadow 2: lower + right
• Character size: Specified in line units
The character size is specified as 1x to 4x independently for the vertical and horizontal directions.
(COM40-2)
No. 7545-47/52
LC74735NW
Box Display (raised/recessed)
Raised
12 dots
Recessed
18 dots
or
16 dots
• Raised/recessed specification: In character units (COM10-2-1 BXS)
• Left side - displayed/undisplayed specification: in character units (COM10-2-1 BXL)
• Right side - displayed/undisplayed specification: in character units (COM10-2-1 BXR)
• Upper side - displayed/undisplayed specification: in character units (COM10-2-1 BXU)
• Lower side - displayed/undisplayed specification: in character units (COM10-2-1 BXD)
• Color specification: In line units
COM50 (Upper side)
COM51 (Lower side)
BXUC3:0: One of 16 colors
BXDC3:0: One of 16 colors
Color table specification
BXUCT0
BXDCT0
’ One of 32 types
Dot width specification: 1 or 2 dots
Each of left, right, upper, and lower can be specified independently. (BXLW BXRW BXUW BXDW)
No. 7545-48/52
LC74735NW
Screen Structure
Screen background color
Wallpaper display screen
Main screen
• QVGA mode (12 × 18 dot characters)
40-character × 13-line QVGA panel
• WVGA mode (12 × 16 dot characters)
33-character × 15-line WVGA panel
• For each screen: Display on/off (transparent) can be specified independently.
• For each screen: The display start position can be specified independently.
The wallpaper display screen and the main screen require xxxx clocks before the horizontal start position is reached.
No. 7545-49/52
LC74735NW
Display Format
• QVGA
Character specification
12 dots
Graphic
12 dots
18H
• WVGA
Character specification
24 dots
Graphic
24 dots
Each dot is 2 × 2 pixels
(A 12 × 16 structure
magnified 2× in both
the horizontal and
vertical directions)
32H
ROM structure
Internal ROM (512 characters)
• Character font
QVGA: 12 × 18-dot structure
WVGA: 24 × 32-dot structure, i.e. 12 × 16 times 4
• Graphics
CQVGA: 12 × 18-dot structure
WVGA: 12 × 16-dot structure, i.e. displayed magnified 2× in both the horizontal and vertical directions.
Note that the contents of ROM differ for QVGA and WVGA.
(That is, different ROMs for QVGA and WVGA must be created.)
No. 7545-50/52
LC74735NW
External ROM (2048 characters)
• Conditions
Use a 16-bit 4M ROM with an access time less than 3 times the dot clock period
Example: DCLK = 50 MHz = 20 ns period × 3 = under 60 ns
DCLK = 10 MHz = 100 ns period × 3 = under 300 ns
• ROM map
• Address
A1 to A0
• Data
D15 to D12, D11 to D0
Unused Used
00
12 dots
01
[2]
10
[3]
11
[4]
A6 to A2
QVGA mode
18 dots
WVGA mode
16 dots
[1]
A17 to A7 (10 bits) = 2048 characters = character codes
• Display appearance
QVGA: 1 character = 12 × 18 dots
Character font: [1]
Graphics: [1] + [2] + [3] + [4]
WVGA: 1 character = 12 × 16 dots
Character font: [1] [2]
[3] [4]
Graphics: ([1] + [2] + [3] + [4]) displayed magnified 2× in both the horizontal and vertical directions.
12
[1]
12
[2]
12
12
[1]+[2]
16
16
16
16
+[3]+[4]
× 2
[3]
[4]
No. 7545-51/52
LC74735NW
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of October, 2003. Specifications and information herein are subject
to change without notice.
PS No. 7545-52/52
相关型号：
©2020 ICPDF网 联系我们和版权申明