LC75281E [SANYO]
Parametric Equalizer System; 参数均衡器系统
| 型号： | LC75281E |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Parametric Equalizer System |
| 文件： | 总10页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN5913
CMOS IC
LC75281E
Parametric Equalizer System
Overview
Package Dimensions
unit: mm
The LC75281E is a four-band stereo parametric equalizer.
A parametric equalizer is a fully general equalizer that
allows all three parameters that define an equalizer’s
characteristics, i.e., the center frequency, gain, and Q, to
be set independently.
3159-QFP64E
[LC75281E]
Functions
• Four-band (low, low mid, high mid, and high) left and
right channels parametric equalizer
• For each band:
Center frequency: 11 positions
Gain: 13 positions in ±2dB steps
Q: Variable over 8 positions
• The center frequency, gain, and Q control settings are
set using serial data input in the CCB format.
Features
SANYO: QFP64E (QIP64E)
• A parametric equalizer with the following features can
be implemented with just two ICs: this IC and a
microcontroller.
• The center frequency, gain, and Q can be controlled by a
single operation.
• Memory recall by a single operation can be implement-
ed using preset values.
• Either shelving or peaking characteristics can be
selected for the low band.
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
101698RM (OT) No. 5913-1/10
LC75281E
Pin Assignment
No. 5913-2/10
LC75281E
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
10.5
Unit
V
VDD max
VIN1 max LIN, RIN
VIN2 max CL, CE, DI
0 to VDD
0 to VDD
V
Maximum input voltage
V
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Ta ≤ 85°C
300
mW
°C
°C
Topr
Tstg
–40 to +85
–50 to +125
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V
SS
Ratings
Parameter
Symbol
Conditions
Unit
min
6.0
typ
max
9.0
Supply voltage
VDD
VIH
V
V
High-level input voltage
Low-level input voltage
Input voltage range
Load resistance
Input pulse width
Setup time
CL, CE, DI
CL, CE, DI
LIN, RIN
4.0
VSS
0
VDD
1.0
VIL
V
VIN
VDD
V
RL
LOUT, ROUT, MIXOUT
1
kΩ
µs
µs
µs
kHz
tøw
CL
1
tsetup
thold
fopg
CL, CE, DI
CL, CE, DI
CL
1
Hold time
1
Operating frequency
500
Electrical Characteristics at Ta = 25°C, f = 1 kHz, V = 8 V, V = 0 V
DD
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Current drain
IDD
VO
VDD
36
50
mA
Vrms
%
Output voltage
LOUT, ROUT: THD = 1%
LOUT, ROUT: Vo = Flat, VIN = 0 dBV
LOUT, ROUT: Vo = Boost,
All bands +2 dB, VIN = –15 dBV
LOUT, ROUT: Vo = Flat,
Rg = 1 kΩ, IHF-A filters
2.2
THD1
0.005
0.01
1
Total harmonic distortion
THD2
VN1
0.1
7
%
µs
µs
15
LOUT, ROUT: Vo = Flat,
Rg = 1 kΩ, DIN filters
VN2
13
LOUT, ROUT, Rg = 1 kΩ, f0 = f1, Q = Q1
IHF-A filter, all bands at full boost, with the external
constants the same as those for the center
frequency (example 1)
Output noise voltage
VN3
VN4
58
µs
µs
LOUT, ROUT, Rg = 1 kΩ, f0 = f1, Q = Q1
IHF-A filters, all bands at full cut, with the external
constants the same as those for the center frequency
(example 1)
23
80
Crosstalk between inputs
High-level input current
Low-level input current
CT
IIH
IIL
VIN = 1 Vrms, f = 1 kHz
CL, DI, CE, VIN = 9 V
CL, DI, CE, VIN = 0 V
60
–1
dB
µA
µA
1
All bands
G = +12 dB, Q: Setting switched from Q1 to Q2
With the external constants the same as those for the
center frequency (example 1) shown on page 7.
DC variation
VDC
–10
+10
mV
Pin Functions
Pin No.
Pin
Function
64
1
LLC2
LLC1
Left channel low band control block.
External capacitor connections.
2
LLC4
3
LLC3
4
LLC5
5
LLMC2
LLMC1
LLMC4
LLMC3
6
Left channel low mid band control block.
External capacitor connections.
7
8
Continued on next page.
No. 5913-3/10
LC75281E
Continued from preceding page.
Pin No.
Pin
Function
10
11
LHMC2
LHMC1
LHMC4
LHMC3
LHMC5
LHC2
Left channel high mid band control block.
12
External capacitor connections.
13
14
15
16
LHC1
Left channel high band control block.
External capacitor connections.
17
LHC4
18
LHC3
19
LHC5
20, 24, 29
56, 57
NC
Unused pins. These pins must be either left open or connected to VSS
.
Internal operational amplifier reference voltage generator outputs.
23
Vref
Several capacitors with values of about 10 µF must be connected with this pin to reduce ripple.
Power supply.
21
22
VSS
VDD
These pins must be connected to the stipulated power supply.
Chip enable input. Data is written to the internal latch and the analog switches operate when this pin
changes from high to low. Data transfer is enabled when this pin is high.
27
CE
26
25
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
58
59
61
62
55
54
52
51
60
53
63
50
DI
Serial data and clock inputs for IC control
CL
RLC2
RLC1
Right channel low band control block.
External capacitor connections.
RLC4
RLC3
RLC5
RLMC2
RLMC1
RLMC4
RLMC3
RLMC5
RHMC2
RHMC1
RHMC4
RHMC3
RHMC5
RHC2
Right channel low mid band control block.
External capacitor connections.
Right channel high mid band control block.
External capacitor connections.
RHC1
Right channel high band control block.
External capacitor connections.
RHC4
RHC3
RHC5
LCUT2
LCUT1
LBOOS2
LBOOS1
RCUT2
RCUT1
RBOOS2
RBOOS1
LIN
Internal filter DC offset voltage exclusion capacitor connections.
Capacitors of about 10 µF must be connected between pins 61 and 62, and between pins 63 and 64.
(These are for the left channel block.)
Internal filter DC offset voltage exclusion capacitor connections.
Capacitors of about 10 µF must be connected between pins 51 and 52, and between pins 49 and 50.
(These are for the right channel block.)
Left channel audio signal input (Must be driven with a low load capacitance.)
Right channel audio signal input (Must be driven with a low load capacitance.)
Left channel audio signal output (Must be received with a low load capacitance.)
Right channel audio signal output (Must be received with a low load capacitance.)
IC test pin.
RIN
LOUT
ROUT
28
TEST
This pin must be left open when not used for IC test.
No. 5913-4/10
LC75281E
Block Diagram
Low band
Low mid band
High mid band
High band
The blocks enclosed in dotted
lines are identical.
No. 5913-5/10
LC75281E
• Center frequency (fo)
Band
Low
f1
f2
f3
50
f4
63
f5
80
f6
f7
f8
160
800
3.15 k
8 k
f9
f10
250
f11
315
External capacitor (µF)
0.047
31.5
160
630
1.6 k
40
100
500
2 k
125
200
1 k
4 k
10 k
Low mid
High mid
High
200
800
2 k
250
1 k
315
1.25 k
3.15 k
400
1.6 k
4 k
630
1.25 k
5 k
1.6 k
6.3 k
16 k
0.0094
2.5 k
6.3 k
0.00235
2.5 k
5 k
12.5 k
0.0094
External capacitor calculations
Figure a shows the LC75281E internal f0 control circuit. The center frequency f0 can be set to one of 11 frequencies in
1/3 octave steps by switching the resistors in the figure.
Figure a
The value of the external capacitor C is determined by substituting the desired center frequency in the following formula.
1
Rb//Rf
Ra + (Rb//Rf)
Cf =
•
2π Rf fo max
fo max: Corresponds to 315 Hz in the low band row in the preceding table.
Equivalent Circuit for Cf calculation
• Gain: 13 positions in 2-dB steps
• Q
Q1
0.404
3
Q2
0.667
2
Q3
1.41
1
Q4
2.15
2/3
Q5
2.87
1/2
Q6
4.32
1/3
Q7
5.76
1/4
Q8
8.65
1/6
Q
OCT
No. 5913-6/10
LC75281E
Data Input Procedure
The LC75281E is controlled by inputting the stipulated serial data to the CE, CL, and DI pins. The data consists of
28 bits, of which 8 bits are the address and 20 bits are the data.
≤
Address code
Q setting
*
Normal/2× control
Channel selection
Normal
2×
Left and right
Band selection and
peaking/shelving selection
Center frequency setting
Gain setting
: Low (Peaking)
: Low mid (Peaking)
: High mid (Peaking)
: Low (Shelving)
Note *: The 2× command doubles the center frequency of all bands. When setting this bit to 1, applications must either enter the band data for one of the
bands in bits D1 to D19, or must set both bits D4 and D5 to 0, in which case all other bits are ignored.
No. 5913-7/10
LC75281E
Sample Application Circuit
No. 5913-8/10
LC75281E
Gain Characteristics (Peaking)
Gain Characteristics (Shelving)
Low band
Low band
Vin = –20 dB V
External capacitor: Cf = 0.047 µF
Settings: f0 = f11
Q = Q1
Vin = –20 dB V
External capacitor: Cf = 0.047 µF
Settings: f0 = f11
Q = Q1
Frequency, f — Hz
Frequency, f — Hz
Q Characteristics (Peaking)
Q Characteristics (Shelving) - 1
High mid band
Vin = –20 dB V
External capacitor: Cf = 0.0022 µF
Settings: f0 = f17
G = ±12 dB
Low band
Vin = –20 dB V
External capacitor:
Cf = 0.047 µF
Settings: f0 = f11
Q = Q1
Frequency, f — Hz
Frequency, f — Hz
Q Characteristics (Shelving) - 2
Center Frequency Characteristics (Peaking)
Low mid band
Vin = –20 dB V
External capacitor: Cf = 0.01 µF
Settings: G = ±12 dB
Q = Q4
Low band
Vin = –20 dB V
External capacitor:
Cf = 0.047 µF
Settings: f0 = f11
G = –12 dB
Frequency, f — Hz
Frequency, f — Hz
Center Frequency Characteristics (Shelving)
Low band
Vin = –20 dB V
External capacitor: Cf = 0.047 µF
Settings: G = ±12 dB
Q = Q1
Frequency, f — Hz
No. 5913-9/10
LC75281E
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any and all SANYO products described or contained herein fall under strategic
products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of
Japan, such products must not be exported without obtaining export license from the Ministry of
International Trade and Industry in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject
to change without notice.
No. 5913-10/10
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