LC75804 [SANYO]
1/3, 1/4 Duty LCD Display Drivers with Key Input Function; 用按键输入功能1/3 ， 1/4占空比LCD显示驱动器
| 型号： | LC75804 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/3, 1/4 Duty LCD Display Drivers with Key Input Function |
| 文件： | 总37页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN6266A
CMOS IC
LC75804E, LC75804W
1/3, 1/4 Duty LCD Display Drivers
with Key Input Function
Overview
Package Dimensions
unit: mm
The LC75804E and LC75804W are 1/3 duty and 1/4 duty
LCD display drivers that can directly drive up to 300
segments and can control up to eight general-purpose
output ports. These products also incorporate a key scan
circuit that accepts input from up to 30 keys to reduce
printed circuit board wiring.
3151A-QFP100E
[LC75804E]
23.2
20.0
80
51
81
50
31
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
100
1
30
• 1/3 duty and 1/4 duty drive schemes can be controlled
from serial data.
0.65
0.3
0.15
(0.58)
• 1/2 bias and 1/3 bias drive schemes can be controlled
from serial data.
• Capable of driving up to 228 segments using 1/3 duty
and up to 300 segments using 1/4 duty.
SANYO: QFP100E(QIP100E)
• Sleep mode and all segments off functions that are
controlled from serial data.
• Segment output port/general-purpose output port
function switching that is controlled from serial data.
• Serial data I/O supports CCB format communication
with the system controller.
unit: mm
3181C-SQFP100
[LC75804W]
16.0
14.0
75
51
50
76
• Direct display of display data without the use of a
decoder provides high generality.
• Independent V
for the LCD driver block (V
can
LCD
LCD
be set to in the range V – 0.5 to 6.0 volts.)
DD
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
• RES pin provided for forcibly initializing the IC internal
circuits.
100
26
1
25
0.5
0.2
0.145
(1.0)
• RC oscillator circuit.
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
SANYO: SQFP100
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51003AS / D2599TH (OT) No. 6266-1/37
LC75804E, LC75804W
Specifications
Absolute Maximum Ratings at Ta=25°C, V =0V
SS
Parameter
Maximum supply voltage
Symbol
DD max
LCD max VLCD
Conditions
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VDD +0.3
–0.3 to VLCD +0.3
–0.3 to +7.0
–0.3 to VDD +0.3
–0.3 to VLCD +0.3
300
Unit
V
V
VDD
V
VIN1
VIN2
VIN3
CE, CL, DI, RES
OSC,TEST
Input voltage
V
VLCD1, VLCD2, KI1 to KI5
V
V
V
OUT1
OUT2
OUT3
DO
Output voltage
OSC
V
S1 to S76, COM1 to COM4, KS1 to KS6, P1 to P8
IOUT1
IOUT2
IOUT3
IOUT4
S1 to S76
µA
mA
COM1 to COM4
KS1 to KS6
P1 to P8
3
Output current
1
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
200
mW
°C
–40 to +85
–55 to +125
Tstg
°C
Allowable Operating Ranges at Ta = –40 to +85°C, V =0V
SS
Ratings
Parameter
Symbol
Conditions
Unit
V
min
4.5
typ
max
6.0
VDD
VDD
Supply voltage
Input voltage
VLCD
VLCD
VLCD
VLCD
VDD – 0.5
6.0
VLCD
V
V
LCD1
LCD2
1
2
2/3 VLCD
1/3 VLCD
V
VLCD
VIH
1
CE, CL, DI, RES
KI1 to KI5
0.8 VDD
0.6 VDD
0
6.0
Input high level voltage
V
V
IH2
VLCD
Input low level voltage
Recommended external resistance
Recommended external capacitance
Guaranteed oscillator range
Data setup time
VIL
ROSC
COSC
fOSC
tds
CE, CL, DI, RES, KI1 to KI5
0.2 VDD
V
kΩ
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
OSC
39
1000
38
OSC
OSC
19
160
160
160
160
160
160
160
76
CL, DI
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
Data hold time
tdh
CL, DI
CE wait time
tcp
CE, CL
CE setup time
tcs
CE, CL
CE hold time
tch
CE, CL
High level clock pulse width
Low level clock pulse width
Rise time
tøH
tøL
tr
CL
CL
CE, CL, DI
160
160
Fall time
tf
CE, CL, DI
1
1
DO output delay time
DO rise time
tdc
DO RPU=4.7 kΩ, CL=10pF *
DO RPU=4.7 kΩ, CL=10pF *
1.5
1.5
tdr
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
No. 6266-2/37
LC75804E, LC75804W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Hysteresis
VH
VDET
IIH
CE, CL, DI, RES, KI1 to KI5
0.1 VDD
3.0
V
V
Power-down detection voltage
Input high level current
Input low level current
Input floating voltage
2.5
3.5
CE, CL, DI, RES: VI = 6.0 V
CE, CL, DI, RES: VI = 0 V
KI1 to KI5
5.0
µA
µA
V
IIL
–5.0
50
VIF
0.05 VDD
250
Pull-down resistance
RPD
IOFFH
KI1 to KI5: VDD = 5.0 V
100
kΩ
µA
Output off leakage current
DO: VO = 6.0 V
6.0
V
V
V
OH1
OH2
OH3
KS1 to KS6: IO = –500 µA
P1 to P8: IO = –1 mA
VLCD – 1.0 VLCD – 0.5 VLCD – 0.2
VLCD – 1.0
Output high level voltage
Output low level voltage
V
S1 to S76: IO = –20 µA
VLCD – 1.0
VOH
4
COM1 to COM4: IO = –100 µA
KS1 to KS6: IO = 25 µA
VLCD – 1.0
V
V
V
V
V
OL1
OL2
OL3
OL4
OL5
0.2
0.5
0.1
1.5
1.0
1.0
1.0
0.5
+ 1.0
+ 1.0
+ 1.0
+ 1.0
+ 1.0
P1 to P8: IO = 1 mA
S1 to S76: IO = 20 µA
V
COM1 to COM4: IO = 100 µA
DO: IO = 1 mA
V
MID1
COM1 to COM4: 1/2 bias, IO = ±100 µA
S1 to S76: 1/3 bias,IO = ±20 µA
S1 to S76: 1/3 bias, IO = ±20 µA
COM1 to COM4: 1/3 bias,IO = ±100 µA
COM1 to COM4: 1/3 bias,IO = ±100 µA
OSC: ROSC = 39 kΩ, COSC = 1000 pF
VDD :Sleep mode
1/2 V
2/3 V
1/3 V
2/3 V
1/3 V
– 1.0
– 1.0
– 1.0
– 1.0
– 1.0
1/2 V
2/3 V
1/3 V
2/3 V
1/3 V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
VMID
2
3
2
Output middle level voltage *
VMID
V
V
MID4
VMID
fosc
5
Oscillator frequency
Current drain
30.4
38
45.6
100
540
5
kHz
I
DD1
DD2
I
VDD: VDD = 6.0 V, output open,fosc = 38 kHz
VLCD : Sleep mode
270
I
LCD1
ILCD
LCD3
µA
VLCD: VLCD = 6.0 V, output open, 1/2 bias,
fosc = 38 kHz
2
200
120
400
240
VLCD: VLCD = 6.0 V, output open, 1/3 bias,
fosc = 38 kHz
I
Nete: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
No. 6266-3/37
LC75804E, LC75804W
VLCD
VLCD1
VLCD2
To the common segment driver
Excluding these registors.
Figure 1
1. When CL is stopped at the low level
VIH1
CE
VIL
t ø H
t ø L
tf
VIH1
50%
CL
VIL
tr
tcp tcs
tch
VIH1
DI
VIL
tds
tdh
tdc
tdr
DO
D0
D1
2. When CL is stopped at the high level
VIH1
CE
VIL
tø L
tø H
VIH1
50%
VIL
CL
DI
tf
tr
tcp tcs
tch
VIH1
VIL
tds
tdh
DO
D0
D1
tdc
tdr
Figure 2
No. 6266-4/37
LC75804E, LC75804W
Pin Assignments
80
51
81
50
S76/KS2
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
KS3
KS4
KS5
KS6
KI1
KI2
KI3
KI4
LC75804E
(QFP100E)
KI5
VDD
VLCD
VLCD1
VLCD2
VSS
TEST
OSC
RES
DO
CE
100
31
1
30
(Top view)
75
51
76
50
COM2
COM1
S75/KS1
S76/KS2
KS3
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
KS4
KS5
KS6
KI1
KI2
KI3
LC75804W
(SQFP100)
KI4
KI5
VDD
VLCD
VLCD1
VLCD2
VSS
TEST
OSC
RES
DO
CE
CL
DI
100
26
1
25
(Top view)
No. 6266-5/37
LC75804E, LC75804W
Block Diagram
VLCD
VLCD1
VLCD2
VSS
SEGMENT DRIVER & LATCH
COMMON
DRIVER
SHIFT REGISTER
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
KEY BUFFER
CL
CE
VDD
VDET
KEY SCAN
No. 6266-6/37
LC75804E, LC75804W
Pin Functions
Pin No.
LC75804E LC75804W
Handling
when unused
Pin
Function
Active
—
I/O
Segment outputs for displaying the display data transferred by serial
data input.
The S1/P1 to S8/P8 pins can be used as general-purpose output ports
under serial data control.
S1/P1 to
S8/P8
S9 to S73
1 to 8
3 to 10
●
OPEN
OPEN
9 to 73
11 to 75
79
78
77
76
77
76
75
74
COM1
COM2
COM3
Common driver outputs
The frame frequency fo is given by : fo = (fOSC/384)Hz.
The COM4/S74 pin can be used as a segment output in 1/3 duty.
—
—
●
COM4/S74
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in
the timing lines to prevent shorts, since these outputs are unbalanced
CMOS transistor outputs, these outputs will not be damaged by shorting
when these outputs are used to form a key matrix. The KS1/S75 and
KS2/S76 pins can be used as segment outputs when so specified by
the control data.
KS1/S75
KS2/S76
KS3 to KS6
80
81
78
79
O
OPEN
82 to 85
80 to 83
Key scan inputs
These pins have built-in pull-down resistors.
KI1 to KI5
OSC
86 to 90
97
84 to 88
95
H
I
GND
VDD
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.
—
I/O
Serial data interface connections to the controller. Note that DO, being
an open-drain output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
CE
CL
DI
100
1
98
99
H
I
I
▲
GND
2
100
97
—
—
I
DO :Output data
DO
99
O
OPEN
Reset signal input
.....
RES = low Display off
Key scan disabled
All key data is reset to low
RES = high Display on
RES
98
96
L
I
VDD
....
Key scan enabled
However, serial data can be transferred when RES is low.
TEST
96
93
94
91
This pin must be connected to ground.
—
—
I
I
—
Used for applying the LCD drive 2/3 bias voltage externally. Must be
connected to VLCD2 when a 1/2 bias drive scheme is used.
VLCD1
OPEN
Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to VLCD1 when a 1/2 bias drive scheme is used.
V
LCD2
94
91
92
89
—
—
I
OPEN
—
Logic block power supply connection. Provide a voltage of between 4.5
and 6.0V.
VDD
—
LCD driver block power supply connection. Provide a voltage of
between VDD – 0.5 and 6.0V.
VLCD
VSS
92
95
90
93
—
—
—
—
—
—
Power supply connection. Connect to ground.
No. 6266-7/37
LC75804E, LC75804W
Serial Data Input
1. 1/3 duty
① When CL is stopped at the low level
CE
CL
0
1
0
0
0
0
1
0
D1
D2
D73 D74 D75 D76 D77 D78
0
0
0
0
0
S0 S1 K0 K1 P0 P1 P2 P3
DT
SC DR
0
0
DI
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Control data
DD
DO
0
1
0
0
0
0
1
0
D79 D80
D151 D152 D153
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D154 D155
D226 D227 D228
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Display data
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
No. 6266-8/37
LC75804E, LC75804W
②When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D79 D80
D154 D155
D73 D74 D75 D76 D77 D78
0
0
0
0
0
S0 S1 K0 K1 P0 P1 P2 P3 SC DR
0
0
DT
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Control data
DD
DO
0
1
0
0
0
0
1
0
D151 D152 D153
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D226 D227 D228
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
............
..............
......................
......................
..................
CCB address
D1 to D228
S0, S1
K0, K1
P0 to P3
SC
DR
DT
42H
Display data
Sleep control data
Key scan output/segment output selection data
Segment output port/general-purpose output port selection data
Segment on/off control data
1/2 bias or 1/3 bias drive selection data
1/3 duty or 1/4 duty drive selection data
............................
............................
............................
No. 6266-9/37
LC75804E, LC75804W
2. 1/4duty
① When CL is stopped at the low level
CE
CL
0
1
0
0
0
0
1
0
D1
D77
D153
D229
D72 D73 D74 D75 D76
0
0
0
0
0
0
0
S0 S1 K0 K1 P0 P1 P2 P3 SC DR DT
0
0
DI
B0 B1 B2 B3 A0 A1 A2 A3
Control data
Display data
DD
DO
0
1
0
0
0
0
1
0
D148 D149 D150 D151 D152
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D224 D225 D226 D227 D228
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
1
D300
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
No. 6266-10/37
LC75804E, LC75804W
②When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S0 S1 K0 K1 P0 P1 P2 P3 SC DR DT
0
0
D1
D72 D73 D74 D75 D76
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Control data
DD
DO
0
1
0
0
0
0
1
0
D148 D149 D150 D151 D152
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D77
D153
D229
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D224 D225 D226 D227 D228
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
Display data
DD
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
D300
Fixed data
B0 B1 B2 B3 A0 A1 A2 A3
Display data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
............
..............
......................
......................
..................
CCB address
D1 to D300
S0, S1
K0, K1
P0 to P3
SC
DR
DT
42H
Display data
Sleep control data
Key scan output/segment output selection data
Segment output port/general-purpose output port selection data
Segment on/off control data
1/2 bias or 1/3 bias drive selection data
1/3 duty or 1/4 duty drive selection data
............................
............................
............................
No. 6266-11/37
LC75804E, LC75804W
Control Data Functions
1. S0, S1 : Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
outputs during key scan standby.
Control data
S0 S1
Output pin states during key scan standby
Segment outputs
Common outputs
Mode
OSC oscillator
KS1
H
KS2
H
KS3
H
KS4
H
KS5
H
KS6
H
0
0
Normal
Sleep
Sleep
Sleep
Operating
Stopped
Stopped
Stopped
Operating
0
1
1
1
0
1
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
H
H
H
H
Note: This assumes that the KS1/S75 and KS2/S76 output pins are selected for key scan output.
2. K0, K1 : Key scan output /segment output selection data
These control data bits switch the functions of the KS1/S75 and KS2/S76 output pins between key scan output and
segment output.
Control data
K0 K1
Output pin state
Maximum number of
input keys
KS1/S75
KS2/S76
KS2
0
0
KS1
S75
S75
30
25
20
0
1
1
KS2
X
S76
X: don’t care
Note: KSn(n = 1 or 2) : Key scan output
Sn (n = 75 or 76): Segment output
3. P0 to P3 : Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S8/P8 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
0
P1
0
P2
P3
0
S1/P1
S1
S2/P2
S2
S3/P3
S3
S4/P4
S4
S5/P5
S5
S6/P6
S6
S7/P7
S7
S8/P8
S8
0
0
1
1
0
0
1
1
0
0
0
1
P1
S2
S3
S4
S5
S6
S7
S8
0
0
0
P1
P2
S3
S4
S5
S6
S7
S8
0
0
1
P1
P2
P3
S4
S5
S6
S7
S8
0
1
0
P1
P2
P3
P4
S5
S6
S7
S8
0
1
1
P1
P2
P3
P4
P5
S6
S7
S8
0
1
0
P1
P2
P3
P4
P5
P6
S7
S8
0
1
1
P1
P2
P3
P4
P5
P6
P7
S8
1
0
0
P1
P2
P3
P4
P5
P6
P7
P8
Note: Sn(n=1 to 8): Segment output port
Pn(n=1 to 8): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to
be general-purpose output ports.
Corresponding display data
Output pin
1/3 duty
1/4 duty
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
D1
D1
D4
D5
D7
D9
D10
D13
D16
D19
D22
D13
D17
D21
D25
D29
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level (V ) when the display data D13 is 1, and will output a low level
LCD
(Vss) when D13 is 0.
No. 6266-12/37
LC75804E, LC75804W
4. SC : Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
0
Display state
on
off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
5. DR : 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR
0
Bias drive scheme
1/3 bias drive
1
1/2 bias drive
6. DT : 1/3 duty or 1/4 duty drive selection data
This control data bit switches between LCD 1/3 duty or 1/4 duty drive.
DT
0
Duty drive scheme
1/4 duty drive
Output pin state (COM4/S74)
COM4
S74
1
1/3 duty drive
Note: COM4: Common output
S74 : Segment output
Display Data and Output Pin Correspondence
1. 1/3 duty
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9
COM1
D1
COM2
D2
COM3
D3
Output pin
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
COM1
D79
COM2
D80
COM3
D81
Output pin
S53
COM1
D157
D160
D163
D166
D169
D172
D175
D178
D181
D184
D187
D190
D193
D196
D199
D202
D205
D208
D211
D214
D217
D220
D223
D226
COM2
D158
D161
D164
D167
D170
D173
D176
D179
D182
D185
D188
D191
D194
D197
D200
D203
D206
D209
D212
D215
D218
D221
D224
D227
COM3
D159
D162
D165
D168
D171
D174
D177
D180
D183
D186
D189
D192
D195
D198
D201
D204
D207
D210
D213
D216
D219
D222
D225
D228
D4
D5
D6
D82
D83
D84
S54
D7
D8
D9
D85
D86
D87
S55
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D88
D89
D90
S56
D91
D92
D93
S57
D94
D95
D96
S58
D97
D98
D99
S59
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
S60
S61
S10
S62
S11
S63
S12
S64
S13
S65
S14
S66
S15
S67
S16
S68
S17
S69
S18
S70
S19
S71
S20
S72
S21
S73
S22
COM4/S74
KS1/S75
KS2/S76
S23
S24
S25
S26
Note: This is for the case where the output pins S1/P1 to S8/P8, COM4/S74, KS1/S75 and KS2/S76 are selected for use as segment outputs.
No. 6266-13/37
LC75804E, LC75804W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
0
D32
0
D33
0
The LCD segments for COM1, COM2 and COM3 are off.
The LCD segment for COM3 is on.
0
0
1
0
1
0
The LCD segment for COM2 is on.
0
1
1
The LCD segments for COM2 and COM3 are on.
The LCD segment for COM1 is on.
1
0
0
1
0
1
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1, COM2 and COM3 are on.
1
1
0
1
1
1
2. 1/4 duty
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9
COM1
D1
COM2
D2
COM3
D3
COM4
D4
Output pin
S39
COM1
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
D209
D213
D217
D221
D225
D229
D233
D237
D241
D245
D249
D253
D257
D261
D265
D269
D273
D277
D281
D285
D289
D293
D297
COM2
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
D210
D214
D218
D222
D226
D230
D234
D238
D242
D246
D250
D254
D258
D262
D266
D270
D274
D278
D282
D286
D290
D294
D298
COM3
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
D211
D215
D219
D223
D227
D231
D235
D239
D243
D247
D251
D255
D259
D263
D267
D271
D275
D279
D283
D287
D291
D295
D299
COM4
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D212
D216
D220
D224
D228
D232
D236
D240
D244
D248
D252
D256
D260
D264
D268
D272
D276
D280
D284
D288
D292
D296
D300
D5
D6
D7
D8
S40
D9
D10
D11
D12
S41
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D14
D15
D16
S42
D18
D19
D20
S43
D22
D23
D24
S44
D26
D27
D28
S45
D30
D31
D32
S46
D34
D35
D36
S47
S10
D38
D39
D40
S48
S11
D42
D43
D44
S49
S12
D46
D47
D48
S50
S13
D50
D51
D52
S51
S14
D54
D55
D56
S52
S15
D58
D59
D60
S53
S16
D62
D63
D64
S54
S17
D66
D67
D68
S55
S18
D70
D71
D72
S56
S19
D74
D75
D76
S57
S20
D78
D79
D80
S58
S21
D82
D83
D84
S59
S22
D86
D87
D88
S60
S23
D90
D91
D92
S61
S24
D94
D95
D96
S62
S25
D98
D99
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
S63
S26
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
S64
S27
S65
S28
S66
S29
S67
S30
S68
S31
S69
S32
S70
S33
S71
S34
S72
S35
S73
S36
KS1/S75
KS2/S76
S37
S38
Note: This is for the case where the output pins S1/P1 to S8/P8, KS1/S75 and KS2/S76 are selected for use as segment outputs.
No. 6266-14/37
LC75804E, LC75804W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D41
0
D42
0
D43
0
D44
0
The LCD segments for COM1,COM2,COM3 and COM4 are off.
The LCD segment for COM4 is on.
0
0
0
1
0
0
1
0
The LCD segment for COM3 is on.
0
0
1
1
The LCD segments for COM3 and COM4 are on.
The LCD segment for COM2 is on.
0
1
0
0
0
1
0
1
The LCD segments for COM2 and COM4 are on.
The LCD segments for COM2 and COM3 are on.
The LCD segments for COM2,COM3 and COM4 are on.
The LCD segment for COM1 is on.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
The LCD segments for COM1 and COM4 are on.
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1,COM3 and COM4 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1,COM2 and COM4 are on.
The LCD segments for COM1,COM2 and COM3 are on.
The LCD segments for COM1,COM2,COM3 and COM4 are on.
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Serial Data Output
1. When CL is stopped at the low level
CE
CL
1
1
0
0
0
0
1
0
DI
B0 B1 B2 B3 A0 A1 A2 A3
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
DO
X: don't care
Note: B0 to B3, A0 to A3······CCB address
2. When CL is stopped at the high level
CE
CL
1
1
0
0
0
0
1
0
DI
B0 B1 B2 B3 A0 A1 A2
A3
X KD1 KD2 KD3
KD28 KD29 KD30 SA
X
DO
Output data
X: don't care
Note: B0 to B3, A0 to A3······CCB address
......
CCB address
KD1 to KD30
SA
43H
Key data
Sleep acknowledge data
........
........................
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
No. 6266-15/37
LC75804E, LC75804W
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S75
KS2/S76
KS3
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
KS4
KS5
KS6
When the KS1/S75 and KS2/S76 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S8/P8 outputs can be used as general-purpose output ports according to the state of the P0 to P3 control data
bits, even in sleep mode. (See the control data description for details.)
No. 6266-16/37
LC75804E, LC75804W
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75804E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75804E/W cannot detect a key press shorter than 615T(s).
*3
*3
*3
*3
*3
1
1
*3
*3
*3
*3
*3
KS1
KS2
KS3
KS4
KS5
KS6
2
2
3
3
1
fosc
T=
4
4
5
5
6
6
Key on
576T[s]
Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from
pins that are set low.
2. In normal mode
•
•
The pins KS1 to KS6 are set high.
When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
1
——
) the LC75804E/W outputs a key data read request (a
•
•
If a key is pressed for longer than 615T(s) (Where T=
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75804E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 kΩ).
Key input 1
Key input 2
Key scan
CE
615T[s]
615T[s]
615T[s]
Serial data transfer Key address (43H) Serial data transfer
Key address
Key address
Serial data transfer
DI
DO
Key data read
Key data read
Key data read
Key data read request
Key data read request
Key data read request
1
fosc
T=
No. 6266-17/37
LC75804E, LC75804W
3. In sleep mode
•
The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
•
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
1
——
) the LC75804E/W outputs a key data read request (a
•
•
•
If a key is pressed for longer than 615T(s)(Where T=
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75804E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
Sleep mode key scan example
Example: S0 = 0, S1 = 1 (sleep with only KS6 high)
[L] KS1
[L] KS2
[L] KS3
[L] KS4
[L] KS5
[H] KS6
*4
When any one of these keys is pressed,
the oscillator on the OSC pin is started
and the keys are scanned.
KI1
KI2
KI3
KI4
KI5
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5
lines are pressed at the same time.
Key input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
DI
Serial data transfer
1
fosc
Key address
Serial data transfer Key address (43H)
Serial data transfer
T=
DO
Key data read
Key data read
Key data read request
Key data read request
Multiple Key Presses
Although the LC75804E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No. 6266-18/37
LC75804E, LC75804W
1/3 Duty, 1/2 Bias Drive Technique
fosc
[Hz]
384
VLCD
VLCD1,VLCD2
0V
COM1
COM2
COM3
VLCD
VLCD1,VLCD2
0V
VLCD
VLCD1,VLCD2
0V
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are turned off.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are on.
1/3 Duty, 1/2 Bias Waveforms
No. 6266-19/37
LC75804E, LC75804W
1/3 Duty, 1/3 Bias Drive Technique
fosc
[Hz]
384
VLCD
VLCD1
VLCD2
0V
COM1
VLCD
VLCD1
VLCD2
0V
COM2
COM3
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are turned off.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2 and COM3 are on.
1/3 Duty, 1/3 Bias Waveforms
No. 6266-20/37
LC75804E, LC75804W
1/4 Duty, 1/2 Bias Drive Technique
fosc
[Hz]
384
VLCD
VLCD1,VLCD2
0V
COM1
VLCD
VLCD1,VLCD2
0V
COM2
COM3
VLCD
VLCD1,VLCD2
0V
VLCD
VLCD1,VLCD2
0V
COM4
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/2 Bias Waveforms
No. 6266-21/37
LC75804E, LC75804W
1/4 Duty, 1/3 Bias Drive Technique
fosc
[Hz]
384
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM1
COM2
COM3
VLCD
VLCD1
VLCD2
0V
COM4
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/3 Bias Waveforms
No. 6266-22/37
LC75804E, LC75804W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage V rise time when the logic block power is first applied and the
DD
logic block power supply voltage V fall time when the voltage drops are both at least 1 ms. (See Figure 3 and Figure 4.)
DD
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3 and Figure 4.)
• Power on :Logic block power supply(V ) on → LCD driver block power supply(V
) on
LCD
DD
• Power off:LCD driver block power supply(V ) off → Logic block power supply(V ) off
LCD DD
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75804E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
(1) Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage V rise time when logic block power is applied, a system
DD
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage V fall time when logic block power drops, a system reset will be applied in
DD
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (1/3 duty: the display data D1 to D228 and the control data, 1/4 duty: the display data D1 to
D300 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data,
after all the direction data has been transferred. However, the above operations will be performed regardless of the state
(high or low) of the RES pin. If RES is high, the reset will be cleared at the point the above operations are completed. On
the other hand, if RES is low, the system will remain in the reset period as long as RES is not set high, even if the above
operations are completed. (See Figure 3 and Figure 4.)
No. 6266-23/37
LC75804E, LC75804W
• 1/3 duty
t1 t2
t3 t4
VDD
VDET
VDET
VLCD
CE
VIL
Display and control data transfer
D1 to D78
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
S0, S1, K0, K1
P0 to P3, SC, DR, DT
Internal data
Undefined
Internal data (D79 to D153)
Undefined
Internal data (D154 to D228)
System reset period
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 3
• 1/4 duty
t1 t2
t3 t4
VDD
VDET
VDET
VLCD
CE
VIL
Display and control data transfer
D1 to D76
Undefined
Undefined
Undefined
Undefined
S0, S1, K0, K1
P0 to P3, SC, DR, DT
Internal data
Defined
Defined
Defined
Defined
Undefined
Internal data (D77 to D152)
Undefined
Undefined
Internal data (D153 to D228)
Undefined
Internal data (D229 to D300)
System reset period
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 4
No. 6266-24/37
LC75804E, LC75804W
(2) Reset when the logic block power supply voltage is in the allowable operating range (V = 4.5 to 6.0V)
DD
The system is reset when the RES pin is set low, and the reset is cleared by setting RES pin high.
2. LC75804E/W internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
No. 6266-25/37
LC75804E, LC75804W
VLCD
VLCD1
VLCD2
VSS
SEGMENT DRIVER & LATCH
SHIFT REGISTER
COMMON
DRIVER
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
KEY BUFFER
CL
CE
VDD
VDET
KEY SCAN
Blocks that are reset
3. Output pin states during the reset period
Output pin
S1/P1 to S8/P8
S9 to S73
State during reset
L *5
L
COM1 to COM3
COM4/S74
KS1/S75, KS2/S76
KS3 to KS5
KS6
L
L *6
L *5
X *7
H
DO
H *8
X: don’t care
Notes:*5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is
transferred, either the common output or the segment output function is selected.
*7. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*8. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
No. 6266-26/37
LC75804E, LC75804W
Sample Application Circuit 1
1/3 duty, 1/2 bias (for use with normal panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
COM1
*9
COM2
COM3
P1/S1
P2/S2
VSS
TEST
+5.5V
VLCD
P8/S8
S9
VLCD1
VLCD2
C ≥ 0.047 µF
S73
C
COM4/S74
S S
7 7
6 5
/ /
K K
S S
2 1
RES
CE
CL
DI
DO
*10
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S
6 5 4 3
To the controller
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-27/37
LC75804E, LC75804W
Sample Application Circuit 2
1/3 duty, 1/2 bias (for use with large panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
VSS
COM1
COM2
COM3
P1/S1
P2/S2
*9
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
TEST
+5.5V
VLCD
P8/S8
S9
R
R
VLCD1
VLCD2
C
S73
COM4/S74
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
S S S S
6 5 4 3
To the controller
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-28/37
LC75804E, LC75804W
Sample Application Circuit 3
1/3 duty, 1/3 bias (for use with normal panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
VSS
COM1
COM2
COM3
P1/S1
P2/S2
*9
TEST
+5.5V
VLCD
P8/S8
S9
VLCD1
VLCD2
C ≥ 0.047 µF
S73
C
C
COM4/S74
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
S S S S
6 5 4 3
To the controller
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-29/37
LC75804E, LC75804W
Sample Application Circuit 4
1/3 duty, 1/3 bias (for use with large panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
VSS
COM1
COM2
COM3
P1/S1
P2/S2
*9
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
TEST
+5.5V
VLCD
R
R
R
P8/S8
S9
VLCD1
VLCD2
C
C
S73
COM4/S74
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
S S S S
6 5 4 3
To the controller
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-30/37
LC75804E, LC75804W
Sample Application Circuit 5
1/4 duty, 1/2 bias (for use with normal panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
COM1
COM2
COM3
*9
VSS
TEST
S74/COM4
P1/S1
+5.5V
VLCD
P2/S2
VLCD1
VLCD2
P8/S8
S9
C ≥ 0.047 µF
C
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
S73
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
S S S S
6 5 4 3
To the controller
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-31/37
LC75804E, LC75804W
Sample Application Circuit 6
1/4 duty, 1/2 bias (for use with large panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
COM1
COM2
COM3
*9
VSS
TEST
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
S74/COM4
P1/S1
VLCD
P2/S2
+5.5V
R
R
VLCD1
VLCD2
P8/S8
S9
C
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
S73
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
To the controller
S S S S
6 5 4 3
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-32/37
LC75804E, LC75804W
Sample Application Circuit 7
1/4 duty, 1/3 bias (for use with normal panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
VSS
COM1
COM2
COM3
*9
TEST
S74/COM4
P1/S1
+5.5V
VLCD
P2/S2
VLCD1
VLCD2
P8/S8
S9
C ≥ 0.047 µF
C
C
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
S73
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
S S S S
6 5 4 3
To the controller
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 6266-33/37
LC75804E, LC75804W
Sample Application Circuit 8
1/4 duty, 1/3 bias (for use with large panels)
(P1)
(P2)
(general-purpose output ports)
Used with the backlight
controller or other circuit.
(P8)
OSC
+5V
VDD
COM1
COM2
COM3
*9
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
VSS
TEST
S74/COM4
P1/S1
+5.5V
VLCD
P2/S2
R
R
R
VLCD1
VLCD2
P8/S8
S9
C
C
S S
7 7
6 5
/ /
K K
S S
2 1
RES*10
CE
CL
S73
From the controller
(S75)
(S76)
K K K K K K K K K
I I I I I
5 4 3 2 1
DI
DO
To the controller
S S S S
6 5 4 3
To the controller
power supply
*11
Key matrix
(up to 30 keys)
Notes:*9. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75804E/W is reset by the VDET.
*10. If the RES pin is not used for system reset, it must be connected to the logic block power supply VDD
.
*11. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
When using the LC75804E/W in 1/3 duty, applications transfer the display data (D1 to D228) in three operations, and in
1/4 duty, they transfer the display data (D1 to D300) in four operations. In either case, applications should transfer all of
the display data within 30 ms to maintain the quality of the displayed image.
No. 6266-34/37
LC75804E, LC75804W
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
CE = [L]
NO
DO = [L]
YES
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
DI
t8
t8
t8
Key address
t7
t7
t7
Key data read
DO
Key data read request
t9
t9
t9
t9
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No. 6266-35/37
LC75804E, LC75804W
2. Interrupt based key data acquisition
(1) Flowchart
CE = [L]
NO
DO = [L]
YES
Key data read
processing
Wait for at
least t10
CE = [L]
NO
DO = [H]
YES
Key OFF
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t5
t6
t5
CE
t8
t8
t8
t8
Key address
DI
t7
t7
t7
t7
Key data read
DO
Key data read request
t10
t10
t10
t10
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key on)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
T = ———
fosc
No. 6266-36/37
LC75804E, LC75804W
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of May, 2003. Specifications and information herein are subject to
change without notice.
PS No. 6266-37/37
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