LC75839PW [SANYO]
1/4 and 1/3-Duty General-Purpose LCD Display Driver; 1/4和1/ 3占空比通用液晶显示驱动
| 型号： | LC75839PW |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/4 and 1/3-Duty General-Purpose LCD Display Driver |
| 文件： | 总27页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1953
CMOS IC
1/4 and 1/3-Duty General-Purpose
LCD Display Driver
LC75839PW
Overview
The LC75839PW is 1/4 duty and 1/3 duty general-purpose microprocessor-controlled LCD driver that can be used in
applications such as frequency display in products with electronic tuning. In addition to being able to drive up to 208
segments directly, the LC75839PW can also control up to 4 general-purpose output ports. Because it has the PWM
output of a maximum of 3 ch, the brightness control of the LED backlight of RGB can be done. Incorporation of an
oscillation circuit helps to reduce the number of external resistors and capacitors required.
Features
• Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control.
When 1/4-duty: Capable of driving up to 208 segments
When 1/3-duty: Capable of driving up to 159 segments
• Serial data input supports CCB format communication with the system controller. (Support 3.3V and 5V operation)
• Serial data control of the power-saving mode based backup function and the all segments forced off function.
• Serial data control of switching between the segment output port and general-purpose output port function.
(Support for up to 4 general-purpose output ports)
• Support for the PWM output function of a maximum of 3ch. (It can output from the general-purpose output port ).
• Support for clock output function of 1ch.
• Serial data control of the frame frequency of the common and segment output waveforms.
• Serial data control of switching between the internal oscillator operating mode and external clock operating mode.
• High generality, since display data is displayed directly without the intervention of a decoder circuit.
• The INH pin allows the display to be forced to the off state.
• Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation)
• CCB is a registered trademark of SANYO Semiconductor Co., Ltd.
• CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO
Semiconductor for this format.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
62911HKPC 20110412-S00001 No.A1953-1/27
LC75839PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0V
SS
Parameter
Maximum supply voltage
Input voltage
Symbol
Conditions
Ratings
-0.3 to +6.5
Unit
V
V
max
V
DD
V
DD
CE, CL, DI,
1
INH
-0.3 to +6.5
IN
V
V
2
OSCI, V 1, V
2
-0.3 to V +0.3
DD
IN
DD DD
Output voltage
Output current
V
S1 to S53, COM1 to COM4, P1 to P4
S1 to S52
-0.3 to V +0.3
DD
V
OUT
1
I
I
I
300
μA
OUT
OUT
OUT
2
3
COM1 to COM4, S53
P1 to P4
3
5
mA
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta=85°C
200
mW
°C
-40 to +85
-55 to +125
Tstg
°C
Allowable Operating Ranges at Ta = -40 to +85°C, V = 0V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
4.5
max
6.0
Supply voltage
V
V
V
V
V
V
DD
DD
DD
DD
Input voltage
V
V
1
1
2
2/3V
1/3V
V
V
DD
DD
DD
DD
2
DD
DD
6.0
Input high-level voltage
Input low-level voltage
V
1
CE, CL, DI,
INH
OSCI: External clock operating mode
CE, CL, DI,
0.4V
0.4V
IH
DD
V
V
V
2
V
0.2V
0.2V
IH
DD
0
DD
DD
DD
V
V
f
1
INH
IL
2
OSCI: External clock operating mode
0
10
30
IL
External clock operating frequency
External clock duty cycle
Data setup time
OSCI: External clock operating mode [Figure 4]
OSCI: External clock operating mode [Figure 4]
300
50
600
70
kHz
%
CK
D
CK
tds
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 2][Figure 3]
[Figure 5][Figure 6]
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Data hold time
tdh
tcp
tcs
tch
tφH
tφL
tr
CE wait time
CE setup time
CE hold time
High-level clock pulse width
Low-level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
160
160
Fall time
tf
switching time
tc
, CE
INH
INH
10
No.A1953-2/27
LC75839PW
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Pin
Conditions
Unit
V
min
max
Hysteresis
V
H
CE, CL, DI,
CE, CL, DI,
OSCI
INH
INH
0.03V
DD
Input high-level current
Input low-level current
Output high-level voltage
I
I
1
2
V = 6.0V
I
5.0
5.0
IH
μA
V = V : External clock operating mode
DD
IH
I
I
1
2
CE, CL, DI,
OSCI
V = 0V
I
INH
-5.0
IL
μA
I
V = 0V: External clock operating mode
I
-5.0
-0.9
IL
V
1
S1 to S53
I
= -20μA
V
V
V
OH
O
O
DD
DD
DD
V
2
COM1
I
= -100μA
OH
V
-0.9
-0.9
to COM4
P1 to P4
V
3
1
2
I
I
I
= -1mA
= 20μA
= 100μA
OH
O
O
O
Output low-level voltage
V
S1 to S53
0.9
0.9
OL
OL
V
COM1
V
to COM4
P1 to P4
V
3
I
=1mA
0.9
DD
OL
O
Output middle-level
voltage *1
V
V
V
V
1
2
3
4
S1 to S53
1/3 bias I = ±20μA
2/3V
2/3V
MID
MID
MID
MID
O
DD
-0.9
+0.9
S1 to S53
1/3 bias I = ±20μA
1/3V
1/3V
DD
O
DD
-0.9
+0.9
V
COM1
1/3 bias I = ±100μA
2/3V
2/3V
DD
O
DD
to COM4
COM1
-0.9
+0.9
1/3 bias I = ±100μA
1/3V
1/3V
DD
O
DD
to COM4
Internal
-0.9
+0.9
Oscillator frequency
Current drain
fosc
Internal oscillator operating mode
240
300
800
360
100
kHz
oscillator circuit
I
1
V
Power-saving mode
DD
DD
I
2
V
V
= 6.0V
DD
DD
DD
Output open
1600
Internal oscillator operating mode
I
3
V
V
= 6.0V
DD
DD
DD
μA
Output open
External clock operating mode
800
1600
f
= 300kHz
2 = 0.5V
CK
V
V
IH
DD
2 = 0.1V
IL
DD
Note: *1 Excluding the bias voltage generation divider resistors built in the V 1 and V 2. (See Figure 1.)
DD DD
V
DD
V
V
1
2
DD
To the common and segment drivers
DD
Except these resistors.
V
SS
[Figure 1]
No.A1953-3/27
LC75839PW
1. When CL is stopped at the low level
V
1
IH
CE
V
1
IL
tφH
tφL
V
1
IH
CL 50%
V
1
IL
tr
tf
tcp tcs
tch
V
1
1
IH
DI
V
IL
tds
tdh
[Figure 2]
2. When CL is stopped at the high level
V
1
IH
CE
V 1
IL
tφL
tφH
V
1
IH
50%
IL
CL
DI
V
1
tf
tr
tcp tcs
tch
V
1
IH
V
1
IL
tds
tdh
[Figure 3]
3. OSCI pin clock timing in external clock operating mode
1
t
H
t
L
CK
CK
f
=
[kHz]
CK
t
t
H+t
L
L
CK
CK
CK
V
2
IH
50%
IL
OSCI
t
H
V
2
CK
H+t
D
=
×100[%]
CK
CK
[Figure 4]
No.A1953-4/27
LC75839PW
Package Dimensions
unit : mm (typ)
3190A
12.0
10.0
48
33
49
32
17
64
1
16
0.15
0.5
0.18
(1.25)
SANYO : SQFP64(10X10)
Pin Assignment
48
33
49
32
S49
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S50
S51/COM4
COM3
COM2
COM1
S52
V
LC75839PW
(SQFP64)
DD
V
V
1
DD
DD
2
V
SS
S53/OSCI
INH
CE
CL
DI
64
17
1
16
Top view
No.A1953-5/27
LC75839PW
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER & LATCH
INH
CLOCK
GENERATOR
CONTROL
REGISTER
S53/OSCI
V
DD
SHIFT REGISTER
V
1
DD
2
DD
CCB INTERFACE
V
V
SS
No.A1953-6/27
LC75839PW
Pin Functions
Handling
when
Symbol
Pin No.
Function
Active
I/O
O
unused
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
data control.
S1/P1 to S4/P4
S5 to S50
S52
1 to 4
5 to 50
55
-
-
OPEN
Common driver outputs
COM1 to COM3
COM4/S51
54 to 52
51
The frame frequency is fo[Hz].
O
OPEN
OPEN
The COM4/S51 pin can be used as a segment output in 1/3 duty.
Segment output. This pin can also be used as the external clock input pin when the
external clock operating mode is selected by control data.
Serial data transfer inputs. Must be connected to the controller.
CE: Chip enable
S53/OSCI
60
-
I/O
CE
CL
DI
62
63
64
H
I
I
I
GND
CL: Synchronization clock
-
DI: Transfer data
Display off control input
• INH = low (V ) ...Display forced off
SS
S1/P1 to S4/P4 = low (V
)
SS
(These pins are forcibly set to the general-purpose output port
function and held at the V
S5 to S50, S52=low (V
level.)
SS
)
SS
COM1 to COM3=low (V
)
SS
COM4/S51=low (V
S53/OSCI=low (V
)
SS
)
SS
INH
61
(These pins are forcibly set to the segment output port function
L
I
GND
and held at the V level.)
SS
Stops the internal oscillator.
Inhibits external clock input.
• INH = high (V )...Display on
DD
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
However, serial data transfer is possible when the display is forced off.
Used to apply the LCD drive 2/3 bias voltage externally.
Used to apply the LCD drive 1/3 bias voltage externally.
Power supply pin. A power voltage of 4.5 to 6.0V must be applied to this pin.
Ground pin. Must be connected to ground.
V
V
1
2
57
58
56
59
-
-
-
-
I
I
OPEN
DD
OPEN
DD
V
-
-
-
-
DD
V
SS
No.A1953-7/27
LC75839PW
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
1
0
1
0
D1 D2
D53 D54
D105 D106
D47 D48 D49 D50 D51 D52
0
0
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
18 bits
Display data
52 bits
DD
2 bits
8 bits
1
0
0
0
1
0
1
0
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
0
0
0
PS2 PS3 PS4 PF0 PF1 PF2 PF3
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
52 bits
Control data
18 bits
DD
2 bits
1
0
0
0
1
0
1
0
D151 D152
0
0
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
48 bits
Control data
22 bits
DD
2 bits
1
0
0
0
1
0
1
0
D153 D154
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
56 bits
Fixed data
14 bits
DD
2 bits
Note: DD is the direction data.
No.A1953-8/27
LC75839PW
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
1
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52
0
0
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
18 bits
Display data
52 bits
CCB address
8 bits
DD
2 bits
1
0
0
0
1
0
1
0
D53 D54
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
0
0
0
PS2 PS3 PS4 PF0 PF1 PF2 PF3
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
52 bits
Control data
18 bits
DD
2 bits
8 bits
1
0
0
0
1
0
1
0
D105 D106
D151 D152
0
0
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
48 bits
Control data
22 bits
DD
2 bits
8 bits
1
0
0
0
1
0
1
0
D153 D154
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
56 bits
Fixed data
14 bits
DD
2 bits
8 bits
Note: DD is the direction data.
• CCB address ......................... “51H”
• D1 to D208 ........................... Display data
• PS10, PS11, PS2 to PS4........ General-purpose output port (P1 to P4) function setting control data
• EXF ...................................... External clock operating frequency setting control data
• P0 to P2 ................................ Segment output port/general-purpose output port switching control data
• DT ........................................ 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• DN ........................................ S52 pin and S53/OSCI pin state setting control data
• FC0 to FC2 ........................... Common/segment output waveform frame frequency control data
• OC ........................................ Internal oscillator operating mode/external clock operating mode switching control data
• SC ......................................... Segment on/off control data
• BU ........................................ Normal mode/power-saving mode control data
• PF0 to PF3 ............................ PWM output waveform frame frequency setting control data
• W10 to W15, W20 to W25,... PWM data of the PWM output
W30 to W35
No.A1953-9/27
LC75839PW
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
1
0
1
0
D1 D2
D55 D56
D109 D110
D47 D48 D49 D50 D51 D52 D53 D54
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
16 bits
Display data
54 bits
CCB address
8 bits
DD
2 bits
1
0
0
0
1
0
1
0
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
PS2 PS3 PS4 PF0 PF1 PF2 PF3
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
54 bits
Control data
16 bits
DD
2 bits
1
0
0
0
1
0
1
0
D155 D156 D157 D158 D159
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Control data
19 bits
DD
2 bits
Note: DD is the direction data.
No.A1953-10/27
LC75839PW
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
1
0
1
0
D1 D2
D55 D56
D109 D110
D47 D48 D49 D50 D51 D52 D53 D54
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Control data
16 bits
Display data
54 bits
CCB address
8 bits
DD
2 bits
1
0
0
0
1
0
1
0
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
0
0
0
0
0
PS2 PS3 PS4 PF0 PF1 PF2 PF3
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
54 bits
Control data
16 bits
DD
2 bits
1
0
0
0
1
0
1
0
D155 D156 D157 D158 D159
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Control data
19 bits
DD
2 bits
Note: DD is the direction data.
• CCB address ......................... “51H”
• D1 to D159 ........................... Display data
• PS10, PS11, PS2 to PS4........ General-purpose output port (P1 to P4) function setting control data
• EXF ...................................... External clock operating frequency setting control data
• P0 to P2 ................................ Segment output port/general-purpose output port switching control data
• DT ........................................ 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• DN ........................................ S52 pin and S53/OSCI pin state setting control data
• FC0 to FC2 ........................... Common/segment output waveform frame frequency control data
• OC ........................................ Internal oscillator operating mode/external clock operating mode switching control data
• SC ......................................... Segment on/off control data
• BU ........................................ Normal mode/power-saving mode control data
• PF0 to PF3 ............................ PWM output waveform frame frequency setting control data
• W10 to W15, W20 to W25,... PWM data of the PWM output
W30 to W35
No.A1953-11/27
LC75839PW
Serial Data Transfer Example
1. 1/4 duty
• When 153 or more segments are used
All 288 bits of serial data must be sent.
8 bits
72 bits
1
0
0
0
1
0
1
0
D1 D2
D53 D54
D105 D106
D153 D154
D47 D48 D49 D50 D51 D52
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
1
1
0
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0 PS2 PS3 PS4 PF0 PF1 PF2 PF3
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
D151 D152
0
0
0
0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 153 segments are used
216 bits of serial data shown below (the D1 to D152 display data and the control data) must always be sent.
8 bits
72 bits
1
0
0
0
1
0
1
0
D1 D2
D53 D54
D105 D106
D47 D48 D49 D50 D51 D52
D99 D100 D101 D102 D103 D104
0
0
0
0
0
0
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0 PS2 PS3 PS4 PF0 PF1 PF2 PF3
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
D151 D152
0
0
0
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
2. 1/3 duty
All 216 bits of serial data must be sent.
8 bits
72 bits
1
0
0
0
1
0
1
0
D1 D2
D55 D56
D109 D110
D47 D48 D49 D50 D51 D52 D53 D54
D101 D102 D103 D104 D105 D106 D107 D108
0
0
0
0
PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU
0
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0 PS2 PS3 PS4 PF0 PF1 PF2 PF3
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
1
0
1
0
D155 D156 D157 D158 D159 0 W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
B0 B1 B2 B3 A0 A1 A2 A3
No.A1953-12/27
LC75839PW
Control Data Functions
(1) PS10 and PS11, PS2 to PS4 … General-purpose output port (P1 to P4) function setting control data
These control data bits set the general-purpose output function (High or low level output), clock output function or
PWM output function of the P1 output pin, and the general-purpose output function (High or low level output) or
PWM output function of the P2 to P4 output pins.
However, be careful of being unable to set a PWM output function when the external clock operating frequency is
set the f 2=38[kHz] typ (EXF="1") in external clock operating mode (OC= "1").
CK
PS10
PS11
General-purpose output port (P1) function
0
1
0
1
0
0
1
1
General-purpose output function (High or low level output)
Clock output function (Clock frequency : fosc/2, f /2)
CK
Clock output function (Clock frequency : fosc/8, f /8)
CK
PWM output function (Support for PWM data W10 to W15)
PS2
0
General-purpose output port (P2) function
General-purpose output function (High or low level output)
PWM output function (Support for PWM data W20 to W25)
1
PS3
0
General-purpose output port (P3) function
General-purpose output function (High or low level output)
PWM output function (Support for PWM data W30 to W35)
1
PS4
0
General-purpose output port (P4) function
General-purpose output function (High or low level output)
PWM output function (Support for PWM data W10 to W15)
1
(2) EXF … External clock operating frequency setting control data
This control data sets the operating frequency of the external clock which input into the OSCI pin, when the external
clock operating mode (OC=”1”) is set. However, this control data is effective only when external clock operating
mode (OC= "1") is set.
EXF
External clock operating frequency f [kHz]
CK
0
f
1=300[kHz]typ
CK
f
1
2=38[kHz]typ
CK
No.A1953-13/27
LC75839PW
(3) P0 to P2 … Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4
output pins.
Control data
Output pin state
S2/P2 S3/P3
S2 S3
P0
0
P1
0
P2
0
S1/P1
S1
S4/P4
S4
0
0
1
P1
S2
P2
P2
P2
S3
S3
P3
P3
S4
0
1
0
P1
S4
0
1
1
P1
S4
Note: Sn (n=1 to 4): Segment output ports
Pn (n=1 to 4): General-purpose output ports
1
0
0
P1
P4
Note: When are setting (P0,P1,P2)=(1,0,1), (1,1,0), and (1,1,1), the all P1/S1 to P4/S4 output pins selects the
segment output port.
The table below lists the correspondence between the display data and the output pins when these pins are selected
to be general-purpose output ports.
Correspondence display data
Output pin
1/4 duty
1/3 duty
S1/P1
S2/P2
S3/P3
S4/P4
D1
D1
D5
D4
D9
D7
D13
D10
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level when the display data D13 is 1, and will output a low level when
D13 is 0.
(4) DT … 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
This control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive.
DT
Drive scheme
The COM4/S51 pin state
0
1/4-duty 1/3-bias drive
1/3-duty 1/3-bias drive
COM4
S51
Note: COM4: Common output
S51 : Segment output
1
(5) DN … S52 pin and S53/OSCI pin state setting control data
This control data bit sets state of the S52 pin and the S53/OSCI pin.
Number of display segments
DN
Pin state
1/4 duty
1/3 duty
S52
S53/OSCI
0
Up to 200 segments
Up to 208 segments
Up to 153 segments
Up to 159 segments
“L” (V
)
“L” (V )/OSCI
SS
SS
1
S52
S53/OSCI
Note: “L” (V
S52
)
: Low (V ) level output
SS
: Segment output
SS
“L” (V )/OSCI : Low (V ) level output in internal oscillator operating mode (OC=0)
SS
SS
: External clock input in external clock operating mode (OC=1)
S53/OSCI
: Segment output in internal oscillator operating mode (OC=0)
External clock input in external clock operating mode (OC=1)
No.A1953-14/27
LC75839PW
(6) FC0 to FC2 … Common/segment output waveform fram frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
Frame frequency fo[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
External clock operating mode
(The control data OC is 1
External clock operating mode
(The control data OC is 1
FC0
FC1
FC2
and EXF is 0, f 1=300[kHz]typ)
CK
and EXF is 1, f 2=38[kHz]typ)
CK
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fosc/6144
fosc/4608
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/6144
1/4608
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/768
2/576
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, f 1/3072, f 2/384).
CK CK
(7) OC … Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
I/O pin (S53/OSCI) state
OC
Fundamental clock operating mode
Internal oscillator operating mode
External clock operating mode
0
S53
1
OSCI
Note: S53: Segment output
OSCI: External clock input
(8) SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
Off
1
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
(9) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
Mode
0
Normal mode
Power saving mode
In this mode, the internal oscillator circuit stops oscillation (the S53/OSCI pin is configured for segment
output) if the IC is in the internal oscillator operating mode (OC=0) and the IC stops receiving external
clock signals (the S53/OSCI pin is configured for external clock input) if the IC is in the external clock
1
operating mode (OC=1). The common and segment output pins go to the V
SS
level. However, the S1/P1
to S4/P4 output pins can be used as general-purpose output ports under the control of the data bits P0 to
P2. (The general-purpose output port P1 to P4 can not be used as clock output or PWM output.)
No.A1953-15/27
LC75839PW
(10) PF0 to PF3 … PWM output waveform frame frequency setting control data
These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the f 2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1"), these control data bits become
CK
invalid.
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
External clock operating mode
PF0
PF1
PF2
PF3
(The control data OC is 0,
fosc=300[kHz] typ)
(The control data OC is 1 and EXF is 0,
f
1=300[kHz] typ)
CK
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
fosc/1536
fosc/1408
fosc/1280
fosc/1152
fosc/1024
fosc/896
fosc/768
fosc/640
fosc/512
fosc/384
fosc/256
f
f
f
f
f
1/1536
1/1408
1/1280
1/1152
1/1024
1/896
CK
CK
CK
CK
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
CK
f
CK
CK
CK
CK
CK
CK
f
f
f
f
f
1/768
1/640
1/512
1/384
1/256
Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame
frequency at the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, f 1/896).
CK
X: don’t care
No.A1953-16/27
LC75839PW
(11) W10 to W15, W20 to W25, W30 to W35 … PWM data of the PWM output
These control data bits set the pulse width of the PWM output P1 to P4. However, when the PWM output function
isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the
f
2=38[kHz]typ (EXF="1") in external clock operating mode (OC= "1"), these control data bits become invalid.
CK
Pulse width of
Pulse width of
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
PWM output
PWM output
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1/64)×Tp
(2/64)×Tp
(3/64)×Tp
(4/64)×Tp
(5/64)×Tp
(6/64)×Tp
(7/64)×Tp
(8/64)×Tp
(9/64)×Tp
(10/64)×Tp
(11/64)×Tp
(12/64)×Tp
(13/64)×Tp
(14/64)×Tp
(15/64)×Tp
(16/64)×Tp
(17/64)×Tp
(18/64)×Tp
(19/64)×Tp
(20/64)×Tp
(21/64)×Tp
(22/64)×Tp
(23/64)×Tp
(24/64)×Tp
(25/64)×Tp
(26/64)×Tp
(27/64)×Tp
(28/64)×Tp
(29/64)×Tp
(30/64)×Tp
(31/64)×Tp
(32/64)×Tp
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(33/64)×Tp
(34/64)×Tp
(35/64)×Tp
(36/64)×Tp
(37/64)×Tp
(38/64)×Tp
(39/64)×Tp
(40/64)×Tp
(41/64)×Tp
(42/64)×Tp
(43/64)×Tp
(44/64)×Tp
(45/64)×Tp
(46/64)×Tp
(47/64)×Tp
(48/64)×Tp
(49/64)×Tp
(50/64)×Tp
(51/64)×Tp
(52/64)×Tp
(53/64)×Tp
(54/64)×Tp
(55/64)×Tp
(56/64)×Tp
(57/64)×Tp
(58/64)×Tp
(59/64)×Tp
(60/64)×Tp
(61/64)×Tp
(62/64)×Tp
(63/64)×Tp
(64/64)×Tp
Note: W10 to W15 … PWM data of the output pin S1/P1 and S4/P4
W20 to W25 … PWM data of the output pin S2/P2
n=1 to 3
1
W30 to W35 … PWM data of the output pin S3/P3
Tp=
fp
No.A1953-17/27
LC75839PW
Display Data and Output Pin Correspondence (1/4 Duty)
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
COM2
COM3
COM4
Output pin
COM1
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
COM2
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
COM3
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
COM4
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D1
D2
D3
D4
S27
D5
D6
D7
D8
S28
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
S29
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
S30
S31
S6
S32
S7
S33
S8
S34
S9
S35
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S52
S53/OSCI
Note: This table assumes that pins S1/P1 to S4/P4 and S53/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81
0
D82
0
D83
0
D84
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
The LCD segment corresponding to COM2 is on.
0
1
0
0
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segments corresponding to COM2, COM3, and COM4 are on.
The LCD segment corresponding to COM1 is on.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1, COM3, and COM4 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM4 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
No.A1953-18/27
LC75839PW
Display Data and Output Pin Correspondence (1/3 Duty)
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
COM2
COM3
Output pin
COM1
COM2
D83
COM3
D84
D1
D2
D3
S28
D82
D4
D5
D6
S29
D85
D86
D87
D7
D8
D9
S30
D88
D89
D90
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
S31
D91
D92
D93
S32
D94
D95
D96
S6
S33
D97
D98
D99
S7
S34
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
S8
S35
S9
S36
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51/COM4
S52
S53/OSCI
Note: This table assumes that pins S1/P1 to S4/P4, S51/COM4, and S53/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D61
0
D62
0
D63
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
The LCD segment corresponding to COM3 is on.
0
0
1
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segment corresponding to COM1 is on.
1
0
0
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
0
1
1
1
No.A1953-19/27
LC75839PW
Output waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
V
V
DD
DD
DD
1
2
COM1
COM2
COM3
COM4
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
1
2
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when only LCD segments
corresponding to COM3 are on.
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
0V
V
V
V
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
1
2
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when only LCD segments
corresponding to COM4 are on.
0V
V
V
V
DD
DD
DD
1
2
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
0V
V
V
V
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
1
2
0V
Control data
FC1
Frame frequency fo[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
External clock operating mode
(The control data OC is 1
and EXF is 0, f 1=300[kHz]typ)
CK
External clock operating mode
(The control data OC is 1
and EXF is 1, f 2=38[kHz]typ)
CK
FC0
FC2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fosc/6144
fosc/4608
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/6144
1/4608
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/768
2/576
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, f 1/3072, f 2/384).
CK CK
No.A1953-20/27
LC75839PW
Output waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
V
V
DD
DD
DD
1
2
COM1
COM2
COM3
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM1 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM2 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when only LCD segments
corresponding to COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
1
2
0V
V
V
V
DD
DD
DD
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are on.
1
2
0V
Control data
FC1
Frame frequency fo[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
External clock operating mode
(The control data OC is 1
and EXF is 0, f 1=300[kHz]typ)
CK
External clock operating mode
(The control data OC is 1
and EXF is 1, f 2=38[kHz]typ)
CK
FC0
FC2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fosc/6144
fosc/4608
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/6144
1/4608
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/768
2/576
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, f 1/3072, f 2/384).
CK CK
No.A1953-21/27
LC75839PW
PWM output waveforms
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
P1/P4
(56/64)×Tp
(56/64)×Tp
(48/64)×Tp
(40/64)×Tp
(1)
(2)
(3)
P2
(48/64)×Tp
(40/64)×Tp
P3
P1/P4
P2
(8/64)×Tp
(8/64)×Tp
(16/64)×Tp
(24/64)×Tp
(32/64)×Tp
(32/64)×Tp
(32/64)×Tp
(16/64)×Tp
(24/64)×Tp
(32/64)×Tp
(32/64)×Tp
(32/64)×Tp
P3
P1/P4
P2
P3
1
fp
Tp=
Tp
Tp
Control data
PWM output
waveforms
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
0
0
(1)
(2)
(3)
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz] typ)
External clock operating mode
(The control data OC is 1 and
PF0
PF1
PF2
PF3
EXF is 0, f 1=300[kHz] typ)
CK
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
fosc/1536
fosc/1408
fosc/1280
fosc/1152
fosc/1024
fosc/896
fosc/768
fosc/640
fosc/512
fosc/384
fosc/256
f
f
f
f
f
1/1536
1/1408
1/1280
1/1152
1/1024
1/896
CK
CK
CK
CK
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
CK
f
CK
CK
CK
CK
CK
CK
f
f
f
f
f
1/768
1/640
1/512
1/384
1/256
Note: When is setting (PF0,PF1,PF2,PF3)=(1,1,0,1) and (X,X,1,1), the frame frequency is same as frame frequency at
the time of the (PF0,PF1,PF2,PF3)=(1,0,1,0) setting (fosc/896, f 1/896). X: don’t care
CK
No.A1953-22/27
LC75839PW
Clock output waveforms
Control data
Clock frequency of clock output P1
fc(=1/Tc)[Hz]
PS10
PS11
P1
Tc/2
1
0
0
1
Clock output function (fosc/2, f /2)
CK
Clock output function (fosc/8, f /8)
CK
Tc
1
Tc=
fc
No.A1953-23/27
LC75839PW
Display Control and the INH Pin
Since the LSI internal data (1/4 duty : the display data D1 to D208 and the control data, 1/3 duty : the display data D1 to
D159 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S50, COM1 to COM3, COM4/S51,
S52, and S53/OSCI pins to the V level.) and during this period send serial data from the controller. The controller
SS
should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless display at
power on.
(See Figure 5, Figure 6.)
(1)1/4 duty
t1
t2
V
DD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
D1 to D52,PS10,PS11,
EXF,P0 to P2,DT,DN,
FC0 to FC2,OC,SC,BU
Defined
Internal data
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
D53 to D104,PS2 to PS4,
PF0 to PF3
Internal data
Internal data
Defined
Defined
D105 to D152,W10 to W15,
W20 to W25, W30 to W35
Internal data (D153 to D208)
Defined
Undefined
Notes: t1>1ms
t2>0
tc…10μs min
[Figure 5]
(2)1/3 duty
t2
t1
V
DD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
D1 to D54,PS10,PS11,
EXF,P0 to P2,DT,DN,
FC0 to FC2,OC,SC,BU
Internal data
Internal data
Internal data
Undefined
Defined
Defined
Undefined
Undefined
Undefined
D55 to D108,PS2 to PS4,
PF0 to PF3
Undefined
Undefined
D109 to D159,W10 to W15,
W20 to W25, W30 to W35
Defined
Notes: t1>1ms
t2>0
tc…10μs min
[Figure 6]
No.A1953-24/27
LC75839PW
Notes on Controller Transfer of Display Data
When using the LC75839 in 1/4 duty, applications transfer the display data (D1 to D208) in four operations, and in 1/3
duty, they transfer the display data (D1 to D159) in three operations. In either case, applications should transfer all of
the display data within 30 ms to maintain the quality of displayed image.
S53/OSCI Pin Peripheral Circuit
(1) Internal oscillator operating mode (control data OC=0)
Connect the S53/OSCI pin to the LCD panel when the internal oscillator operating mode is selected.
OSCI/S53
To LCD panel
(2) External clock operating mode (control data OC=1)
When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22kΩ) between
the S53/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according
to the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
External clock output pin
External oscillator
OSCI/S53
Rg
V
DD
Rg
Note: Allowable current value at external clock output pin >
(3) Unused pin treatment
When the S53/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0)
to keep the pin open.
OPEN
OSCI/S53
P1 to P4 pin peripheral circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output
P1 to P4
+5V
LED
P1 to P4
No.A1953-25/27
LC75839PW
Sample Applications Circuit1
1/4 Duty, 1/3 Bias
General-purpose
output ports
(P1)
(P2)
(P3)
(P4)
Used for functions
such as backlight
control
+5V
V
V
COM1
COM2
COM3
S51/COM4
P1/S1
DD
1
DD
V
V
2
DD
C
C
P2/S2
SS
P3/S3
P4/S4
S5
C≥0.047μF
INH
CE
CL
DI
From the
controller
S50
S52
*2
*3 OSCI/S53
*2 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3 Connect the S53/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode (see “S53/OSCI Pin Peripheral Circuit”).
Sample Application Circuit 2
1/3 Duty, 1/3 Bias
General-purpose
output ports
(P1)
(P2)
(P3)
(P4)
Used for functions
such as backlight
control
+5V
V
V
COM1
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
DD
DD
1
V
V
2
DD
C
C
SS
C≥0.047μF
S50
COM4/S51
S52
INH
CE
CL
DI
From the
controller
*2
OSCI/S53
*3
*2 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3 Connect the S53/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode (see “S53/OSCI Pin Peripheral Circuit”).
No.A1953-26/27
LC75839PW
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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intellectual property rights which has resulted from the use of the technical information and products mentioned
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This catalog provides information as of June, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1953-27/27
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