LC75897PW [SANYO]
1/3, 1/4-Duty General-Purpose LCD Display Driver; 三分之一，四分之一，职务通用液晶显示驱动
| 型号： | LC75897PW |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/3, 1/4-Duty General-Purpose LCD Display Driver |
| 文件： | 总34页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN*A0549
CMOS IC
1/3, 1/4-Duty General-Purpose
LCD Display Driver
LC75897PW
Overview
The LC75897PW is 1/3 duty and 1/4 duty general-purpose LCD display driver that can be used for frequency display in
electronic tuners under the control of a microcontroller. The LC75897PW can drive an LCD with up to 512 segments
directly. The LC75897PW can also control up to 8 general-purpose output ports. The LC75897PW has a built-in of up to
three PWM output port channels, which enables to adjust the brightness of the RGB LED backlight.
Features
• Switching between 1/3 duty and 1/4 duty drive techniques under serial data control.
• Switching between 1/2 bias and 1/3 bias drive techniques under serial data control.
• Up to 387 segments for 1/3 duty drive and 512 segments for 1/4 duty drive can be displayed.
• Switching between the segment, general-purpose, PWM, and clock output ports can be controlled using serial data
(up to 8 general-purpose output ports, up to 3-channel PWM output ports, and one clock output port).
• Serial data input supports CCB format communication with the system controller.
• Serial data control of the power-saving mode based backup function and all the segments forced off function.
• Serial data control of the frame frequency for common and segment output waveforms.
• Serial data control of switching between the RC oscillator operating mode and external clock operating mode.
• High generality, since display data is displayed directly without decoder intervention.
• Built-in display contrast adjustment circuit
• Independent V
for the LCD driver block
LCD
• The INH pin can force the display to the off state.
• RC oscillator circuit
• CCB is a trademark of SANYO Electric Co., Ltd.
• CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
'
s products or
equipment.
41807HKIM No.A0549-1/34
LC75897PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0V
SS
Parameter
Symbol
Conditions
Ratings
-0.3 to +7.0
Unit
V
Maximum supply voltage
V
max
V
V
DD
DD
V
max
1
-0.3 to +7.0
-0.3 to +7.0
LCD
V
LCD
INH
2
Input voltage
CE, CL, DI,
OSC
IN
V
V
2
V
-0.3 to V +0.3
DD
IN
IN
3
V
1, V
-0.3 to V
+0.3
LCD
LCD
LCD
Output voltage
Output current
V
1
OSC
V
-0.3 to V +0.3
DD
OUT
OUT
V
V
I
2
0, S1 to S129, COM1 to COM4, P1 to P8
-0.3 to V
+0.3
300
3
LCD
LCD
1
S1 to S129
COM1 to COM4
P1 to P8
µA
mA
OUT
OUT
OUT
I
I
2
3
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
200
mW
°C
-40 to +85
Tstg
-55 to +125
°C
Allowable Operating Ranges at Ta = -40 to +85°C, V = 0V
SS
Ratings
typ
Parameter
Supply voltage
Symbol
Conditions
unit
V
min
max
6.0
V
V
2.7
4.0
DD
DD
V
V
V
,
LCD
LCD
LCD
6.0
6.0
0 = 0.70V
LCD
to 0.95V
LCD
V
V
V
V
, V
0 = V
LCD
2.7
2.7
LCD LCD
Output voltage
Input voltage
V
V
V
0
1
2
0
V
V
V
LCD
LCD
LCD
LCD
LCD
1
2/3V
0
0
V
V
0
LCD
LCD
LCD
2
1/3V
LCD
0
LCD
LCD
INH
Input high-level voltage
Input low-level voltage
V
1
2
CE, CL, DI,
OSC external clock operating mode
INH
0.8V
0.7V
6.0
IH
DD
V
V
V
V
V
IH
DD
0
DD
DD
DD
1
CE, CL, DI,
0.2V
0.3V
IL
IL
V
2
OSC external clock operating mode
OSC RC oscillator operating mode
0
Recommended external resistor
for RC oscillation
R
C
f
OSC
10
kΩ
Recommended external capacitor
for RC oscillation
OSC RC oscillator operating mode
OSC RC oscillator operating mode
OSC
470
300
300
pF
Guaranteed range of RC oscillation
150
150
600
600
kHz
kHz
OSC
External clock operating frequency
f
OSC external clock operating mode
[Figure 4]
CK
External clock duty cycle
D
OSC external clock operating mode
[Figure 4]
CK
30
50
70
%
Data setup time
Data hold time
CE wait time
tds
tdh
tcp
tcs
tch
tφH
tφL
tr
CL,DI
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 2],[ Figure 3]
[Figure 5],[ Figure 6]
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
160
160
160
160
160
160
160
CL,DI
CE,CL
CE,CL
CE,CL
CL
CE setup time
CE hold time
High-level clock pulse width
Low-level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
160
160
Fall time
tf
INH
, CE
switching time
tc
INH
10
No.A0549-2/34
LC75897PW
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Pin
Conditions
unit
V
min
max
INH
INH
Hysteresis
V
H
CE, CL, DI,
CE, CL, DI,
OSC
0.1V
DD
Input high-level current
Input low-level current
Output high-level voltage
I
I
1
V = 6.0V
I
5.0
5.0
IH
IH
µA
µA
2
V = V
I
DD
External clock operating mode
INH
I
1
2
CE, CL, DI,
OSC
V = 0V
I
-5.0
-5.0
IL
I
V = 0V
I
IL
External clock operating mode
V
V
V
1
S1 to S129
I
I
I
I
I
I
= -20µA
= -100µA
= -1mA
= 20µA
= 100µA
= 1mA
V
V
0-0.9
0-0.9
-0.9
OH
OH
OH
O
O
O
O
O
O
LCD
2
3
1
2
3
COM1 to COM4
P1 to P8
V
V
LCD
V
LCD
Output low-level voltage
V
V
V
S1 to S129
0.9
0.9
0.9
OL
OL
OL
COM1 to COM4
P1 to to P8
Output middle-level
V
V
V
V
V
f
1
2
3
4
5
COM1 to COM4
1/2 bias, I = ±100µA
1/2V
2/3V
1/3V
2/3V
1/3V
0
1/2V
2/3V
1/3V
2/3V
1/3V
0
MID
MID
MID
MID
MID
O
LCD
-0.9
LCD
+0.9
voltage *1
S1 to S129
S1 to S129
COM1 to COM4
COM1 to COM4
OSC
1/3 bias, I = ±20µA
0
0
O
LCD
-0.9
LCD
+0.9
1/3 bias, I = ±20µA
0
0
O
LCD
-0.9
LCD
+0.9
V
1/3 bias, I = ±100µA
0
0
O
LCD
-0.9
LCD
+0.9
1/3 bias, I = ±100µA
0
0
LCD
O
LCD
-0.9
+0.9
390
Oscillator frequency
Current drain
RC oscillator operating mode
OSC
R
C
= 10kΩ
210
300
700
kHz
OSC
OSC
= 470pF
I
1
2
V
Power-saving mode
10
1400
15
DD
DD
I
V
V = 6.0V, output open,
DD
DD
DD
f
= 300kHz
OSC
I
I
1
2
V
Power-saving mode
V = 6.0V, output open,
LCD
LCD
V
LCD
LCD
LCD
1/2 bias, f
= 300kHz,
600
500
450
350
1200
1000
900
OSC
0 = 0.70V
V
to 0.95V
LCD
LCD
LCD
= 6.0V, output open,
= 300kHz,
I
I
I
3
4
5
V
V
LCD
LCD
LCD
LCD
LCD
µA
1/2 bias, f
OSC
0 = V
V
LCD
LCD
= 6.0V, output open,
= 300kHz,
V
V
LCD
LCD
1/3 bias, f
OSC
0 = 0.70V
V
to 0.95V
LCD
LCD
LCD
= 6.0V, output open,
= 300kHz,
V
V
LCD
LCD
1/3 bias, f
700
OSC
V
0 = V
LCD LCD
Note: *1 Excluding the bias voltage generation divider resistors built in the V
(See Figure 1.)
0, V
1, V 2, and V .
LCD LCD SS
LCD
V
LCD
CONTRAST
ADJUSTER
V
0
1
2
LCD
LCD
LCD
V
V
To the common and segment drivers
Except these resistors.
V
SS
Figure 1
No.A0549-3/34
LC75897PW
1. When CL is stopped at the low level
V
1
IH
CE
V 1
IL
tφH
tφL
V
1
IH
50%
CL
DI
V
1
IL
tr
tf
tch
tcp tcs
V
1
1
IH
V
IL
tds
tdh
Figure 2
2. When CL is stopped at the high level
V
1
IH
CE
V
1
IL
tφL
tφH
V
1
IH
50%
CL
DI
V
1
IL
tf
tr
tch
tcp tcs
V
1
IH
V
1
IL
tds
tdh
Figure 3
3. OSC pin clock timing in external clock operating mode
1
t
H
t
L
CK
CK
f
=
[kHz]
CK
t
t
H+t
L
L
CK
CK
CK
V
2
IH
50%
IL
OSC
t
H
V
2
CK
H+t
D
=
×100[%]
CK
CK
Figure 4
No.A0549-4/34
LC75897PW
Package Dimensions
unit : mm (typ)
3214A
22.0
20.0
108
73
109
72
144
37
1
36
0.145
0.5
0.2
(1.25)
SANYO : SQFP144 (20X20)
Pin Assignment
108
73
72
109
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
LC75897PW
S126
S127
S128
S129/COM4
COM3
COM2
COM1
V
LCD
DD
V
V
V
V
0
1
2
SS
SS
LCD
LCD
LCD
V
V
OSC
INH
CE
CL
DI
144
37
1
36
Top view
No.A0549-5/34
LC75897PW
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER & LATCH
INH
CLOCK
GENERATOR
CONTROL
REGISTER
OSC
V
DD
V
LCD
SHIFT REGISTER
CONTRAST
ADJUSTER
CCB INTERFACE
V
V
V
0
1
2
LCD
LCD
LCD
V
SS
No.A0549-6/34
LC75897PW
Pin Functions
Handling
when
Symbol
Pin No.
Function
Active
-
I/O
O
unused
OPEN
S1/P1 to S8/P8
S9 to S128
1 to 8
Segment outputs for displaying the display data transferred by serial data
input. Also, by the control data, S1/P1 to S3/P3 can be used as a general-
purpose output port or PWM output port, while S4/P4 can be used as a
general-purpose output port or clock output port and S5/P5 to S8/P8 can be
used as a general-purpose output port.
9 to 128
COM1 to COM3
COM4/S129
OSC
132 to 130
129
Common driver outputs. The frame frequency is fo [Hz]. The COM4/S129 pin
can be used as a segment output in 1/3 duty.
-
-
O
OPEN
140
Oscillator connection. An oscillator circuit is formed by connecting an
external resistor and capacitor to this pin. This pin can also be used as the
external clock input pin as controlled by control data.
Serial data transfer inputs. These pins are connected to the control
microprocessor.
I/O
V
DD
CE
CL
DI
142
143
144
H
-
I
I
I
GND
GND
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
INH
141
Display off control input
L
I
INH
•
= low (V ) ...Off
SS
S1/P1 to S8/P8 = low (V
)
SS
(These pins are forcibly set to the segment output port
function and fixed at the V
level.)
SS
S9 to S128 = low (V
)
SS
COM1 to COM3 = low (V
)
SS
COM4/S129 = low (V
)
SS
OSC = "Z" (high impedance)
RC oscillation stopped
External clock input inhibited
Display contrast adjustment circuit stopped
= high (V ) ...On
INH
•
DD
RC oscillation enabled (RC oscillator operating mode)
Enables external clock input (external clock operating
mode).
Display contrast adjustment circuit enabled
Note that serial data transfers can be performed when the display is forced
off by this pin.
V
0
135
LCD drive 3/3 bias voltage (high level) supply. This level can be modified
-
O
OPEN
LCD
using the display contrast adjustment circuit. However, note that V
0
LCD
must be greater than or equal to 2.7V. Also, since this IC provides the built-
in display contrast adjustment circuit, applications must not attempt to
provide this level from external circuits.
V
V
1
2
136
137
LCD drive 2/3 bias voltage (middle level) supply. It is possible to supply the
-
-
I
I
OPEN
OPEN
LCD
2/3V
0 voltage to this pin externally. This pin must be shorted to V
LCD
2
LCD
if 1/2 bias is used.
LCD drive 1/3 bias voltage (middle level) supply. It is possible to supply the
1/3V 0 voltage to this pin externally. This pin must be shorted to V
LCD
1
LCD
LCD
if 1/2 bias is used.
V
133
134
Logic block power supply. Provide a voltage in the range 2.7 to 6.0V.
-
-
-
-
-
-
DD
V
LCD driver block power supply. When V
0 is between 0.70V
and
LCD
LCD
LCD
0 and
0.95V
, supply a voltage in the range 4.0 to 6.0V. When V
LCD LCD
V
will be equal, supply a voltage in the range 2.7 to 6.0V.
LCD
V
138,139
Ground pin. Connect to ground.
-
-
-
SS
No.A0549-7/34
LC75897PW
Serial Data Transfer Formats
(1) 1/3 duty
1. When CL is stopped at the low level
• When the display data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119
1
D120 D121 D122 D123 D124D125 D126 D127D128 D129
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
0
1
1
0
0
0
0
1
D130
D241 D242 D243 D244 D245D246 D247 D248
0
D249 D250 D251 D252 D253D254 D255 D256D257 D258
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
0
1
1
0
0
0
0
1
D259
D370 D371 D372 D373 D374D375 D376 D377
1
D378 D379 D380 D381 D382D383 D384 D385D386 D387
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0
0
0
0
DD
3 bits
Note: DD is the direction data.
No.A0549-8/34
LC75897PW
2. When CL is stopped at the high level
• When the display data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119
1
D120 D121 D122 D123 D124D125 D126 D127D128 D129
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
0
1
1
0
0
0
0
1
D130
D241 D242 D243 D244 D245D246 D247 D248
0
D249 D250 D251 D252 D253D254 D255 D256D257 D258
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
0
1
1
0
0
0
0
1
D259
D370 D371 D372 D373 D374D375 D376 D377
1
D378 D379 D380 D381 D382D383 D384 D385D386 D387
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
129 bits
Fixed data
4 bits
DD
3 bits
No.A0549-9/34
LC75897PW
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0
0
0
0
DD
3 bits
Note: DD is the direction data.
• CCB address ....... "86H"
• D1 to D387 ......... Display data
• W10 to W15, W20 to W25, W30 to W35
......... PWM data at PWM output ports
• PC1 to PC8 ......... General-purpose output port state setting control data
• PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8
......... Segment output port/general-purpose output port/PWM output port/clock output port switching
control data
• CT0 to CT2 ......... Display contrast setting control data
• DR ...................... 1/2 bias drive or 1/3 bias drive switching control data
• DT ...................... 1/3 duty drive or 1/4 duty drive switching control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• FC0 to FC2 ......... Common and segment output waveforms frame frequency setting control data
• PF0 to PF2 ......... PWM output waveforms frame frequency setting control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0549-10/34
LC75897PW
(2) 1/4 duty
1. When CL is stopped at the low level
• When the display data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119
1
D120 D121 D122 D123 D124D125 D126 D127D128
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
0
1
1
0
0
0
0
1
D129
D240 D241 D242 D243 D244D245 D246 D247
0
D248 D249 D250 D251 D252D253 D254 D255D256
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
0
1
1
0
0
0
0
1
D257
D368 D369 D370 D371 D372D373 D374 D375
1
D376 D377 D378 D379 D380D381 D382 D383D384
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
0
1
1
0
0
0
0
1
D385
D496 D497 D498 D499 D500D501 D502 D503
0
D504 D505 D506 D507 D508D509 D510 D511D512
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0
0
0
0
DD
3 bits
Note: DD is the direction data.
No.A0549-11/34
LC75897PW
2. When CL is stopped at the high level
• When the display data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
D1
D112 D113 D114 D115 D116D117 D118 D119
1
D120 D121 D122 D123 D124D125 D126 D127D128
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
0
1
1
0
0
0
0
1
D129
D240 D241 D242 D243 D244D245 D246 D247
0
D248 D249 D250 D251 D252D253 D254 D255D256
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
0
1
1
0
0
0
0
1
D257
D368 D369 D370 D371 D372D373 D374 D375
1
D376 D377 D378 D379 D380D381 D382 D383D384
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
0
1
1
0
0
0
0
1
D385
D496 D497 D498 D499 D500D501 D502 D503
0
D504 D505 D506 D507 D508D509 D510 D511D512
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
128 bits
Fixed data
5 bits
DD
3 bits
No.A0549-12/34
LC75897PW
• When the control data is transferred
CE
CL
DI
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
PS10 PS11 PS20 PS21 PS30 PS31 PS40 PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0
0
0
0
DD
3 bits
Note: DD is the direction data.
• CCB address ....... "86H"
• D1 to D512 ......... Display data
• W10 to W15, W20 to W25, W30 to W35
......... PWM data at PWM output ports
• PC1 to PC8 ......... General-purpose output port state setting control data
• PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8
......... Segment output port/general-purpose output port/PWM output port/clock output port switching
control data
• CT0 to CT2 ......... Display contrast setting control data
• DR ...................... 1/2 bias drive or 1/3 bias drive switching control data
• DT ...................... 1/3 duty drive or 1/4 duty drive switching control data
• OC ...................... RC oscillator operating mode/external clock operating mode switching control data
• FC0 to FC2 ......... Common and segment output waveforms frame frequency setting control data
• PF0 to PF2 ......... PWM output waveforms frame frequency setting control data
• SC ...................... Segments on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0549-13/34
LC75897PW
Serial Data Transfer Example
(1) 1/3 duty
• When 259 or more segments are used
All 496 bits of serial data (including CCB addresses) must be sent.
56 bits
8 bits
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10PS11PS20PS21PS30PS31PS40PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0
0
0
0
8 bits
136 bits
0
1
1
0
0
0
0
1
D1
D130
D259
D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128 D129
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
B0 B1 B2 B3 A0 A1 A2 A3
0
1
1
0
0
0
0
1
D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258
D370 D371 D372 D373 D374 D375 D376 D377 D378 D379 D380 D381 D382 D383 D384 D385 D386 D387
B0 B1 B2 B3 A0 A1 A2 A3
0
1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 259 segments are used
Either 208 or 352 bits (including CCB addresses) of serial data may be sent, depending on the number of
segments used. However, the serial data shown below (control data) must be sent.
56 bits
8 bits
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10PS11PS20PS21PS30PS31PS40PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0 0 0 0
No.A0549-14/34
LC75897PW
(2) 1/4 duty
• When 385 or more segments are used
All 640 bits of serial data (including CCB addresses) must be sent.
56 bits
8 bits
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10PS11PS20PS21PS30PS31PS40PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0
0
0
0
136 bits
8 bits
0
1
1
0
0
0
0
1
D1
D129
D257
D385
D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
0
1
1
0
0
0
0
1
D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256
D368 D369 D370 D371 D372 D373 D374 D375 D376 D377 D378 D379 D380 D381 D382 D383 D384
D496 D497 D498 D499 D500 D501 D502 D503 D504 D505 D506 D507 D508 D509 D510 D511 D512
B0 B1 B2 B3 A0 A1 A2 A3
0
1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
0
1 1 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 385 segments are used
Either 208, 352 or 496 bits (including CCB addresses) of serial data may be sent, depending on the number of
segments used. However, the serial data shown below (control data) must be sent.
56 bits
8 bits
0
1
1
0
0
0
0
1
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8
B0 B1 B2 B3 A0 A1 A2 A3
PS10PS11PS20PS21PS30PS31PS40PS41 PS5 PS6 PS7 PS8 CT0 CT1 CT2 DR DT OC FC0 FC1 FC2 PF0 PF1 PF2 SC BU
0 0 0 0
No.A0549-15/34
LC75897PW
Control Data Functions
(1) W10 to W15, W20 to W25, W30 to W35: PWM data at PWM output ports
This control data determines the pulse width of the PWM at PWM output ports P1/S1 to P3/S3.
Pulse width of
Pulse width of
PWM output
port Pn
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
PWM output
port Pn
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1/64)×Tp
(2/64)×Tp
(3/64)×Tp
(4/64)×Tp
(5/64)×Tp
(6/64)×Tp
(7/64)×Tp
(8/64)×Tp
(9/64)×Tp
(10/64)×Tp
(11/64)×Tp
(12/64)×Tp
(13/64)×Tp
(14/64)×Tp
(15/64)×Tp
(16/64)×Tp
(17/64)×Tp
(18/64)×Tp
(19/64)×Tp
(20/64)×Tp
(21/64)×Tp
(22/64)×Tp
(23/64)×Tp
(24/64)×Tp
(25/64)×Tp
(26/64)×Tp
(27/64)×Tp
(28/64)×Tp
(29/64)×Tp
(30/64)×Tp
(31/64)×Tp
(32/64)×Tp
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(33/64)×Tp
(34/64)×Tp
(35/64)×Tp
(36/64)×Tp
(37/64)×Tp
(38/64)×Tp
(39/64)×Tp
(40/64)×Tp
(41/64)×Tp
(42/64)×Tp
(43/64)×Tp
(44/64)×Tp
(45/64)×Tp
(46/64)×Tp
(47/64)×Tp
(48/64)×Tp
(49/64)×Tp
(50/64)×Tp
(51/64)×Tp
(52/64)×Tp
(53/64)×Tp
(54/64)×Tp
(55/64)×Tp
(56/64)×Tp
(57/64)×Tp
(58/64)×Tp
(59/64)×Tp
(60/64)×Tp
(61/64)×Tp
(62/64)×Tp
(63/64)×Tp
(64/64)×Tp
Note: Wn0 to Wn5 (n = 1 to 3): PWM data at output pins S1/P1 to S3/P3
1
Tp =
fp
(2) PC1 to PC8: General-purpose output port state setting control data
This control data is used to set the high/low state of general-purpose output ports P1 to P8.
Output pins
P1
P2
P3
P4
P5
P6
P7
P8
Control data
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
Note: PCn = 1: The output pin Pn is set high (V
) (n = 1 to 8).
LCD
PCn = 0: The output pin Pn is set low (V ) (n = 1 to 8).
SS
For example, if output pins S4/P4 and S5/P5 are selected as general-purpose output ports, setting PC4 to 1 and PC5 to 0
causes the output pin P4 to be set high (V ) and P5 to be set low (V ).
LCD SS
No.A0549-16/34
LC75897PW
(3) PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, PS5 to PS8: Segment output port/general-purpose output
port/PWM output port/clock output port switching control data
This control data is used to set the state of output pins S1/P1 to S8/P8.
PS10 and PS11: Output pin (S1/P1) state settings
PS20 and PS21: Output pin (S2/P2) state settings
PS10
PS11
Output pin (S1/P1) state
PS20
PS21
Output pin (S2/P2) state
0
1
0
0
0
1
Segment output port (S1)
0
1
0
0
0
1
Segment output port (S2)
General-purpose output port (P1)
PWM output port (P1)
General-purpose output port (P2)
PWM output port (P2)
PS30 and PS31: Output pin (S3/P3) state settings
PS40 and PS41: Output pin (S4/P4) state settings
PS30
PS31
Output pin (S3/P3) state
PS40
PS41
Output pin (S4/P4) state
0
1
0
0
0
1
Segment output port (S3)
0
1
0
0
Segment output port (S4)
General-purpose output port (P3)
PWM output port (P3)
General-purpose output port (P4)
Clock output port (P4)
0
1
1
1
(clock frequency fosc/2, f /2)
CK
Clock output port (P4)
(clock frequency fosc/8, f /8)
CK
PS5: Output pin (S5/P5) state settings
PS6: Output pin (S6/P6) state settings
PS5
Output pin (S5/P5) state
PS6
Output pin (S6/P6) state
0
Segment output port (S5)
0
Segment output port (S6)
1
General-purpose output port (P5)
1
General-purpose output port (P6)
PS7: Output pin (S7/P7) state settings
PS8: Output pin (S8/P8) state settings
PS7
Output pin (S7/P7) state
PS8
Output pin (S8/P8) state
0
Segment output port (S7)
0
Segment output port (S8)
1
General-purpose output port (P7)
1
General-purpose output port (P8)
For example, if PS10 and PS11 are set to 0 and 1 respectively, PS20 and PS21 to 0 and 1 respectively, PS30 and PS31
to 0 and 1 respectively, PS40 and PS41 to 1 and 0 respectively, PS5 to 1, PS6 to 1, PS7 to 0, and PS8 to 0, the output
pins S1/P1 to S3/P3 are selected as PWM output ports, the output pins S4/P4 to S6/P6 as general-purpose output ports,
and the output pins S7/P7 and S8/P8 as segment output ports.
(4) CT0 to CT2: Display contrast setting control data
This control data is used to set the display contrast.
CT0 to CT2: Display contrast settings (7 steps)
CT0
CT1
CT2
Level of LCD drive bias 3/3 voltage power supply V 0
LCD
0
0
0
1.00V
0.95V
0.90V
0.85V
0.80V
0.75V
0.70V
= V
= V
= V
= V
= V
= V
= V
- (0.05V
- (0.05V
- (0.05V
- (0.05V
- (0.05V
- (0.05V
- (0.05V
×0)
×1)
×2)
×3)
×4)
×5)
×6)
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
Note that although the contrast of the display can be adjusted by running the internal display contrast adjustment circuit,
it is also possible to adjust it by changing the voltage level on the LCD driver block power supply V
pin. However,
LCD
V
0 must always be greater than or equal to 2.7V.
LCD
(5) DR: 1/2 bias drive or 1/3 bias drive switching control data
This control data bit selects either 1/2 bias drive or 1/3 bias drive.
DR
Bias drive scheme
0
1/3 bias drive
1
1/2 bias drive
No.A0549-17/34
LC75897PW
(6) DT: 1/3 duty drive or 1/4 duty drive switching control data
This control data bit selects either 1/3 duty drive or 1/4 duty drive.
DT
Duty drive scheme
Output pin state (COM4/S129)
0
1/4 duty drive
COM4
S129
1
1/3 duty drive
Note: COM4: Common output
S129: Segment output
(7) OC: RC oscillator operating mode/external clock operating mode switching control data
This control data bit selects either RC oscillator operating mode or external clock operating mode.
OC
OSC pin function
RC oscillator operating mode
External clock operating mode
0
1
Note: When selecting the RC oscillator operating mode, be sure to connect an external resistor Rosc and an external
capacitor Cosc to the OSC pin.
(8) FC0 to FC2: Common and segment output waveforms frame frequency setting control data
This control data bits set the frame frequency for the common and segment output waveforms.
Control data
Common/segment output waveform
frame frequency fo [Hz]
FC0
0
FC1
0
FC2
0
fosc/6144, f /6144
CK
1
0
0
fosc/4608, f /4608
CK
0
1
0
fosc/3072, f /3072
CK
1
1
0
fosc/2304, f /2304
CK
0
0
1
fosc/1536, f /1536
CK
(9) PF0 to PF2: PWM output waveforms frame frequency setting control data
This control data bits set the frame frequency for the PWM output waveforms.
Control data
PWM output waveform
frame frequency fp [Hz]
PF0
0
PF1
0
PF2
0
fosc/1536, f /1536
CK
1
0
0
fosc/1408, f /1408
CK
0
1
0
fosc/1280, f /1280
CK
1
1
0
fosc/1152, f /1152
CK
0
0
1
fosc/1024, f /1024
CK
1
0
1
fosc/896, f /896
CK
0
1
1
fosc/768, f /768
CK
1
1
1
fosc/640, f /640
CK
(10) SC: Segments on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
Off
1
However, note that the segments are turned off by setting SC to 1, the segments are turned off by outputing segment off
waveforms from the segment output pins.
(11) BU: Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
Mode
Normal mode
0
Power save mode
The LC75897PW stops the oscillation at the OSC pin if it is set up for the RC oscillator operating mode (OC = 0) and stops
receiving the external clock if it is set up for the external clock operating mode (OC = 1). The IC also sets the common and
1
segment output pins to the V
SS
level. The output pins S1/P1 to S8/P8, however, remain available as general-purpose
output ports as configured by control data bits PS10, PS11, PS20, PS21, PS30, PS31, PS40, PS41, and PS5 to PS8 (not
available as PWM output or clock output ports).
No.A0549-18/34
LC75897PW
Display Data to Segment Output Pin Correspondence
1. 1/3 duty
Segment
Segment
Segment
COM1
COM2
COM3
COM1
COM2
COM3
COM1
COM2
COM3
Output pins
Output pins
Output pins
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9
D1
D4
D2
D5
D3
D6
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
D130
D133
D136
D139
D142
D145
D148
D151
D154
D157
D160
D163
D166
D169
D172
D175
D178
D181
D184
D187
D190
D193
D196
D199
D202
D205
D208
D211
D214
D217
D220
D223
D226
D229
D232
D235
D238
D241
D244
D247
D250
D253
D256
D131
D134
D137
D140
D143
D146
D149
D152
D155
D158
D161
D164
D167
D170
D173
D176
D179
D182
D185
D188
D191
D194
D197
D200
D203
D206
D209
D212
D215
D218
D221
D224
D227
D230
D233
D236
D239
D242
D245
D248
D251
D254
D257
D132
D135
D138
D141
D144
D147
D150
D153
D156
D159
D162
D165
D168
D171
D174
D177
D180
D183
D186
D189
D192
D195
D198
D201
D204
D207
D210
D213
D216
D219
D222
D225
D228
D231
D234
D237
D240
D243
D246
D249
D252
D255
D258
S87
S88
D259
D262
D265
D268
D271
D274
D277
D280
D283
D286
D289
D292
D295
D298
D301
D304
D307
D310
D313
D316
D319
D322
D325
D328
D331
D334
D337
D340
D343
D346
D349
D352
D355
D358
D361
D364
D367
D370
D373
D376
D379
D382
D385
D260
D263
D266
D269
D272
D275
D278
D281
D284
D287
D290
D293
D296
D299
D302
D305
D308
D311
D314
D317
D320
D323
D326
D329
D332
D335
D338
D341
D344
D347
D350
D353
D356
D359
D362
D365
D368
D371
D374
D377
D380
D383
D386
D261
D264
D267
D270
D273
D276
D279
D282
D285
D288
D291
D294
D297
D300
D303
D306
D309
D312
D315
D318
D321
D324
D327
D330
D333
D336
D339
D342
D345
D348
D351
D354
D357
D360
D363
D366
D369
D372
D375
D378
D381
D384
D387
D7
D8
D9
S89
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
D76
D79
D82
D85
D88
D91
D94
D97
D100
D103
D106
D109
D112
D115
D118
D121
D124
D127
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
D77
D80
D83
D86
D89
D92
D95
D98
D101
D104
D107
D110
D113
D116
D119
D122
D125
D128
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D78
D81
D84
D87
D90
D93
D96
D99
D102
D105
D108
D111
D114
D117
D120
D123
D126
D129
S90
S91
S92
S93
S94
S95
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
COM4/S129
Note: This applies to the case where the S1/P1 to S8/P8, and COM4/S129 output pins are set to be segment output
ports.
No.A0549-19/34
LC75897PW
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D31
0
D32
0
D33
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
The LCD segment corresponding to COM3 is on.
0
0
1
The LCD segment corresponding to COM2 is on.
0
1
0
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segment corresponding to COM1 is on.
0
1
1
1
0
0
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
0
1
1
1
0
1
1
1
2. 1/4 duty
Segment
Segment
COM1
COM2
COM3
COM4
COM1
COM2
COM3
COM4
Output pins
Output pins
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9
D1
D5
D2
D6
D3
D7
D4
D8
D145
D149
D153
D157
D161
D165
D169
D173
D177
D181
D185
D189
D193
D197
D201
D205
D209
D213
D217
D221
D225
D229
D233
D237
D241
D245
D249
D253
D257
D261
D265
D269
D273
D277
D281
D285
D146
D150
D154
D158
D162
D166
D170
D174
D178
D182
D186
D190
D194
D198
D202
D206
D210
D214
D218
D222
D226
D230
D234
D238
D242
D246
D250
D254
D258
D262
D266
D270
D274
D278
D282
D286
D147
D151
D155
D159
D163
D167
D171
D175
D179
D183
D187
D191
D195
D199
D203
D207
D211
D215
D219
D223
D227
D231
D235
D239
D243
D247
D251
D255
D259
D263
D267
D271
D275
D279
D283
D287
D148
D152
D156
D160
D164
D168
D172
D176
D180
D184
D188
D192
D196
D200
D204
D208
D212
D216
D220
D224
D228
D232
D236
D240
D244
D248
D252
D256
D260
D264
D268
D272
D276
D280
D284
D288
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
D98
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
D99
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
D97
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
Continued on next page.
No.A0549-20/34
LC75897PW
Continued from preceding page.
Segment
Segment
COM1
COM2
COM3
COM4
COM1
COM2
COM3
COM4
Output pins
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
S95
S96
S97
S98
S99
S100
Output pins
D289
D293
D297
D301
D305
D309
D313
D317
D321
D325
D329
D333
D337
D341
D345
D349
D353
D357
D361
D365
D369
D373
D377
D381
D385
D389
D393
D397
D290
D294
D298
D302
D306
D310
D314
D318
D322
D326
D330
D334
D338
D342
D346
D350
D354
D358
D362
D366
D370
D374
D378
D382
D386
D390
D394
D398
D291
D295
D299
D303
D307
D311
D315
D319
D323
D327
D331
D335
D339
D343
D347
D351
D355
D359
D363
D367
D371
D375
D379
D383
D387
D391
D395
D399
D292
D296
D300
D304
D308
D312
D316
D320
D324
D328
D332
D336
D340
D344
D348
D352
D356
D360
D364
D368
D372
D376
D380
D384
D388
D392
D396
D400
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
S128
D401
D405
D409
D413
D417
D421
D425
D429
D433
D437
D441
D445
D449
D453
D457
D461
D465
D469
D473
D477
D481
D485
D489
D493
D497
D501
D505
D509
D402
D406
D410
D414
D418
D422
D426
D430
D434
D438
D442
D446
D450
D454
D458
D462
D466
D470
D474
D478
D482
D486
D490
D494
D498
D502
D506
D510
D403
D407
D411
D415
D419
D423
D427
D431
D435
D439
D443
D447
D451
D455
D459
D463
D467
D471
D475
D479
D483
D487
D491
D495
D499
D503
D507
D511
D404
D408
D412
D416
D420
D424
D428
D432
D436
D440
D444
D448
D452
D456
D460
D464
D468
D472
D476
D480
D484
D488
D492
D496
D500
D504
D508
D512
Note: This applies to the case where the S1/P1 to S8/P8 output pins are set to be segment output ports.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D41
0
D42
0
D43
0
D44
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
The LCD segment corresponding to COM2 is on.
0
1
0
0
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segments corresponding to COM2, COM3, and COM4 are on.
The LCD segment corresponding to COM1 is on.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1, COM3, and COM4 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM4 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
No.A0549-21/34
LC75897PW
Output Waveforms (1/3-Duty 1/2-Bias Drive Scheme)
fo[Hz]
V
V
0
LCD
LCD
COM1
COM2
COM3
1,V
2
2
2
2
2
2
2
2
2
2
2
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
0V
V
V
0
LCD
LCD
1,V
0V
V
V
0
LCD
LCD
1,V
0V
V
V
0
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are turned off.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM1 are on.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM2 are on.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM3 are on.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
1,V
0V
V
V
0
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2,
and COM3 are on.
1,V
0V
Control data
Common/segment output waveform
frame frequency fo [Hz]
FC0
0
FC1
0
FC2
0
fosc/6144, f /6144
CK
1
0
0
fosc/4608, f /4608
CK
0
1
0
fosc/3072, f /3072
CK
1
1
0
fosc/2304, f /2304
CK
0
0
1
fosc/1536, f /1536
CK
No.A0549-22/34
LC75897PW
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
V
V
0
1
2
LCD
LCD
LCD
COM1
COM2
COM3
0V
V
V
V
0
1
2
LCD
LCD
LCD
0V
V
V
V
0
1
2
LCD
LCD
LCD
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are turned off.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2,
and COM3 are on.
0V
Control data
Common/segment output waveform
frame frequency fo [Hz]
FC0
0
FC1
0
FC2
0
fosc/6144, f /6144
CK
1
0
0
fosc/4608, f /4608
CK
0
1
0
fosc/3072, f /3072
CK
1
1
0
fosc/2304, f /2304
CK
0
0
1
fosc/1536, f /1536
CK
No.A0549-23/34
LC75897PW
Output Waveforms (1/4-Duty 1/2-Bias Drive Scheme)
fo[Hz]
V
V
0V
0
1,V
LCD
LCD
COM1
COM2
COM3
COM4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
V
V
0V
0
1,V
LCD
LCD
V
V
0V
0
1,V
LCD
LCD
V
V
0V
0
1,V
LCD
LCD
V
V
0V
0
1,V
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are turned off.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM1 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM2 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM3 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM4 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
V
V
0V
0
1,V
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are on.
Control data
Common/segment output waveform
frame frequency fo [Hz]
FC0
0
FC1
0
FC2
0
fosc/6144, f /6144
CK
1
0
0
fosc/4608, f /4608
CK
0
1
0
fosc/3072, f /3072
CK
1
1
0
fosc/2304, f /2304
CK
0
0
1
fosc/1536, f /1536
CK
No.A0549-24/34
LC75897PW
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
V
V
0
1
2
LCD
LCD
LCD
COM1
COM2
COM3
COM4
0V
V
V
V
0
1
2
LCD
LCD
LCD
0V
V
V
V
0
1
2
LCD
LCD
LCD
0V
V
V
V
0
1
2
LCD
LCD
LCD
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are turned off.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM1 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM2 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1, COM2,
and COM3 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM4 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
0V
V
V
V
0
1
2
LCD
LCD
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3,
and COM4 are on.
0V
Control data
Common/segment output waveform
frame frequency fo [Hz]
FC0
0
FC1
0
FC2
0
fosc/6144, f /6144
CK
1
0
0
fosc/4608, f /4608
CK
0
1
0
fosc/3072, f /3072
CK
1
1
0
fosc/2304, f /2304
CK
0
0
1
fosc/1536, f /1536
CK
No.A0549-25/34
LC75897PW
PWM output port waveforms
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD
P1
SS
(56/64)×Tp
(56/64)×Tp
LCD
SS
(1)
P2
P3
P1
P2
P3
P1
P2
P3
(48/64)×Tp
(40/64)×Tp
(48/64)×Tp
(40/64)×Tp
LCD
SS
LCD
SS
(8/64)×Tp
(8/64)×Tp
LCD
SS
(2)
(16/64)×Tp
(16/64)×Tp
LCD
SS
(24/64)×Tp
(32/64)×Tp
(24/64)×Tp
(32/64)×Tp
LCD
SS
LCD
SS
(3)
(32/64)×Tp
(32/64)×Tp
(32/64)×Tp
(32/64)×Tp
LCD
SS
1
fp
Tp
Tp
Tp=
Control data
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
PWM output
port waveforms
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
0
0
(1)
(2)
(3)
Control data
PWM output waveform
frame frequency fp [Hz]
PF0
PF1
0
PF2
0
0
1
0
1
0
1
0
1
fosc/1536, f /1536
CK
0
0
fosc/1408, f /1408
CK
1
0
fosc/1280, f /1280
CK
1
0
fosc/1152, f /1152
CK
0
1
fosc/1024, f /1024
CK
0
1
fosc/896, f /896
CK
1
1
fosc/768, f /768
CK
1
1
fosc/640, f /640
CK
Clock output port waveform
Clock output port P4
clock signal frequency
fc (=1/Tc) [Hz]
Control data
PS40
PF41
1
P4
Tc=
fc
Tc/2
0
1
1
1
Clock output port (fosc/2, f /2)
CK
Clock output port (fosc/8, f /8)
CK
Tc
No.A0549-26/34
LC75897PW
The INH pin and Display Control
Since the IC internal data (1/3 duty: the display data D1 to D387 and the control data, 1/4 duty: the display data D1 to
D512 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S8/P8, S9 to S128, COM1 to COM3, and
COM4/S129 to the V level.) and during this period send serial data from the controller. The controller should then set
SS
the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See
Figures 5 and 6.)
Notes on the Power On/Off Sequences
Applications should observe the following sequences when turning the LC75897PW power on and off.
(See Figures 5 and 6)
• At power on: Logic block power supply (V ) on → LCD driver block power supply (V
DD LCD
) on
• At power off: LCD driver block power supply (V
) off → Logic block power supply (V ) off
LCD DD
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and
off at the same time.
1. 1/3 duty
t2
t1
t3
V
V
DD
LCD
INH
CE
V
1
IL
tc
V
1
IL
W10 to W15, W20 to W25, W30 to W35,
PC1 to PC8, PS10, PS11, PS20,
Display data and control data transter
Internal data PS21, PS30, PS31, PS40, PS41,
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
PS5 to PS8, CT0 to CT2, DR, DT, OC,
FC0 to FC2, PF0 to PF2, SC, BU
Internal data (D1 to D129)
Internal data (D130 to D258)
Defined
Internal data (D259 to D387)
Defined
Note: t1≥0
t2>0
t3≥0 (t2>t3)
tc⋅⋅⋅10µs min
Figure 5
No.A0549-27/34
LC75897PW
2. 1/4 duty
t2
t1
t3
V
V
DD
LCD
INH
V
1
IL
tc
CE
V
1
IL
W10 to W15, W20 to W25, W30 to W35,
PC1 to PC8, PS10, PS11, PS20,
Display data and control data transter
Internal data PS21, PS30, PS31, PS40, PS41,
PS5 to PS8, CT0 to CT2, DR, DT, OC,
FC0 to FC2, PF0 to PF2, SC, BU
Undefined
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
Undefined
Internal data (D1 to D128)
Internal data (D129 to D256)
Defined
Internal data (D257 to D384)
Internal data (D385 to D512)
Defined
Note: t1≥0
t2>0
t3≥0 (t2>t3)
tc⋅⋅⋅10µs min
Figure 6
No.A0549-28/34
LC75897PW
Notes on Controller Transfer of Display Data
Since the LC75897PW accepts the display data (D1 to D387) divided into three separate transfer operations when using
1/3 duty drive scheme and the data (D1 to D512) divided into four separate transfer operations when using 1/4 duty
drive scheme, we recommend that applications transfer all of the display data within a period of less than 30ms to
prevent observable degradation of display quality.
OSC pin peripheral circuits
(1) RC oscillator operating mode (control data OC = 0)
When RC oscillator operating mode is selected, an external resistor Rosc and an external capacitor Cosc must be
connected between the OSC pin and GND.
OSC
Rosc
Cosc
(2) External clock operating mode (control data OC = 1)
When selecting the external clock operating mode, connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator). Determine the value of the resistance according
to the maximum allowable current value of the external clock output pin. Also make sure that the waveform of the
external clock is not excessively distorted.
External clock output pin
External oscillator
OSC
Rg
Note:
V
DD
Rg
Allowable current value at external clock output pin >
P1 to P3 pin peripheral circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using PWM output
ports P1 to P3.
+5V
LED
P1 to P3
No.A0549-29/34
LC75897PW
Sample Application Circuit 1
1/3 Duty, 1/2 Bias (for use with normal panels)
(P1)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
V
V
DD
SS
COM3
P1/S1
P2/S2
P3/S3
V
SS
+5.8V
V
V
V
LCD
LCD
LCD
OPEN
0
1
P4/S4
P5/S5
P8/S8
S9
V
2
LCD
C≥0.047µF
C
INH
CE
CL
DI
S127
S128
From the controller
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
Sample Application Circuit 2
1/3 Duty, 1/2 Bias (for use with large panels)
(P1)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
+5.8V
V
V
DD
SS
COM3
P1/S1
P2/S2
P3/S3
V
SS
V
LCD
LCD
LCD
P4/S4
P5/S5
V
V
0
1
R
P8/S8
S9
10kΩ≥R≥2.2kΩ
C≥0.047µF
V
2
LCD
C
R
INH
CE
CL
DI
S127
S128
From the controller
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-30/34
LC75897PW
Sample Application Circuit 3
1/3 Duty, 1/3 Bias (for use with normal panels)
(P1)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
V
V
DD
COM3
P1/S1
P2/S2
P3/S3
SS
V
SS
+5.8V
V
V
V
LCD
LCD
LCD
P4/S4
P5/S5
OPEN
0
1
P8/S8
S9
V
2
LCD
C≥0.047µF
C
C
INH
CE
CL
DI
S127
S128
From the controller
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
(P1)
Sample Application Circuit 4
1/3 Duty, 1/3 Bias (for use with large panels)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
V
V
DD
SS
COM3
P1/S1
P2/S2
P3/S3
V
V
SS
+5.8V
LCD
LCD
V
0
1
P4/S4
P5/S5
R
V
LCD
LCD
R
P8/S8
S9
10kΩ≥R≥2.2kΩ
C≥0.047µF
V
2
C
C
R
INH
CE
CL
DI
S127
S128
From the controller
COM4/S129
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-31/34
LC75897PW
Sample Application Circuit 5
1/4 Duty, 1/2 Bias (for use with normal panels)
(P1)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
V
V
DD
SS
COM3
S129/COM4
V
SS
P1/S1
P2/S2
P3/S3
+5.8V
V
V
V
LCD
LCD
LCD
OPEN
0
1
P4/S4
P5/S5
V
2
LCD
P8/S8
S9
C≥0.047µF
C
INH
CE
CL
DI
From the controller
S127
S128
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
(P1)
General-purpose
output ports
Sample Application Circuit 6
1/4 Duty, 1/2 Bias (for use with large panels)
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
+5.8V
V
V
DD
SS
COM3
S129/COM4
V
SS
P1/S1
P2/S2
P3/S3
V
LCD
LCD
LCD
V
V
0
1
P4/S4
P5/S5
R
10kΩ≥R≥2.2kΩ
C≥0.047µF
V
2
LCD
C
R
P8/S8
S9
INH
CE
CL
DI
From the controller
S127
S128
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-32/34
LC75897PW
Sample Application Circuit 7
1/4 Duty, 1/3 Bias (for use with normal panels)
(P1)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
V
V
DD
SS
COM3
S129/COM4
V
SS
P1/S1
P2/S2
P3/S3
V
+5.8V
LCD
LCD
LCD
V
V
0
1
OPEN
P4/S4
P5/S5
V
2
LCD
P8/S8
S9
C
C
C≥0.047µF
INH
CE
CL
DI
From the controller
S127
S128
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
(P1)
Sample Application Circuit 8
1/4 Duty, 1/3 Bias (for use with large panels)
General-purpose
output ports
(P2)
(P3)
(P4)
(P5)
Used for functions
such as backlight
control
(P8)
OSC
*2
COM1
COM2
+3.3V
V
V
DD
SS
COM3
S129/COM4
V
V
SS
P1/S1
P2/S2
P3/S3
+5.8V
LCD
LCD
V
V
0
1
R
P4/S4
P5/S5
LCD
LCD
R
10kΩ≥R≥2.2kΩ
V
2
P8/S8
S9
C≥0.047µF
C
C
R
INH
CE
CL
DI
From the controller
S127
S128
Note: *2 Connect an external resistor Rosc and an external capacitor Cosc between the OSC pin and GND when
selecting the RC oscillator operating mode and connect a current protection resistor Rg (2.2 to 22kΩ) between
the OSC pin and the external clock output pin (external oscillator) when selecting the external clock operating
mode (see the note on the OSC pin peripheral circuits).
No.A0549-33/34
LC75897PW
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of April, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0549-34/34
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