LC7940YD [SANYO]
Dot-matrix LCD Drivers; 点阵LCD驱动器
| 型号： | LC7940YD |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Dot-matrix LCD Drivers |
| 文件： | 总11页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number: EN 6158
CMOS IC
LC7940YD,7941YD
Dot-matrix LCD Drivers
Overview
Package Dimensions
The LC7940YD and LC7941YD are segment driver ICs unit: mm
for driving large, dot
bit parallel or serial input, display data from a controller
into an 80 bit latch, and then generate LCD drive signals
–matrix LCD displays. They read 4–
3180
–
QIP100D
–
[LC7940YD, LC7941YD]
corresponding to that data.
23.2
20.0
1.6
51
The LC7940YD and LC7941YD feature mirror–image pin
0.65
0.575
80
0.3
0.15
assignments, allowing them to be used together to increase
component density. They are designed to be used with the
LC7942YD common driver to drive large LCD panels.
81
50
Features
• 80 built
• 1/8 to l/128display duty cycle
• Serial or 4 bit parallel data input
–in LCD display drive circuits
31
–
100
• Chip disable for low power dissipation for large
–
sized
1
30
panels
2.15
• Bias supply voltags can be supplied externally
• Operating supply voltage and ambient temperature
- 2.7 to 5.5 V logic supply ( V ) at Ta = 20 to +85°C
) at Ta = 20 to
21.6
0.8
–
DD
SANYO : QFP100D (QIP100D)
- 8 to 20V LCD supply (V
+85 °C
–
V
–
DD
EE
• CMOS process
• 100–pin flat plastic package
Specifications
Absolute Maximum Ratings at Ta = 25 ± 2°C, V = 0 V
SS
Parameter
Symbol
max
Ratings
Unit
V
Logic supply voltge
V
–0.3 to +7.0
0 to 22
DD
LCD supply voltage, See Note below.
Input voltage
V
– V max
V
DD
EE
V max
–0.3 to V + 03
V
I
DD
■
■
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co., Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63099RM (ID) No. 6158—1/11
LC7940YD, LC7941YD
Parameter
Operating temperature range
Symbol
Ratings
–20 to +85
–40 to +125
Unit
°C
T
opr
Storage temperature range
T
°C
stg
Note
V
≥ V > V > V > V
1 3 4 EE
DD
Recommended Operating Condltions at Ta = –20 to + 85°C, V = 0V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Logic supply voltage
V
2.7
8
–
5.5
20
V
V
DD
LCD supply voltage
V
– V
See Notes 1 and 2.
–
DD
EE
CP, CDl, DI1 to DI3, M,
SDl, P/S, DISPOFF and
LOAD
HIGH–level input voltage
V
0.8V
–
–
V
V
IH
DD
–
CP, CDI, Dl1 to DI3, M,
SDl, P/S,DISPOFF and
LOAD
LOW–level inpvt voltage
V
–
0.2V
DD
IL
CP shift clock frequency
CP pulsewidth
f
–
–
–
–
–
–
–
–
–
–
–
–
3.3
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CP
t
100
100
80
80
0
WC
LOAD pulsewidth
t
–
WL
DIn and SDI to CP setup time
DIn and SDI to CP hold time
t
–
SETUP
t
–
HOLD
t
t
–
CL1
CL2
CP to LOAD time
100
100
–
–
LOAD to CP time
CP rise time
t
–
LC
t
50
50
50
50
R
CP fall time
t
–
F
LOAD rise time
LOAD fall time
t
–
RL
t
–
FL
Notes
1. V ≥ V > V > V > V
EE
DD
l
3
4
2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supply
should be cut after or simultaneously with the LCD supply.
Electrlcai Characterfstlcs at Ta = 25 ± 2°C,V = 0V, V = 2.7 to 5.5 V
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
V
=V ; LOAD, CP, CDI,
DD
IN
HIGH–level input current
I
P/S, DI1 to DI3, SDl, M,
and DISPOFF
–
–
–
1
µA
IH
V
= V ; LOAD, CP, CDl,
SS
IN
LOW–level input current
I
P/S, DI1 to DI3, SDI, M,
and DISPOFF
–
–1
µA
IL
CDO HIGH–level output voltage
CDO LOW–levef output voltage
V
I
I
= –400 µA
= 400 µA
V
DD
– 0.4
–
–
–
–
V
V
OH
OH
OL
V
0.4
OL
V
– V = 18 V,
EE
DD
O1 to O80 driver ON resistance
R
|V – V |= 0.25 V.
–
2
4
kΩ
ON
DE
O
See note
No. 6158—2/11
LC7940YD, LC7941YD
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
CDI = V
,
DD
V
– V = 18 V,
= 3.3 MHz,
DD
EE
V
V
V
to V standby supply current
I
–
–
–
–
200
µA
DD
DD
DD
SS
ST
SS
EE
f
CP
no output load ; V
SS
V
– V = 18 V,
EE
= 3.3 MHz,
= 5.156 kHz,
= 52 Hz ;VSS
DD
f
I
f
CP
to V operating supply current
I
I
–
1.0
mA
SS
LOAD
M
V
– V = 18V,
EE
= 3.3 MHz,
= 5,156 kHz,
DD
f
f
f
CP
to V operating supply current
–
5
0.1
–
mA
pF
EE
LOAD
= 52 Hz ; V
M
EE
CP input capacitance
C
f
= 3.3 MHz ; CP
–
I
CP
Note
V
= V or V , or V or V , V = V , V = 9/11 × (V
–
V
), V = 2/11 × (V
–
V
)
DD
1
3
4
EE
1
DD
3
DD
EE
4
DD
EE
Switching Characteristics at Ta = 25 ± 2°C,V = 0 V, V = 2.7 to 5.5 V
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
200
CDO output delay time
t
C
= 30 pF
L
–
–
ns
D
Switching Characteristics Waveform
t
t
WC
WC
t
t
F
R
0.8VDD
CP
0.2VDD
t
SET
UP
t
HOLD
SDI
DI1 to 3
t
t
FL
RL
t
t
CL (2)
CL (1)
t
LC
LOAD
CDO
t
WL
t
t
D
D
No. 6158—3/11
LC7940YD, LC7941YD
Pad Layout (Top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
050
049
048
047
046
045
044
043
042
041
040
039
038
037
036
035
034
033
032
031
NC
CDO
NC
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DISP OFF
P/S
VSS
VEE
V4
V3
NC
LC7940YD
VDD
V1
M
DI1
DI2
DI3
SDI
LOAD
CDI
CP
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
031
032
033
034
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
CP
CDI
LOAD
SDI
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DI3
DI2
DI1
M
V1
VDD
LC7941YD
NC
V3
V4
VEE
VSS
P/S
DISP OFF
NC
CDO
NC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
No. 6158—4/11
LC7940YD, LC7941YD
Block Diagram
01 02 03
079 080
V1
VDD
V3
V4
4 Level LCD Drive Circuit
(80 bits)
VSS
VEE
80
Level Shifter (80 bits)
M
DISP OFF
80
2nd Latch (80 bits)
80
1st Latch (80 bits)
4
20
SDI
DI3
DI2
DI1
Address Decoder
CLK
4 bits
Data Bus
Interface
Address Counter
(7 bits)
Chip Disable &
Latch Control
SER/PAR
Control
P/S
CDI
CDO
CP
LOAD
Pin Functions
Pin No.
Synbol
I/O
Functions
LC7940YD
LC7941YD
91
86
87
92
89
88
l00
90
95
94
89
92
93
81
V
DD
V
V
– V is the logic supply.
SS
DD
DD
V
V
Supply
SS
EE
– V is the LCD supply.
EE
V
1
3
4
LCD panel drive voltage supplies
V
V
V
Supply
and V are selected levels.
1
3
EE
and V are not–selected levels.
4
V
CP
I
I
Display data Input clock (falling–edge trigger).
Chip disable.
99
82
CDI
Data is read in when LOW, and not road in when HIGH.
Display data latch clock (falling–edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
98
97
83
84
LOAD
SDI
I
I
Serial data input.
No. 6158—5/11
LC7940YD, LC7941YD
Pin No.
Synbol
I/O
Functions
LC7940YD
LC7941YD
96
95
85
86
DI3
DI2
4–bit parallel data input pins.
Data input
SDI
LCD driver outputs
O4
O3
O2
O1
O8
O7
O6
O5
O80
O79
O78
O77
DI3
I
DI2
94
87
D11
DI1
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
LCD panel drive voltage output alternation control signal.
93
85
88
96
M
I
I
P/S
Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW
Cascade connection pin for extension segment drivers. Data is read out when HIGH.
Goes LOW after data is read out. Connected to the CDI input of the next chip.
82
1 to 80
84
99
80 to 1
97
CDO
O
LCD drive outputs.
The output drive level is determined by the display data, M signal and DISP OFF
input as shown below.
M
Q
DISP OFF
HIGH
Output
LOW
LOW
HIGH
HIGH
×
LOW
HIGH
LOW
HIGH
×
V
V
V
3
1
4
HIGH
Ol to O80
O
HIGH
HIGH
V
EE
LOW
V
1
Note
x = don’t care (tied HIGH or LOW)
O1 to O80 output control input pin.
DISPOFF
I
When LOW, V1 is output on the O1 to 080 outputs, See the truth table.
No connection.
81
83
90
91
98
NC
NC
NC
–
100
No. 6158—6/11
LC7940YD, LC7941YD
Application Notes
LCD Panel 1
1
2
6 4 1
6 4 2
1 5 9
1 6 0
7 9 9
8 0 0
1 6 1
1 6 2
8 0 1
8 0 2
3 1 9
3 2 0
9 5 9
9 6 0
3 2 1
3 2 2
9 6 1
9 6 2
4 7 9
4 8 0
1 1 1 9
1 1 2 0
4 8 1
4 8 2
1 1 2 1
1 1 2 2
6 3 9
6 4 0
1 2 7 9
1 2 8 0
No. 6158—7/11
LC7940YD, LC7941YD
LCD Panel 2
No. 6158—8/11
LC7940YD, LC7941YD
100 × 240–pixel LCD Panel Application
A 100 × 240–pixel LCD panel requires the following
drivers.
• 3 × LC7940YD (or LC7941YD) drivers
• 2 × LC7942YD drivers
An example using l/l00 duty cycle is shown below.
(m,n) : pixel address
1,79
Segment line (n)
Common line (m)
Frame signel
1,1
2,1
1,2
2,2
1,79
1,80
1,81
1,82
1,160
1,161
1,240
2,240
DI01 01
RS/LS 02
LC7942YD
---
---
---
#1
LCD panel (100 × 240 pixels)
CP
M
063
63,1
64,1
65,1
66,1
63,2
64,2
65,2
66,2
---
---
---
---
---
DI064 064
64,80 64,81
64,160 64,161
65,160 65,161
64,240
65,240
65,80 65,81
---
DI01 01
RS/LS 02
LC7942YD
#2
CP
M
---
---
---
100,1 100,2
100,79 100,80 100,81 100,82
100,160 100,161
100,240
080
036
DI064
O37 to O64
are open.
01
02
079
080
01
02
080
01
LC7940YD
LC7940YD
LC7940YD
#1
#2
#2
CDO
CDI
CDO
CDI
CDO
CDI
(LC7941YD)
(LC7941YD)
(LC7941YD)
1. The LC7942YD chips are cascaded by connecting
DIO64 on chip I to DIO1 on chip 2. For a 100
–bit shift
register, 037 to 064 on chip 2 are left open.
2. The LC7940YD (or LC7941YD) chips are cascaded
by connecting CDO on chip I to CDI on chip 2, and
CDO on chip 2 to CDI on chip 3. CDI on chip I is tied
to GND, and CDO on chip 3 is not used. This
configuration allows the input of 240–bit serial data.
No. 6158—9/11
LC7940YD, LC7941YD
100 x 240-pixel LCD Panel Timing Diagram
M
LOAD
CP
1,1
1,2
---
1,79
1,80
1,81
---
1,160
1,161
---
1,240
SDI
#1
SDO
#2
#3
Chip 1 data read
1 line (240 bits)
Chip 2 data read
Chip 3 data read
M
LOAD
CP
1,1
1,2
---
1,239
1,240
2,1
---
2,240
3,1
---
100,240
SDI
1st line data read
2nd line data read
1 frame (100 × 240 bits)
M
#1 DIO1
LOAD
---
---
98,1
98,2
99,1
100,1
100,2
1,1
1,2
---
---
99,1
99,2
100,1
100,2
01
1,1
1,2
2,1
2,2
99,2
99,80
99,81
02
#1
---
98,80
98,81
100,80
100,81
1,80
1,81
---
99,80
99,81
100,80
100,81
1,80
2,80
080
01
#2
---
---
---
---
1,81
2,81
98,160 99,160 100,160 1,160
99,160 100,160
1,160
2,160
080
01
#3
---
---
98,161 99,161 100,161 1,161
98,240 99,240 100,240 1,240
---
---
99,161 100,161
99,240 100,240
1,161
1,240
2,161
2,240
080
No. 6158—10/11
LC7940YD, LC7941YD
Segment Data Not Multiples of 4
Example.
LCD panel (100 × 230 pixels)
---
---
01
080
01
080
01
080
LC7940YD
#1
LC7940YD
#2
LC7940YD
#3
LOAD
SDI
m,1
m,2
---
,228
m,229
m,230
m+1,1
m+1,2
,228 m+1,229 m+1,230
If this timing data is sent, data elements (m, 229), (m, in 4–bit units, which also decreases power dissipation . For
230), (m+1, 229), (m+1. 230)... will not appear in the data that is not a multiple of 4, like 230, the following
output (O69 and O70 on chip 3). This is because the scheme is used.
LC7940YD (or LC7941YD) converts serial/parallel data
LOAD
m,1
m,2
---
Vaild display data
Multiple of 4
,228
m,229
m,230
m,231
m,232
SDI
Dummy data
In this case, (m, 231) is output on O71 on chip 3, and (m, connected to the panel and are, therefore, invalid.
232) on O72 on chip 3. However, these outputs are not
■
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
■
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could give
rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that
could cause damage to other property. When designing equipment, adopt safety measures so that these
kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits
and error prevention circuits for safe design, redundant design, and structural design.
■
In the event that any or all SANYO products(including technical data,services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products
must not be exported without obtaining the export license from the authorities concerned in accordance
with the above law.
■
■
■
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for
the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no
guarantees are made or implied regarding its use or any infringements of intellectual property rights or
other rights of third parties.
This catalog provides information as of June, 1999. Specifications and information herein are subject to
change without notice.
No. 6158—11/11
相关型号：
©2020 ICPDF网 联系我们和版权申明