LC863364 [SANYO]
8-Bit Single Chip Microcontroller; 8位单片机
| 型号： | LC863364 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-Bit Single Chip Microcontroller |
| 文件： | 总20页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6696
CMOS IC
LC863364/56/48/40A
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC863364/56/48/40A are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.424µs
- On-chip ROM capacity
Program ROM : 64K/56K/48K/40K bytes
CGROM : 16K bytes
- On-chip RAM capacity : 640 bytes
- OSD RAM : 352 × 9 bits
- Five channels 8-bit AD Converter
×
- Three channels × 7-bit PWM
- Two 16-bit timer/counters, 14-bit base timer
- 8-bit synchronous serial interface circuit
- IIC-bus compliant serial interface circuit (Multi-master type)
- ROM correction function
- 15-source 9-vectored interrupt system
- Integrated system clock generator and display clock generator
X tal oscillator (32.768kHz) for PLL reference is used for TV control.
’
All of the above functions are fabricated on a single chip
Ver.0.91
51299
91400 RM (IM) HS No.6696-1/20
LC863364/56/48/40A
Features
(1) Read-Only Memory (ROM) :
65024 × 8 bits / 57344 × 8 bits / 49152 × 8 bits
40960 8 bits for program
×
16128 × 8 bits for CGROM
(2) Random Access Memory (RAM) :
(3) OSD functions
640 × 8 bits (including 128 bytes for ROM correction function)
352 9 bits (for CRT display)
×
- Screen display
- RAM
: 36 characters 16 lines (by software)
: 352 words (9 bits per word)
×
Display area
Control area
- Characters
Up to 252 kinds of 16 32 dot character fonts
: 36 words 8 lines
×
: 8 words × 8 lines
×
(4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts :
a 16 × 17 dot and 8 × 9 dot character font
- Various character attributes
Character colors
Character background colors
Fringe / shadow colors
Full screen colors
: 16 colors
: 16 colors
: 16 colors
: 16colors
Rounding
Underline
Italic character (slanting)
- Attribute can be changed without spacing
- Vertical display start line number can be set for each row independently (Rows can be overlapped)
- Horizontal display start position can be set for each row independently
- Horizontal pitch (bit 9 - 16)*1 and vertical pitch (bit-32) can be set for each row independently
- Different display modes can be set for each row independently
Caption
Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode
•
- Ten character sizes *1
Horez. × Vert. = (1 × 1), (1 × 2), (2 × 2), (2 × 4), (0.5 × 0.5)
(1.5 1), (1.5 2), (3 2), (3 4), (0.75 0.5)
×
- Shuttering and scrolling on each row
- Simplified Graphic Display
×
×
×
×
*1 Note : range depends on display mode : refer to the manual for details.
(4) Bus Cycle Time / Instruction-Cycle Time
Bus cycle time
0.424 s
Instruction cycle time
0.848 s
System clock oscillation
Internal VCO
Oscillation Frequency
14.156MHz
Voltage
4.5V to 5.5V
µ
µ
(Ref : X tal 32.768kHz)
’
Internal RC
800kHz
4.5V to 5.5V
4.5V to 5.5V
7.5 s
15.0 s
µ
µ
Crystal
32.768kHz
183.1 s
366.2 s
µ
µ
(5) Ports
- Input / Output Ports
Data direction programmable in nibble units
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
: 5 ports (28 terminals)
: 1 port (8 terminals)
Data direction programmable for each bit individually
- Input port
: 4 ports (20 terminals)
: 1 port (1 terminal)
No.6696-2/20
LC863364/56/48/40A
(6) AD converter
- 5 channels × 8-bit AD converters
(7) Serial interfaces
- IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
- Synchronous 8-bit serial interface
(8) PWM output
- 3 channels 7-bit PWM
×
(9) Timer
- Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
- Timer 1 : 16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable bit PWM (9 to 16 bits)
In mode0/1,the resolution of Timer1/PWM is 1 tCYC
In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC
- Base timer
Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976 s, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer
µ
clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
(10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function
- Polarity switching
(11) Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
(12) ROM correction function
Max 128 bytes / 2 addresses
(13) Interrupts
- 15 sources 9 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Timer T1H,T1L
7. SIO0
8. Vertical synchronous signal interrupt ( VS), horizontal line ( HS ), AD
9. IIC, Port 0
No.6696-3/20
LC863364/56/48/40A
- Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 9 listed above. For the external interrupt INT0 and INT1, high
or highest priority can be set.
(14) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(15) Multiplication/division instruction
- 16 bits × 8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(16) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X tal oscillation circuit used for base timer, system clock and PLL reference
’
(17) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X tal oscillations. This mode can be
’
released by the following conditions.
Pull the reset terminal (
) to low level.
RES
•
•
•
Feed the selected level to either P70/INT0 or P71/INT1.
Input the interrupt condition to Port 0.
(18) Package
- DIP42S
- QIP48E
(19) Development tools
- Flash EEPROM:
2 Flash microcontrollers are available:LC86F3364A,LC86F3348A. Flash version is different on
which microcontroller is used.
LC86F3364A (LC863364A / LC863356A) (under development)
LC86F3348A (LC863348A / LC863340A)
- Evaluation chip:
- Emulator:
LC863096
EVA86000 (main) + ECB863200 (evaluation chip board)
+ POD863300 (pod: DIP42S) or POD863301 (QIP48E)
No.6696-4/20
LC863364/56/48/40A
System Block Diagram
Interrupt Control
IR
PLA
Standby Control
ROM
X’tal
RC
VCO
PC
PLL
IIC
ROM Correct Control
ACC
B Register
C Register
SIO0
XRAM
Timer 0
Bus Interface
Timer 1
Port 1
Port 6
ALU
Base Timer
ADC
Port 7
Port 8
PSW
RAR
RAM
INT0-3
Noise Rejection Filter
PWM
CGROM
VRAM
OSD
Control
Circuit
Stack Pointer
Port 0
Watch Dog Timer
No.6696-5/20
LC863364/56/48/40A
Pin Assignment
• DIP42S
P10/SO0
P11/SI0
P12/SCK0
P13/PWM1
P14/PWM2
P15/PWM3
P16
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P07
2
P06
3
P05
4
P04
Package Dimension
5
P03
(unit : mm)
6
P02
3025B
7
P01
P17/PWM
VSS
8
P00
9
P73/INT3/T0IN
XT1
10
11
12
13
14
15
16
17
18
19
20
21
P72/INT2/T0IN
XT2
P71/INT1
VDD
P70/INT0
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P63/SCLK1
P62/SDA1
P61/SCLK0
P60/SDA0
I
RES
FILT
SANYO : DIP-42S(600mil)
BL
B
G
R
P83/AN3
VS
HS
• QIP48E
Package Dimension
(unit : mm)
3156
1
36
P02
P15/PWM3
P16
2
35
34
33
32
31
30
29
28
27
26
25
P01
3
P00
P17/PWM
VSS
4
NC
5
P73/INT3/T0IN
P72/INT2/T0IN
P71/INT1
P70/INT0
P63/SCLK1
P62/SDA1
P61/SCLK0
P60/SDA0
XT1
6
XT2
7
VDD
8
NC
9
P84/AN4
P85/AN5
P86/AN6
P87/AN7
10
11
12
SANYO : QIP-48E
No.6696-6/20
LC863364/56/48/40A
Pin Description
Pin Description Table
Terminal
VSS
I/O
-
Function Description
Negative power supply
Option
XT1
XT2
VDD
I
O
-
Input terminal for crystal oscillator
Output terminal for crystal oscillator
Positive power supply
I
Reset terminal
RES
FILT
O
I
Filter terminal for PLL
Vertical synchronization signal input terminal
Horizontal synchronization signal input terminal
VS
HS
R
G
B
I
O
O
O
O
O
Red (R) output terminal of RGB image output
Green (G) output terminal of RGB image output
Blue (B) output terminal of RGB image output
Intensity ( I ) output terminal of RGB image output
Fast blanking control signal
I
BL
Switch TV image signal and OSD image signal
•8-bit input/output port,
Port 0
Pull-up resistor
I/O
I/O
Input/output can be specified in nibble unit
•Other functions
HOLD release input
Interrupt input
•8-bit input/output port
provided/not provided
Output Format
CMOS/Nch-OD
P00 - P07
Port 1
P10 - P17
Output Format
CMOS/Nch-OD
Input/output can be specified in a bit
•Other functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 PWM1 output
P14 PWM2 output
P15 PWM3 output
P17 Timer1 (PWM) output
Port 6
P60 - P63
•4-bit input/output port
Input/output can be specified for each bit
•Other functions
I/O
P60 IIC0 data I/O
P61 IIC0 clock output
P62 IIC1 data I/O
P63 IIC1 clock output
No.6696-7/20
LC863364/56/48/40A
Terminal
I/O
I/O
Function Description
•4-bit input/output port
Input or output can be specified for each bit
•Other function
Option
Port 7
P70
P71 - P73
P70 INT0 input/HOLD release input/
Nch-Tr. output for wachdog timer
P71 INT1 input/HOLD release input
P72 INT2 input/Timer 0 event input
P73 INT3 input (noise rejection filter
connected)/
Timer 0 event input
Interrupt receiver format, vector addresses
rising falling rising/ H level L level vector
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
•1-bit input port
Port 8
P83
I
4-bit input/output port
Input or output can be specified for each bit
•Other function
P84-P87
I/O
AD converter input port (5 lines)
unused terminal
NC
-
Leave open
Output form and existance of pull-up resistor for all ports can be specified for each bit.
Programmable pull-up resistor is always connected regardless of port option, CMOS or N-ch open drain output in port 1.
•
•
Port status in reset
•
Terminal
I/O
Pull-up resistor status at selecting pull-up option
Port 0
Port 1
I
I
Pull-up resistor OFF, ON after reset release
Programmable pull-up resistor OFF
No.6696-8/20
LC863364/56/48/40A
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
V
VDD[V]
min.
-0.3
-0.3
max.
+7.0
VDD+0.3
Supply voltage
Input voltage
VDDMAX
VI(1)
VDD
• RES , HS , VS ,
CVIN
Output voltage
VO(1)
VIO
R, G, B, I, BL,
FILT
•Ports 0, 1, 6, 7,
8
-0.3
-0.3
-4
VDD+0.3
VDD+0.3
Input/output
voltage
High
Peak
IOPH(1)
IOPH(2)
•Ports 0, 1, 7, 8
•CMOS output
•For each pin.
•CMOS output
•For each pin.
Total of all pins.
Total of all pins.
Total of all pins.
For each pin.
For each pin.
For each pin.
Total of all pins.
Total of all pins.
Total of all pins.
mA
level
output
current
output
current
R, G, B, I, BL
-5
Total
output
current
•Ports 0, 1
Ports 7, 8
R, G, B, I, BL
Ports 0, 1, 6, 8
Port 7
R, G, B, I, BL
Ports 0, 1
Ports 6, 7, 8
R, G, B, I, BL
DIP42S
-20
-10
-15
∑IOAH(1)
∑IOAH(2)
∑IOAH(3)
IOPL(1)
IOPL(2)
IOPL(3)
∑IOAL(1)
∑IOAL(2)
∑IOAL(3)
Pdmax
Low
Peak
20
15
5
40
40
level
output
current
output
current
Total
output
current
15
Maximum power
dissipation
Operating
temperature
range
800
400
+70
mW
Ta=-10 to +70°C
QIP48E
Topr
Tstg
-10
-55
°C
Storage
+125
temperature
range
No.6696-9/20
LC863364/56/48/40A
2. Recommended Operating Range at Ta=-10°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Operating
supply voltage
range
Symbol
VDD(1)
Pins
Conditions
unit
V
VDD[V]
min.
4.5
max.
5.5
VDD
VDD
0.844µs ≤ tCYC
≤ 0.852µs
4µs ≤ tCYC ≤
400µs
RAMs and the
registers data are
kept in HOLD
mode.
VDD(2)
VHD
4.5
2.0
5.5
5.5
Hold voltage
High level
input voltage
VIH(1)
VIH(2)
Port 0 (Schumitt)
Output disable
4.5 - 5.5 0.6VDD
4.5 - 5.5 0.75VDD
VDD
VDD
•Ports 1,6 (Schumitt)
•Port 7 (Schumitt)
port input/interrupt
Output disable
• HS , VS , RES
(Schumitt)
VIH(3)
VIH(4)
Port 70
Watchdog timer input
•Port 8
Output disable
Output disable
4.5 - 5.5 VDD-0.5
4.5 - 5.5 0.7VDD
VDD
VDD
port input
Low level input VIL(1)
Port 0 (Schumitt)
•Ports 1,6 (Schumitt)
•Port 7 (Schumitt)
port input/interrupt
Output disable
Output disable
4.5 - 5.5
4.5 - 5.5
VSS
VSS
0.2VDD
0.25VDD
voltage
VIL(2)
• HS , VS , RES
(Schumitt)
Port 70
Watchdog timer input
Port 8
VIL(3)
Output disable
Output disable
4.5 - 5.5
4.5 - 5.5
5.0
VSS
VSS
0.6VDD
0.3VDD
VIL(4)
port input
CVIN
CVIN
VCVIN
tCYC(1)
tCYC(2)
1Vp-p
-3dB
0.844
1Vp-p
0.848
1Vp-p Vp-p
+3dB
0.852
*
µs
Operation
cycle time
•All functions
operating
•AD converter
operating
4.5 - 5.5
4.5 - 5.5
0.844
30
•OSD and Data
slicer are not
operating
tCYC(3)
FmRC
•OSD, AD
4.5 - 5.5
4.5 - 5.5
0.844
0.4
400
3.0
converter and
Data slicer are
not operating
Internal RC
oscillation
Oscillation
frequency
range
0.8
MHz
* Vp-p : Peak-to-peak voltage
No.6696-10/20
LC863364/56/48/40A
3. Electrical Characteristics at Ta=-10°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
IIH(1)
Pins
Conditions
unit
VDD[V]
4.5 - 5.5
min.
max.
1
High level
input current
Ports 0, 1, 6, 7, 8
•Output disable
•Pull-up MOS Tr.
OFF
µA
•VIN=VDD
(including the off-
leak current of the
output Tr.)
IIH(2)
•VIN=VDD
4.5 - 5.5
4.5 - 5.5
1
• RES
• HS , VS
Ports 0, 1, 6, 7, 8
Low level input IIL(1)
current
•Output disable
•Pull-up MOS
Tr. OFF
-1
-1
•VIN=VSS
(including the off-
leak current of the
output Tr.)
IIL(2)
VIN=VSS
4.5 - 5.5
• RES
• HS , VS
High level
output voltage
VOH(1)
•CMOS output of
ports 0,1,71-73,8
R, G, B, I, BL
Ports 0,1,71-73,8
Ports 0,1,71-73,8
•R, G, B, I, BL
•Port 6
IOH=-1.0mA
4.5 - 5.5 VDD-1
V
VOH(2)
VOL(1)
VOL(2)
VOL(3)
IOH=-0.1mA
IOL=10mA
IOL=1.6mA
IOL=3.0mA
4.5 - 5.5 VDD-0.5
4.5 - 5.5
4.5 - 5.5
Low level
output voltage
1.5
0.4
0.4
4.5 - 5.5
VOL(4)
VOL(5)
Rpu
Port 6
Port 70
•Ports 0, 1, 7, 8
IOL=6.0mA
IOL=1mA
VOH=0.9VDD
4.5 - 5.5
4.5 - 5.5
4.5 - 5.5
0.6
0.4
80
Pull-up MOS
Tr. resistance
Bus terminal
short circuit
resistance
13
38
kΩ
RBS
•P60-P62
•P61-P63
4.5 - 5.5
130
Ω
(SCL0-SCL1,
SDA0-SDA1)
Hysteresis
VHIS
•Ports 0, 1, 6, 7
• RES
Output disable
4.5 - 5.5
0.1VDD
V
voltage
• HS , VS
CVIN
Input clump
votage
Pin capacitance CP
VCLMP
5.0
2.3
2.5
10
2.7
All pins
•f=1MHz
4.5 - 5.5
pF
•Every other
terminals are
connected to VSS.
•Ta=25°C
No.6696-11/20
LC863364/56/48/40A
4. Serial Input/Output Characteristics at Ta=-10°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Cycle
Symbol
Pins
Conditions
unit
VDD[V]
4.5 - 5.5
min.
2
max.
tCKCY(1) •SCK0
•SCLK0
Refer to figure 4.
tCYC
Low Level
pulse width
High Level
pulse width
Cycle
tCKL(1)
1
1
2
tCKH(1)
tCKCY(2) •SCK0
•SCLK0
tCKL(2)
•Use pull-up
4.5 - 5.5
4.5 - 5.5
resistor (1kΩ)
when Nch open-
drain output.
Low Level
pulse width
High Level
1/2tCKCY
1/2tCKCY
•Refer to figure 4.
tCKH(2)
pulse width
Data set up time
tICK
SI0
•Data set-up to
SCK0.
•Data hold from
SCK0.
0.1
0.1
µs
Data hold time
tCKI
•Refer to figure 4.
Output delay time
(Using external
clock)
Output delay time
(Using internal
tCKO(1)
tCKO(2)
SO0
SO0
•Data hold from
SCK0.
•Use pull-up
resistor (1kΩ)
when Nch open-
drain output.
•Refer to figure 4.
4.5 - 5.5
4.5 - 5.5
7/12tCYC
+0.2
1/3tCYC
+0.2
clock)
5. IIC Input/Output Conditions at Ta=-10°C to +70°C, VSS=0V
Standard
High speed
Parameter
Symbol
unit
min.
0
max.
min.
max.
SCL Frequency
fSCL
tBUF
tHD;STA
tLOW
100
-
-
-
-
-
-
-
0
400
kHz
µs
µs
µs
µs
µs
µs
ns
BUS free time between stop - start
HOLD time of start, restart condition
L time of SCL
4.7
4.0
4.7
4.0
4.7
0
250
-
-
1.3
0.6
1.3
0.6
0.6
0
-
-
-
-
-
H time of SCL
tHIGH
Set-up time of restart condition
HOLD time of SDA
Set-up time of SDA
Rising time of SDA, SCL
Falling time of SDA, SCL
Set-up time of stop condition
tSU;STA
tHD;DAT
tSU;DAT
tR
0.9
-
100
1000
300
-
20+0.1Cb
20+0.1Cb
0.6
300
300
-
ns
ns
µs
tF
tSU;STO
4.0
Refer to figure 10
(Note)
Cb : Total capacitance of all BUS (unit : pF)
No.6696-12/20
LC863364/56/48/40A
6. Pulse Input Conditions at Ta=-10°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V]
4.5 - 5.5
min.
1
max.
High/low level tPIH(1)
pulse width
•INT0, INT1
•INT2/T0IN
INT3/T0IN
(1/1 is selected for
noise rejection
clock.)
INT3/T0IN
(1/16 is selected for •Timer0-countable
noise rejection
clock.)
INT3/T0IN
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
•Timer0-countable
tCYC
tPIL(1)
tPIH(2)
tPIL(2)
4.5 - 5.5
4.5 - 5.5
4.5 - 5.5
2
tPIH(3)
tPIL(3)
•Interrupt acceptable
32
tPIH(4)
tPIL(4)
•Interrupt acceptable
128
(1/64 is selected for •Timer0-countable
noise rejection
clock.)
tPIL(5)
Reset acceptable
RES
4.5 - 5.5
4.5 - 5.5
200
8
µs
tPIH(6)
tPIL(6)
•Display position
controllable (Note)
•The active edge of
HS , VS
HS and VS must
be apart at least
1 tCYC.
•Refer to figure 6.
Rising/falling
time
tTHL
tTLH
Refer to figure 6.
4.5 - 5.5
500
ns
HS
7. AD Converter Characteristics at Ta=-10°C to + 70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V]
4.5 – 5.5
min.
max.
±1.5
Resolution
Absolute
precision
Conversion
time
Analog input
voltage range
Analog port
input current
N
ET
8
bit
LSB
(Note 3)
tCAD
VAIN
ADCR2=0 (Note 4)
ADCR2=1 (Note 4)
16
32
tCYC
V
AN4 - AN7
VSS
-1
VDD
1
IAINH
IAINL
VAIN=VDD
VAIN=VSS
µA
(Note 3) Absolute precision does not include quantizing error (1/2LSB).
(Note 4) Conversion time is the time till the complete digital conversion value for analog input value is set to a register after
the instruction to start conversion is sent.
No.6696-13/20
LC863364/56/48/40A
8. Sample Current Dissipation Characteristics at Ta=-10°C to +70°C, VSS=0V
The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the
recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents
through the output transistors and the pull-up MOS transistors are ignored.
Ratings
typ.
19
Parameter
Symbol
Pins
VDD
Conditions
unit
mA
VDD[V]
4.5 - 5.5
min.
max.
32
Current dissipation
during basic
operation
IDDOP(1)
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
VCO
(Note 3)
•VCO for OSD
operating
•Internal RC
oscillation stops
•HALT mode
•FmX’tal=32.768kHz
X’tal oscillation
•System clock :
VCO
•VCO for OSD stops
•Internal RC
oscillation stops
Current dissipation
in HALT mode
IDDHALT(1) VDD
IDDHALT(2) VDD
IDDHALT(3) VDD
4.5 - 5.5
7
12
mA
(Note 3)
•HALT mode
4.5 - 5.5
300
1200
µA
•FmX’tal=32.768kHz
X’tal oscillation
•VCO for system
stops
•VCO for OSD stops
•System clock :
Internal RC
•HALT mode
4.5 - 5.5
50
200
•FmX’tal=32.768kHz
X’tal oscillation
•VCO for system
stops
•VCO for OSD stops
•System clock : X’tal
•HOLD mode
Current dissipation
in HOLD mode
IDDHOLD
VDD
4.5 - 5.5
0.05
20
µA
•All oscillation stops.
(Note 3)
(Note 3) The currents through the output transistors and the pull-up MOS transistors are ignored.
No.6696-14/20
LC863364/56/48/40A
Recommended Oscillation Circuit and Sample Characteristics
The sample oscillation circuit characteristics in the table below is based on the following conditions:
• Recommended circuit parameters are verified by an oscillator manufacturer using a Sanyo provided oscillation evaluation
board.
• Sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally.
Recommended oscillation circuit and sample characteristics (Ta = -10 to +70°C)
Operating
supply voltage
range
Oscillation
stabilizing
time
Notes
Recommended circuit parameters
Frequency
Manufacturer Oscillator
C1
C2
Rf
Rd
typ.
max
32.768kHz
Seiko Epson
C-002RX
18pF
18pF
Open
4.5 – 5.5V
1.00s 1.50s
390kΩ
Notes
The oscillation stabilizing time period is the time until the VCO oscillation for the internal system becomes stable
after the following conditions. (Refer to Figure 2.)
1. The VDD becomes higher than the minimum operating voltage after the power is supplied.
2. The HOLD mode is released.
The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator
manufacturer with the following notes in your mind.
•
Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the
oscillation frequency on the production board.
• The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10°C
to +70°C. For the use with the temperature outside of the range herein, or in the applications requiring high reliability
such as car products, please consult with oscillator manufacturer.
• When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo
sales personnel.
Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low
gain in order to reduce the power dissipation, refer to the following notices.
• The distance between the clock I/O terminal (XT1 terminal XT2 terminal) and external parts should be as short as
possible.
• The capacitors’ VSS should be allocated close to the microcontroller’s GND terminal and be away from other GND.
• The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit.
XT1
XT2
Rf
Rd
C1
C2
X’tal
Figure 1 Recommended oscillation circuit.
No.6696-15/20
LC863364/56/48/40A
VDD
VDD limit
0V
Power supply
RES
Reset time
Internal RC
resonato
oscillation
XT1,XT2
VCO for system
Operation mode
tmsVCO
stable
Unfixed
Reset
Instruction execution mode
<Reset time and oscillation stabilizing time>
HOLD release signal
Valid
Internal RC
resonato
oscillation
XT1,XT2
VCO for system
Operation mode
tmsVCO
stable
HOLD
Instruction execution mode
<HOLD release signal and oscillation stabilizing time>
Figure 2 Oscillation stabilizing time
No.6696-16/20
LC863364/56/48/40A
VDD
RRES
RES
(Note) Determine the CRES, RRES value to
generate more than 200µs reset time.
CRES
Figure 3 Reset circuit
0.5VDD
<AC timing measurement point>
tCKCY
VDD
tCKL
tCKH
SCK0
1KΩ
tICK
tCKI
SI0
tCKO
50pF
SO0
SB0
< Timing >
< Test load >
Figure 4 Serial input / output test condition
No.6696-17/20
LC863364/56/48/40A
tPIL (1)-(5)
tPIH (1)-(4)
Figure 5 Pulse input timing condition – 1
tPIL(6)
HS
VS
0.75VDD
0.25VDD
tTLH
tPIL(6)
more than ±1tCYC
Figure 6 Pulse input timing condition - 2
LC863364A
10kΩ
HS
HS
C536
Figure 7 Recommended Interface circuit
No.6696-18/20
LC863364/56/48/40A
Noise filter
1 F
µ
C-Video
CVIN
200
Ω
1000pF
Coupling capacitor
Output impedance of C-Video before Noise filter should be less then 100Ω.
Figure 8 CVIN recommended circuit
100Ω
FILT
+
1M
Ω
2.2µF
33000pF
-
Figure 9 FILT recommended circuit
(Note) Place FILT parts on board as close to the microcontroller as possible.
P
S
Sr
P
SDA
SCL
tBUF
tHD;STA
tR
tF
tHD;STA
tsp
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S : start condition
P : stop condition
Sr : restart condition
tsp : Spike suppression
Standard mode : not exist
High speed mode : less than 50ns
Figure 10 IIC timing
No.6696-19/20
LC863364/56/48/40A
memo:
No.6696-20/20
PS
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