LC865628 [SANYO]
8-Bit Single Chip Microcontroller with the One-Time Programmable UVEPROM; 8位单片机与一次性可编程UVEPROM
| 型号： | LC865628 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-Bit Single Chip Microcontroller with the One-Time Programmable UVEPROM |
| 文件： | 总21页 (文件大小：671K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6744
CMOS IC
LC86E5632
8-Bit Single Chip Microcontroller
with the One-Time Programmable UVEPROM
Preliminary
Overview
The LC86E5632 is a CMOS 8-bit single chip microcontroller with one-time UVEPROM for the LC865600 series.
This microcontroller has the function and the pin description of the LC865600 series mask ROM version, and 32K-byte
EPROM. The program data is rewritable.
It is suitable to developing the program.
Features
(1) Option switching by EPROM data
The option function of the LC865600 series can be specified by the EPROM data.
LC86E5632 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time EPROM capacity : 32768 bytes
(3) Internal RAM capacity
Mask ROM version
:
512 bytes
PROM capacity
RAM capacity
512 bytes
512 bytes
512 bytes
384 bytes
384 bytes
384 bytes
384 bytes
LC865632
LC865628
LC865624
LC865620
LC865616
LC865612
LC865608
32512 bytes
28672 bytes
24576 bytes
20480 bytes
16384 bytes
12288 bytes
8192 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package
stamping and the screening. Contact our representative for further information.
Ver.1.02
30399
91400 RM (IM) HK No.6744-1/21
LC86E5632
: 4.5V to 6.0V
: 0.98µs to 400µs
: +10°C to +40°C
(4) Operating supply voltage
(5) Instruction cycle time
(6) Operating temperature
(7) The pin compatible with mask ROM version
(8) Applicable mask ROM version
: LC865632/ LC865628/ LC865624/LC865620/LC865616/
LC865612/ LC865608
: DIC64S, QFC64E
(9) Factory shipment
Notice for use
LC86E5632 is provided for the first release and small shipping of the LC865600 series.
At using, take notice of the followings.
(1) A point of difference LC86E5632 and LC865600 series
Item
LC86E5632
LC865632/28/24/20/16/12/08
Port form at reset
Operation after reset
releasing
Please refer “Port form at reset” on next page.
The option is specified until 3ms after The program is executed from 00H of the
going to a ‘H’ level to the reset terminal program counter immediately after going to
by dgrees. The program is executed a ‘H’ level to reset terminal.
from 00H of the program counter.
Operating supply voltage
range (VDD)
4.5V to 6.0V
2.7V to 6.0V
Operating temperature
range (Topg)
+10°C to +40°C
-30°C to +70°C
Total output current
[∑IOAH(1)]
∑
[ IOAH(2)]
Refer to ‘electrical characteristics’ on the semiconductor news.
Power dissipation
[IDDOP(1)]
[IDDOP(2)]
[IDDOP(3)]
[IDDOP(4)]
• A kind of the option corresponding of the LC86E5632
A kind of option
Pins, Circuits
Contents of the option
1. Input : No pull-up MOS Tr.
Output : N-channel open drain
Input/output form of
Input/output ports
Port 0
(Specified in a bit)
2. Input
: Pull-up MOS Tr.
Output : CMOS
Port 1,2
1. Input
: Programmable pull-up MOS Tr.
(Specified in a bit)
Output : N-channel open drain
2. Input
: Programmable pull-up MOS Tr.
Output : CMOS
Port 3,4,5
1. Input
: No Programmable pull-up MOS Tr.
(Specified in a bit)
Output : N-channel open drain
2. Input
: Programmable pull-up MOS Tr.
Output : CMOS
Pull-up MOS Tr. Of port7
port7
1. Pull-up MOS Tr. not provided
2. Pull-up MOS Tr. provided
(Specified in a bit)
* P74 has on pull-up resistor option.
The port operation related the option is different at reset. Refer to the next table.
No.6744-2/21
LC86E5632
•Port form at reset
Pin
P0
Contents of the option
LC86E5632
LC865632/28/24/20/16/12/08
Input : Not pull-up MOS Tr.
Output : N-channel open drain
Input : Pull-up MOS Tr.
Output : CMOS
(Same as the mask version)
Input mode without pull-up
MOS Tr. (Output is OFF)
Input mode without pull-up
Input mode
•The pull-up MOS Tr. is not provided MOS Tr. (Output is OFF)
during reset or several hundred
microseconds after releasing reset.
After that, the pull-up MOS Tr. is
provided. (Output is OFF)
P1,
P2
Input : Programmable pull-up (Same as the mask version)
Input mode without pull-up
MOS Tr. (Output is OFF)
MOS Tr.
Output : N-channel open drain
Input : Programmable pull-up (Same as the mask version)
Input mode without pull-up
MOS Tr. (Output is OFF)
MOS Tr.
Output : CMOS
P3,
P4,
P5
Input : Not Programmable
pull-up MOS Tr.
(Same as the mask version)
Input mode without pull-up
MOS Tr. (Output is OFF)
Output : N-channel open drain
Input : Programmable pull-up (Same as the mask version)
Input mode without pull-up
MOS Tr. (Output is OFF)
MOS Tr.
Output : CMOS
P7
Pull-up MOS Tr. not provided
(Same as the mask version)
Input mode
Input mode without pull-up
MOS Tr.
Pull-up MOS Tr. provided
Input mode without pull-up
•The pull-up MOS Tr. is not provided MOS Tr.
during reset or several hundred
microseconds after releasing reset.
After that, the pull-up MOS Tr. is
provided.
(2) Option
LC86E5632 uses 256 bytes which is addressed on 7F00H to 7FFFH in the program memory as option data area. This
area does not affect the execution of program but the program memory capacity of LC865632 is 32512 bytes which is
addressed on 0000H to 7EFFH.
The option data is created by the option specified program “SU865000.EXE”. The created option data is linked to the
program area by linkage loader “L865000.EXE”.
No.6744-3/21
LC86E5632
(3) ROM space
7FFFH
Opt ion data
Area 256 bytes
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
Opt ion
Data Area
7F00H
7EFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
Program area
32K bytes
Program area
28K bytes
Program area
24K bytes
Program area
20K bytes
Program area
16K bytes
Program area
12K bytes
Program area
8K bytes
0000H
LC865632
LC865628
LC865624
LC865620
LC865616
LC865612
LC865608
How to use
(1) Specification of option
Programming data for EPROM of the LC86E5632 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P5632.
(2) How to program for the EPROM
LC86E5632 can be programmed by the EPROM programmer with attachment ; W86EP5032D,
W86EP5032Q.
• Recommended EPROM programmer
Productor
EPROM programmer
Advantest
Andou
R4945, R4944, R4943
AF-9704
AVAL
PKW-1100, PKW-3000
MODEL 1890A
Minato electronics
• “27512 (Vpp=12.5V) Intel high speed programming” mode available. The address must be set to
“0000H to 7FFFH” and a jumper (DASEC) must be set to ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is the disabled function to read the data of the EPROM.
The following is the process in order to execute the data security.
1. Set ‘ON’ the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
• Data security is not executed when the data of all address have ‘FF’ at the sequence 2 above.
• The programming by a sequential operation “BLANK PROGRAM VERIFY” cannot be executed data security at the
sequence 2 above.
• Set to ‘OFF’ the jumper after executing the data security.
No.6744-4/21
LC86E5632
(4) How to eliminate
The programming data can be erased by using the EPROM eraser.
(5) Shielding
The UVEPROM (ultraviolet erasable programmable ROM) is in it. Put the seal on the window in use.
1 pin mark
of LSI
Data security
Data security
Not data security
Not data security
1 pin
1 pin
W86EP5032D
W86EP5032Q
No.6744-5/21
LC86E5632
Pin Assignment
SANYO:DIC64S
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P07
P06
P05
P04
P03
P02
P01
P00
P27
P26
P25
P24
P23
P22
P21
P20
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
2
3
4
5
6
7
8
9
RES
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XT1/P74
XT2
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P70/INT0
P71/INT1
P72/INT2/T0IN
P73/INT3/T0IN
P30
P31
P32
P33
SANYO:QFC64E
TEST1
RES
XT1/P74
XT2
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P27
P26
P25
P24
P23
P22
P21
P20
VSS
CF1
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
VDDVPP
VSS
P51
P50
P47
P46
P45
P44
No.6744-6/21
LC86E5632
System Block Diagram
Interrupt Control
Standby Control
IR
PLA
A15-A0
D7-D0
TA
EPROM
Control
CE
OE
DASEC
VDDVPP
CF
RC
EPROM (32KB)
X’tal
PC
Base Timer
SIO0
Bus Interface
Port 1
ACC
B Register
C Register
SIO1
Port 7
Timer 0
Timer 1
ADC
Port 8
ALU
Port 2
Port 3
PSW
RAR
INT0 to 3
Noise Filtter
Port 4
Real Time Service
Port 5
RAM
RAM
(128 bytes)
Stack Pointer
Port 0
Watch Dog Timer
No.6744-7/21
LC86E5632
LC86E5632 Pin description
Pin name
VSS
I/O
Function description
Option
PROM mode
-
-
-
Power pin (-)
Power pin (+)
Power pin (+)
-
-
-
-
-
VDD
VDDVPP
PORT0
Power for programming
-
I/O •8-bit input/output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
•Pull-up resistor :
Provided/Not provided
•Output form :
CMOS/N-channel open
drain
P00 to P07
PORT1
I/O •8-bit input/output port
Output form :
Data line
D0 to D7
P10 to P17
•Input/output can be specified in a bit unit
•Other pin functions
CMOS/N-channel open
drain
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
PORT2
Output form :
CMOS/N-channel open
drain
P20 to P27
PORT3
I/O •8-bit input/output port
Output form :
CMOS/N-channel open
drain
Address input
A7 to A0
P30 to P37
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
I/O •8-bit input/output port
PORT4
Output form :
CMOS/N-channel open
drain
Address input
A14 to A8 (*5)
P47 : TA (*4)
P40 to P47
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
I/O •2-bit input/output port
PORT5
Output form :
CMOS/N-channel open
drain
P50 to P51
•Input/output can be specified in a bit unit
•15V withstand at N-channel open drain output
•5-bit input port
PORT7
•Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
• P74 has no pull-up
resistor.
Input of PROM
control signals
DASEC (*1)
OE (*2)
•Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P70
I/O P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
CE (*3)
P71 to P74
I
P73 : INT3 input with noise filter/timer 0 event
input
P74 : 32.768kHz crystal oscillation terminal XT1
•Interrupt received forms, the vector addresses
rising
&
falling
rising falling
high
level
low
level
vector
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
Continue.
No.6744-8/21
LC86E5632
Pin name
I/O
I
Function description
Option
PROM mode
PORT8
•8-bit input port
•Other function
-
-
P80 to 87
AD input port (AN7 to AN0)
Reset pin
RES
I
-
-
-
-
TEST1
O
Test pin
Should be left unconnected.
XT1/ P74
XT2
I
•Input pin for 32.768kHz crystal oscillation
•Other function : Input port P74
-
-
-
-
In case of non use, connect to VDD.
•Output pin for 32.768kHz crystal oscillation
•Other function
O
In case of non use, should be left unconnected.
Input pin for the ceramic resonator oscillation
Output pin for the ceramic resonator oscillation
CF1
CF2
I
-
-
-
-
O
♦ All of port options can be specified in bit unit.
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 TA ! PROM control signal input
*5 A14 ! Address input
* Connect like the following figure to reduce noise into a VDD terminal.
Short-circuit the VDD terminal to the VDDVPP terminal.
Short-circuit the VSS terminal to the VSS terminal.
LSI
VDD
Power
Supply
VDDVPP
VSS
VSS
No.6744-9/21
LC86E5632
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
V
[V]
VDD
min.
-0.3
-0.3
max.
+7.0
Supply voltage
Input voltage
VDDMAX VDD,VDDVPP
VDD=VDDVPP
VI(1)
•Ports 71,72,73, 74
•Port 8
VDD+0.3
• RES
Input/Output
voltage
VIO(1)
•Ports 0,1,2
-0.3
VDD+0.3
15
•Ports 3,4,5 at CMOS
output
VIO(2)
Ports 3,4,5 at N-ch open
drain output option
•Ports 0,1,2,3,4,5
-0.3
-4
High
Peak
IOPH(1)
•CMOS output
•At each pins
mA
level
output
current
Total
output
current
ΣIOAH(1) Ports 0,1,2
ΣIOAH(2) Ports 3,4,5
The total of all pins
The total of all pins
-25
-20
output
current
Low
Peak
IOPL(1)
IOPL(2)
Ports 0,1,2,3,4,5
Port 70
At each pins
At each pins
20
15
level
output
current
Total
output
current
ΣIOAL(1) Ports 0,1,70
The total of all pins
The total of all pins
The total of all pins
40
40
output
current
Σ
IOAL(2) Port 2
ΣIOAL(3) Ports 3,4,5
Pdmax(1) DIP64S
Pdmax(2) QFP64E
Topr
80
°
Maximum power
dissipation
Ta=+10 to+40 C
720
420
40
mW
Ta=+10 to+40°C
Operating
10
°C
Temperature range
Storage
Tstg
-65
150
Temperature range
No.6744-10/21
LC86E5632
2. Recommended Operating Range at Ta=+10°C to +40°C, VSS=0V
Ratings
typ.
Parameter
Operating
Symbol
VDD(1)
Pins
Conditions
unit
V
VDD[V]
min.
4.5
max.
6.0
VDD
VDD
0.98µs ≤ tCYC
≤
µ
Supply voltage
Hold voltage
tCYC 400 s
VHD
RAMs and the
2.0
6.0
registers hold voltage
at HOLD mode.
Output disable
Input high
voltage
VIH(1)
VIH(2)
VIH(3)
Port 0
(Schmitt)
4.5 to 6.0 0.4VDD
+0.9
VDD
VDD
VDD
•Ports 1,2
Output disable
4.5 to 6.0 0.75VDD
•Ports 72,73 (Schmitt)
•Port 70
Output N-channel
Tr. OFF
4.5 to 6.0 0.75VDD
(Port input/interrupt)
•Port 71
• RES
(Schmitt)
VIH(4)
VIH(5)
VIH(6)
VIH(7)
Port 70
Output N-channel
Tr. OFF
4.5 to 6.0 0.9VDD
4.5 to 6.0 0.75VDD
4.5 to 6.0 0.75VDD
4.5 to 6.0 0.75VDD
VDD
VDD
VDD
13.5
(Watchdog timer)
•Port 74
Output N-channel
Tr. OFF
•Port 8
Ports 3,4,5 of
Output disable
CMOS output (Schmitt)
Ports 3,4,5 of open drain
Output disable
output
(Schmitt)
(Schmitt)
Input low
voltage
VIL(1)
VIL(2)
Port 0
Output disable
Output disable
4.5 to 6.0
4.5 to 6.0
VSS
VSS
0.2VDD
0.25VDD
•Ports 1,2,3,4,5
•Ports 72,73 (Schmitt)
•Port 70
VIL(3)
N-channel Tr.OFF
4.5 to 6.0
VSS
0.25VDD
(Port input/interrupt)
•Port 71
• RES
(Schmitt)
VIL(4)
VIL(5)
tCYC
Port 70
N-channel Tr.OFF
N-channel Tr.OFF
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
VSS
VSS
0.98
0.8VDD
-1.0
(Watchdog timer)
•Port 74
0.25VDD
•Port 8
Operation
cycle time
Oscillation
frequency
range
400
µs
FmCF(1)
CF1, CF2
CF1, CF2
•6MHz
6
MHz
(ceramic resonator
oscillation)
(Note 1)
•Refer to figure 1
•1.5MHz
FmCF(2)
4.5 to 6.0
1.5
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
FmRC
FsXtal
4.5 to 6.0
4.5 to 6.0
0.3
0.8
3.0
XT1, XT2
32.768
kHz
(crystal oscillation)
•Refer to figure 2
Continue.
No.6744-11/21
LC86E5632
Ratings
typ.
Parameter
Oscillation
Symbol
Pins
Conditions
unit
ms
VDD[V]
4.5 to 6.0
min.
max.
tmsCF(1)
CF1, CF2
•6MHz
stabilizing
time period
(ceramic resonator oscillation)
•Refer to figure 3
•1.5MHz
(Note 1)
tmsCF(2)
tssXtal
CF1, CF2
XT1, XT2
4.5 to 6.0
4.5 to 6.0
(ceramic resonator oscillation)
•Refer to figure 3
•32.768kHz (crystal oscillation)
•Refer to figure 3
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6744-12/21
LC86E5632
3. Electrical Characteristics at Ta=+10°C to +40°C, VSS=0V
Ratings
typ.
Parameter
Symbol
IIH(1)
Pins
Conditions
•Output disable
unit
VDD[V]
4.5 to 6.0
min.
max.
5
µ
A
Input high
current
Ports 3,4,5 at open
drain output
•VIN=13.5V
(including off-leakage
current of the output Tr.)
•Output disable
IIH(2)
IIH(3)
•Port 0 without
pull-up MOS Tr.
•Ports 1,2,3,4,5
4.5 to 6.0
4.5 to 6.0
1
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of the output Tr.)
VIN=VDD
•Ports 70,71,72,73
without pull-up
MOS Tr.
1
1
•Port 8
IIH(4)
IIL(1)
RES
VIN=VDD
4.5 to 6.0
4.5 to 6.0
Input low
current
•Ports 1,2,3,4,5
•Port 0 without
pull-up MOS Tr.
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
-1
-1
(including off-leakage
current of the output Tr.)
VIN=VSS
IIL(2)
IIL(3)
•Ports 70,71,72,73
without pull-up
MOS Tr.
4.5 to 6.0
•Port 8
RES
VIN=VSS
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
-1
Output high
voltage
VOH(1) Ports 0,1,2,3,4,5 at
CMOS output
IOH=-1.0mA
IOH=-0.1mA
IOL=10mA
IOL=1.6mA
IOL=1mA
VDD-1
VDD-0.5
V
VOH(2)
Output low
voltage
VOL(1) Ports 0,1,2,3,4,5
VOL(2)
1.5
0.4
0.4
0.4
VOL(3) Port 70
VOL(4)
IOL=0.5mA
Ω
k
Pull-up MOS
Tr. resistor
Hysteresis
voltage
Rpu
•Ports 0,1,2,3,4,5
•Ports 70,71,72,73
•Ports 0,1,2,3,4,5
•Ports 70,71,72,73
• RES
VOH=0.9VDD
4.5 to 6.0
15
40
70
VHIS
Output disable
4.5 to 6.0
0.1VDD
V
Pin capacitance CP
All pins
•f=1MHz
4.5 to 6.0
10
pF
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
No.6744-13/21
LC86E5632
4. Serial Input/Output Characteristics at Ta=+10°C to +40°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
SCK0,
Conditions
unit
VDD[V]
4.5 to 6.0
min.
max.
Cycle
tCKCY(1)
tCKL(1)
Refer to figure 5
2
1
tCYC
SCK1
Low Level
pulse width
High Level
pulse width
Cycle
tCKH(1)
1
2
tCKCY(2)
tCKL(2)
SCK0,
SCK1
•Use pull-up
4.5 to 6.0
Ω
resistor (1k ) in
Low Level
pulse width
High Level
pulse width
1/2tCKCY
1/2tCKCY
the open drain
output.
tCKH(2)
tICK
•Refer to figure 5
µ
s
•SI0,SI1
•Data set-up to
SCK0,1
4.5 to 6.0
4.5 to 6.0
0.1
0.1
Data set-up time
•SB0,SB1
•Data hold from
SCK0,1
Data hold time
tCKI
•Refer to figure 5
•Use pull-up
Output delay time
(External clock
using for serial
transfer clock)
Output delay time
(Internal clock
using for serial
transfer clock)
tCKO(1)
•SO0,SO1
•SB0,SB1
7/12
tCYC
+0.2
Ω
resistor (1k ) in
the open drain
output.
•Data hold from
SCK0,1
tCKO(2)
1/3
tCYC
+0.2
•Refer to figure 5
No.6744-14/21
LC86E5632
5. Pulse Input Conditions at Ta=+10°C to +40°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V]
4.5 to 6.0
min.
1
max.
High/low level
pulse width
tPIH(1) •INT0, INT1
•Interrupt acceptable
•Timer0-countable
tCYC
tPIL(1)
•INT2/T0IN
•INT3
tPIH(2) INT3
•Interrupt acceptable
•Timer0-countable
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
2
tPIL(2)
(The noise rejection clock
selected to 1/1.)
tPIH(3) INT3
•Interrupt acceptable
•Timer0-countable
32
tPIL(3)
(The noise rejection clock
selected to 1/16.)
RES
µ
s
tPIL(4)
Reset acceptable
200
6. AD Converter Characteristics at Ta=+10°C to + 40°C, VSS=0V
Ratings
Parameter
Resolution
Symbol
Pins
Conditions
unit
VDD[V]
min.
typ.
8
max.
±1.5
N
4.5 to 6.0
4.5 to 6.0
bit
Absolute precision
(Note 2)
ET
LSB
µ
s
Conversion time
tCAD
AD conversion time = 16
4.5 to 6.0
15.68
(tCYC=
0.98µs)
31.36
65.28
(tCYC=
4.08µs)
130.56
(tCYC=
4.08µs)
VDD
×
tCYC
(ADCR2=0) (Note 3)
AD conversion time = 32
×
tCYC
(tCYC=
0.98µs)
VSS
(ADCR2=1) (Note 3)
Analog input
voltage range
Analog port
input current
VAIN
AN0 to AN7
4.5 to 6.0
V
µ
A
IAINH
IAINL
VAIN=VDD
VAIN=VSS
4.5 to 6.0
4.5 to 6.0
1
-1
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6744-15/21
LC86E5632
7. Current Dissipation Characteristics at Ta=+10°C to +40°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
VDD
Conditions
•FmCF=6MHz
unit
mA
VDD[V]
4.5 to 6.0
min.
max.
26
Current dissipation
during basic operation
(Note 4)
IDDOP(1)
13
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•FmCF=1.5MHz
Ceramic resonator
oscillation
IDDOP(2)
4.5 to 6.0
7
14
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•FmCF=0Hz
IDDOP(3)
IDDOP(4)
4.5 to 6.0
4
4
10
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•FmCF=0Hz
4.5 to 6.0
8
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
Continue.
No.6744-16/21
LC86E5632
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
mA
VDD[V]
4.5 to 6.0
min.
max.
10
Current dissipation
in HALT mode
IDDHALT(1)
•HALT mode
5
•FmCF=6MHz
Ceramic resonator
oscillation
(Note 4)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•HALT mode
•FmCF=1.5MHz
Ceramic resonator
oscillation
IDDHALT(2)
4.5 to 6.0
2.2
4.6
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•HALT mode
FmCF=0Hz
IDDHALT(3)
4.5 to 6.0
550
1000
µA
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•HALT mode
FmCF=0Hz
IDDHALT(4)
4.5 to 6.0
25
100
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
HOLD mode
Current dissipation
in HOLD mode
IDDHOLD(1)
IDDHOLD(2)
VDD
4.5 to 6.0
2.5 to 4.5
0.05
0.02
30
20
(Note 4)
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6744-17/21
LC86E5632
Table 1. Ceramic resonator oscillation recommended constant (main clock)
Oscillation type
Maker
Oscillator
CSA12.0MTZ
CSA12.0MTZ
CST12.0MTW
CSA3.00MG040
CST3.00MGW040
C1
C2
Rf
Rd
560Ω
0Ω
12MHz ceramic resonator
oscillation
Murata
33pF
39pF
33pF
30pF
OPEN
OPEN
OPEN
OPEN
OPEN
Ω
560
on chip
3MHz ceramic resonator
oscillation
Murata
100pF
100pF
1.5Ω
Ω
1.5
on chip
* Both C1 and C2 must use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation recommended constant (sub clock)
Oscillation type
Maker
Kyocera
Oscillator
C3
18pF
4pF
C4
32.768kHz crystal oscillation
KF-38G-13P0200
18pF
4pF
Seiko Epson
MC-306,C-002RX,32.768kHz
* Both C3 and C4 must use J rank (±5%) and CH characteristics.
(It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.)
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2
XT1
XT2
Rf
Rd
X’tal
C1
C2
C3
C4
CF
Figure 1 Main-clock circuit
Ceramic oscillation circuit
Figure 2 Sub-clock circuit
Crystal oscillation
No.6744-18/21
LC86E5632
VDD
VDD limit
OV
Power supply
RES
Reset time
Interrnal RC
resonator
oscillation
tmsCF
tssXtal
CF1, CF2
XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stabilizing time. >
HOLD release signal
Valid
Interrnal RC
resonator
oscillation
tmsCF
tssXtal
CF1, CF2
XT1, XT2
Operation mode
HOLD
Instruction execution mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3 Oscillation stable time
No.6744-19/21
LC86E5632
VDD
RRES
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
CRES
Figure 4 Reset circuit
0.5VDD
<AC timing point>
tCKCY
VDD
tCKL
tCKH
SCK0
SCK1
1KΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
<Test load>
Figure 5 Serial input / output test condition
tPIL
tPIH
Figure 6 Pulse input timing condition
No.6744-20/21
LC86E5632
No.6744-21/21
PS
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