LC866024 [SANYO]
8-Bit Single Chip Microcontroller with One-Time PROM; 8位单片机与一次性PROM
| 型号： | LC866024 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-Bit Single Chip Microcontroller with One-Time PROM |
| 文件： | 总22页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN4212A
CMOS IC
LC86P6032
8-Bit Single Chip Microcontroller
with One-Time PROM
Overview
The LC86P6032 microcontroller, a new addition to the LC866000 series, is a 8-bit single chip CMOS microcontroller with
one-time PROM. This microcontroller has the same function and pin assignment as for the LC866000 series mask ROM
version, and a 32K-byte PROM.
Features
(1) Option switching using PROM data
The optional functions of the LC866000 series can be specified using PROM data.
The functions of the trial products can be evaluated using a mass production board.
(2) Internal one-time PROM capacity
(3) Internal RAM capacity
Mask ROM version
: 32768 bytes
512 bytes
PROM capacity
:
RAM capacity
LC866032
LC866028
32512 bytes
28672 bytes
512 bytes
512 bytes
512 bytes
384 bytes
384 bytes
384 bytes
384 bytes
LC866024
24576 bytes
LC866020
20480 bytes
LC866016
16384 bytes
LC866012
12288 bytes
LC866008
8192 bytes
(4) Operating supply voltage
(5) Instruction cycle time
(6) Operating temperature range
: 4.5V to 6.0V
: 0.98µs to 400µs
: -30°C to +70°C
(7) Pin and package compatible with the mask ROM version
(8) Applicable mask ROM version
: LC866032/LC866028/LC866024/LC866020/LC866016/LC866012
/LC866008
: DIP64S
(9) Factory shipment
: QFP64E
Programming service
We offer various services at nominal charges. These include ROM writing, ROM reading, and package stamping and
screening. Contact our local representatives for further information.
Ver.1.02G
31293
91400 RM (IM) TW No.4212-1/22
LC86P6032
Notice for use
When using, please take note of the following.
(1) Differences between the LC86P6032 and the LC866000 series
Item
LC86P6032
LC866032/28/24/20/16/12/08
Port status at reset
Operation after releasing
reset
Please refer to “Port status at reset” on the next page.
The option is specified by degrees within The program located at 00H is executed
3ms after applying a ‘H’ level to the reset immediately after applying a ‘H’ level to
pin.
the reset pin.
The program located at 00H is
executed.
Output form of segment
•S0/T0 to S6/T6
•S7/T7 to S15/T15
•S16 to S23
Pulldown resistor
Not provided
Pulldown resistor : Provided/Not provided
Specified by the option
Provided(fixed)
Provided(fixed)
Provided(fixed)
Not provided
Specified by the option
Specified by the option
2.5V to 6.0V
•S24 to S29
Operating supply
voltage range (VDD)
Power dissipation
4.5V to 6.0V
Refer to “electrical characteristics” on the semiconductor news.
LC86P6032 uses 256 bytes that is addressed on 7F00H to 7FFFH in the program memory as the option
configuration data area. This option configuration cannot execute all options which LC866000 series have. Next
tables show the options that correspond and not correspond to LC86P6032.
• LC86P6032 Options
Option
Configuration of input/output ports
Pins, Circuits
Port 0
Option Settings
1. Input : No pull-up MOS transistor
Output : N-channel open drain
(Can be specified for
each bit.)
2. Input : Pull-up MOS transistor
Output : CMOS
Port 1
1. Input : Programmable pull-up MOS transistor
Output : N-channel open drain
(Can be specified for
each bit.)
2. Input : Programmable Pull-up MOS transistor
Output : CMOS
Port 7 pull-up MOS transistor
Port 7
1. Pull-up MOS transistor not provided.
(Can be specified for 2. Pull-up MOS transistor provided.
each bit.)
• A kind of option not corresponding LC86P6032
Option Pins, Circuits
LC86P6032
LC866032/28/24/20/16/12/08
Pull-down resistor of high ·S0/T0 to S6/T6
voltage withstand output ·S16 to S23
Not provided
Provided(fixed)
Not provided
Specified by the option
Specified by the option
Specified by the option
terminal
·S24 to S29
(specified in a bit)
The port operation related to the option is different at reset. Please refer to the next table.
No.4212-2/22
LC86P6032
• Port configuration at reset
Pin Option settings
P0
LC86P6032
LC866032/28/24/20/16/12/08
Input : No pull-up MOS transistor
Output : N-channel open drain
Input : Pull-up MOS transistor
Output : CMOS
(Same as for the mask version)
Input mode without pull-up
MOS transistor (Output is OFF)
Input mode with pull-up MOS
Input mode
•The Pull-up MOS transistor is transistor (Output is OFF)
not present during reset or several
hundred
microseconds
after
releasing reset. After that, the
pull-up MOS transistor is present.
(Output is OFF)
P1
P7
Input : Programmable pull-up MOS (Same as for the mask version)
Input mode without pull-up
transistor
MOS transistor (Output is OFF)
Output : N-channel open drain
Input : Programmable pull-up MOS (Same as for the mask version)
Input mode without pull-up
transistor
MOS transistor (Output is OFF)
Output : CMOS
Pull-up MOS transistor not
provided
(Same as for the mask version)
Input mode
Input mode without pull-up
MOS transistor
Pull-up MOS transistor provided
Input mode with pull-up MOS
•The Pull-up MOS transistor is transistor
not present during reset or several
hundred
microseconds
after
releasing reset. After that, the
pull-up MOS transistor is present.
(2) Option
The option data is created by the option specified program “SU866000.EXE”. The created option data is linked to the
program area by the linkage loader “L866000.EXE”.
(3) ROM space
LC86P6032 and LC866000 series use 256 bytes that is addressed on 07F00H to 07FFFH in the program memory as the
option specified data area. These program memory capacity are 32512 bytes that is addressed on 0000H to 7EFFH.
7FFFH
7F00H
7EFFH
Option data
area 256 bytes
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
Option
Data Area
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0000H
32K
28K
24K
20K
16K
12K
8K
LC866032
LC866028
LC866024
LC866020
LC866016
LC866012
LC866008
LC86P6032
(4) Ordering information
1.When ordering identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
No.4212-3/22
LC86P6032
How to use
(1) Specification of option
LC86P6032 is programmed after specifying option data. The option is specified by the SU866000.EXE. The specified
option file and the file created by our macro assembler (M866000.EXE) are linked by our linker (L866000.EXE) which
creates HEX file, then the option code is put in the option specified area (07F00H to 07FFFH) of its HEX file.
(2) How to program for the EPROM
The LC86P6032 can be programmed by an EPROM programmer with attachments W86EP6032D and W86EP6032Q.
- Recommended EPROM programmer
Supplier
Advantest
EPROM programmer
R4945, R4944, R4943
AF-9704
Andou
AVAL
PKW-1100, PKW-3000
MODEL 1890A
Minato electronics
- “27512 (Vpp=12.5V) Intel high-speed programming” mode available. The address must be set to “0000H to 07FFFH”
and the jumper (DASEC) must be set ‘OFF’ at programming.
(3) How to use the data security function
“Data security” is a function to prevent EPROM data from being read.
Instructions on using the data security function :
1. Set the jumper of attachment “ON”.
2. Attempt to program the EPROM. The EPROM programmer will display an error. The error indication is a result of
normal activity of the data security feature. This is not a problem with the EPROM programmer chip.
(Notes)
• The data security function is not carried out when the data of all addresses contain “FF” at step 2 above.
• Data security cannot be executed when the sequential operation “BLANK=>PROGRAM=>VERIFY” is used at step 2 above.
• Set the jumper “OFF” after execution of data security.
1 pin mark
of LSI
Data security
Data security
Not data security
W86EP6032Q
Not data security
1 pin
1 pin
W86EP6032D
No.4212-4/22
LC86P6032
Pin Assignment
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
2
P06
3
P05
4
P04
5
P03
P14/SI1/SB1
P15/SCK1
P16/BUZ
P17/PWM
TEST1
6
P02
7
P01
8
P00
9
S29
RES
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S28
S27
XT1
XT2
S26
S25
VSS
S24
CF1
S23
CF2
S22
VDD
S21
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P70/INT0
P71/INT1
72/INT2/T0IN
73/INT3/T0IN
S0/T0
S20
S19
S18
S17
S16
VP
VDDVPP
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S1/T1
S2/T2
S3/T3
S4/T4
S5/T5
S6/T6
S7/T7
Package Dimension
(unit : mm)
3071
SANYO : DIP-64S(750mil)
No.4212-5/22
LC86P6032
Pin Assignment
TEST1
RES
XT1
XT2
VSS
CF1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
VP
CF2
VDD
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P70/INT0
P71/INT1
72/INT2/T0IN
73/INT3/T0IN
VDDVPP
Package Dimension
(unit : mm)
3159
SANYO : QIP-64E
Notes
• The QFP packages should be heat-soaked for 24 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours.
No.4212-6/22
LC86P6032
System Block Diagram
Interrupt Control
Stand-by Control
IR
PLA
A15-A0
D7-D0
TA
CE
OE
PROM
Control
DASEC
VDDVPP
CF
RC
PROM(32KB)
PC
X’tal
Base Timer
SIO0
Bus Interface
Port 1
ACC
B Register
C Register
SIO1
Port 7
Timer 0
Timer 1
ADC
Port 8
ALU
PSW
RAR
INT0 to 3
Noise Rejection Filter
Real Time Service
RAM
Stack Pointer
Port 0
XRAM
(128 bytes)
VFD Controller
Watch dog Timer
High Voltage Output
No.4212-7/22
LC86P6032
Pin Description
Pin Description Table
Pin name
VSS
I/O
Function Description
Power supply pin (-)
Power supply pin (+)
Option
Function in PROM mode
Power for programming
-
-
-
VDD
VP
Power supply pin (-) for the VFD output
pull-down resist
VDDVPP
PORT0
-
Power supply pin (+) *6
I/O •8-bit Input / output port
•Input for port 0 interrupt
•Input/output in nibble units
•Input for HOLD release
•Pull-up resistor :
Present/Not present
•Output form :
CMOS/N-channel
open drain
P00 to P07
PORT1
I/O •8-bit input/output port
•Data direction can be specified for each bit.
•Other pin functions
Output form :
Data input/output
D0 to D7
P10 to P17
CMOS/N-channel
open drain
P10 : SIO0 data output
P11 : SIO0 data input/bus input/output
P12 : SIO0 clock input/output
P13 : SIO1 : data output
P14 : SIO1 : data input/bus input/output
P15 : SIO1 clock input/output
P16 : Buzzer output
P17 : Timer 1 output (PWM output)
•4-bit input port
PORT7
P70
•Pull-up resistor :
•Other pin functions
Present/Not present
I/O
I
P70 : INT0 input/HOLD release/N-channel
Tr. output for watchdog timer
Input of PROM control
signal
P71 to P73
P71 : INT1 input/HOLD release
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0
event input
•DASEC (*1)
• OE (*2)
• CE (*3)
•Interrupt received format, vector address
Rising
Falling
Rising
H level L level
Vector
/falling
INT0
INT1
INT2
INT3
Enable
Enable
Enable
Enable
Enable Disable Enable
Enable Disable Enable
Enable
Enable
03H
0BH
13H
1BH
Enable
Enable
Enable Disable Disable
Enable Disable Disable
PORT8
I
•4-bit input port
P80 to P83
•Other pin functions
AD input port (4 port pins)
S0/T0 to
S6/T6 *7
S7/T7 to
S15/T15
O
O
Output for VFD display controller
segment/timing in common
•Output for VFD display controller
segment/timing in common
•S14/T14 : TA (*4)
•S15/T15 : A14 (*5)
•Internal pull-down resistor output
*8
S16 to S23
O
O
I
•Output for VFD display controller
segment
Address input
A13 to A0
*9
•Internal pull-down resistor output
•Output for VFD display controller
segment
S24 to S29
*10
RES
Reset pin
No.4212-8/22
LC86P6032
Pin name
TEST1
I/O
O
Function Description
Option
Function in PROM mode
Test pin
Should be left open
XT1
XT2
I
Input pin for 32.768kHz crystal oscillation
When not used, connect to VDD
O
Output pin for 32.768kHz crystal oscillation
When not used, should be left open
CF1
CF2
I
Input pin for ceramic resonator oscillation
Output pin for ceramic resonator oscillation
O
• All port options can be specified in bit units.
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 TA ! PROM control signal input
*5 A14 ! Address input
*6 Connect as shown in the following figure to reduce noise into VDD pin.
• Short-circuit the VDD pin to the VDDVPP pin.
LSI
VDD
Power
Supply
VDDVPP
VSS
*7 S0/T0 to S6/T6 : not provided the pull-down resistor
*8 S7/T7 to S15/T15 : provided the pull-down resistor (fixed)
*9 S16 to S23 : provided the pull-down resistor (fixed)
*10 S24 to S29 : not provided the pull-down resistor
No.4212-9/22
LC86P6032
1. Absolute Maximum Ratings at VSS=0V and Ta=25°C
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
V
VDD[V]
min.
-0.3
-0.3
max.
+7.0
Supply voltage
Input voltage
VDDMAX VDD,VDDVPP
VDD+0.3
VI(1)
•Ports 71,72,3,8
• RES
VI(2)
VO
VP
VDD-4.5
VDD-4.
5
VDD+0.3
VDD+0.3
Output voltage
•S0/T0 to S15/T15
•S16 to S29
•Ports 0, 1
•Port 70
Input/Output
voltage
VIO
-0.3
VDD+0.3
High
Peak
IOPH(1)
Ports 0, 1
•CMOS output
•At each pin
-4
mA
level
output
current
output
current
IOPH(2)
IOPH(3)
S0/T0 to S15/T15 •At each pin
-30
-15
S16 to S29
•At each pin
Total
∑IOAH(1) Port 0
∑IOAH(2) Port 1
Total of all pins
Total of all pins
-10
output
current
-10
∑IOAH(3) •S0/T0 to S15/T15 Total of all pins
-130
•S16 to S29
Low
Peak
IOPL(1)
IOPL(2)
Ports 0, 1
Port 70
At each pin
At each pin
20
15
level
output
current
Total
output
current
∑IOAL(1) Port 0
Total of all pins
Total of all pins
40
40
output
current
∑IOAL(2) Ports 1, 70
Power dissipation Pdmax(1)
DIP64S
QFP64E
Ta=-30 to+70°C
Ta=-30 to+70°C
760
430
+70
mW
(max.)
Pdmax(2)
Topr
Operating
-30
-65
°C
temperature range
Storage
Tstg
+150
temperature range
Notes
• The QFP packages should be heat-soaked for 24 hours at 125°C immediately prior to mounting (This baking is called
pre-baking).
• After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a
temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours.
No.4212-10/22
LC86P6032
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
VDD
Pins
Conditions
unit
V
VDD[V]
min.
4.5
max.
6.0
Operating
supply voltage
range
VDD
VDD
0.98µs ≤ tCYC ≤
400µs
Hold voltage
VHD
RAM and registers
retain their
2.0
6.0
pre-HOLD mode
values
Pull-down
voltage
VP
VP
4.5 to 6.0
-35
VDD
VDD
VDD
Input high
voltage
VIH(1)
VIH(2)
Port 0 (Schmitt)
Output disable
Output disable
4.5 to 6.0 0.4VDD
+0.9
•Port 1
4.5 to 6.0 0.75VDD
•Ports 72,73
(Schmitt)
VIH(3)
•Port 70
Output N-channel 4.5 to 6.0 0.75VDD
Tr. OFF
VDD
VDD
port input/interrupt
•Port 71
• RES
(Schmitt)
VIH(4)
Port 70
Output N-channel 4.5 to 6.0 0.9VDD
Tr. OFF
Watchdog timer
Port 8
VIH(5)
VIL(1)
VIL(2)
4.5 to 6.0 0.75VDD
VDD
Input low
voltage
Port 0 (Schmitt)
•Port 1
Output disable
Output disable
4.5 to 6.0 VSS
4.5 to 6.0 VSS
0.2VDD
0.25VDD
•Ports 72,73
(Schmitt)
VIL(3)
•Port 70
N-channel
Tr. OFF
4.5 to 6.0 VSS
0.25VDD
port input/interrupt
•Port 71
• RES
(Schmitt)
VIL(4)
Port 70
N-channel
Tr. OFF
4.5 to 6.0 VSS
4.5 to 6.0 VSS
0.8VDD
-1.0
Watchdog timer
Port 8
VIL(5)
tCYC
0.25VDD
400
Operation
cycle time
4.5 to 6.0
0.98
µs
continue
No.4212-11/22
LC86P6032
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V]
min.
max.
12.24 MHz
Oscillation
frequency
range
FmCF(1) CF1,CF2
•12MHz (ceramic 4.5 to 6.0 11.76
resonator
12
oscillation)
(Note 1)
•Refer to figure 1
FmCF(2) CF1,CF2
•3MHz (ceramic
resonator
4.5 to 6.0
2.94
0.4
3
3.06
oscillation)
•Refer to figure 1
RC oscillation
FmRC
FsXtal
4.5 to 6.0
4.5 to 6.0
0.8
2.0
XT1,XT2
•32.768kHz
32.768
kHz
(crystal resonator
oscillation)
•Refer to figure 2
Oscillation
stable time
period
tmsCF(1) CF1,CF2
tmsCF(2) CF1,CF2
•12MHz (ceramic 4.5 to 6.0
resonator
0.02
0.1
1
0.2
1
ms
oscillation)
(Note 1)
•Refer to figure 3
•3MHz (ceramic
resonator
4.5 to 6.0
4.5 to 6.0
oscillation)
•Refer to figure 3
•32.768kHz
tssXtal
XT1,XT2
1.5
s
(crystal resonator
oscillation)
•Refer to figure 3
(Note 1)
The oscillation constants are shown on Table 1 and Table 2.
No.4212-12/22
LC86P6032
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
IIH(1)
Pins
Conditions
unit
VDD[V]
4.5 to 6.0
min.
max.
1
Input high
current
•Port 1
•Output disabled
•Pull-up MOS Tr.
OFF
µA
•Port 0 without
pull-up MOS Tr.
•VIN=VDD
(including off-state
leak current of
output Tr.)
IIH(2)
•Port 7 without
pull-up MOS Tr.
•Port 8
VIN=VDD
4.5 to 6.0
1
1
IIH(3)
IIL(1)
RES
VIN=VDD
4.5 to 6.0
4.5 to 6.0
Input low
current
•Port 1
•Output disabled
•Pull-up MOS Tr.
OFF
-1
•Port 0 without
pull-up MOS Tr.
•VIN=VSS
(including off-state
leak current of
output Tr.)
IIL(2)
•Port 7 without
pull-up MOS Tr.
•Port 8
VIN=VSS
4.5 to 6.0
4.5 to 6.0
-1
-1
IIL(3)
RES
VIN=VSS
Output high
voltage
VOH(1)
VOH(2)
VOH(3)
VOH(4)
Ports 0, 1 at
CMOS output
IOH=-1.0mA
IOH=-0.1mA
4.5 to 6.0 VDD-1
4.5 to 6.0 VDD-0.5
V
VDD-1.8
4.5 to 6.0
S0/T0 to S15/T15 IOH=-20mA
•IOH=-1mA
4.5 to 6.0 VDD-1
•The current IOH at
each pin should be
between 0 and
-1mA.
VOH(5)
VOH(6)
S16 to S29
IOH=-5mA
4.5 to 6.0 VDD-1.8
4.5 to 6.0 VDD-1
•IOH=-1mA
•The current IOH at
each pin should be
between 0 and
-1mA.
Output low
voltage
VOL(1)
VOL(2)
Ports 0, 1
IOL=10mA
4.5 to 6.0
4.5 to 6.0
1.5
0.4
•IOL=1.6mA
•When the total
current of the
ports 0, 1 is not
over 40mA.
VOL(3)
Rpu
Port 70
IOL=1mA
4.5 to 6.0
0.4
70
Pull-up MOS
Tr. resistance
•Ports 0, 1
•Port 7
VOH=0.9VDD
4.5 to 6.0
15
40
KΩ
continue
No.4212-13/22
LC86P6032
Ratings
typ.
Parameter
Symbol
IOFF(1)
Pins
Conditions
unit
VDD[V]
min.
-1
max.
200
Output off-
leakage
S0/T0 to S6/T6, •Output P-ch Tr. OFF 4.5 to 6.0
S24 to S29 without •VOUT=VSS
µA
current
pull-down resistor
IOFF(2)
Rpd
•Output P-ch Tr. OFF 4.5 to 6.0
•VOUT=VDD-40V
-30
60
Pull-down
resistor
S7/T7 to S15/T15, •Output P-ch Tr. OFF
S16 to S23 with
•VOUT=3V
pull-down resistor •Vp=-30V
5.0
100
0.1VDD
10
KΩ
V
Hysteresis
voltage
VHIS
CP
•Ports 0, 1
•Port 7
Output disable
4.5 to 6.0
4.5 to 6.0
• RES
Pin
All pins
•f=1MHz
pF
capacitance
•Unmeasured input
pins are set to
VSS level
•Ta=25 C
°
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V] min.
max.
Cycle
tCKCY(1) SCK0,
Refer to figure 5.
4.5 to 6.0
4.5 to 6.0
2
1
tCYC
SCK1
Low-level
pulse width
High-level
pulse width
Cycle
tCKL(1)
tCKH(1)
4.5 to 6.0
1
2
tCKCY(2) SCK0,
•Use pull-up
4.5 to 6.0
4.5 to 6.0
SCK1
resistor (1kΩ)
when set to open-
drain output.
Low-level
pulse width
High-level
pulse width
Data set up time
tCKL(2)
tCKH(2)
tICK
1/2
tCKCY
1/2
4.5 to 6.0
•Refer to figure 5.
tCKCY
•SI0,SI1
•Data set-up to
SCK0,1
4.5 to 6.0 0.1
µs
•SB0,SB1
•Data hold from
SCK0,1
Data hold time
tCKI
4.5 to 6.0 0.1
4.5 to 6.0
•Refer to figure 5.
Output delay time
(Serial clock is
external clock)
tCKO(1)
•SO0,SO1
•SB0,SB1
•Use pull-up
7/12
tCYC
+0.2
resistor (1kΩ)
when set to open-
drain output.
•Data hold from
SCK0,1
Output delay time
(Serial clock is
internal clock)
tCKO(2)
4.5 to 6.0
1/3
tCYC
+0.2
•Refer to figure 5.
No.4212-14/22
LC86P6032
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
VDD[V]
4.5 to 6.0
min.
1
max.
High/low level tPIH(1)
•INT0, INT1
•INT2/T0IN
•Interrupt acceptable
•Timer0 pulse
tCYC
pulse width
tPIL(1)
countable
tPIH(2)
tPIL(2)
INT3/T0IN
•Interrupt acceptable
4.5 to 6.0
4.5 to 6.0
4.5 to 6.0
2
(The noise rejection •Timer0 pulse
clock selected to
1/1.)
countable
tPIH(3)
tPIL(3)
INT3/T0IN
•Interrupt acceptable
128
200
(The noise rejection •Timer0 pulse
clock selected to
1/64.)
countable
tPIL(4)
Reset acceptable
µs
RES
6. AD Converter Characteristics at Ta=-30°C to +70°C, VSS=0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 to 6.0
4.5 to 6.0
min.
typ.
8
max.
unit
bit
Resolution
N
Absolute precision ET
(Note 2)
±1.5
LSB
µs
Conversion time
tCAD
AD conversion time 4.5 to 6.0 15.68
65.28
= 16 × tCYC
(ADCR2=0)
(Note 3)
(tCYC=
(tCYC=
4.08µs)
0.98µs)
AD conversion time
= 32 × tCYC
(ADCR2=1)
(Note 3)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
Analog input
voltage range
Analog port
input current
VAIN
AN0 to AN3
4.5 to 6.0 VSS
VDD
1
V
IAINH
IAINL
VAIN=VDD
VAIN=VSS
4.5 to 6.0
µA
4.5 to 6.0
-1
(Note 2) Quantizing error (±1/2 LSB) is ignored.
(Note 3) The conversion time is the period from execution of the instruction to start conversion to the completion of shifting
the A/D converted value to the register.
No.4212-15/22
LC86P6032
7. Current Drain Characteristics at Ta=-30°C to +70°C, VSS=0V
Ratings
typ.
Parameter
Symbol
Pins
VDD
Conditions
unit
mA
VDD[V]
4.5 to 6.0
min.
max.
26
Current drain during IDDOP(1)
basic operation
•FmCF=12MHz for
Ceramic resonator
oscillation
13
(Note 4)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
•FmCF=3MHz for
Ceramic resonator
oscillation
IDDOP(2)
4.5 to 6.0
6.5
14
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
•FmCF=0Hz
IDDOP(3)
IDDOP(4)
4.5 to 6.0
4
10
(when oscillator
stops)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
RC oscillator
•FmCF=0Hz
4.5 to 6.0
3.5
9
(when oscillator
stops)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
crystal oscillator
•Internal RC
oscillator stopped
Continue.
No.4212-16/22
LC86P6032
Ratings
typ.
Parameter
Symbol
Pins
Conditions
•HALT mode
unit
mA
VDD[V]
4.5 to 6.0
min.
max.
10
Current drain at
HALT mode
IDDHALT(1) VDD
5
•FmCF=12MHz for
Ceramic resonator
oscillation
(Note 4)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
•HALT mode
IDDHALT(2)
4.5 to 6.0
1.8
4.6
•FmCF=3MHz for
Ceramic resonator
oscillation
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
CF oscillator
•Internal RC
oscillator stopped
•HALT mode
IDDHALT(3)
4.5 to 6.0
400
800
µA
•FmCF=0Hz
(when oscillator
stops)
•FsXtal=32.768kHz
crystal oscillator
•System clock :
RC oscillator
IDDHALT(4)
•HALT mode
4.5 to 6.0
20
60
•FmCF=0Hz
(when oscillator
stops)
•FsXtal=32.768kHz for
crystal oscillator
•System clock :
crystal oscillator
•Internal RC
oscillator stopped
HOLD mode
Current drain at
HOLD mode
IDDHOLD(1) VDD
IDDHOLD(2)
4.5 to 6.0
2.5 to 4.5
0.05
0.02
30
20
(Note 4)
(Note 4) The currents of output transistors and pull-up MOS transistors are ignored.
No.4212-17/22
LC86P6032
Table 1. Ceramic resonator oscillation circuit recommended constants (main-clock)
Oscillation type
Supplier
Murata
Oscillator
CSA12.0MTZ
CSA12.0MT
CST12.0MTW
KBR-12.0M
CSA3.00MG
CST3.00MGW
KBR-3.0MS
C1
C2
12MHz ceramic resonator
oscillation
33pF
33pF
33pF
33pF
on chip
on chip
Kyocera
Murata
33pF
33pF
33pF
33pF
3MHz ceramic resonator
oscillation
Kyocera
47pF
47pF
* For both C1 and C2, the K rank (±10%) and SL characteristics must be used.
Table 2. Crystal oscillation circuit recommended constants (sub-clock)
Oscillation type
Supplier
Daishinku
Kyocera
Oscillator
C3
C4
32.768kHz crystal
oscillation
DT-38(1TA252E00)
KF-38G-13P0200
18pF
18pF
18pF
18pF
(Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
•If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
X’tal
CF
C1
C2
C3
C4
Figure 1 Ceramic resonator oscillation
Figure 2 Crystal oscillation
No.4212-18/22
LC86P6032
VDD
VDD limit
0V
Power supply
RES
Reset time
Internal RC
resontor
oscillation
tmsCF
tssXtal
CF1, CF2
XT1, XT2
Unfixed
Reset
Instruction execution mode
Operation mode
< Reset time and oscillation stable time. >
HOLD release signal
Valid
Internal RC
resontor
oscillation
tmsCF
tssXtal
CF1, CF2
XT1, XT2
Operation mode HOLD
Instruction execution mode
< Hold release signal and oscillation stable time. >
Figure 3 Oscillation stable time
VDD
RRES
(Note) The values of CRES and RRES should
be determined such that reset time is at
least 200µs, measured from the
moment the power exceeds the VDD
lower limit.
RES
CRES
Figure 4 Reset circuit
No.4212-19/22
LC86P6032
0.5VDD
<AC timing point>
tCKCY
VDD
tCKL
tCKH
SCK0
SCK1
1K
Ω
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
<Test load>
Figure 5 Serial input/output test conditions
tPIL
tPIH
Figure 6 Pulse input timing conditions
No.4212-20/22
LC86P6032
Notice for use
• The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO
to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown
in the following figure should always be followed.
• It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed.
• Should be stored in dry conditions (QFP type only)
The environment must be held at a temperature of 30°C or less and a humidity level of 70% or less.
• After opening the packing (QFP type only)
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the
substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment must be
held at a temperature of 30°C or less and a humidity level of 70% or less. Please solder within 8 hours.
a. Shipping with a blank PROM (Data to be programmed by customer)
This microcomputer is provided DIP/QFP packages, but the condition before mounting is not same.
Refer to the mounting precedure as follows;
DIP
QFP
Programming and verifying
Programming and verifying
Recommended process of screening
Recommended process of screening
Heat-soak
+1
Heat-soak
+1
150±5 C, 24
Hr
150±5 C, 24
Hr
°
°
-0
-0
Program reading test
Program reading test
Baking before mounting
125 C, 24 hours
°
Baking
Mounting
Mounting
No.4212-21/22
LC86P6032
b. Shipping with programmed PROM (Data programmed by Sanyo)
DIP
QFP
Baking before mounting
125 C, 24 hours
°
Baking
Mounting
Mounting
No.4212-22/22
PS
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