LC866416B [SANYO]
8-Bit Single Chip Microcontroller; 8位单片机
| 型号： | LC866416B |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-Bit Single Chip Microcontroller |
| 文件： | 总21页 (文件大小：662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6699
CMOS IC
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B microcontrollers are 8-bit single chip microcontrollers
with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond)
- On-chip ROM Maximum Capacity : 48K bytes
- On-chip RAM Capacity : 1152/768/640/512 bytes
(LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B)
- 16-bit timer /counter (or two 8-bit timers)
- 16-bit timer /PWM (or two 8-bit timers)
- 8-channel × 8-bit AD converter
- Two 8-bit synchronous serial-interface circuits (1-channel × 16bit, 1-channel × 8bit)
- 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Ver.1.05
O0499
91400 RM (IM) SK No.6699-1/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Features
(1) Read-Only Memory (ROM)
: LC866448B
: LC866444B
: LC866440B
: LC866436B
: LC866432B
: LC866428B
: LC866424B
: LC866420B
: LC866416B
: LC866412B
: LC866408B
49152 × 8 bits
45056 × 8 bits
40960 × 8 bits
36864 × 8 bits
32768 × 8 bits
28672 × 8 bits
24576 × 8 bits
20480 × 8 bits
16384 × 8 bits
12288 × 8 bits
8192 × 8 bits
1152 × 8 bits
768 × 8 bits
(2) Random Access Memory (RAM) : LC866448B/44B/40B/36B
: LC866432B/28B/24B
: LC866420B/16B
640 × 8 bits
: LC866412B/08B
512 × 8 bits
(3) Bus Cycle Time/Instruction Cycle Time
The LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B are constructed to read ROM twice within one
instruction cycle. It has 1.7 times more performance capability within the same instruction cycle compared to our 4-bit
microcomputers (LC66000 series).
Bus cycle time indicates the speed to read ROM.
Bus cycle time
0.5µs
Cycle time Clock divider
System clock oscillation
Ceramic resonator oscillation
Ceramic resonator oscillation
RC resonator oscillation
Crystal oscillation
Oscillation Frequency Voltage
1µs
4µs
1/1
1/1
1/1
1/2
6MHz
3MHz
4.5V to 6.0V
2.5V to 6.0V
2.5V to 6.0V
2.5V to 6.0V
2µs
7.5µs
15µs
366µs
800kHz
32.768kHz
183µs
(4) Ports
- Input/output ports
: 1 port (8 terminals : port 1)
Input/output programmable in a bit
- 15V withstand Input/Output ports
: 2 ports (12 terminals)
Input/output port programmable in nibble unit
: 1 port (8 terminals : port 0)
(When the N-channel open drain output is selected, the data in a bit can be inputted.)
Input/output port programmable in a bit
- Input port
- VFD output port
: 1 port (4 terminals : port 3)
: 2 ports (14 terminals : port 7,8)
: 38 terminals
Large current output for digit
Pull-down resistor option available
- Other function
: 16 terminals
Input/output port
: 1 port (6 terminals : port E)
Input port
: 2 ports (16 terminals : port C,D)
(5) VFD automatic dislay controller
-Segment/digit output pattern programmable
Any segment/digit combination available
VFD parallel-drive available
- 16-step dimmer function available
(6) AD converter
- 8-channel × 8-bit AD converter
(7) Serial-interface
- 1 channel × 16-bit serial-interface circuits
- 1 channel × 8-bit serial-interface circuits
- LSB first / MSB first function available
- Internal 8-bit baud-rate generator in common with two serial-interface circuits
No.6699-2/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
(8) Timer
- Timer 0
16-bit timer/counter
2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with programmable prescaler
Mode 1 : 8-bit timer with programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with programmable prescaler
Mode 3 : 16-bit counter
The resolution of Timer is tCYC. (tCYC: cycle time)
- Timer 1
16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1,the resolution of Timer and PWM is tCYC.
In Mode 2 and Mode 3,the resolution of Timer and PWM selectable: tCYC or 1/2 tCYC by program
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock)
Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer clock)
The Base timer clock selectable; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable; 4KHz, 2KHz (using 32.768kHz crystal oscillation for Base
timer clock)
(10) Remote-control receiver circuit (Shares with the P73/INT3/T0IN terminal)
- Noise Rejection function (the time constant of noize rejection filter: 1tCYC/16tCYC/64tCYC)
(tCYC: instruction cycle time)
- Switch Polarity function
(11) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable: interrupt system, system reset
(12) Interrupt system
- 14-source 10-vectored interrupts :
1. External interrupt INT0 (include watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, Timer/counter T0L (Lower 8-bit)
4. External interrupt INT3, Base timer
5. Timer/counter T0H (Upper 8-bit)
6. Timer T1L, Timer T1H
7. Serial-interface SIO0
8. Serial-interface SIO1
9. AD converter
10. VFD automatic display controller, Port 0
- Built-in Interrupt Priority control register
Microcontroller allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0
(i.e. the above interrupt number from three through ten). It can also specify a low level or the highest level interrupt
priority to INT0 and INT1.
No.6699-3/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
(13) Real-time service operation
The Real-Time Service (RTS) functions the 4-byte data-transfer between the Special Function Registers at
acknowledging the interrupt request.
The RTS starts within 1 instruction cycle-time and completes within 5 instructions cycle-time after occurring the
interrupt request.
(14) Subroutine stack levels
- 128 levels (Max.): Stack area included in RAM area
(15) Multiplication and division
16-bit × 8-bit (7 instruction cycle times)
16-bit / 8-bit (7 instruction cycle times)
(16) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock.
- On-chip CF oscillation circuit using for the system clock.
- On-chip crystal oscillation circuit using for the system clock and for time-base clock.
(17) Standby function
- HALT mode function
The HALT mode is used to reduce power dissipation. In this operation mode, program execution is stopped. This
operation mode can be released by interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to freeze all the oscillations;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations.
• Reset terminal ( RES ) set to Low level
• P70/INT0/T0IN, P71/INT1/T0IN terminals set to assigned level (programmable)
• Input a Port 0 interrupt condition
(18) Factory shipment
• QFP80E delivery form
(19) Development support tools
Evaluation (EVA) chip
EPROM version
One time version
Emulator
: LC866097
: LC86E6449
: LC86P6449
: EVA-86000 + ECB866400 (Evaluation chip board) + POD866400 (POD)
Notice for use
1. Set VDD=4.0V to 6.0V at using S16 to S37 as input port.
2. Follow the under table.
Frequency range of the system clock
15kHz to 30kHz
Voltage range Clock Divider
Note
4.5V to 6.0V
1/1
1/1,1/2
1/1
Can not use 1/2 divider
30kHz to 6MHz
15kHz to 30kHz
2.5V to 6.0V
Can not use 1/2 divider
Can not use 1/1 divider
Can not use 1/1 divider
30kHz to 1.5MHz
1/1,1/2
1/2
1.5MHz to 3MHz
Internal RC oscillation
4.5V to 6.0V
2.5V to 6.0V
1/1,1/2
1/2
No.6699-4/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Pin Assignment
QIP80E
P00
P01
P02
P03
P04
P05
P06
P07
VSS2
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/BUZ
S4/T4
S3/T3
S2/T2
S1/T1
S0/T0
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
No.6699-5/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
System Block Diagram
Interrupt Control
Standby Control
IR
PLA
ROM
CF
RC
PC
X’tal
Base Timer
SIO0
Bus Interface
Port 1
ACC
B Register
C Register
SIO1
Port 3
Timer 0
Timer 1
ADC
Port 7
ALU
Port 8
PSW
RAR
RAM
INT0 to 3
Noise Filtter
Real Time Service
RAM
Stack Pointer
Port 0
(128 bytes)
VFD Controller
High voltage Output
Watchdog Timer
No.6699-6/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Pin description
Pin name I/O
Function description
Power pin (-) Short-circuit VSS1 to VSS2.
Option
VSS1,2
VDD1,2
VP
-
-
-
-
Power pin (+) *1
Refer to Notes
-
Power pin (+) for the VFD output pull-down resistor
-
PORT0
P00 to P07
I/O •8-bit input/output port
•Input for port 0 interrupt
•Pull-up resistor :
Provided/Not provided (each nibble)
•Output form :
•Input/output in nibble units
•Input for HOLD release
CMOS/N-channel open drain (each bit)
•15V withstand at N-channel open drain output
I/O •8-bit input/output port
•Input/output can be specified in a bit unit
•Other pin functions
PORT1
Output form :
P10 to P17
CMOS/N-channel open drain (each bit)
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
I/O •4-bit input/output port
•Input/output in bit unit
PORT3
Output form :
P30 to P33
CMOS/N-channel open drain (each bit)
•15V withstand at N-channel open drain output
•6-bit input port
PORT7
Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
•Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P74 , P75 don’t have the pull-up
*
resistor option.
P70
I/O
I
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P71 to P75
P73 : INT3 input with noise filter/timer 0 event input
P74 : 32.768kHz crystal oscillation terminal XT1
P75 : 32.768kHz crystal oscillation terminal XT2
•Interrupt received forms, the vector addresses
rising falling rising
high
level
low vector
level
&
falling
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
Continue.
No.6699-7/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Pin name I/O
Function description
Option
PORT8
I
•8-bit input port
•Other function
-
P80 to 87
AD input port (8 Port pins)
Output for VFD display controller
segment/timing in common
S0/T0 to
S6/T6
O
O
Pull-down resistor :
Provided/Not provided (each nibble)
S7/T7 to
S15/T15
•Output for VFD display controller
segment/timing with internal pull-down resistor in
common
•Internal pull-down resistor output
S16 to S31 I/O •Output for VFD display controller segment
•Other function
Pull-down resistor :
Provided/Not provided (each nibble)
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
S32 to S37 I/O •Output for VFD display controller Segment
•Other function
Pull-down resistor :
Provided/Not provided (each nibble)
S32 : High voltage I/O port PE0
S33 : High voltage I/O port PE1
S34 : High voltage I/O port PE2
S35 : High voltage I/O port PE3
S36 : High voltage I/O port PE4
S37 : High voltage I/O port PE5
RES
I
I
Reset pin
-
-
XT1/ P74
•Input pin for 32.768kHz crystal oscillation
•Other function
P74 for input port
•In case of non use, connect to VDD1.
•Output pin for 32.768kHz crystal oscillation
•Other function
XT2/P75
O
-
P75 for input port
•In case of non use,
At using as oscillator, should be left opened.
At using as a port, connect to VDD1.
Input pin for the ceramic resonator oscillation
Output pin for the ceramic resonator oscillation
CF1
CF2
I
-
-
O
* All of port options (except pull-up resistor of port 0) can be specified in bit unit.
No.6699-8/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
*A state of pins at reset
Pin name
Input/output mode A state of pull-up resistor specified at pull-up option
Port 0
Input
Input
Input
Fixed pull-up resistor OFF
Ports 1,3
Programmable pull-up resistor OFF
Fixed pull-up resistor OFF
Ports 70,71,72,73
P channel Transistor OFF
P channel Transistor OFF
S0/T0 to S15/T15
S16 to S37
[Notes]
When connecting to the power supply, the power pins must be connected like following figure.
In case for the LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
LSI
VDD1
Power
Supply
For back-up
VDD2
(VFD power
pin)
VSS1 VSS2
In case for the LC866432A/28A/24A/20A/16A/12A/08A
LSI
VDD1
Power
Supply
For back-up
VDD2
(VFD power
pin)
VSS1 VSS2
*1 Each of the power pins, VDD1 and VDD2, should be connected the capacitors for reducing the noise into the VDD1 pin.
No.6699-9/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C
Ratings
typ.
Parameter
Symbol
Pins
Conditions
unit
V
VDD[V]
min.
-0.3
-0.3
max.
+7.0
Supply voltage
Input voltage
VDDMAX VDD1,VDD2
VDD1=VDD2
VI(1)
•Ports 71,72,73
VDD+0.3
74
•Ports
•Port 8
• RES
VP
,75
VI(2)
VO
VDD-45
VDD-45
-0.3
VDD+0.3
VDD+0.3
VDD+0.3
Output voltage
Input/Output
voltage
S0/T0 to S15/T15
•Port 1
VIO(1)
•Port 70
•Ports 0, 3 at CMOS
output option
VIO(2)
VIO(3)
Ports 0, 3 at N-ch open
drain output option
S16 to S37
-0.3
15
VDD-45
-10
VDD+0.3
High
level
Peak
IOPH(1) Ports 0, 1, 3
•CMOS output
•At each pins
mA
output
output current
current
IOPH(2) S0/T0 to S15/T15
IOPH(3) S16 to S37
ΣIOAH(1) Ports 0, 1, 3
ΣIOAH(2) S0/T0 to S15/T15
ΣIOAH(3) S16 to S37
IOPL(1) Ports 0, 1, 3
IOPL(2) Port 70
At each pins
-30
-15
At each pins
Total
The total of all pins
The total of all pins
The total of all pins
At each pins
-30
output
current
-55
-115
Low
level
Peak
20
15
output
At each pins
output current
current
Total
ΣIOAL(1) Port 0
The total of all pins
The total of all pins
40
40
output
current
ΣIOAL(2) Ports 1,3
Maximum
power
Pdmax
Topr
QFP80E
Ta=-30 to+70°C
480
70
mW
dissipation
Operating
temperature
range
-30
-55
°C
Storage
Tstg
125
temperature
range
No.6699-10/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Symbol
VDD(1)
Pins
Conditions
unit
V
VDD[V]
min.
4.5
max.
6.0
Operating
Supply
VDD1=VDD2
0.98µs ≤ tCYC
tCYC ≤ 400µs
3.9µs ≤ tCYC
tCYC ≤ 400µs
RAMs and the
registers hold
voltage at HOLD
mode.
voltage
VDD(2)
VHD
2.5
2.0
6.0
6.0
Hold voltage
VDD1=VDD2
Pull-down
voltage
VP
VP
2.5 to 6.0
-35
VDD
VDD
Input high
voltage
VIH(1)
VIH(2)
VIH(3)
Port 0 at CMOS output
Output disable
2.5 to 6.0 0.33VDD
+1.0
Port 0 at N-ch open drain Output disable
output
4.0 to 6.0 0.8VDD
2.5 to 4.0 0.75VDD
2.5 to 6.0 0.75VDD
13.5
13.5
•Port 1
Output disable
VDD
•Ports 72,73
•Port 3 at CMOS
output option
Port 3 at N-ch open
drain output option
VIH(4)
VIH(5)
Output disable
Tr. OFF
4.5 to 6.0 0.8VDD
2.5 to 4.0 0.75VDD
13.5
13.5
•Port 70
Output N-channel 2.5 to 6.0 0.75VDD
Tr. OFF
VDD
Port input/interrupt
•Port 71
• RES
VIH(6)
VIH(7)
VIH(8)
VIL(1)
VIL(2)
VIL(3)
VIL(4)
Port 70
Output N-channel 2.5 to 6.0 0.9VDD
Tr. OFF
VDD
VDD
Watchdog timer
•Port 8
Using as port
2.5 to 6.0 0.75VDD
•Ports 74 ,75
S16 to S37
Output P-channel 4.0 to 6.0 0.33VDD
VDD
Tr. OFF
+1.0
Input low
voltage
Port 0 at CMOS
output option
Port 0 at N-ch open
drain output
•Ports 1,3
Output disable
2.5 to 6.0 VSS
0.2VDD
0.25VDD
0.25VDD
0.25VDD
Output disable
Output disable
2.5 to 6.0 VSS
2.5 to 6.0 VSS
•Ports 72,73
•Port 70
Output N-channel 2.5 to 6.0 VSS
Tr. OFF
Port input/interrupt
•Port 71
• RES
VIL(5)
VIL(6)
VIL(7)
tCYC
Port 70
Output N-channel 2.5 to 6.0 VSS
Tr. OFF
0.8VDD
-1.0
Watchdog timer
•Port 8
Using as port
2.5 to 6.0 VSS
0.25VDD
•Ports 74 ,75
S16 to S37
Output P-channel 4.0 to 6.0
Tr. OFF
VP
0.2VDD
Operation
cycle time
4.5 to 6.0
0.98
3.9
400
400
µs
2.5 to 6.0
Continue.
No.6699-11/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Ratings
typ.
Parameter
Symbol
Pins
Conditions
•6MHz
unit
VDD[V]
min.
max.
Oscillation
frequency
range
FmCF(1)
CF1, CF2
CF1, CF2
4.5 to 6.0 To be
deter-min
ed
6
To be MHz
deter-min
ed
(ceramic resonator
oscillation)
(Note 1)
•Refer to figure 1
•3MHz
FmCF(2)
2.5 to 6.0 To be
deter-min
ed
3
To be
deter-min
ed
(ceramic resonator
oscillation)
•Refer to figure 1
RC oscillation
•32.768kHz
FmRC
FsXtal
2.5 to 6.0
2.5 to 6.0
0.3
0.8
3.0
XT1, XT2
CF1, CF2
32.768
kHz
(crystal oscillation)
•Refer to figure 2
•6MHz
Oscillation
stabilizing
time period
tmsCF(1)
tmsCF(2)
tssXtal
4.5 to 6.0
0..1
3.0
ms
(ceramic resonator
oscillation)
(Note 1)
•Refer to figure 3
•3MHz
CF1, CF2
XT1, XT2
4.5 to 6.0
2.5 to 6.0
0.1
0.1
3.0
3.0
(ceramic resonator
oscillation)
•Refer to figure 3
•32.768kHz
4.5 to 6.0
2.5 to 6.0
0.7
1.4
0.8
2.2
s
(crystal oscillation)
•Refer to figure 3
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6699-12/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Ratings
typ. max.
Parameter Symbol
Pins
Conditions
•Output disable
unit
VDD[V]
2.5 to 6.0
min.
Input high
current
IIH(1) Ports 0,3 at open
drain output
5
µA
•VIN=13.5V
(including off-leakage
current of the output Tr.)
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VDD
(including off-leakage
current of the output Tr.)
VIN=VDD
IIH(2) •Port 0 without
pull-up MOS Tr.
•Ports 1,3
2.5 to 6.0
2.5 to 6.0
1
IIH(3) •Ports 70,71,72,73
without pull-up
MOS Tr.
1
•Port 8
IIH(4)
RES
VIN=VDD
2.5 to 6.0
2.5 to 6.0
1
1
IIH(5) Ports 74 ,75
•Using as port
•VIN=VDD
•Output disable
•VIN=VDD
IIH(6) S16 to S37 without
pull-down resistor
(Ports C,D,E)
2.5 to 6.0
2.5 to 6.0
1
Input low
current
IIL(1) •Ports 1,3
•Port 0 without
•Output disable
•Pull-up MOS Tr. OFF.
•VIN=VSS
(including off-leakage
current of the output Tr.)
VIN=VSS
-1
-1
pull-up MOS Tr.
IIL(2) •Ports 70,71,72,73
without pull-up
MOS Tr.
2.5 to 6.0
•Port 8
IIL(3)
RES
VIN=VSS
2.5 to 6.0
2.5 to 6.0
-1
-1
IIL(4) Ports 74 ,75
•VIN=VSS
•Using as port
IOH=-1.0mA
Output high VOH(1) Ports 0,1,3 of
4.5 to 6.0 VDD-1
2.5 to 6.0 VDD-0.5
4.5 to 6.0 VDD-1.8
2.5 to 6.0 VDD-1
V
voltage
CMOS output
VOH(2)
IOH=-0.1mA
VOH(3) S0/T0 to S15/T15
VOH(4)
IOH=-20mA
•IOH=-1mA
•The current of any
unmeasurement pin is not
over 1mA.
VOH(5) S16 to S37
VOH(6)
IOH=-5mA
4.5 to 6.0 VDD-1.8
2.5 to 6.0 VDD-1
The current of any
unmeasurement pin is not
over 1mA.
Output low
voltage
VOL(1) Ports 0,1,3
VOL(2)
IOL=10mA
4.5 to 6.0
4.5 to 6.0
2.5 to 6.0
1.5
0.4
0.4
IOL=1.6mA
VOL(3)
•IOL=1.0mA
•The current of any
unmeasurement pin is not
over 1mA.
VOL(4) Port 70
VOL(5)
IOL=1mA
4.5 to 6.0
2.5 to 6.0
0.4
0.4
IOL=0.5mA
Pull-up MOS Rpu
Tr. resistor
•Ports 0,1,3
•Ports 70,71,72,73
VOH=0.9VDD
4.5 to 6.0
2.5 to 4.5
15
25
40
70
70
kΩ
150
Continue.
No.6699-13/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Ratings
typ. max.
Parameter Symbol
Pins
Conditions
unit
VDD[V]
2.5 to 6.0
min.
-1
Output off-
leak current
IOFF(1) S0/T0 to S6/T6,
•Output P-channel Tr. OFF
µA
S16 to S37 without •VOUT=VSS
pull-down resistor
IOFF(2)
•Output P-channel Tr. OFF
•VOUT=VDD-40V
2.5 to 6.0
4.0 to 6.0
-30
Resistance of Rinpd
the low level
hold Tr.
S16 to S37
•Output P-channel Tr. OFF
•Using as input ports
200
100
kΩ
High voltage Rpd
pull-down
S0/T0 to S15/T15,
•Output P-channel Tr. OFF
5.0
60
200
S16 to S37 without •VOUT=3V
resistor
pull-down resistor
•Port 1
•Vp=-30V
0.1VDD
10
Hysteresis
voltage
VHIS
CP
Output disable
2.5 to 6.0
2.5 to 6.0
V
•Ports 70,71,72,73
• RES
Pin
All pins
•f=1MHz
pF
capacitance
•VIN=VSS for all
unmeasured terminals.
•Ta=25°C
4. Serial input/output characteristics / Ta=-30°C to +70°C, VSS1=VSS2=0V
Ratings
Parameter
Symbol
Pins
Conditions
unit
VDD[V] min.
typ.
max.
Cycle
tCKCY(1)
tCKL(1)
SCK0,SCK1 Refer to figure 5
2.5 to 6.0
2
1
tCYC
Low Level
pulse width
High Level
pulse width
Cycle
tCKH(1)
1
2
tCKCY(2)
tCKL(2)
SCK0,SCK1 •Use pull-up
resistor (1kΩ) in
the open drain
2.5 to 6.0
Low Level
pulse width
High Level
pulse width
1/2tCKCY
1/2tCKCY
output.
tCKH(2)
tICK
•Refer to figure 5
•SI0,SI1
•Data set-up to
SCK0,1
4.5 to 6.0 0.1
µs
Data set-up time
•SB0,SB1
2.5 to 6.0 0.4
4.5 to 6.0 0.1
2.5 to 6.0 0.4
•Data hold from
SCK0,1
Data hold time
tCKI
•Refer to figure 5
•Use pull-up
resistor (1kΩ) in
the open drain
output.
Output delay time tCKO(1)
(External clock
•SO0,SO1
•SB0,SB1
4.5 to 6.0
2.5 to 6.0
4.5 to 6.0
2.5 to 6.0
7/12
tCYC
+0.2
7/12
tCYC
+1
using for serial
transfer clock)
•Data hold from
SCK0,1
•Refer to figure 5
Output delay time tCKO(2)
(Internal clock
1/3
tCYC
+0.2
1/3
using for serial
transfer clock)
tCYC
+1
No.6699-14/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V
Ratings
Parameter
Symbol
Pins
Conditions
unit
VDD[V] min. typ. max.
High/low level tPIH(1) •INT0, INT1
•Interrupt acceptable
•Timer0-countable
•Interrupt acceptable
2.5 to 6.0
1
tCYC
pulse width
tPIL(1) •INT2/T0IN
tPIH(2) INT3/T0IN
2.5 to 6.0
2
tPIL(2) (The noise rejection clock •Timer0-countable
selected to 1/1.)
tPIH(3) INT3/T0IN
•Interrupt acceptable
2.5 to 6.0
32
tPIL(3) (The noise rejection clock •Timer0-countable
selected to 1/16.)
tPIH(4) INT3/T0IN
•Interrupt acceptable
2.5 to 6.0 128
2.5 to 6.0 200
tPIL(4) (The noise rejection clock •Timer0-countable
selected to 1/64.)
tPIL(5) RES
Reset acceptable
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Resolution
Symbol
Pins
Conditions
unit
VDD[V]
4.5 to 6.0
4.5 to 6.0
min.
max.
±1.5
N
8
bit
Absolute precision
(Note 2)
ET
LSB
Conversion time
tCAD
AD conversion time = 4.5 to 6.0 15.68
65.28
(tCYC=
4.08µs)
µs
16 × tCYC
(tCYC=
(ADCR2=0)
(Note 3)
0.98µs)
AD conversion time =
32 × tCYC
(ADCR2=1)
(Note 3)
31.36
(tCYC=
0.98µs)
130.56
(tCYC=
4.08µs)
Analog input
voltage range
Analog port
input current
VAIN AN0 to AN7
4.5 to 6.0 VSS
VDD
1
V
IAINH
IAINL
VAIN=VDD
VAIN=VSS
4.5 to 6.0
4.5 to 6.0
µA
-1
(Note 2) Absolute precision excepts the quantizing error (±1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
No.6699-15/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V
Ratings
Parameter
Symbol
Pins
Conditions
unit
mA
VDD[V]
4.5 to 6.0
min.
typ.
10
max.
25
Current dissipation
during basic
operation
IDDOP(1)
•FmCF=6MHz
Ceramic resonator
oscillation
(Note 4)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
IDDOP(2)
IDDOP(3)
•FmCF=3MHz
Ceramic resonator
oscillation
4.5 to 6.0
2.5 to 4.5
3
9
5
1.5
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
IDDOP(4)
IDDOP(5)
•FmCF=0Hz
4.5 to 6.0
2.5 to 4.5
0.7
0.4
3.4
2.8
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
IDDOP(6)
IDDOP(7)
•FmCF=0Hz
4.5 to 6.0
2.5 to 4.5
35
15
130
70
µA
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
32.768kHz
•Internal RC
oscillation stops
•1/2 divided
Continue.
No.6699-16/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Ratings
Parameter
Symbol
Pins
Conditions
•HALT mode
unit
mA
VDD[V]
4.5 to 6.0
min.
typ.
5
max.
14
Current dissipation
in HALT mode
(Note 4)
IDDHALT(1)
•FmCF=6MHz
Ceramic resonator
oscillation
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/1 divided
IDDHALT(2)
IDDHALT(3)
•HALT mode
•FmCF=3MHz
Ceramic resonator
oscillation
4.5 to 6.0
2.5 to 4.5
2.2
0.8
7
4
•FsXtal=32.768kHz
crystal oscillation
•System clock :
CF oscillation
•Internal RC
oscillation stops
•1/2 divided
IDDHALT(4)
IDDHALT(5)
•HALT mode
FmCF=0Hz
4.5 to 6.0
2.5 to 4.5
400
200
1600
1300
µA
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•1/2 divided
IDDHALT(6)
IDDHALT(7)
•HALT mode
FmCF=0Hz
4.5 to 6.0
2.5 to 4.5
25
8
100
55
(The oscillation
stops)
•FsXtal=32.768kHz
crystal oscillation
•System clock :
crystal oscillation
•Internal RC
oscillation stops
•1/2 divided
Current dissipation
in HOLD mode
(Note 4)
IDDHOLD(1)
IDDHOLD(2)
HOLD mode
4.5 to 6.0
2.5 to 4.5
0.05
0.02
30
20
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6699-17/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
Table 1. Ceramic resonator oscillation recommended constant (main-clock)
Oscillation type
Maker
Oscillator
CSA6.00MG
C1
C2
6MHz ceramic resonator oscillation
Murata
33pF
33pF
CST6.00MGW
KBR-6.0MSB
on chip
Kyocera
33pF
33pF
33pF
33pF
PBRC6.00A(chip type)
KBR-6.0MKC
PBRC6.00B(chip type)
CSA3.00MG
on chip
3MHz ceramic resonator oscillation
Murata
33pF
33pF
47pF
CST3.00MGW
KBR-3.0MS
on chip
Kyocera
47pF
* Both C1 and C2 must be use K rank (±10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub-clock)
Oscillation type
Maker
Oscillator
C-002RX
C3
18pF
C4
Rd
32.768kHz crystal oscillation
EPSON
18pF 680kΩ
* Both C3 and C4 must be use J rank (±5%) and CH characteristics.
(Not in need of high precision, use K rank (±10%) and SL characteristics.)
(Notes) • Please place the oscillation-related parts as close to the oscillation pins as possible with the shortest
possible pattern length since the circuit pattern affects the oscillation frequency.
• If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
Rd
CF
C1
C2
C3
C4
X’tal
Figure 1 Main-clock circuit
Ceramic resonator oscillation
Figure 2 Sub-clock circuit
Crystal oscillation
No.6699-18/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
VDD
VDD limit
OV
Power supply
RES
Reset time
Interrnal RC
resonator
oscillation
tmsCF
CF1, CF2
tssXtal
XT1, XT2
Instruction
Operation mode
execution mode
Unfixed
Reset
Instruction execution mode
OCR6=1
< Reset time and oscillation stabilizing time. >
HOLD release signal
Valid
Interrnal RC
resonator
oscillation
tmsCF
tssXtal
CF1, CF2
XT1, XT2
HOLD
Instruction execution mode
Operation mode
< HOLD release signal and oscillation stabilizing time. >
Figure 3 Oscillation stable time
No.6699-19/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
VDD
RES
R
(Note) Fix the value of CRES, RRES that is
sure to reset until 200µs, after Power
supply has been over inferior limit of
supply voltage.
RES
RES
C
Figure 4 Reset circuit
0.5VDD
<AC timing point>
tCKCY
VDD
tCKL
tCKH
SCK0
SCK1
1KΩ
tICK
tCKI
SI0
SI1
tCKO
50pF
SO0, SO1
SB0, SB1
<Timing>
<Test load>
Figure 5 Serial input / output test condition
tPIL
tPIH
Figure 6 Pulse input timing condition
No.6699-20/21
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
memo:
No.6699-21/21
PS
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