概述
规格参数
数据手册LC89201 概述
9600-bps Facsimile Modem 9600 bps的传真调制解调器 调制解调器
LC89201 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | QFP | 包装说明： | QFP, QFP80,.55X.8,32 |
| 针数： | 80 | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.92 |
| Is Samacsys： | N | 其他特性： | HALF DUPLEX |
| 传真率： | 9.6 kbps | JESD-30 代码： | R-PQFP-G80 |
| JESD-609代码： | e0 | 长度： | 20 mm |
| 功能数量： | 1 | 端子数量： | 80 |
| 最高工作温度： | 70 °C | 最低工作温度： | -30 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | QFP |
| 封装等效代码： | QFP80,.55X.8,32 | 封装形状： | RECTANGULAR |
| 封装形式： | FLATPACK | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 2.8 mm | 子类别： | Modems |
| 标称供电电压： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 电信集成电路类型： | MODEM-FAX |
| 温度等级： | OTHER | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 0.8 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 14 mm | Base Number Matches： | 1 |
LC89201 数据手册
通过下载LC89201数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Ordering number : EN*4974
CMOS LSI
LC89201
9600-bps Facsimile Modem
Preliminary
Overview
The LC89201 is a CMOS single-chip, synchronous, half-
duplex, 9600-bps fax modem designed for use with public
telephone networks. Built in are such essential features for
Group III facsimile systems as modulator, demodulator,
transmission filters, and V.24 interface.
The LSI supports the V.29, V.27ter, V.21ch2, T.30, and
T.4 telecommunications standards promulgated by the
ITU-T (formerly the CCITT) for transmission at 9600,
7200, 4800, 2400 and 300 bps. Advanced signal
processing provides reliable data transmissions even under
adverse circuit conditions. Built-in High-level Data Link
Control (HDLC) support permits the construction of Error
Correction Mode (ECM) facsimile machines.
• Built-in eye pattern generator.
• Adaptive differential pulse-code modulation (ADPCM).
• Caller ID detection.
• Built-in diagnostics.
• Energy-saving CMOS design (typ. 250 mW).
• Single 5 V power supply.
• 80-pin flat package (QIP-80E).
Package Dimensions
unit: mm
3174-QFP80E
[LC89201]
Features
• Support for the following ITU-T standards: V.29 (9600,
7200 and 4800 bps), V.27ter (4800 and 2400 bps),
V.21ch2 (300 bps), T.30, and T.4.
• Half-duplex operation.
• Group III facsimile support.
• Automatic switching between high- (V.29 and V.27ter)
and low-speed (V.21ch2) incoming facsimiles.
• Short training (for ITU-T V.27ter only).
• HDLC framing and deframing (V.29, V.27ter, and
V.21ch2).
SANYO: QIP80E
• Tone generation and detection.
• Dual-tone multifrequency (DTMF) generation and
detection.
• Call progress tone detection.
• Pseudo link back tone generation.
• Built-in automatic adaptive equalizer.
• Built-in fixed-amplitude amplifier.
— Link amplitude equalizer
— Cable amplitude equalizer
• Built-in transmission filters (digital filters).
• Programmable transmission level adjustment.
• Dynamic range for reception of 0 to –47 dBm.
• Programmable reception sensitivity adjustment.
• DTE interface.
— Serial interface (ITU-T V.24)
— Parallel interface (4 words × 8 bits, with built-in
FIFO)
• Programmable interrupt generator.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92995HA (OT) No. 4974-1/8
LC89201
System Block Diagram
No. 4974-2/8
LC89201
Internal Block Diagram
No. 4974-3/8
LC89201
Pin Assignment
Pin Functions
1. Power Supply, Clock and Test Pins
Pin No.
Symbol
I/O
Function
14
31
54
63
73
DV
DD
P
Digital power supply
8
13
24
35
53
64
74
DGND
P
Digital ground
38
51
AV
DD
P
P
Analog power supply
Analog ground
37
52
AGND
1
PV
DD
P
P
P
I
Frequency multiplier PLL power supply
Frequency multiplier PLL ground
Reference power supply. This must be half AV
System clock input (29.4912 MHz)
Oscillator amplifier output
7
PGND
50
9
V
.
DD
REF
X2
10
80
56
55
X1
O
O
I
CLKOUT
TESTMB
CKSB
Output clock, one-quarter the frequency of the internal master clock (9.216 MHz).
Test pin. Connect to DV
Test pin. Connect to DV
.
.
DD
I
DD
No. 4974-4/8
LC89201
2. DTE Interface Pins
Pin No.
Symbol
I/O
B
Function
29
28
27
26
25
23
22
21
D0
D1
D2
D3
D4
D5
D6
D7
Data bus to host CPU
20
19
18
17
16
A0
A1
A2
A3
A4
I
Address bus to host CPU
30
32
33
34
15
CSB
I
I
Chip select signal
READB
WRITEB
IREQB
Interface memory read signal
Interface memory write signal
Interrupt request to host CPU
System reset signal
I
O
I
RESETB
3. Eye Pattern Interface Pins
Pin No.
67
Symbol
EYECLK
EYESYNC
I/O
O
Function
Timing clock for generating eye pattern data. This may be used as the shift clock for an external shift register.
Eye pattern synchronization signal
68
O
66
65
EYEX
EYEY
O
Eye pattern data serial outputs (8 bits, MSB first)
4. V.24 (RS-232C) Interface Pins
Pin No.
57
Symbol
RTSB
I/O
I
Function
Request to send signal. The low level at this pin starts transmission; the high level suspends it.
Clear to send signal. The low level at this pin signals the availability of data for transmission; the high level indicates
that the data is invalid.
59
58
CTSB
O
O
Received line signal data signal. The low level at this pin gives the timing for transferring the data received to the
terminal.
RLSDB
61
60
62
TXD
RXD
I
Transmit data input
O
O
Receive data output
DCLK
Transmission data clock output
5. Analog Signal Pins
Pin No.
39
Symbol
TXA
I/O
O
I
Function
Transmitter analog output
44
RXA
Receiver analog input
43
AUXIN
OPA2P
OPA2M
OPA2O
OPA1P
OPA1M
OPA1O
PGCI
I
Auxiliary analog input
40
I
41
I
Transmission buffer input/output pins. (For details, see circuit diagram.)
Reception buffer input/output pins (For details, see circuit diagram.)
42
O
I
47
46
I
45
O
I
49
Reception gain adjustment circuit input. (For details, seecircuit diagram.)
Reception gain adjustment circuit output.
48
PGCO
O
No. 4974-5/8
LC89201
6. System signal pins
Pin No.
Symbol
MC
I/O
Function
11
78
77
6
I
I
Program mode control signal. Connect to DV
.
DD
HOLDB
HOLDAB
PRTSB
PO
System hold signal. Connect to DV
System hold confirmation signal.
.
DD
O
I
Frequency multiplier PLL reset input. (For details, see circuit diagram.)
Phase comparator output. (For details, see circuit diagram.)
Voltage-controlled oscillator input. (For details, seecircuit diagram.)
Voltage-controlled oscillator output
3
O
I
4
VCOI
5
VCOO
RIN
O
I
2
Voltage-controlled oscillator adjustment input. (For details, see circuit diagram.)
Oscillator amplifier STOP input
36
STOPB
I
Note: All other pins are to be left unconnected.
Specifications
Absolute Maximum Ratings at DGND, AGND, PGND = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
V
DV
max Ta = 25°C
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
DD
DD
DD
Maximum supply voltage
AV
PV
max Ta = 25°C
max Ta = 25°C
V
V
I/O voltages
V V
Ta = 25°C
–0.3 to V
DD
+ 0.3
400
V
I
O
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta ≤ 70°C
mW
°C
°C
°C
°C
–30 to +70
–55 to +125
350
Tstg
Hand soldering (3 seconds)
Reflow (10 seconds)
Soldering heat resistance
235
Allowable Operating Ranges at Ta = –30 to +70°C, DGND, AGND, PGND = 0 V
Parameter
Symbol
Conditions
min
4.5
4.5
4.5
0
typ
5.0
5.0
5.0
max
5.5
5.5
5.5
Unit
V
DV
DD
Supply voltage
AV
DD
V
PV
DD
V
Input voltage
V
V
V
IN
DD
No. 4974-6/8
LC89201
Electrical Characteristics at Ta = –30 to +70°C, DGND, AGND, PGND = 0 V, DV , AV , PV = 4.5 to 5.5 V
DD
DD
DD
Parameter
Input high level voltage
Input low level voltage
Symbol
Conditions
min
typ
max
Unit
V
TTL levels: RESETB, PRSTB, STOPB, A0 to A4,
D0 to D7, CSB, READB, WRITEB, RTSB, TXD,
HOLDB, MC, TESTMB, CKSB
V
2.2
IH
V
IL
0.8
V
V
= DGND, AGND, PGND, DV , AV , PV
:
DD
IN
DD
DD
RESETB, PRSTB, STOPB, A0 to A4, D0 to D7, CSB,
READB, WRITEB, RTSB, TXD, HOLDB, MC, TESTMB,
CKSB
Input leak current
I
–1
+1
µA
V
L
I
= –3 mA, TTL levels: WEB, MENB, CLKOUT,
OH
HOLDAB, PA0 to PA5, D0 to D7, IREQB, CTSB,
RLSDB, RXD, DCLK, VCOO, EYEX, EYEY, EYECLK,
EYESYNC
Output high level voltage
Output low level voltage
V
2.4
OH
I
= 3 mA, TTL levels: WEB, MENB, CLKOUT,
OL
HOLDAB, PA0 to PA5, D0 to D7, IREQB, CTSB,
RLSDB, RXD, DCLK, VCOO, EYEX, EYEY, EYECLK,
EYESYNC
V
0.4
V
OL
Output leak current
Oscillator frequency
I
For high-impedance output: D0 to D7
X2, X1
–10
+10
29.4912
/2
µA
MHz
V
OZ
f
OSC
V
V
input voltage
impedance
V
V
V
REF
REF
REF
REF
DD
R
V
1
*0.2
*0.2
MΩ
REF
REF
RIN, VCOI, OPA1M, OPA1P, RAX, OPA2M, OPA2P,
PGCI
V
V
V
V
*0.8
DD
V
Input voltage range
IA
DD
Output voltage range
Output impedance
V
TXA, PGCO, OPA1O, OPA2O
TXA, PGCO, OPA1O, OPA2O
V
*0.8
7
V
OA
DD
DD
R
O
kΩ
mA
mA
V
V
= 5.5 V
= 5.0 V
80
DD
Current drain
I
DD
50
DD
AC Characteristics
1. DTE interface timing
Read cycle timing
No. 4974-7/8
LC89201
Parameter
Symbol
TAR
Conditions
min
15
typ
max
30
Unit
ns
Address stabilization time
(relative to READB signal)
Chip select stabilization time
(relative to READB signal)
TCR
0
ns
Data propagation delay
TRD
TDF
ns
ns
Data float propagation delay
10
10
Address hold time
(relative to READB signal)
TRA
TAW
TCW
ns
ns
ns
Address stabilization time
(relative to WRITEB signal)
15
0
Chip select stabilization time
(relative to WRITEB signal)
Data setup time
Data hold time
TDW
TWD
20
5
ns
ns
Address hold time
(relative to WRITEB signal)
TWA
10
ns
2. Reset timing
Parameter
Symbol
T1
Conditions
min
500
typ
max
Unit
µs
PRTSB pulse width
PRTSB propagation delay
relative to RESETB
T2
T3
5
ms
ns
RESETB pulse width
500
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 1995. Specifications and information herein are subject to
change without notice.
PS No. 4974-8/8
Caption
P.2
P.7/8
A4 to A0
D7 to D0
A4 to A0
D7 to D0
1.
2.
Host CPU
29.4912-MHz
crystal oscillator
or
crystal resonator
3.
4.
Telephone line
Power
supply
5.
6.
Auxiliary analog input
Eye
pattern
generator
7.
8.
Oscilloscope
Power-on reset circuit
P.3
1.
2.
3.
4.
Interface memory
Timing generator
V.24 interface
Eye pattern
generator
5.
HDLC block
6.
Analog front end
New
P2/8
2.
29.4912-MHz
crystal oscillator
or
crystal resonator
8.
Power-on reset circuit
D0 to D7
A0 to A4
P3/8
D7 to D0
A4 to A0
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