LC895299W [SANYO]
48 x Speed ATAPI (IDE) CD-ROM Decoder with On-Chip Digital Servo System; 48倍速ATAPI （ IDE ） CD -ROM解码器，片上数字伺服系统
| 型号： | LC895299W |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 48 x Speed ATAPI (IDE) CD-ROM Decoder with On-Chip Digital Servo System |
| 文件： | 总12页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN6249A
CMOS IC
LC895299W, 895299L
48× Speed ATAPI (IDE) CD-ROM Decoder
with On-Chip Digital Servo System
• Bilingual support
• Built-in digital audio interface (supports both CLV and
CAV)
• Built-in digital deemphasis
• Built-in 8× oversampling digital filters
• Built-in D/A converters
Overview
The LC895299W and LC895299L are CD-ROM drive
digital servo system ICs that integrate all signal-
processing functions after the RF head amplifier on a
single chip.
Functions
• Built-in digital servo and ATAPI (IDE) CD-ROM,
CD-DSP, CAV audio, and1-Mbit DRAM functions
CD-ROM Decoder and ATAPI (IDE) Interface
Block
• Built-in ATAPI (IDE) interface
• The user can freely set the CD main channel, C2 flag,
and subcode areas in internal DRAM.
• Batch transfer function (Function for transferring the CD
main channel, C2 flag, or subcode data in a single
operation.)
• Multiple transfer function (Function for transferring
multiple blocks automatically in a single operation.)
• CAV audio functions
Features
CD-DSP Block
• Supports full CAV operation at 48× speed
• Assures stable data readout by performing frame sync
signal detection, protection, and interpolation.
• Demodulates the EFM signal to produce 8-bit symbol
data.
• Intelligent functions (auto buffering, auto decoding, and
CD-R functions)
• Subcode P to W buffering function (No ECC) and
CD-TEXT support
• Supports Ultra DMA MODE2, MODE1, and MODE0
• Built in 1-Mbit DRAM
• Applies a CRC check to the subcode Q signal and then
outputs that signal via parallel I/O to the system
microprocessor.
• Performs unscrambling and deinterleaving operations to
rearrange the demodulated EFM signal in the stipulated
order.
• Detects and corrects error signals and processes flags
(C1: 2 errors, C2: 4 errors)
• References the C1 flags and the C2 error check result to
set the C2 flags and interpolates or mutes the signal
depending on the C2 flags.
• Provides two types of muting: zero-cross muting and
soft muting.
• Independent left and right channel digital attenuators
(8-bit resolution)
Provides two types of attenuation: direct attenuation and
soft attenuation.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
13100TH (OT)/31599HA (OT) No. 6249-1/12
LC895299W, 895299L
Package Dimensions
unit: mm
3230-SQFP176
3244-LQFP176
[LC895299W]
[LC895299L]
26.0
22.0
20.0
0.4
24.0
0.125
1.25
0.5
1.25
132
133
89
(1.4)
88
132
89
88
133
45
176
45
176
1
44
0.125
1
44
0.15
0.2
(0.5)
0.5
0.5
0.5
SANYO: SQFP176
SANYO: LQFP176
Specifications
Absolute Maximum Ratings at V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
–0.3 to +6.0
–0.3 to +4.6
–0.3 to VDD5 + 0.3
–0.3 to VDD3 + 0.3
550
Unit
V
VDD5 max Ta = 25°C
VDD3 max Ta = 25°C
V
VI5, VO5
VI3, VO3
Pd max
Topr
Ta = 25°C
Ta = 25°C
Ta ≤ 70°C
V
Input and output voltages
V
Allowable power dissipation
Operating temperature
mW
°C
°C
°C
mA
–30 to +70
–55 to +125
235
Storage temperature
Tstg
Soldering conditions (pins only)
Input and output power
10 seconds
II, IO
±20 *
Note: * Per single input or output basic cell.
Allowable Operating Ranges at Ta = 0 to +70°C, V = 0 V
SS
I/O Cell 5.0-V Power Supply
Ratings
typ
5.0
Parameter
Symbol
Conditions
Unit
min
4.5
max
5.5
VDD
Supply voltage
Input voltage range
VDD
VIN
V
V
0
Note: The input voltage range for speeds of 45× or over is 4.5 to 5.25 V.
Internal Cell 3.3-V Power Supply
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Supply voltage
Input voltage range
VDD
VIN
3.0
0
3.3
3.8
V
V
VDD
Note: The input voltage range differs depending on the drive speed used. Contact your Sanyo representative for details.
No. 6249-2/12
LC895299W, 895299L
DC Characteristics at Ta = 0 to +70°C, V = 0 V, V = 4.5 to 5.5 V
SS
DD
Ratings
typ
Parameter
Symbol
Conditions
Applicable pins *
Unit
min
2.2
max
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Analog input voltage
VIH
VIL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
TTL level inputs
1
7
0.8
VIH
VIL
2.2
2.2
TTL level inputs with pull-up resistors
TTL level inputs with pull-down resistors
0.8
0.8
VIH
VIL
2
VIH
VIL
2.4
TTL level inputs
Schmitt inputs
3, 9
19, 20
4
0.8
VIH
VIL
2.4
TTL level inputs
Schmitt inputs with pull-up resistors
0.8
VIH
VIL
0.8 VDD
0.7 VDD
CMOS level inputs
Schmitt inputs
0.2 VDD
VIH
VIL
CMOS level inputs with pull-up resistors
5
0.3 VDD
3/4 VDD
VANI
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOL
VOL
VOL
VANO
IIL
18
1/4 VDD
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output high-level voltage
Output low-level voltage
Output low-level voltage
Output low-level voltage
Output low-level voltage
Analog output voltage
Input leakage current
IOH = –2 mA
IOL = 2 mA
IOH = –8 mA
IOL = 8 mA
IOH = –4 mA
IOL = 24 mA
IOH = –4 mA
IOL = 4 mA
IOL = 24 mA
IOL = 1 mA
IOL = 8 mA
VDD – 2.1
6, 17
0.4
0.4
0.4
VDD – 2.1
VDD – 2.1
VDD – 2.1
7, 8, 14
9, 12, 10, 20
16
0.4
0.4
11, 21
13
0.4
15
0.4
22
1/4 VDD
–10
3/4 VDD
+10
VI = VSS, VDD
1, 3, 4, 9
9, 11, 13,
14, 16, 17
Output leakage current
IOZ
During high-impedance output
–10
+10
µA
Pull-up resistance
Pull-up resistance
Pull-up resistance
Pull-down resistance
Pull-down resistance
RUP
RUP
RUP
RDN
RDN
5
7, 15
19, 20, 21
2
50
20
7
100
40
200
80
kΩ
kΩ
kΩ
kΩ
kΩ
10
13
50
7
100
10
200
13
10
Note: * The applicable pin column entries refer to the following sets.
INPUT
1 : ATPINSEL, SUA0 to SUA7
2 : TEST0 to TEST2
3 : DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZHRST, ZCS, ZRD, ZWR
4 : ZRESET, ZDSPRST
5 : FG
18 : AD0, AD1, PH, BH, RREC, FE, TE, VREF, CSS, AD2
19 : ZDMACK, CSEL
OUTPUT
6 : FSEQ
8 : HFLO, FSX, EFLG, C2F, WRQ, DIR, PCK, EFMOUT
13 : HINTRQ
11 : ZIOCS16
10 : DMARQ
13 : PDS1 to PDS3
14 : DOUT
15 : ZSWAIT, ZINT0, ZINT1
21 : IORDY
16 : DSLB, EQS, OUTPORT0 to OUTPORT2, MCK
17 : RHLD, TSH, BHH, GHS, LDON
22 : PHC, BHC, FBAL, TBAL, SGC, TOFST, TDO, FDO, SLDO, SPDO
INOUT
7 : D0 to D7, TRV, TRV2
9 : DD0 to DD15
20 : ZDASP, ZPDIAG
Note: XTAL, XTALCK
The above pins are not included in the DC Characteristics.
No. 6249-3/12
LC895299W, 895299L
Block Diagram
Driver
TDO, FDO
FG
SLDO, SPDO
DRAM
Address bus[0:18]
Data bus[0:7]
Data bus[0:15]
VCEC
PLL
*11
CAV-AUDIO
ZDSPRST
Address generator
*1
LA9238
*12
*2
CD-DSP
Sub-code
SYNC
Detector
*14
*3
SRAM
De-scramble
&
Buffering
Audio
Circuit
Address generator
CD-DSP I/F
&
ZRESET
SYNC
ECC & EDC
Detector
Address generator
Each Block
Bus control
signal
*4
*5
*6
ATAPI
I/F
Bus Arbiter
HOST
Buffer
DRAM
&
DRAM
controller
ZINT 1
ZINT 0
Each Block
Register
WRQ
*7
Data output input I/F
Address generator
Micro
controller
decoder
*8
ZSWAIT
Micro controller
RAM access
XTALCK
XTAL
PLL Clock
generator
Address generator
Each Block
*13
A12530
*9
*10
*1 EFMIN, EFMIN2, PH, BH, FE, TE, TES, RREC
*2 RHLD, TSH, EQS, BHH, GHS, LDON, FBAL, TBAL, TOFST, SGC
*3 LOUT, ROUT, DOUT
*4 DD0 to DD15, ZDASP, ZPDIAG
*5 ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK, ZHRST, CSEL
*6 DMARQ, HINTRQ, ZIOCS16, IORDY
*7 ZRD, ZWR, ZCS, CSCTRL, SUA0 to SUA7
*8 D0 to D7
*9 DIR/FLOCK, HFLO/TLOCK, FSEQ, FSX/LRCK, EFLG/CK2, C2F, EFMOUT, PCK, TRV2/DATA, TRV, PORT OUT0 to OUT2
*10 ATPINSEL, TEST0 to TEST2
*11 RPO, OPP, PCKISTF, PCKISTP, PDO, POS1 to POS3, FR
*12 SLCO0 to SLCO3, JITC, DSLB, PHC, BHC
*13 PLL1 to PLL3
*14 SLCIT1 to SLCIT2, JITIN, AD0 to AD2, VREF, CSS
No. 6249-4/12
LC895299W, 895299L
Pin Functions
Type
LC895299 Pin Functions 1
(When pin 95, ATPINSEL, is low)
I
INPUT
B
P
BIDIRECTION
POWER
NC
NOT CONNECT
O
OUTPUT
Pin No.
1
Pin
Type
P
O
O
O
O
O
O
I
Function
VSS
Logic system ground
Monitor outputs
2
FLOCK/CRCERR
3
DIR/TLOCK
ZSWAIT
WRQ/HFLO
ZINT0
ZINT1
TEST0
D0
4
Wait signal output to the microcontroller
Monitor output
5
6
Microcontroller interrupt
7
8
Test pin (Must be tied to ground during normal operation.)
9
B
B
B
B
B
B
B
B
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
D1
D2
D3
D4
Microcontroller data bus
D5
D6
D7
MCK
ZCS
Clock output to the microcontroller
Microcontroller ZCS signal
NC
NC
P
P
P
P
NC
NC
I
VDDD
VDD1
VSS
DRAM VDD: 5 V
3.3 V
Logic system ground
DRAM ground
VSSD
SUA0
SUA1
I
SUA2
I
SUA3
I
Microcontroller address bus
SUA4
I
SUA5
I
SUA6
I
SUA7
I
ZWR
I
Microcontroller write signal
Microcontroller read signal
Frame synchronization detection
Digital output/tes output
ZRD
I
FSEQ
DOUT/TESO
VDD0
O
O
P
P
I
I/O system power supply: 5 V
Logic system ground
VSS
PLL1
PLL2
I
System Clock PLL
PLL3
O
P
P
I
PLL1 VDD
PLL1 VSS
CSEL
Logic PLL VDD: 3.3 V
Logic PLL system ground
ZHRST
ZDASP
ZCS3FX
ZCS1FX
VSS1
I
B
I
ATAPI I/F
I
I
I/F ground
VDD0
I
I/O system power supply: 5 V
Continued on next page.
No. 6249-5/12
LC895299W, 895299L
Continued from preceding page.
Pin No.
53
Pin
DA2
I/O
I
Function
54
DA0
I
55
ZPDIAG
DA1
B
I
ATAPI I/F
56
57
ZIOCS16
VSS1
O
P
O
I
58
I/F ground
ATAPI I/F
59
HINTRQ
ZDMACK
IORDY
ZDIOR
ZDIOW
DMARQ
VDD0
60
61
O
I
62
63
I
64
O
P
P
P
B
B
B
B
B
P
B
B
B
B
B
P
B
B
B
B
B
B
P
O
P
P
O
P
O
I
65
I/O system power supply: 5 V
66
VDD1
3.3 V
67
VSS1
I/F ground
68
DD15
69
DD0
70
DD14
ATAPI I/F
I/F ground
ATAPI I/F
I/F ground
71
DD1
72
DD13
73
VSS1
74
DD2
75
DD12
76
DD3
77
DD11
78
DD4
79
VSS1
80
DD10
81
DD5
82
DD9
ATAPI I/F
83
DD6
84
DD8
85
DD7
86
VDD0
I/O system power supply: 5 V
D/A converter output
87
ROUT
AUVDD
AUVSS
LOUT
88
D/A converter VDD: 5 V
DAC ground
89
90
D/A converter output
91
VSS
Logic system ground
92
XTAL
XTALCK output
93
XTALCK
VDD0
XTALCK input (33.8688 MHz)
I/O system power supply: 5 V
ATAPI pin assignment selection
94
P
I
95
ATPINSEL
TEST1
FSX/LRCK
EFLG/CK2
TRV2/DATA
TRV
96
I
Test pin (Must be tied to ground during normal operation.)
97
O
O
B
B
O
O
O
O
O
O
NC
Monitor outputs
98
99
General-purpose I/O ports
100
101
102
103
104
105
106
107
C2F
C2F output
PCK output
EFM output
PCK
EFMOUT
OUTPORT0
OUTPORT1
OUTPORT2
General-purpose output ports
Continued on next page.
No. 6249-6/12
LC895299W, 895299L
Continued from preceding page.
Pin No.
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Pin
I/O
NC
P
P
P
P
NC
NC
O
P
I
Function
VSSD
VDD1
VSS
DRAM ground
3.3 V
Logic GND
DRAM VDD: 5 V
VDDD
DSLB
AVDD
SLCIST1
SLCIST2
SLCO0
SLCO1
SLCO2
SLCO3
EFMIN
EFMIN2
AVSS
JITIN
JITC
SLC PWM output
Slice level VDD: 3.3 V
EFM slice level setting
EFM slice level outputs
EFM input
I
O
O
O
O
I
I
P
I
Slice level ground
Jitter detection input
Jitter output
O
O
I
RPO
P/N balance adjustment
OPP
PCKISTF
PCKISTP
PLL2VDD
PLL2VSS
PDO
I
Frequency comparator charge pump setting
Phase comparator charge pump setting
VCEC PLL VDD: 3.3 V
I
P
P
O
O
O
O
I
VCEC PLL ground
Charge pump filter
PDS1
PDS2
PDS3
FR
Charge pump selection
VCO frequency setting
Servo system ground
A/D converter input 0
A/D converter input 1
Peak hold circuit
SVSS
AD0
P
I
AD1
I
PH
I
BH
I
Bottom hold circuit
Optical recognition input
FE input
RREC
FE
I
I
TE
I
TE input
TES
I
TES comparator input
VREF input
VREF
CSS
I
I
Center servo input
A/D converter input 2
PH slice capacitor connection
BH slice capacitor connection
Focus balance
AD2
I
PHC
O
O
O
P
P
O
O
O
O
O
O
O
BHC
FBAL
SVDD
SVSS
TBAL
SGC
Servo system VDD: 5V
Servo system ground
Tracking balance
Servo gain adjustment
Tracking offset adjustment
Tracking output
TOFST
TDO
FDO
Focus output
SLDO
SPDO
Sled output
Spindle output
Continued on next page.
No. 6249-7/12
LC895299W, 895299L
Continued from preceding page.
Pin No.
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Pin
VDD0
I/O
P
P
P
O
O
O
O
O
O
I
Function
A/D and D/A converter VDD: 5 V
VSS
Logic ground
VDD1
3.3 V
RHLD
TSH
RF AGC hold output
TS frequency switching
RF equalizer selection
BH frequency switching
RF and TS signal gain switching
Laser control
EQS
BHH
GHS
LDON
TEST2
FG
Test pin (Must be tied to ground during normal operation.)
I
FG input
ZDSPRST
ZRESET
VDD0
I
DSP RESET
CHIP RESET
I/O system VDD: 5 V
I
P
All NC pins must be left open.
Pins whose name begin with Z operate with inverted (negative) logic.
Applications must supply 5 V to VDD0, 3.3 V to VDD1, the 1-bit D/A converter 5 V to AUVDD, the logic PLL 3.3 V to PLL1VDD, the VCEC PLL 3.3 V to
PLL2VDD, the slice level 3.3 V to AVDD, the servo system 5 V to SVDD, and the DRAM 5 V to VDDD
SS is the logic system ground, AUVSS is the 1-bit D/A converter ground, VSS1 is the IDE interface driver ground, PLL1VSS is the logic PLL ground, PLL2VSS
is the VCEC PLL ground, AVSS is the slice level ground, SVSS is the servo system ground, and VSSD is the DRAM ground.
.
V
No. 6249-8/12
LC895299W, 895299L
Pin Functions
Type
LC895299 Pin Functions 2
(When pin 95, ATPINSEL, is high)
I
INPUT
B
P
BIDIRECTION
POWER
NC
NOT CONNECT
O
OUTPUT
Pin No.
1
Pin
Type
P
O
O
O
O
O
O
I
Function
VSS
Logic system ground
Monitor outputs
2
FLOCK/CRCERR
3
DIR/TLOCK
ZSWAIT
WRQ/HFLO
ZINT0
ZINT1
TEST0
D0
4
Wait signal output to the microcontroller
Monitor output
5
6
Microcontroller interrupt
7
8
Test pin (Must be tied to ground during normal operation.)
9
B
B
B
B
B
B
B
B
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
D1
D2
D3
Microcontroller data bus
D4
D5
D6
D7
MCK
ZCS
Clock output to the microcontroller
Microcontroller ZCS signal
NC
NC
P
P
P
P
NC
NC
I
VDDD
VDD1
VSS
DRAM VDD: 5 V
3.3 V
Logic system ground
DRAM ground
VSSD
SUA0
SUA1
SUA2
SUA3
SUA4
SUA5
SUA6
SUA7
ZWR
I
I
I
Microcontroller address bus
I
I
I
I
I
Microcontroller write signal
Microcontroller read signal
Frame synchronization detection
Digital output/tes output
ZRD
I
FSEQ
DOUT/TESO
VDD0
O
O
P
P
I
I/O system power supply: 5 V
Logic system ground
VSS
PLL1
PLL2
I
System Clock PLL
PLL3
O
P
P
I
PLL1 VDD
PLL1 VSS
CSEL
DD7
Logic PLL VDD: 3.3 V
Logic PLL ground
B
B
B
B
P
P
DD8
ATAPI I/F
DD6
DD9
VSS1
I/F ground
VDD0
I/O system power supply: 5 V
Continued on next page.
No. 6249-9/12
LC895299W, 895299L
Continued from preceding page.
Pin No.
53
Pin
DD5
I/O
B
B
B
B
B
P
B
B
B
B
B
B
P
P
P
B
O
I
Function
54
DD10
55
DD4
ATAPI I/F
I/F GND
56
DD11
57
DD3
58
VSS1
59
DD12
60
DD2
61
DD13
ATAPI I/F
62
DD1
63
DD14
64
DD0
65
VDD0
I/O system power supply: 5 V
66
VDD1
3.3 V
67
VSS1
I/F GND
68
DD15
69
DMARQ
ZDIOW
ZDIOR
IORDY
VSS1
70
ATAPI I/F
I/F GND
ATAPI I/F
I/F GND
71
I
72
O
P
I
73
74
ZDMACK
HINTRQ
ZIOCS16
DA1
75
O
O
I
76
77
78
ZPDIAG
VSS1
B
P
I
79
80
DA0
81
DA2
I
82
ZCS1FX
ZCS3FX
ZDASP
ZHRST
VDD0
I
ATAPI I/F
83
I
84
B
I
85
86
P
O
P
P
O
P
O
I
I/O system power supply: 5 V
D/A converter output
87
ROUT
AUVDD
AUVSS
LOUT
88
D/A converter VDD: 5 V
DAC ground
89
90
D/A converter output
91
VSS
Logic system ground
92
XTAL
XTALCK output
93
XTALCK
VDD0
XTALCK input (33.8688 MHz)
I/O system power supply: 5 V
ATAPI pin assignment selection
94
P
I
95
ATPINSEL
TEST1
FSX/LRCK
EFLG/CK2
TRV2/DATA
TRV
96
I
Test pin (Must be tied to ground during normal operation.)
97
O
O
B
B
O
O
O
O
O
O
NC
Monitor outputs
98
99
General-purpose I/O ports
100
101
102
103
104
105
106
107
C2F
C2F output
PCK output
EFM output
PCK
EFMOUT
OUTPORT0
OUTPORT1
OUTPORT2
General-purpose output ports
Continued on next page.
No. 6249-10/12
LC895299W, 895299L
Continued from preceding page.
Pin No.
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Pin
I/O
NC
P
P
P
P
NC
NC
O
P
I
Function
VSSD
VDD1
VSS
DRAM ground
3.3 V
Logic system ground
DRAM VDD: 5 V
VDDD
DSLB
AVDD
SLCIST1
SLCIST2
SLCO0
SLCO1
SLCO2
SLCO3
EFMIN
EFMIN2
AVSS
JITIN
JITC
SLC PWM output
Slice level VDD: 3.3 V
EFM slice level setting
EFM slice level outputs
EFM input
I
O
O
O
O
I
I
P
I
Slice level ground
Jitter detection input
Jitter output
O
O
I
RPO
P/N balance adjustment
OPP
PCKISTF
PCKISTP
PLL2VDD
PLL2VSS
PDO
I
Frequency comparator charge pump setting
Phase comparator charge pump setting
VCEC PLL VDD: 3.3 V
I
P
P
O
O
O
O
I
VCEC PLL ground
Charge pump filter
PDS1
PDS2
PDS3
FR
Charge pump selection
VCO frequency setting
Servo system ground
A/D converter input 0
A/D converter input 1
Peak hold circuit
SVSS
AD0
P
I
AD1
I
PH
I
BH
I
Bottom hold circuit
Optical recognition input
FE input
RREC
FE
I
I
TE
I
TE input
TES
I
TES comparator input
VREF input
VREF
CSS
I
I
Center servo input
A/D converter input 2
PH slice capacitor connection
BH slice capacitor connection
Focus balance
AD2
I
PHC
O
O
O
P
P
O
O
O
O
O
O
O
BHC
FBAL
SVDD
SVSS
TBAL
SGC
Servo system VDD: 5V
Servo system ground
Tracking balance
Servo gain adjustment
Tracking offset adjustment
Tracking output
TOFST
TDO
FDO
Focus output
SLDO
SPDO
Sled output
Spindle output
Continued on next page.
No. 6249-11/12
LC895299W, 895299L
Continued from preceding page.
Pin No.
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Pin
VDD0
I/O
P
P
P
O
O
O
O
O
O
I
Function
A/D and D/A converter VDD: 5 V
VSS
Logic system ground
3.3 V
VDD1
RHLD
TSH
RF AGC hold output
TS frequency switching
RF equalizer selection
BH frequency switching
RF and TS signal gain switching
Laser control
EQS
BHH
GHS
LDON
TEST2
FG
Test pin (Must be tied to ground during normal operation.)
I
FG input
ZDSPRST
ZRESET
VDD0
I
DSP RESET
CHIP RESET
I/O system VDD: 5 V
I
P
All NC pins must be left open.
Pins whose name begin with Z operate with inverted (negative) logic.
Applications must supply 5 V to VDD0, 3.3 V to VDD1, the 1-bit D/A converter 5 V to AUVDD, the logic PLL 3.3 V to PLL1VDD, the VCEC PLL 3.3 V to
PLL2VDD, the slice level 3.3 V to AVDD, the servo system 5 V to SVDD, and the DRAM 5 V to VDDD
.
V
SS is the logic system ground, AUVSS is the 1-bit D/A converter ground, VSS1 is the IDE interface driver ground, PLL1VSS is the logic PLL ground, PLL2VSS
is the VCEC PLL ground, AVSS is the slice level ground, SVSS is the servo system ground, and VSSD is the DRAM ground.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of January, 2000. Specifications and information herein are subject
to change without notice.
PS No. 6249-12/12
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