LE24LB642M_10 [SANYO]
Two Wire Serial Interface EEPROM (64k EEPROM); 两线串行接口EEPROM （ 64K EEPROM ）
| 型号： | LE24LB642M_10 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Two Wire Serial Interface EEPROM (64k EEPROM) |
| 文件： | 总12页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1201A
CMOS IC
Two Wire Serial Interface EEPROM
(64k EEPROM)
LE24LB642M
Overview
The LE24LB642M is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by
incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I2C memory
protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory.
Functions
• Capacity: 64k bits (8k × 8 bits)
• Single supply voltage: 1.8V to 5.5V
• Interface: Two wire serial interface (I2C Bus*)
• Operating clock frequency: 400kHz
• Low power consumption
: Standby: 2μA (max)
: Active (Read): 0.5mA (max)
• Automatic page write mode: 32 Bytes
• Read mode: Sequential read and random read
• Erase/Write cycles: 106 cycles (Page writing), 105 cycles (Byte writing)
• Data Retention: 20 years
• High reliability: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
* I2C Bus is a trademark of Philips Corporation.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
10511 SY/60408 SY IM 20080415-S00009 No.1201-1/12
LE24LB642M
Package Dimensions
unit:mm (typ)
3032E
5.0
8
1
2
(0.6)
1.27
0.15
0.35
SANYO : MFP8(225mil)
Pin Assignment
Pin Descriptions
PIN.1
PIN.2
PIN.3
PIN.4
PIN.5
PIN.6
PIN.7
PIN.8
NC
Nonconnected pin
Nonconnected pin
Nonconnected pin
Ground
NC
NC
NC
1
2
3
4
8
7
6
5
V
DD
NC
WP
GND
SDA
SCL
WP
Serial data input
Serial clock input/output
Write protect
NC
SCL
SDA
GND
V
Power supply
DD
Block Diagram
WP
Write controller
High voltage generator
SCL
EEPROM Array
Y decoder & Sense AMP
Serial-Parallel converter
SDA
No.1201-2/12
LE24LB642M
Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
Ratings
-0.5 to +6.5
unit
V
DC input voltage
Over-shoot voltage
-0.5 to +5.5
-1.0 to +6.5
-65 to +150
V
Below 20ns
V
Storage temperature
Tstg
°C
Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Operating Conditions
Parameter
Operating supply voltage
Operating temperature
Symbol
Conditions
Ratings
unit
V
1.8 to 5.5
-40 to +85
°C
DC Electrical Characteristics
V
=1.8V to 5.5V
DD
Parameter
Symbol
Conditions
unit
min
typ
max
Supply current at reading
Supply current at writing
CMOS standby current
Input leakage current
Output leakage current
Input low voltage
I
I
I
I
I
1
2
f=400kHz, V =V
DD DD
max
0.5
3
mA
mA
μA
μA
μA
V
CC
CC
SB
LI
f=400kHz, t
=10ms, V =V
max
WC
DD DD
V
V
V
=V
or V , V =V
SS DD DD
max
max
max
2
IN DD
=GND to V , V =V
DD DD DD
-2
-2
2
IN
=GND to V , V =V
DD DD DD
2
LO
IN
V
V
V
V
V
V
V
*0.2
IL
DD
Input low voltage (CMOS)
Input high voltage
0.2
V
ILC
IH
V
*0.8
-0.2
V
DD
Input high voltage (CMOS)
Output low voltage
V
DD
V
IHC
1
I
=3.0mA, V =2.5V to 5.5V
OL DD
0.4
0.2
V
OL
2
I
=0.7mA, V =1.8V to 5.5V
DD
V
OL
OL
Capacitance/Ta=25°C, f=1MHz
Parameter
Input pin capacitance
In/output pin capacitance
Symbol
Conditions
=0V (other than SDA)
=0V (SDA)
max
unit
C
C
V
V
10
10
pF
pF
I
IN
I/O
I/O
Note: This parameter is sampled and not 100% tested.
V
DD
AC Electric Characteristics
Input pulse level
0.1×V
to 0.9×V
DD
DD
Input pulse rise / fall time
Output detection voltage
Output load
20ns
0.5×V
DD
R=3.0kΩ
50pF+Pull up resistor 3.0kΩ
SDA
C=50pF
Output Load Circuit
No.1201-3/12
LE24LB642M
V
=1.8V to 5.5V
typ
DD
Parameter
Slave mode SCL clock frequency
Symbol
unit
min
max
f
400
900
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
SCLS
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
t
1200
600
100
100
600
600
100
0
LOW
t
HIGH
t
AA
t
DH
t
SU.STA
t
HD.STA
t
SU.DAT
Data in hold time
t
HD.DAT
Stop condition setup time
SCL SDA rise time
t
600
SU.STO
t
300
300
R
SCL SDA fall time
t
F
Bus release time
t
1200
BUF
Noise suppression time
Write cycle time
t
50
10
SP
t
WC
Bus Timing
t
t
t
LOW
F
HIGH
t
R
t
SP
SCL
t
t
t
HD.DAT
SU.DAT
t
t
t
SU.STA
SU.STO
HD.STA
SDA/IN
t
SP
t
BUF
t
DH
AA
SDA/OUT
Write Timing
t
WC
SCL
SDA
D0
Start
condition
Stop
condition
Write Data
Acknowledge
No.1201-4/12
LE24LB642M
Pin Functions
SCL (serial clock input) pin
The SCL pin is a serial clock input pin that processes signals at the rising and falling edges of SCL clock signals.
SDA (serial data input/output) pin
The SDA pin is used to transfer serial data to the input/output, and it consists of a signal input pin and n-channel
transistor open drain output pin.
Like the SCL pin, the SDA pin must be pulled up by a resistor to the V
(or open collector) output device for use.
level and wired-ORed with an open drain
DD
WP (write protect) pin
When the WP pin is high, write protection is enabled, and writing into the 64k bit memory areas is prohibited. When
the pin is low, writing is possible to all memory areas. Read operations can be performed regardless of the WP pin
status.
Functional Description
1 Start condition
When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low.
The operation of the EEPROM as a slave starts in the start condition.
2 Stop condition
When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high.
When the device is set up for the read sequence, the read operation is suspended when the stop condition is received,
and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended
when the stop condition is received, and the EEPROM internal write operation is started.
t
t
t
SU.STA
SU.STO
HD.STA
SCL
SDA
Stop
condition
Start
condition
3 Data transfer
Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL
line is high, the resulting condition will be recognized as the start or stop condition.
t
t
HD.DAT
SU.DAT
SCL
SDA
No.1201-5/12
LE24LB642M
4 Acknowledge
During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the
system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has
been received. The acknowledge signal is not sent during an EEPROM internal write operation.
SCL
(EEPROM input)
8
1
9
SDA
(Master output)
Acknowledge
bit output
SDA
(EEPROM output)
Start
condition
t
t
DH
AA
5 Device addressing
For the purposes of communication, the master device in the system generates the start condition for the slave device.
Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is
7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition.
The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” This
device has the upper 3-bit of the Slave Device address as the Slave address (S0, S1, S2), which fixed on the inside.
The value of Slave address are S0=0, S1=0, S2=0.
When the device code input from SDA and the slave addresses are compared with the product’s device code and slave
addresses that were set at the mounting stage and found to match, the product sends the acknowledge signal during
the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command
code. If they do not match, the EEPROM returns to standby mode. When a read operation is performed immediately
after the slave device has been switched, the random read command must be used.
Slave
Address
Device Code
1
0
1
0
S2
S1
S0
R/W
LSB
MSB
Device address word
No.1201-6/12
LE24LB642M
6 EEPROM write operation
6-1. Byte writing
When the EEPROM receives the 7-bit device address and write command code "0" after the start condition, it
generates an acknowledge signal. After this, if it receives 4-bit don’t-care bits and a 12-bit word address, generates an
acknowledge signal, receives the 8-bit writing data, and generates an acknowledge signal when it receives the stop
condition, the rewrite operation of the EEPROM in the designated memory address will start. Rewriting is completed
in the t
period after the stop condition. During an EEPROM rewrite operation, no input is accepted and no
acknowledge signals are generated.
WC
Word Address
Data
A A
12 11 10
A
1
0
1
0 S2 S1 S0
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
SDA
W
*
*
*
ACK
R/W
ACK
*: don’t care
6-2. Page writing
This product enables pages with up to 32 bytes to be written. The basic data transfer procedure is the same as for byte
writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and
data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,
after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data
equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit
write data and generating the acknowledge signals.
At the point when the write data (n+1) has been input, the lower 5 bits (A0-A4) of the word addresses are
automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the
word address on the page is incremented each time the write data is input. If the write data exceeds 32 bytes or the
last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the
same address two or more times, but in such cases the write data that was input last will take effect. Finally, the
EEPROM internal write operation corresponding to the page size for which the write data is received starts from the
designated memory address when the stop condition is received.
Word Address(n)
Data(n)
A
12
A
11 10
A
S2 S1 S0
SDA
1
0
1
0
W
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
*
*
*
ACK
ACK
R/W
Data(n+x)
Data(n+1)
…
D7 D6 - D1 D0
ACK
D7 D6 - D1 D0
ACK
D7 D6 - D1 D0
D7 D6 - D1 D0
ACK
ACK
ACK
*: don’t care
No.1201-7/12
LE24LB642M
6-3. Acknowledge polling
Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop
condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to
the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is
completed, the start condition, device address and write command code are sent from the master device to the
EEPROM (slave device), and the response of the slave device is detected.
In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is
in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been
completed.
When codes are sent by the master device during acknowledge polling, if a write or random read is to be performed
next, the write command "0" is executed. If a current read or sequential read is to be performed next, the read
command "1" is executed. After the write command "0" is executed and ACK="L" is confirmed, the start
condition/stop condition is entered to cancel the command and change to standby mode.
During Write
During Write
End of Write
…
0
0
W
0
1
0
1 0 1 0
S2 S1 S0
S2 S1 S0
S2 S1 S0
1
W
SDA
1
1
W
NO ACK
R/W
NO ACK
R/W
ACK
R/W
7 EEPROM read operations
7-1. Current address reading
The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for
both write* and read operations. Therefore, provided that the master device has recognized the position of the
EEPROM address pointer, data can be read from the memory address with the current address pointer without
specifying the word address.
As with writing, current address reading involves receiving the 7-bit device address and read command code “1”
following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data
of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending
an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to
standby mode.
If the previous read address is the last address, the address for the current address reading is rolled over to become
address 0.
*: If the write data is 1 or more bytes but less than 32 bytes, the current address after page writing is the address
equivalent to the number of bytes to be written in the specified word address +1. If the write data is 32 or more bytes,
it is the designated word address. If the last address (A4-A0=11111b) on the page has been designated by byte write
as the word address, the first address (A4-A0=0000b) on the page serves as the internal address after writing.
Device Address
Data(n+1)
S2 S1 S0
SDA
1
0
1
0
R
D7 D6 D5 D4 D3 D2 D1 D0
ACK
NO ACK
R/W
No.1201-8/12
LE24LB642M
7-2. Random read
Random read is a mode in which a selected memory address is specified and its data is read. The address is specified
by a dummy write input.
First, when the EEPROM receives the 7-bit device address and write command code "0" following the start condition,
it generates an acknowledge signal. It then receives 4-bit don’t-care bits and a 12-bit word address and generates an
acknowledge signal. These operations are used to load the word address to the address counter in the EEPROM.
Next, the start condition is input again, and the current read is performed. This generates the word address data that
was input using the dummy write input. After the data is generated, if the stop condition is input without the input of
an acknowledge signal, reading is completed, and standby mode is established.
Device Address
Word Address(n)
A
A A
12 11 10
SDA
1
0
1
0
S2 S1 S0
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
W
*
*
*
ACK
R/W
ACK
Dummy Write
Device Address
Data(n)
S2 S1 S0
1
0
1
0
R
D7 D6 - D1 D0
ACK
ACK
NO ACK
R/W
Current Read
*: don’t care
7-3. Sequential read
In this mode, the data is read continuously, and sequential read operations can be performed with both current address
read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued
without issuing the stop condition, the address is incremented, and the data of the next address is output.
If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output
while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data
continues to be read. As with current address read and random read, the operation is completed by inputting the stop
condition without sending an acknowledge signal.
Device Address
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
S2 S1 S0
SDA
1
0
1
0
R
D7 D6 - D1 D0
ACK
D7 D6 - D1 D0
ACK
D7 D6 - D1 D0
ACK
D7 D6 - D1 D0
NO ACK
ACK
R/W
No.1201-9/12
LE24LB642M
Application Notes
1) Software reset function
Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in
order to avoid erroneous operation after power-on and to reset while the command input sequence. During the
dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for
the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H
will result in an overcurrent flow.
Note that this software reset function does not work during the internal write cycle.
Dummy clock cycle × 9
1
8
2
9
SCL
SDA
Start condition
Start condition
2) Pull-up resistor of SDA pin
Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a
resistance from several kΩ to several tens of kΩ) without fail. The appropriate value must be selected for this
resistance (R ) on the basis of the V and I of the microcontroller and other devices controlling this product as
PU IL IL
well as the V –I characteristics of the product. Generally, when the resistance is too high, the operating
OL OL
frequency will be restricted; conversely, when it is too low, the operating current consumption will increase.
R
PU
maximum resistance
The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (I )
L
of the input leaks of the devices connected to the SDA bus and by R , can completely satisfy the input high level
PU
(V min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time t and fall
IH
time t must be set.
R
F
R
PU
maximum value = (V
- V )/I
IH L
DD
Example: When V =3.0V and I = 2μA
DD
L
R
PU
maximum value = (3.0V − 3.0V × 0.8)/2μA = 300kΩ
R
PU
R
PU
minimum value
EEPROM
A resistance corresponding to the low-level output
voltage (V max) of SANYO’s EEPROM must be set.
Master
device
SDA
OL
I
I
C
BUS
L
L
R
PU
minimum value = (V
− V )/I
DD OL OL
Example: When V =3.0V, V
DD
PU
= 0.4V and I = 1mA
OL
OL
minimum value = (3.0V − 0.4)/1mA = 2.6kΩ
R
Recommended R
setting
is set to strike a good balance between the operating frequency requirements and power consumption. If it is
PU
R
PU
assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns, R
will be about
PU
R
PU
= 500ns/50pF = 10kΩ.
No.1201-10/12
LE24LB642M
3) Notes on write protect operation
This product prohibits all 32k bit writing when the WP pin is high. To ensure full write protection, the WP is set high
for all periods from the start condition to the stop condition, and the conditions below must be satisfied.
V
=1.8 to 5.5V
typ
DD
Item
Symbol
unit
min
max
WP Setup time
WP Hold time
t
t
600
600
ns
ns
SU.WP
HD.WP
WP
t
t
HD.WP
SU.WP
SCL
SDA
Start condition
Stop condition
4) Precautions when turning on the power
This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is
turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data
guarantees are given in the event of an instantaneous power failure during the internal write operation.
V
=1.8 to 5.5V
typ
DD
Item
Symbol
unit
min
max
Power rise time
t
t
100
0.2
ms
ms
V
RISE
Power off time
10
OFF
Power bottom voltage
V
bot
t
RISE
V
DD
t
OFF
Vbot
0V
Notes:
1) The SDA pin must be set to high and the SCL pin to low or high.
2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.
No.1201-11/12
LE24LB642M
A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise
After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high.
V
V
DD
DD
t
LOW
SCL
SDA
SCL
SDA
t
t
SU.DAT
SU.DAT
t
DH
B. If it is not possible to satisfy the instruction 2 in Note above
After the power has stabilized, software reset must be executed.
C. If it is not possible to satisfy the instructions both 1 and 2 in Note above
After the power has stabilized, the steps in A must be executed, then software reset must be executed.
5) Noise filter for the SCL and SDA pins
This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 50ns or less are not
recognized because of this function.
6) Function to inhibit writing when supply voltage is low
This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed
operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages
(typ.) of 1.3V and below.
7) Slave address setting
This product does not include a slave address pin, but the information for the slave addresses, S0, S1 and S2, are
held internally. The slave addresses of this product are set to S0=0, S1=0, and S2=0 when it is shipped. During
device addressing, execute this slave address code after the device code.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
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intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of January, 2011. Specifications and information herein are subject
to change without notice.
PS No.1201-12/12
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LE25ABD-TRLE
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