LE25CB5122M [SANYO]
Serial SPI EEPROM (SPI Bus)(512Kbit); SPI串行EEPROM（ SPI总线） （达512Kbit ）
| 型号： | LE25CB5122M |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Serial SPI EEPROM (SPI Bus)(512Kbit) |
| 文件： | 总13页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1679A
Serial SPI EEPROM
(SPI Bus)(512Kbit)
LE25CB5122M
Overview
The LE25CB5122M is a 512Kbit EEPROM that supports serial peripheral interface (SPI). It realizes high speed operation
and high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. The interface is
compatible with SPI bus protocol, therefore, it is best suited for applications that require small-scale rewritable nonvolatile
parameter memory. Moreover, the LE25CB5122M has a 128 bytes page rewrite function that provides rapid data
rewriting.
Features
• Capacity
• Single supply voltage
• Serial interface
: 512Kbits (64K×8bits)
: 2.7V to 3.6V
: SPI Mode0, Mode3 supported
• Operating clock frequency : 5MHz
• Low current dissipation
: Standby
: Active (Read)
: 5μA (max.)
: 3mA (max.)
: Active (Rewrite) : 5mA (max.)
• Page write function
• Rewrite time
• Number of rewrite times
• Data retention period
• High reliability
: 128bytes
: 5ms
: 106 times (Page Write)
: 20years
: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Incorporates a feature to prohibit write operations under low voltage conditions.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
10511 SY/31710 SY 20100205-S00001 No.NA1679-1/13
LE25CB5122M
Package Dimensions
unit : mm (typ)
3032E
[LE25CB5122M]
5.0
8
1
2
(0.6)
1.27
0.15
0.35
SANYO : MFP8(225mil)
Packages
MFP8 (225mil)
: LE25CB5122M
Pin Assignment
Pin Descriptions
PIN.1
PIN.2
PIN.3
PIN.4
PIN.5
PIN.6
PIN.7
PIN.8
CS
SO
WP
V
Chip select
Serial data output
Write protect
Ground
CS
SO
WP
1
2
3
4
8
7
6
5
V
DD
SS
HOLD
SI
Serial data input
Serial clock
Hold
SCK
SI
SCK
HOLD
V
SS
V
Power supply
DD
Block Diagram
X-
EEPROM
Cell Array
DECODER
ADDRESS
BUFFERS
&
LATCHES
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
CS SCK SI
SO
WP
HOLD
No.NA1679-2/13
LE25CB5122M
Specifications
Absolute Maximum Rating/If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Parameter
Symbol
Conditions
Ratings
Unit
°C
V
Storage temperature
-65 to +150
-0.5 to 4.6
Supply voltage
DC input voltage
-0.5 to V +0.5
DD
V
Overshoot voltage (below 20ns)
-1.0 to V +1.0
DD
V
Operating Conditions
Parameter
Symbol
Conditions
Conditions
Ratings
Unit
Operating temperature
Operating supply voltage
-40 to +85
2.7 to 3.6
°C
V
DC Electrical Characteristics
Parameter
Symbol
R
min
typ
max
3
Unit
mA
Supply current when reading
I
CS = 0.1V , HOLD = WP = 0.9V
DD
CC
DD
SI = 0.1V /0.9V , SO = Open
DD
DD
Operating frequency = 5MHz,
V
= V Max
DD
DD
Supply current when writing
CMOS standby current
I
I
W
V
= V
max.
5
5
mA
CC
DD
DD
CS = V , V = V
DD IN DD
or V
SS
μA
SB
V
= V Max
DD
DD
to V , V
Input leakage current
I
I
V
= V
SS
= V
max.
max.
2
2
μA
LI
IN
DD DD
DD
Output leakage current
Input low voltage
V
V
V
I
= V
SS
to V , V
DD DD
= V
μA
V
LO
IN
DD
V
V
V
V
= V
max.
min.
-0.3
0.3V
DD
IL
DD
DD
DD
Input high voltage
Output low voltage
Output high voltage
= V
0.7V
V
+0.3
0.4
V
IH
DD
DD
DD
= 3.0mA, V
= 2.7V to 3.6V
DD
= -0.4mA, V = 2.7V to 3.6V
DD
V
OL
OL
I
0.8V
V
OH
OH
DD
Capacitance at Ta = 25°C, f = 1.0MHz
Parameter
Symbol
Conditions
min
typ
max
Unit
pF
Output pin capacitance
C
C
V
V
= 0V
12
6
DQ
DQ
= 0V
pF
Input pin capacitance
IN
IN
Note : These parameters are sampled and not 100% tested.
AC Electrical Characteristics
Input pulse level
0.2×V
10ns
to 0.8×V
DD
DD
Input pulse rise/fall time
Output detection voltage
Output load
0.5×V
30pF
DD
No.NA1679-3/13
LE25CB5122M
AC Characteristics (at FCLK = 5MHz)/V
= 2.7V to 3.6V
DD
Parameter
Clock frequency
Symbol
FCLK
Conditions
min
typ
max
Unit
MHz
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
5
1
SCK logic high level pulse width
SCK logic low level pulse width
Input signal rise/fall time
CS setup time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
90
90
CLHI
CLLO
RF
90
90
20
30
90
90
90
CSS
CLS
DS
SCK setup time
Data setup time
Data hold time
DH
CS hold time
CSH
CLH
CPH
CHZ
V
SCK hold time
CS standby pulse width
CS output high impedance time
SCK output data time
Output data hold time
WP setup time
150
80
0
30
30
30
30
HO
WPS
WPH
HS
WP hold time
HOLD setup time
HOLD hold time
HH
HOLD output low impedance time
HOLD output high impedance time
Write cycle time
50
100
5
HLz
HHz
WC
CLZ
SCK output low impedance time
0
Table 1 Command Settings
1st bus
2nd bus
cycle
3rd bus
cycle
4th bus
5th bus
cycle
6th bus
cycle
nth bus
cycle
Command
cycle
cycle
Write enable
06h
(WREN)
Write disable
04h
(WRDI)
Status register read
05h
(RDSR)
Status register write
01h
DATA
A15-A8
A15-A8
(WRSR)
Read
03h
A7-A0
A7-A0
(READ)
Write
*1
*1
*1
*1
02h
PD
PD
PD
PD
(WRITE)
Explanatory notes for Table 1
The “h” following each code indicates that the number given is in hexadecimal notation.
*1: “PD” stands for page program data. Any amount of data from 1 to 128 bytes is input.
No.NA1679-4/13
LE25CB5122M
Figure 2 Serial Input Timing
(SPI Mode 0)
t
CPH
CS
t
t
t
t
t
t
CLH
CLS CSS
CLLO
CLHI
CSH
SCK
SI
t
t
DS
DH
DATA VALID
High Impedance
High Impedance
SO
(SPI Mode 3)
t
CPH
CS
SCK
SI
t
t
t
t
t
t
CLH
CLS
CSS
CLLO CLHI
CSH
t
t
DH
DS
DATA VALID
High Impedance
High Impedance
SO
No.NA1679-5/13
LE25CB5122M
Figure 3 Serial Output Timing
(SPI Mode 0)
CS
SCK
t
t
t
CHZ
CLZ
HO
DATA VALID
SO
SI
t
V
(SPI Mode 3)
CS
SCK
SO
SI
t
t
t
CLZ
HO
CHZ
DATA VALID
t
V
No.NA1679-6/13
LE25CB5122M
Description of Commands and Their Operations
“Table 1 Command Settings” provides a list and overview of the commands. A detailed description of the functions and
operations corresponding to each command is presented below.
1. Read (READ)
Consisting of the first through third bus cycles, the read command inputs the 16-bit addresses following (03h), and the
data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling edge of third
bus cycle bit0 as a reference. “Figure 4 READ” shows the timing waveforms.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest
address, the internal address returns to the lowest address (0000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
Figure 4 READ
CS
Mode3
Mode0
0
1
2
3
4
5
6
7
8
15 16
23 24 25 26 27 28 29 30 31
SCK
SI
8CLK
03h
Add.
Add.
(00000011)
(A15-A8)
(A7-A0)
High Impedance
7
6
5
4
3
2
1
0
7
SO
Data Out(N)
Data Out(N+1)
• In synchronization with the rising edges of 0 to 23 clock signals, the command is identified and the addresses are
taken in through SI.
• In synchronization with the falling edges of 23 clock signal or later, the data is output to SO.
No.NA1679-7/13
LE25CB5122M
2. Status Registers
The status registers read the operating and setting statuses inside the device from outside (status register read) and set
the protect information (status register write). There are 8 bits in total, and “Table 2 Status Registers” gives the
significance of each bit.
Table 2 Status Registers
Power-on time
Bit
Name
RDY
Logic
Function
Information
0
Bit0
0
1
0
1
0
1
0
1
0
0
0
0
1
Ready
Busy (in write operation)
Write disabled
Bit1
Bit2
Bit3
WEN
BP0
BP1
0
Write enabled
Nonvolatile
information
Block protect information
See status register description on BP0 and BP1
Nonvolatile
information
Bit4
Bit5
Bit6
Bit7
×
Reserved bit
Reserved bit
0
0
0
×
×
Reserved bit
SRWP
Status register write enabled
Status register write disabled
Nonvolatile
information
2-1. Status Register Read (RDSR)
The contents of the status registers can be read using the status register read command. This command can be executed
even during write operation.
“Figure 5 Status Register READ” shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit7) is the first
to be output, and each time one clock is input, all the other bits up to RDY (bit0) are output in sequence, synchronized
to the falling clock edge. If the clock input is continued after RDY (bit0) has been output, the data is output by returning
to the bit (SRWP) that was first output, after which the output is repeated as long as the clock input is continued. The
data can be read by the status register read command at any time.
Figure 5 Status Register Read
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode3
Mode0
SCK
SI
8CLK
05h
(00000101)
Hight Impedance
7
6 5 4 3 2 1 0 7
SO
Status Register Out
No.NA1679-8/13
LE25CB5122M
2-2. Status Register Write (WRSR)
The information in status registers BP0, BP1, and SRWP can be rewritten using the status register write command.
RDY, WEN, bit4, bit5, and bit6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, and
SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at
power-down.
“Figure 6 Status Register Write” shows the timing waveforms of status register write, and Figure 11 shows a status
register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the
internal write operation at the rising CS edge after the data has been input following (01h). By the operation of this
command, the information in bits BP0, BP1, and SRWP can be rewritten. Since bits RDY (bit0), WEN (bit1), bit4, bit5,
and bit6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value
when rewriting the status register. Status register write ends can be detected by RDY of status register read. Information
in the status register can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin
must be set high and the status register WEN must be set to “1”.
Figure 6 Status Register Write
Self-timed
Write Cycle
t
WC
CS
WP
SCK
SI
t
t
WPS
WPH
0
1
2
3
4
5
6
7
8
15
Mode3
Mode0
8CLK
01h
DATA
(00000001)
Hight Impedance
SO
2-3. Contents of Each Status Register
RDY (bit0)
Ready/Busy detection
The RDY register is for detecting the write end. When it is “1”, the device is in a busy state, and when it is “0”, it means
that the write operation is completed.
WEN (bit1)
Write enable
The WEN register is for detecting whether the device can perform write operations. If it is set to “0”, the device will not
perform the write operation even if the write command is input. If it is set to “1”, the device can perform write operation
in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to “1”, and by inputting the write disable command (04h), it can be set to “0”. In the following
states, WEN is automatically set to “0” in order to protect against unintentional writing.
• At power-on
• Upon completion of write
• Upon completion of status register write
∗ If a write operation has not been performed inside the device because, for instance, the command input for any of the
write operations has failed or a write operation has been performed for a protected address, WEN will retain the status
established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
No.NA1679-9/13
LE25CB5122M
BP0, BP1 (bits2, 3)
Block Protect Settings
Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be
set depending on these bits. For the setting conditions, refer to “Table 3 Protect Level Setting Conditions.”
Table 3 Protect Level Setting Conditions
Status Register Bits
Protection Block (Level)
Protected Area
BP1
0
BP0
0
0 (Whole area unprotected)
1 (Upper 1/4 area protected)
2 (Upper 1/2 area protected)
3 (Whole area protected)
None
0
1
C000h to FFFFh
8000h to FFFFh
0000h to FFFFh
1
0
1
1
SRWP (bit7)
Status Register Write Protect Settings
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is “1” and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are
not protected regardless of the SRWP state. The SRWP setting conditions are shown in “Table 4 SRWP Setting
Conditions.”
Table 4 SRWP Setting Conditions
WP Pin
SRWP
Mode
Status Register
Unprotected
Protected Area
Protected
Unprotected Area
Unprotected
1
0
1
0
0
1
Software protected
(SPM)
Hardware protected
(HPM)
0
1
Protected
Protected
Unprotected
Bit4, bit5, and bit6 are reserved bits, and have no significance.
3. Write Enable (WREN)
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is
the same as for setting status register WEN to “1”, and the state is enabled by inputting the write enable command.
“Figure 7 Write Enable” shows the timing waveforms when the write enable operation is performed. The write enable
command consists only of the first bus cycle, and it is initiated by inputting (06h).
• Write (WRITE)
• Status register write (WRSR)
4. Write Disable (WRDI)
The write disable command sets status register WEN to “0” to prohibit unintentional writing. “Figure 8 Write Disable”
shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by
inputting (04h).
The write disable state (WEN “0”) is exited by setting WEN to “1” using the write enable command (06h).
Figure 7 Write Enable
Figure 8 Write Disable
CS
CS
Mode3
Mode0
Mode3
Mode0
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7
SCK
SI
SCK
SI
8CLK
06h
8CLK
04h
(00000110)
(00000100)
High Impedance
High Impedance
SO
SO
No.NA1679-10/13
LE25CB5122M
5. Write (WRITE)
The LE25CB5122M enables pages with up to 128bytes to be written. Any number of bytes from 1 to 128bytes can be
written within the same sector page (page addresses : A15 to A7). “Figure 9 Write” shows the write timing waveforms,
and Figure 12 shows a write flowchart. After the falling CS edge, the command (02H) is input followed by the 16-bit
addresses (Add). The write data is then loaded until the rising CS edge, and the internal addresses (A6 to A0) are
incremented (Add+1) every time the data is loaded in 1-byte increments. The data loading continues until the rising CS
edge. If the data loaded has exceeded 128bytes, the 128bytes loaded last are written. The write data must be loaded in
1-byte increments, and the write operation is not performed at the rising CS edge occurring at any other timing. The
write time is 5ms (max.) when 128bytes (1page) are written at one time.
Figure 9 Write
Self-timed
Write Cycle
t
WC
CS
Mode3
Mode0
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
47
1047
SCK
SI
8CLK
02h
Add.
(A15-A8)
Add.
(A7-A0)
PD
PD
(N+1)
PD
(N+2)
PD
(N+127)
(00000010)
(N)
High Impedance
SO
6. Hold Function
Using HOLD pin, the hold function suspends serial communication (it places it in the hold status). “Figure 10 HOLD”
shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of
SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must
not rise or fall. The hold function takes effect when the logic of CS is low, and the hold status is exited and serial
communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI
and SCK are “don’t care.”
Figure 10 HOLD
Active
HOLD
Active
CS
t
t
HS
HS
SCK
HOLD
SO
t
t
HH
HH
t
t
HLZ
HHZ
High Impedance
7. Hardware Data Protection
In order to protect against unintentional writing at power-on, the LE25CB5122M incorporates a power-on reset
function.
No.NA1679-11/13
LE25CB5122M
8. Software Data Protection
This product eliminates the possibility of unintentional operations by not recognizing commands under the following
conditions.
• When a write command is input and the rising CS edge timing is not in a bus cycle (8CLK units of SCK).
• When the write data is not in 1-byte increments.
• When the status register write command is input for 2bus cycles or more.
9. Power-on
In order to protect against unintentional writing, CS must be kept at V
at power-on. After power-on, the supply
DD
voltage has stabilized at 2.7V or higher, wait for 10μs (t _READ) before inputting the command to start a read
PU
operation. Similarly, wait for 10ms (t _WRITE) after the supply voltage has stabilized at 2.7V or higher before
PU
inputting the command to start a write operation.
10. Decoupling Capacitor
A0.1μF ceramic capacitor must be provided to each device and connected between V
that the device will operate stably.
and V in order to ensure
SS
DD
Figure 11 Status Register Write Flowchart
Figure 12 Write Flowchart
Status register write
Write
Start
Start
Set write enable
command
Set write enable
command
06h
06h
02h
Address 1
Address 2
Data 0
01h
Set status register
write command
Set write command
Data
Program start on
rising edge of CS
Set status register
read command
Data 1
05h
Data n
NO
Bit 0= “0” ?
YES
Write start on rising
edge of CS
Set status register
read command
End of status
register write
05h
*Automatically placed in write
disabled state at the end of the
status register write.
NO
Bit 0= “0” ?
YES
*Automatically placed
in write disabled state
at the end of the write.
End of write
No.NA1679-12/13
LE25CB5122M
Application Note
1) Precautions at Power-on
In order to protect against unintentional writing, the LE25CB5122M incorporates a power-on rest circuit. The
following conditions must be met in order to ensure that the power-on reset circuit will operate stably. No guarantees
are given for data in the event of an instantaneous power failure occurring during the write operation.
V
= 2.7 to 3.6V
DD
Symbol
Item
Unit
min
typ
max
t
Power rise time
100
0.2
ms
ms
V
RISE
t
Power off time
10
OFF
Vbot
Power bottom voltage
t
RISE
V
DD
t
OFF
Vbot
0V
Note:
1). The CS pin must be set high.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of January, 2011. Specifications and information herein are subject to
change without notice.
No.NA1679-13/13
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STMICROELECTR
LE25CZ-APLE
2.5V FIXED POSITIVE LDO REGULATOR, 0.5V DROPOUT, BCY3, ROHS COMPLIANT, TO-92, 3 PIN
STMICROELECTR
LE25CZ-TRLE
2.5V FIXED POSITIVE LDO REGULATOR, 0.5V DROPOUT, BCY3, ROHS COMPLIANT, TO-92, 3 PIN
STMICROELECTR
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