LE25FV051T [SANYO]
512k (64k word x 8bits) Serial flash EEPROM; 512K （ 64K字X 8位）串行闪存EEPROM
| 型号： | LE25FV051T |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 512k (64k word x 8bits) Serial flash EEPROM |
| 文件： | 总11页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
memory contents within the addressed sector are erased
and other sectors are not inadvertently erased. The erase
operation begins with the rising edge of the pulse and
terminates automatically by using an internal timer.
Termination of this mode is found out by using Status
Register Read.
Command Definition
Table 2 contains a command list and a brief summary
of the commands. The following is a detailed description
of the options initiated by each command.
CS
Read
Fig.5 shows the timing waveform of read operation.
The read operation is initiated by READ command. After
writing OPcode of “FFH” and following 24bit address and
16 dummy bits, SO is transformed into Low-impedance
state, and the specified addresses’ data are read out
synchronously with SCK clock. While the SCK clock is
continuously on, the device counts up the next address
automatically and reads the data in order. When the
address reaches its maximum, while the read operation
still be continuing, the address is reset to the lowest one,
and the device continues reading data from the beginning.
Byte_Program
Fig.8 shows the timing waveform of Byte_Program.
Byte_Program command consists of 6 bus cycles from 1st
bus cycle to 6th bus cycle, and stages the device for Byte
programmable. To execute the Byte_Program operation,
program address, program data and Dummy bits must be
written to the command register after writing the OPcode
of (10H). The program operation begins with the rising
edge of the
pulse and terminates automatically by
CS
using an internal timer. Termination of this mode is found
out by using Status Register Read.
When
is set High so as to deselect the device,
CS
the read operation terminates with the output in High-
impedance state. Do not execute read operation while the
device is in Byte_Program or Sector_Erase Cycle to
prevent inadvertent writes.
Reset
Fig.9 shows the timing waveform of Reset operation.
Reset operation is effective while the device is already in
Program or Erase mode. But the data of specified
address are not guaranteed. The Reset Command can be
provided as a means to safely abort the Erase or Program
Command sequences. Following 4th bus cycles (erase or
program) with a write of (FFH) in 5th bus cycle will safely
abort the operation. Memory contents will not be altered.
Status_Register Read
Fig.6 shows the timing waveform of Status_Register
Read.
Status_Register can be read while the device is in
Program or Erase mode. As is shown in the table below,
the LSB (Least Significant Bit) of Status_Register is set to
with other bits intact. By setting
to LOW and
CS
BSY
writing “9FH” in command register, the contents of the
Status_Register come out from MSB. The LSB of the
Status_Register stands for if the device is busy or not.
Therefore,”0” stands for busy and “1” for not in Program
Hardware Write Protection
Setting
to LOW prevents inadvertent writes by
WP
inhibiting write operation. As
is connected internally
WP
to the Vcc, don’t connect externally to any nodes when
this function is not necessary. To prevent inadvertent
writes during system power-up, LE25FV051T has power-
on-reset circuit.
or Erase mode. When
goes High, Status Register
CS
reading
terminates with the output pin in High-
impedance state.
7(MSB)
X
6
5
4
3
2
1
0(LSB)
To perform power up more safely, the usage of
X
X
X
X
X
X
BSY
is recommended as follows. By holding
RESET
RESET
LOW during system power up and setting to High after
Vcc reaches operation voltage, inadvertent writes can be
prevented (see Fig.10). Don’t use this function except
Sector_Erase
during power up. As
is connected to Vcc
RESET
Fig.7 shows the timing waveform of Sector_Erase.
Sector_Erase command consists of 6 bus cycles from 1st
bus cycle to 6th bus cycle. This command stages the
device for electrical erasing of all bytes within a sector. A
sector contains 256 bytes. This sector erasability
enhances the flexibility and usefulness of the
internally, don’t connect externally to any nodes when this
function is not necessary.
Decoupling Capacitors
Ceramic capacitors (0.1 µF) must be added between
V
CC and VSS to each device to assure stable flash memory
LE25FV051T
, since most applications only need to
operation.
change a small number of bytes or sectors, not the
entire chip. To execute the Sector_Erase operation, erase
address, 2nd OPcode (D0H) and Dummy bits must be
written to the command register after writing 1st OPcode
of (20H). This two-step sequence ensures that only
SANYO Electric Co., Ltd.
3/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Absolute Maximum Stress Ratings
Storage Temperature........................................................-55 °C ~ 150 °C
Supply Voltage..................................................................-0.5 V ~ 4.6 V
D.C. Voltage on Any Pin to Grand Potential .....................-0.5 V ~ Vcc + 0.5 V
Permanent device damage may occur if ABSOLTE MAXIMUM RATINGS are exceeded.
Operating Range
Ambient Temperature .......................................................0 °C ~ 70 °C
Vcc....................................................................................3.0 V ~ 3.6 V
DC Operating Characteristics
Symbol
Parameter
Limit
unit
mA
mA
mA
µA
Test Condition
Min.
Max.
10
ICCR
Power Supply Current
(Read)
= VIL
SO,
open
WP
CS
SI = VIL / VIH, f = 10MHz, VCC = VCC max.
VCC = VCC max.
ICCW
ISB1
ISB2
Power Supply Current
(Write)
45
3
Standby Vcc Current
(TTL input)
= VIH
SO,
, RESET open
WP
CS
VCC = VCC max.
Standby Vcc Current
(CMOS input)
20
= VCC–0.3V SO,
, RESET open
WP
CS
VCC = VCC max.
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
10
10
µA
µA
V
VIN = VSS ~ VCC, VCC = VCC max.
VIN = VSS ~ VCC, VCC = VCC max.
VCC = VCC max.
ILO
VIL
VIH
VOL
VOH
–0.3
2.4
0.4
Vcc+0.3
0.2
V
VCC = VCC min.
V
IOL = 100 µA, VCC = VCC min.
IOH = –100 µA, VCC = VCC min.
Vcc-0.2
V
Power-up Timing
Symbol
tPU_READ
tPU_WRITE
tPU_RST
Parameter
Minimum
Units
ms
10
10
1
Power-up to Read Operation(without using RESET )
Power-up to Write Operation(without using RESET )
From RESET goes High to Command Entry
ms
µs
Capacitance (Ta = 25 °C, f = 1 MHz)
Symbol
Description
DQ Pin Capacitance
Input Capacitance
Maximum
Unit
pF
Test Condition
VDQ = 0V
CDQ
CIN
12
6
pF
VIN = 0V
Note: These parameters are periodically sampled and are not 100% tested.
SANYO Electric Co., Ltd.
4/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
AC Characteristics
Symbol
Parameter
Limit
unit
Min.
Max.
10
fCLK
tCSS
tCSH
tCPH
tCHZ
tDS
Clock Frequency
MHz
ns
CS setup time
CS hold time
400
400
250
ns
CS standby pulse width
CS to Hi-Z output
ns
250
ns
Data Setup time
30
30
45
45
0
ns
tDH
Data hold time
ns
tCLH
tCLL
tCLZ
tV
SCK High pulse width
SCK Low pulse width
SCK to Lo-Z output
SCK to output valid
Output data hold time
Sector Erase Cycle Time
Byte Program Cycle time
Write Reset Recovery Time
ns
ns
ns
40
ns
tHO
0
ns
tSE
4
35
4
ms
µs
µs
tBP
tRST
AC Test Conditions
Input Pulse Level.................................................0 V ~ 3.0 V
Input Rise/Fall Time..............................................5 ns
Input/Output Timing Level ...................................1.5V
Input Load Levels..................................................30 pF
SANYO Electric Co., Ltd.
5/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Timing waveforms
Figure 3: Serial Input Timing Diagram
( SPI mode 0 )
tCPH
CS
tcss
tCSH
SCK
tDS
tDH
DATA VALID
SI
High Impedance
High Impedance
SO
SPI mode 3 )
(
tCPH
CS
tcss
tCSH
SCK
tDS tDH
VALID
SI
High Impedance
High Impedance
SO
SANYO Electric Co., Ltd.
6/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Figure 4: Serial Output Timing Diagram
( SPI mode 0 )
CS
tCLH tCLL
tCSH
SCK
tHO
tCHZ
tcLZ
DATA VALID
SO
SI
tV
( SPI mode 3 )
CS
tCLL tCLH
tCSH
SCK
SO
tHO
tCHZ
tcLZ
DATA VALID
tV
SI
SANYO Electric Co., Ltd.
7/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
(The following is described in SPI mode 0)
Figure 5: Read Cycle Timing Diagram
CS
0
1
2
3
4
5
6
7
8
15 16 23 24 31 32 39 40 47 48 55 56 63 64
71
SCK
SI
FFH
Add. Add. Add.
X
X
N
N+1
N+2
High Impedance
DATA DATA DATA
MSB MSB MSB
SO
Figure 6: Status Register Read Timing Diagram
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
23 24 31
SCK
SI
9FH
High Impedance
DATA
DATA DATA
SO
MSB
MSB
MSB
SANYO Electric Co., Ltd.
8/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Figure 7: Sector_Erase Timing Diagram
Self-timed Sector
Erase Cycle
t SE
CS
0
1
2
3
4
5
6
7
8
15 16 23 24 31 32 39 40 47
SCK
SI
20H
Add. Add.
X
D0H
X
High Impedance
SO
Figure 8: Byte_Program Timing Diagram
Self-timed Byte
Program Cycle
t BP
CS
0
1
2
3
4
5
6
7
8
15 16 23 24 31 32 39 40 47
SCK
SI
10H
Add. Add. Add.
PD
X
High Impedance
SO
SANYO Electric Co., Ltd.
9/10
LE25FV051T
3.3V-only 512k-Bit Serial Flash EEPROM
Preliminary Specifications
Figure 9: Reset Timing Diagram
Reset Command is effective when the device is only in Erase or Program sequence (in tBP or tSE period).
t RST
CS
0
1 2 3 4 5 6 7
SCK
SI
FFH
High Impedance
SO
Figure 10: Command Entry Recover Timing from RESET goes High
Vcc
t PU_RST
RESET
SANYO Electric Co., Ltd.
10/10
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