概述
规格参数
数据手册LM7001 概述
Direct PLL Frequency Synthesizers for Electronic Tuning 直接的PLL频率合成器的电子调谐 锁相环或频率合成电路
LM7001 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | DIP | 包装说明： | DIP, DIP16,.3 |
| 针数： | 16 | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.87 |
| Is Samacsys： | N | 模拟集成电路 - 其他类型： | PLL FREQUENCY SYNTHESIZER |
| JESD-30 代码： | R-PDIP-T16 | JESD-609代码： | e0 |
| 长度： | 19.2 mm | 功能数量： | 1 |
| 端子数量： | 16 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | DIP | 封装等效代码： | DIP16,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 3.65 mm | 子类别： | PLL or Frequency Synthesis Circuits |
| 最大供电电压 (Vsup)： | 6.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | NO |
| 技术： | NMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | THROUGH-HOLE |
| 端子节距： | 2.54 mm | 端子位置： | DUAL |
| 宽度： | 7.62 mm | Base Number Matches： | 1 |
LM7001 数据手册
通过下载LM7001数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Ordering number : EN5262
NMOS LSI
LM7001J, 7001JM
Direct PLL Frequency Synthesizers
for Electronic Tuning
Features
Package Dimensions
unit: mm
• The LM7001J and LM7001JM are PLL frequency
synthesizer LSIs for tuners, making it possible to make
up high-performance AM/FM tuners easily.
• These LSIs are software compatible with the LM7000,
but do not include an IF calculation circuit.
• The FM VCO circuit includes a high-speed
programmable divider that can divide directly.
• Seven reference frequencies: 1, 5, 9, 10, 25, 50, and
100 kHz
3006B-DIP16
[LM7001J]
• Band-switching outputs (3 bits)
• Controller clock output (400 kHz)
• Clock time base output (8 Hz)
• Serial input circuit for data input (using the CE, CL, and
DATA pins)
SANYO: DIP16
unit: mm
3036B-MFP20
[LM7001JM]
SANYO: MFP20
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D3095HA (OT) No. 5262-1/8
LM7001J, 7001JM
Pin Assignments
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
max
Conditions
Ratings
Unit
V
V
V
1, V 2
DD
–0.3 to +7.0
–0.3 to +7.0
DD
DD
V
V
1 max CE, CL, DATA
2 max Input pins other than V
1 max SYC
V
IN
Maximum input voltage
1
–0.3 to V
+ 0.3
V
IN
IN
DD
V
V
V
–0.3 to +7.0
–0.3 to +13
V
OUT
OUT
OUT
Maximum output voltage
2 max BO1 to BO3
V
3 max Output pins other than V
max BO1 to BO3
1 and V
2
–0.3 to V + 0.3
DD
V
OUT
OUT
Maximum output current
I
0 to 3.0
300
mA
mW
mW
°C
°C
OUT
Ta = 85°C: LM7001J (DIP16)
Ta = 85°C: LM7001JM (MFP20)
Allowable power dissipation
Pd max
180
Operating temperature
Storage temperature
Topr
Tstg
–40 to +85
–55 to +125
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V
SS
Parameter
Symbol
Conditions
1, PLL circuit operating
Ratings
4.5 to 6.5
3.5 to 6.5
2.2 to 6.5
0 to 0.7
Unit
V
V
V
1
2
V
V
DD
DD
DD
Supply voltage
2, crystal oscillator time base
V
DD
Input high-level voltage
Input low-level voltage
V
CE, CL, DATA
CE, CL, DATA
SYC
V
IH
V
V
IL
V
V
1
2
0 to 6.5
V
OUT
OUT
Output voltage
Output current
BO1 to BO3
BO1 to BO3, V
0 to 13
V
I
= 4.5 to 6.5 V
DD
0 to 3.0
mA
MHz
MHz
MHz
MHz
MHz
Vrms
Vrms
Vrms
OUT
f
1
2
3
4
XIN, sine wave, capacitor coupled
1.0 to 7.2 typ to 8.0
45 to 130
5 to 30
IN
IN
IN
IN
*1 *3
f
f
f
FMIN, sine wave, capacitor coupled , s = 1
Input frequency
*2 *3
FMIN, sine wave, capacitor coupled , s = 1
*3
AMIN, sine wave, capacitor coupled, s = 0
0.5 to 10
Crystal element for guaranteed oscillation
Input amplitude
Xtal
XIN to XOUT, CI ≤ 30 Ω
5.0 to 7.2 typ to 8.0
0.5 to 1.5
0.1 to 1.5
0.1 to 1.5
V
1
XIN, sine wave, capacitor coupled
FMIN, sine wave, capacitor coupled
AMIN, sine wave, capacitor coupled
IN
IN
IN
V
2
3
V
Note: 1. f = 25, 50, or 100 kHz
ref
2. f = Reference frequencies other than those for *1.
ref
3. “s” refers to the control bit in the serial data.
No. 5262-2/8
LM7001J, 7001JM
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Symbol
Conditions
min
typ
max
Unit
MΩ
kΩ
kΩ
µA
µA
V
R
f1
XIN
1.0
500
500
Built-in feedback resistance
R
f2
FMIN
AMIN
R
f3
Input high-level current
Input low-level current
I
CE, CL, DATA: V = 6.5 V
IN
5.0
5.0
3.5
0.3
1.0
0.3
5.0
3.0
IH
I
CE, CL, DATA: V = 0 V
IN
IL
V
V
V
V
1
2
3
4
1
FMIN, AMIN: I
= 0.5 mA
OL
OL
OL
OL
OUT
*1
SYC: I
= 0.1 mA,
0.02
V
OUT
Output low-level voltage
BO1 to BO3: I
P 1, P 2: I = 0.1 mA
OUT
= 2.0 mA
V
OUT
V
D
D
I
I
SYC: V
= 6.5 V
µA
µA
V
OFF
OUT
Output off leakage current
Output high-level voltage
2
BO1 to BO3: V
= 13 V
OUT
OFF
V
P 1, P 2: I
= –0.1 mA
0.5 V
DD
OH
D
D
OUT
High-level 3-state
off leakage current
I
P 1, P 2: V
= V
0.01
0.01
10.0
10.0
nA
nA
OFFH
D
D
OUT
DD
Low-level 3-state
off leakage current
I
P 1, P 2: V
= 0 V
OFFL
D
D
OUT
*2
I
1
2
V
V
1 + V 2:
25
2.0
2
40
3.5
3
mA
mA
pF
DD
DD
DD
DD
DD
Current drain
I
2: PLL block stopped
Input capacitance
C
FMIN
1
IN
Note: 1. V
= 3.5 to 6.5 V
DD
2. With a 7.2 MHz crystal connected between XIN and XOUT, f 2 = 130 MHz, V 2 = 100 mVrms, other input pins at V , output pins open.
IN
IN
SS
Oscillator Circuit Example
Kinseki, Ltd.
HC43/U: 2114-84521 (1): CL = 10 pF, C1 = 15 (10 to 22) pF, C2 = 15 pF
HC43/U: 2114-84521 (2): CL = 16 pF, C1 = 22 (15 to 33) pF, C2 = 33 pF
Nihon Denpa Kogyou, Ltd.
NR-18: LM-X-0701: CL = 10 pF, C1 = 15 pF, C2 = 15 pF
Since the circuit constants in the crystal oscillator circuit depend on the crystal element used and the printed circuit board
pattern, we recommend consulting with the manufacturer of the crystal element concerning this circuit.
No. 5262-3/8
LM7001J, 7001JM
Equivalent Circuit Block Diagram
Pin Functions
Symbol
Description
SYC
Controller clock (400 kHz)
Crystal oscillator (7.2 MHz)
Local oscillator signal input
Data input
XIN, XOUT
FMIN, AMIN
CE, CL, DATA
BO1 to BO3
Band data output. BO1 can be used as a time base output (8 Hz).
Power supply (Apply power to both V 1 and V 2 when the PLL circuit is operating. V 2 is the crystal oscillator and time base
DD
DD
DD
V
1, V 2, V
SS
DD
DD
power supply. Internal data cannot be maintained on V 2 only.)
DD
P 1, P 2
Charge pump output
D
D
No. 5262-4/8
LM7001J, 7001JM
Data Input Timing
= 2.2 to 6.5 V, V = 0 to 0.7 V, Xtal = 5.00 to 7.20 (typ) to 8.00 MHz
V
IH
IL
Data acquisition: On the CL rising edge
Note: Data transfers must be started only after the crystal oscillator is operating normally, i.e., after a proper input signal
has been supplied to XIN.
Xtal: for frequencies
other than 7.2 MHz
Parameter
Symbol
Xtal: 7.20 MHz
At least 1.5 µs
At least 1.5 µs
At least 1.5 µs
At least 1.5 µs
At least 1.5 µs
At least 1.5 µs
Example: XIN = 2.048 MHz
At least 5.27 µs
1 ×8
Enable setup time
Enable hold time
Data setup time
Data hold time
t
At least [
At least [
At least [
At least [
At least [
At least [
] × 1.35
ES
f Xtal
1 ×8
f Xtal
1 ×8
f Xtal
1 ×8
f Xtal
1 ×8
f Xtal
1 ×8
f Xtal
t
] × 1.35
] × 1.35
] × 1.35
] × 1.35
] × 1.35
At least 5.27 µs
EH
t
At least 5.27 µs
SU
t
At least 5.27 µs
HD
Clock low-level time
Clock high-level time
t
At least 5.27 µs
LO
t
At least 5.27 µs
HI
Rise time
Fall time
t
Up to 1 µs
Up to 1 µs
Up to 1 µs
Up to 1 µs
Up to 1 µs
Up to 1 µs
R
t
F
No. 5262-5/8
LM7001J, 7001JM
Data Input
(1) D0 (LSB) to D13 (MSB): Divisor data
FMIN uses D0 to D13 and AMIN uses D4 to D13.
Sample calculation
① FM 100 kHz steps (f = 100 kHz)
ref
FM VCO = 100.7 MHz (FM RF = 90.0 MHz, IF = 10.7 MHz)
Divisor =
100.7 MHz (FM VCO) ÷ 100 kHz (f ) = 1007 → 3EF
(HEX)
ref
② AM 10 kHz steps (f = 10 kHz)
ref
AM VCO = 1450 kHz (AM RF = 1000 kHz, IF = 450 kHz)
Divisor =
1450 kHz (AM VCO) ÷ 10 kHz (f ) = 145 → 91
ref (HEX)
(2) T0 and T1 are LSI test bits and both should be set to 0.
(3) B0 to B2, TB: Band data
Time base data
Note: *: Determined by R0 to R3. See item (4) on next page.
Input
Output
B0
0
B1
0
0
1
1
0
0
1
1
0
1
0
1
0
B2
0
1
0
1
0
1
0
1
0
0
1
1
0
TB
0
0
0
0
0
0
0
0
1
1
1
1
1
BO1
*
BO2
*
BO3
*
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
TB
TB
TB
TB
TB
*
*
✕
✕
✕
1
1
0
0
1
1
1
0
0
✕: Don’t care
TB: 8 Hz
No. 5262-6/8
LM7001J, 7001JM
(4) R0 to R2: Reference frequency data
R0
0
R1
0
R2
0
f
[kHz]
BO1
1
BO2
BO3
0
ref
100
50
25
5
1
1
1
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
10
9
1
1
1
0
1
1
1
1
1
0
1
0
1
1
1
1
5
0
1
Note: The values listed for BO1, BO2, and BO3 are for the case when the B0 to B2 data is set to all zeros.
(5) S: Divider selection data
1: FMIN, 0: AMIN
Notes on PLL IC Usage
1. PLL IC printed circuit board patterns
① Power supply pins
A capacitor must be inserted between the V and V power supply pins for noise exclusion. This capacitor
DD
SS
must be located as close as possible to these pins.
② FMIN and AMIN pins
The coupling capacitors must be located as close as possible to these pins.
③ PD pins, low-pass filter
Since those are high-impedance pins, they are susceptible to noise. Therefore, the pattern should be kept as short
as possible and the area around this circuit should be covered by the ground pattern.
2. Initial states of the output ports (BO1 to BO3)
The initial states of the output ports after power is applied are undefined until data has been transferred.
In particular, it is possible for the BO1 and BO3 pins to output the internal clock, so data must be transferred as soon
as possible.
However, note that the LSI cannot accept data until the crystal oscillator is operating normally.
No. 5262-7/8
LM7001J, 7001JM
3. VCO
The VCO circuit is designed so that it does not stop oscillating even if the control voltage (Vtune) becomes 0 V.
(This is because the PLL circuit could become deadlocked if the VCO stopped.)
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 5262-8/8
LM7001 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LM7001J | SANYO | Direct PLL Frequency Synthesizers for Electronic Tuning | 获取价格 |
|
| LM7001JM | SANYO | Direct PLL Frequency Synthesizers for Electronic Tuning | 获取价格 |
|
| LM7001M | ETC | Direct PLL Frequency Synthesizers(256.46 k) | 获取价格 |
|
| LM7005 | SANYO | Electronic AV Tuner-Use Electronic Tuning PLL Frequency Synthesizer | 获取价格 |
|
| LM7006 | SANYO | Dual PLL Frequency Synthesizer Circuit | 获取价格 |
|
| LM7006H | SANYO | Dual PLL Frequency Synthesizer Circuit | 获取价格 |
|
| LM7007HM | SANYO | Dual-PLL Frequency Synthesizers | 获取价格 |
|
| LM7007M | SANYO | Dual-PLL Frequency Synthesizers | 获取价格 |
|
| LM7008 | SANYO | Dual-PLL Frequency Synthesizers | 获取价格 |
|
| LM7008HM | SANYO | Dual-PLL Frequency Synthesizers | 获取价格 |
|
LM7001 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
