LV4147W [SANYO]
Bi-CMOS LSI For LCD Panel Drive Single Chip IC; BI -CMOS LSI对于液晶面板驱动单芯片IC型号: | LV4147W |
厂家: | SANYO SEMICON DEVICE |
描述: | Bi-CMOS LSI For LCD Panel Drive Single Chip IC |
文件: | 总26页 (文件大小:430K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ordering number : EN8928A
Bi-CMOS LSI
For LCD Panel Drive
LV4147W
Single Chip IC
Overview
The LV4147W is single chip IC for LCD panel drive.
Functions
• Analog block RGB Decoder/Driver
• Digital block Timing Generator
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Maximum supply voltage
V
V
1 max
Analog LOW type
6
12
CC
2 max
max
Analog HIGH type
V
CC
V
Digital type
4.5
V
DD
Allowable power dissipation
Operating temperature
Storage temperature
Input pin voltage
Pd max
Ta ≤ 75°C * Mounted on a board.
350
mW
°C
°C
V
Topr
Tstg
-15 to +75
-40 to +125
V
V
V
A
D
D
Analog input pin
-0.3 to V 1
CC
IN
IN
IN
Digital input pin (Except pin 10, 11 and 12)
Digital input pin (10, 11, 12pin)
-0.3 to V +0.3
DD
V
-0.3 to +4.5
V
* : Mounted on a board : 30×30×1.6mm3, glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
50907 TI PC B8-6537 No.8928-1/26
LV4147W
Operating Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Recommended supply voltage
V
1
Analog LOW type
3.0
7.0
CC
CC
V
2
Analog HIGH type
Digital type
V
V
3.0
V
DD
Operating voltage range
V
1op
2op
op
Analog LOW type
Analog HIGH type
Digital type
2.7 to 3.6
6 to 9.5
2.7 to 3.6
V
CC
CC
V
V
V
V
DD
Input Signal Voltage
Parameter
Symbol
Yin
Conditions
Ratings
Unit
Vp-p
Vp-p
Vp-p
Recommended Y input signal
Sync chip - white
0.5
0.3
input signal
Color
B-Yin
R-Yin
75% Color bar signal
75% Color bar signal
voltage
Difference
0.24
input signal
Electrical DC Characteristics
Unless otherwise specified, settings 1 and 2 must be made.
Unless otherwise specified, V 1 = 3.0V, V 2 = V COM = 7.0V, GND1 = GND2 = GNDCOM = 0,
CC CC CC
V
1 = V 2 = 3.0V, V 1 = V 2 = 0, Ta = 25°C
DD DD SS SS
[Current Characteristics]
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Current dissipation V 1,
CC
analog LOW
I
I
I
1
2
1
Enter SIG3 to (A), (D) and (E).
TRAP OFF
TRAP ON
18
20
2
26
33
35
6
mA
mA
mA
CC
CC
DD
Measure the current value of I 1.
CC
28
4
Current dissipation V 2,
CC
analog HIGH
Enter SIG3 to (A)
Measure the current value of I 2.
CC
Current dissipation V , logic
DD
Enter SIG3 to (A)
110,000
and
130,000
modes
7
10
12
13
mA
mA
Measure the current value of I 11 and
DD
I
21.
DD
I
1, I 2, I 3 = I 11+I 21
DD DD DD
DD
DD
I
2
180,000
mode
8.5
15.5
DD
[Digital block input/output characteristics]
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
L-level input voltage
H-level input voltage
H-level output voltage
L-level output voltage
Output transition time
V
Digital block input pin (Note 1)
Digital block input pin (Note 1)
0.3V
V
V
IL
DD
V
0.7V
DD
IH
V
1
I
I
= -1.2mA (Note 2)
= 1.2mA (Note 2)
V -0.2
DD
V
OH
OH
OL
V
t
1
0.3
30
30
10
V
OL
Load 50pF (see Fig. 3)
ns
ns
ns
TLH
t
THL
Cross point time difference
CHK duty
ΔT
Load 50pF
CKH1/CKH2 and CKV1/CKV2 and CKH3/CKH4
(See Fig. 4)
DTYHC
Load 50pF
47
50
53
%
Measure the duty of CKH1, CKH2, CKH3 and CKH4.
(Note 1) Digital block input pins : LOAD, DATA, SCLK
(Note 2) Digital block output pins : Pins 15 to 31, 33, 34
No.8928-2/26
LV4147W
Electrical AC Characteristics (1)
Unless otherwise specified, the setting 1 and 2 must be made.
Unless otherwise specified, V 1 = 3.0V, V 2 = V COM = 7.0V, GND1 = GND2 = GNDCOM = 0,
CC CC CC
V
1 = V 2 = 3.0V, V 1 = V 2 = 0, Ta = 25°C
DD SS SS
DD
Unless otherwise specified, measure the non-inverted output of TP40, TP43, and TP45.
[Y signal system]
Parameter
Symbol
Conditions
min
14
typ
16
max
18
unit
dB
Contrast characteristics, TYP
GCNTTP
Enter SIG3 to (A) and measure the ratio between the output
amplitude (white to black) and input amplitude of TP43.
Enter SIG3 to (A) and measure the ratio between the output
amplitude (white to black) and input amplitude of TP43.
Enter SIG3 to (A) and measure the ratio between the output
amplitude (white to black) and input amplitude of TP43.
Contrast characteristics, MIN
Max. video gain
GCNTMN
GV
-2
19
1
4.5
23
dB
dB
21
Y signal frequency
characteristics
FTRPN0
Assume that the output amplitude of
TP43 when SIG1 (0dB, 100kHz) is
entered to (A) is 0dB. Change the input
signal frequency to change and
TRAP OFF
6.0
MHz
FTRPNT
FTRPPL
TRAP ON
NTSC
PAL
3.0
3.5
11
determine the frequency at which the
output amplitude becomes -3dB.
Picture quality adjustment
variable amount 1
(TRAP OFF)
GSHP1X
GSHP1N
Assume that the output amplitude of TP43 when
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
output amplitude ratio of the input SIG6 (2.5MHz).
MAX
MIN
14
-3
dB
dB
dB
dB
0
2
180,000 mode
Picture quality adjustment
variable amount 2
(TRAP OFF)
GSHP2X
GSHP2N
Assume that the output amplitude of TP43 when
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
output amplitude ratio of the input SIG6 (1.8MHz).
MAX
MIN
11
8
14
-1
110,000 and 130,000 modes
Picture quality adjustment
variable amount 3
(TRAP ON)
GSHP3X
GSHP3N
Assume that the output amplitude of TP43 when
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
output amplitude ratio of the input SIG6 (1.8MHz).
MAX
MIN
11
-5
-2
110,000 and 130,000 modes
Picture quality adjustment
variable amount 4
(TRAP ON)
GSHP4X
GSHP4N
Assume that the output amplitude of TP43 when
SIG6 (100kHz) is entered in (A) is 0dB. Determine the
output amplitude ratio of the input SIG6 (2.0MHz).
MAX
MIN
6
9
-6
-3
400
450
180,000 mode
Y signal input/output delay
rate
TDYTRN
TDYTRP
Enter SIG8 to (A). Measure the delay
time from the input signal 2T pulse
peak to the peak of TP43 non-inverted
output.
TRAP ON
200
250
300
350
ns
ns
TRAP OFF
[Color difference signal system]
Ratings
typ
Parameter
Symbol
Conditions
Unit
dB
min
max
Color difference input color
adjustment
GEXCMX
Input SIG4 (V = 0mV) to (A) and SIG1 (0dB,
L
+3
+5
100kHz) to (D) and assume that the output
amplitude (100kHz) of TP40 when COL = 128 is
VCOCOL = 0 is VC2. Assume also that the output
amplitude of TP40 when SIG1 is -10dB and COL =
255 is VC1. Calculate as follows :
GEXCMN
VEXCBL
-20
1.0
-15
1.2
dB
GEXCMX = 20log (VC1 / VCO) +10
GEXCMN = 20log (VC2 / VC0)
Color difference balance
Input SIG4 (V = 0mV) to (A) and SIG1 (0dB,
L
0.8
100kHz) to (D) and (E). Assume that the output
amplitude (100kHz) of TP40 is VB and that
(100kHz) of TP45 is VR. Calculate as follows :
VEXCBL = VR / VB
Continued on next page.
No.8928-3/26
LV4147W
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
dB
min
max
Color difference input balance
adjustment R
GEXRMX
Input SIG4 (V = 0mV) to (A) and SIG1 (-6dB,
L
-5
-2
-2
100kHz) to (D) and (E). Assume that the output
amplitude (100kHz) of TP45 and that (100kHz) of
TP40 when TINT = 128 are VRO and VB0
respectively. The output amplitude of TP45 and
that of TP40 when TINT=255 are VR1 and VB1
respectively. Assume also that the output
amplitude of TP45 and that of TP40 when TINT = 0
are VR2 and VB2 respectively. Then, calculate as
follows :
GEXRMN
GEXBMX
+2
+2
+3
+3
dB
dB
Color difference input balance
adjustment B
GEXBMN
-5
dB
GEXRMX = 20log (VR1 / VR0)
GEXRMN = 20log (VR2 / VR0)
GEXBMX = 20log (VB1 / VB0)
GEXBMN = 20log (VB2 / VB0)
G-γ matrix characteristics
VEXGBN
VEXGBP
VEXGR
Input SIG4 (V = 0mV) to (A) and SIG1
L
NTSC
PAL
0.23
0.17
0.46
0.26
0.20
0.51
0.29
0.23
0.56
(0dB, 100kHz) to (D). Assume that the
output amplitude (100kHz) of TP40 is
VEXB and that of TP43 is VEXBG.
Calculate as follows ;
VEXGB = VEXBG / VEXB
Input SIG4 (V = 0mV) to (A) and SIG1 (0dB,
L
100kHz) to (E). Assume that the output amplitude
(100kHz) of TP45 is VEXR and that of TP43 is
VEXRG. Calculate as follows ;
VEXGR = VEXRG / VEXR
[RGB signal system]
Ratings
typ
Parameter
Symbol
VOUT
Conditions
Unit
V
min
3.3
max
RGB signal and PCD output
DC voltage
Enter SIG4 (V = 0mV) to (A) and adjust BRIGHT
L
3.5
3.7
of serial bus to set TP43 output to 3Vp-p. Then,
measure the DC voltage of TP38, TP40, and
TP43.
RGB signal and PCD output
DC voltage difference
ΔVOUT
Determine the maximum value of difference of
measured values of TP40, TP43, and TP45 of
VOUT as described in the above item.
0
120
mV
V
User brightness change rate
UBRTMX
Measure the change rate of the black level of
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and U-BRT is changed from 128 to
255.
2.0
3.0
UBRTMN
BRTMX
BRTMN
Measure the change rate of the white level of
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and U-BRT is changed from 128 to
0.
-3
2.5
-2.0
V
V
V
Brightness change rate
Measure the change rate of the black level of
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and BRT is changed from 128 to
255.
2.0
Measure the change rate of the white level of
TP40, TP43, and TP45 outputs when SIG2 is
entered to (A) and BRT is changed from 128 to 0.
Enter SIG2 to (A), and measure the TP38 output
amplitude when COM = 255.
-2.5
-2.0
1.5
Antipole output change rate
COMMX
COMMN
SBBRTR
4.6
1.3
Vp-p
Vp-p
V
Enter SIG2 to (A), and measure the TP38 output
amplitude when COM = 0.
Sub-brightness R change
rates
Enter SIG4 (V = 0mV) to (A) and measure the
L
1.7
difference between the black level of TP45 output
when R-BRT = 128 and the black level of output
when R-BRT = 0 and R-BRT = 255.
Continued on next page.
No.8928-4/26
LV4147W
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
V
min
1.3
max
Sub-brightness B change
rates
SBBRTB
Enter SIG4 (V = 0mV) to (A) and measure the
L
1.7
difference between the black level of TP40 output
when B-BRT = 128 and the black level of output
when B-BRT = 0 and 255.
Gain difference between RGB
signals
ΔGRGB
Determine the level difference of non-inverted
output amplitude (white to black) of TP40, TP43,
and TP45 when SIG3 is entered to (A).
Measure the non-inverted output (white to black) of
TP45 for the non-inverted output (white to black) of
TP43 when SIG3 is entered to (A) and when
R-CNT = 0 and R-CNT = 255.
-0.6
2.0
0
0.6
dB
dB
Sub-contrast R change rate
SBCNTR
Sub-contrast B change rate
SBCNTB
ΔGINV
ΔVBL
Input SIG3 to (A) and measure the difference of
the level for B-CNT = 0 and 255 from the TP40
non-inverted output (white-black) when B-CNT =
128.
2.0
dB
dB
RGB inverted/non-inverted
gain difference
Determine the difference of inverted output
amplitude for the non-inverted output amplitude
(white to black) of TP40, TP43, and TP45 when
SIG3 is entered to (A).
-0.5
0
0.5
Black level potential difference
between RGB signals
Determine the difference between highest and
lowest black levels for inverted and non-inverted
outputs of TP40, TP43, and TP45 when SIG3 is
entered to (A).
300
mV
Gamma gain
GγL
GγM
GγH
Enter SIG7 to (A) and set the amplitude (black to
white) of non-inverted output of TP43 to 3.5Vp-p
with CONT and set the level to 1.5V through
BRIGHT adjustment.Measure VG1, VG2, and
VG3 and calculated as follows :
23.0
12.0
18.0
26.0
15.0
22.0
29.0
18.0
26.0
dB
dB
dB
GγL = 20log (VG1/0.0357)
GγM = 20log (VG2/0.0357)
GγH = 20log (VG3/0.0357) (See Fig. 5)
Enter SIG7 to (A) and set the TP43 output (black to
black) to 3Vp-p through BRIGHT adjustment.
Read the γ gain change point at γ1 = 0, γ1 = 255 by
referring to the IRE level of input signal :
Vγ1MN for γ1 = 0
γ1 adjustment variable range
Vγ1MN
Vγ1MX
0
IRE
IRE
100
100
Vγ1MX for γ1 = 255
γ2 adjustment variable range
Vγ2MN
Vγ2MX
Enter SIG7 to (A) and set the TP43 output (black to
black) to 3Vp-p through BRIGHT adjustment.
Read the γ gain change point at γ2 = 0, γ2 = 255
by referring to the IRE level of input signal :
Vγ1MN for γ2 = 0
IRE
IRE
0
Vγ1MX for γ2 = 255
PCD transition time
tCOMH
tCOML
Enter SIG3 to (A) and set the output amplitude of
TP38 to 3Vp-p. Measure tCOMH for rise and
tCOML for fall. Load : 20000pF
1.5
1.5
3
3
μs
μs
RGB output whitelimiter level
VWLIMN
VWLIMX
Enter SIG2 to (A) and measure the amplitude of
the white side limiter level of inverted /
non-inverted TP38, 40, 43, and 45 output.
VWLIMX when WLIM = 15 and VWLIMN when
WLIM = 0.
4
Vp-p
Vp-p
2.2
RGB output black limiter
variable range
VBLIMX
VBLIMN
Enter SIG2 to (A) and measure the amplitude of
the black side limiter level of inverted/non-inverted
TP43 output. VBLIMX for BLIM = 255 and VBLIMN
for BLIM = 0
4.5
Vp-p
Vp-p
2
White limiter DC voltage
Black limiter DC voltage
VWLIM
VBLIM
Enter SIG4 (V = 0mV) to (A) and measure the DC
L
voltage of TP40, TP43, and TP45.
3.3
3.3
3.5
3.5
3.7
3.7
V
V
Input SIG4 (V = 350mV) to (A) and adjust BLIM to
L
set the output of TP43 and TP40 to 3Vp-p.
Measure the DC voltage of TP 40, TP43, and
TP45.
No.8928-5/26
LV4147W
[Filter characteristics]
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
-20
TRAP attenuation amount
ATRAPN
ATRAPP
Input SIG1 (0dB, 3.58MHz and
4.43MHz) in (A) and measure the TP43
output with a spectrum analyzer.
Assuming that the TP43 amplitude in
the TRAP ON mode is 0dB, determine
the attenuation in the COMP input
mode.
NTSC
PAL
-15
dB
dB
-15
-20
R-Y, B-Y LPF characteristics
DEMLPF
Input SIG4 (V = 150mV) in (A) and SIG1
L
1.2
1.6
1.9
MHz
(100kHz) in (B). In this case, assume that the
amplitude of 100kHz component of TP40, TP45
output is 0dB. Change the SIG1 frequency at
which the output amplitude of TP40, TP45
becomes -3dB.
[Sync separation, TG system]
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
2.0
max
Input sync signal width
sensitivity
WSSEP
Enter SIG4 (V = 0mV, VS = 143mV, WS variable)
L
μs
to (A) and confirm synchronization with the TP24
HD output. Narrow WS of SIG5 from 4.7μs and
determine WS at which synchronization between
the input and TP24HD output is lost.
Sync separation input
sensitivity
VSSEP
Enter SIG4 (V = 0mV, WS = 4.7μs, VS variable)
40
60
mV
L
to (A) and confirm synchronization with the TP24
HD output. Reduce VS of SIG4 from 143mV and
determine VS at which synchronization between
the input and TP24HD output is lost.
Sync separation output delay
rate
TDSYL
TDSYH
Enter SIG4 (V = 0mV, WS = 4.7μs, and VS =
300
4.7
500
5.0
700
5.3
ns
L
143mV) to (A) and measure the delay rate from
TP6RPD output. Assume that TDSYL is for a
period from fall of input HSYNC to fall of RPD
output and that TDSYH is for the period up to rise
of RPD output.
μs
Horizontal pull-in range
HPLLN
HPLLP
Enter SIG4 (V = 0 mV, WS = 4.7μs,
NTSC
PAL
500
500
Hz
Hz
L
and VS = 143mV, horizontal frequency
variable) to (A) and confirm
synchronization with TP24 HD output.
Change the horizontal frequency of
SIG5 and determine the frequency f at
H
which synchronization is established
from the condition in which input / output
synchronization is lost. Calculate as
follows : HPLLN = f -15734
H
HPLLP = f -15625
H
No.8928-6/26
LV4147W
[External input output characteristics]
Ratings
typ
Parameter
Symbol
Conditions
Unit
V
min
0.55
max
0.85
External RGB input threshold
value
VTEXTB
Enter SIG4 (V = 0mV) to (A) and SIG5
L
(V variable) to (C), increase the amplitude (V )
0.7
L
L
from 0V. Assume that the voltage at which TP40,
TP43, and TP45 outputs become the black level is
VTEXTB. Further increase the amplitude and
assume the voltage at which they become the
white level.
VTEXTW
1.62
1.8
1.95
V
Propagation delay time
TD1EXT
TD2EXT
Enter SIG4 (V = 0mV) to (A) and SIG5 (V = 3V)
50
70
90
130
150
ns
ns
L
L
between external RGB outputs
to (C) and measure the rise delay TD1EXT and fall
delay TD2EXT of TP40, TP43, and TP45 outputs.
(See Fig. 2)
100
External RGB output blanking
level
EXTBK
EXTWT
TEXMIN
Enter SIG4 (V = 0mV) to (A) and SIG5
L
(V = 1.0V) to (C) and measure the difference of
L
0
V
V
TP40, TP43, and TP45 from the black level.
External RGB output white
level
Enter SIG4 (V = 0mV) to (A) and SIG5
L
(V = 2.7V) to (C). Measure the difference of
L
3.0
TP40, Tp43, and TP45 from the black level.
External RGB input minimum
pulse width
Enter SIG4 (V = 0mV) to (A) and SIG5
L
(V = 2.7V) to (C) and measure the minimum pulse
L
150
ns
width at which TP40, TP43, and TP45 outputs
reach the white side limiter.
Package Dimensions
unit : mm (typ)
3281
9.0
7.0
48
33
49
32
17
64
1
16
0.18
0.125
0.4
(0.5)
SANYO : LQFP64(7X7)
No.8928-7/26
LV4147W
Conditions of setting to measure the electric characteristics
Following settings must be made before measurement of electric characteristics.
Setting 1. System reset
Turn ON SW58 and start V58 from GND in order to perform system reset for MOS block.
(See fig. 1-1.)
The default value is set for the serial bus.
Setting 2. Horizontal AFC adjustment
Enter SIG5 (V = 0mV) to (A) and adjust VCOADJ so that the width of WL and
L
WH becomes equal in the TP6 output waveform. (See fig. 1-2.)
(Note) In order to measure the 2MHz or more band for measurement items, such as the Y-system frequency
characteristics or sharpness characteristics, it is necessary to pass through the sample hold circuit
via serial bus.
V
1, V
DD
2
DD
V58(RESET)
Tr
Tr > 10μs
Fig.1-1 System reset
SIG5
V-sync
TP6
TP6
Approx.1/2V
DD
Fig.1-2 Horizontal AFC adjustment
No.8928-8/26
LV4147W
Electric characteristics measurement method
3V
0V
SIG6
100%
50%
P40, 43, 45
Non-inverted output
TD1EXT
TD2EXT
Fig.2 Delay between external RGB input/output
t
t
THL
TLH
90%
10%
Fig.3 Output transition time measurement contitions
ΔT
50%
ΔT
Fig.4 Cross point time difference measurement conditions
White
VG3
VG2
3.5V
VG1
1.5V
Black
Input
Fig.5 γ characteristics measurement conditions
No.8928-9/26
LV4147W
Block Diagram
Pin Description
For MONI
only
For EVF
only
Pin No.
Pin Name
I/O
Pin Description
Common
1
2
EXTR
EXTG
EXTB
TRAP
I
I
External digital R input (used also for the test)
External digital G input (used also for the test)
External digital B input (used also for the test)
External trap connection pin
Oscillator cell input (3V)
○
○
○
○
○
○
○
○
○
○
○
○
○
○
3
I
4
O
5
V
1
DD
RPD
6
O
Phase comparison output
Oscillator cell GND
7
V
1
SS
8
TEST2
TEST3
LOAD
DATA
SCLK
I
O
I
Test pin 2
9
Test pin 3
10
11
12
13
14
Load input for serial bus
Data input for serial bus
I
I
Clock input for serial bus
Test pin 1
TEST1
I
V
2
Digital 1 system power supply (3V)
DD
Continued on next page.
No.8928-10/26
LV4147W
Continued from preceding page.
For MONI
only
For EVF
only
Pin No.
Pin Name
XSTH2
I/O
Pin Description
Common
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
EVF H-start reverse phase output
○
○
STH2
EVF H-start output
XSTH1
STH1
Monitor H-start reverse phase output
Monitor H-start output
○
○
CKH4
EVF H-clock 2 output
○
○
CKH3
EVF H-clock 1 output
CKH2
Monitor H-clock 2 output
Monitor H-clock 1 output
Drain hold timing pulse reverse-phase output
Drain hold timing pulse output
Backlight HD output
○
○
CKH1
XDSG
DSG
○
○
○
○
○
○
○
○
○
○
○
○
BLHD
HD
H drive output
XSTV/STV2
STV
V-start reverse phase output/EVF V start output
V start output
(○)
(○)
(○)
(○)
CKV2/CKV4
CKV1/CKV2
VD
V clock 2 output/EVF CKV2
V clock 1 output/Monitor CKV2
V drive output
V
2
Digital 1 system GND
SS
XENB
O
O
O
I
Enable reverse-phase output
Enable output
ENB
SCAN
For scan selection (for monitor)
Time constant pin for antipole output DC return
Antipole output gland
○
FBCOM
GNDCOM
COMOUT
○
○
○
○
○
○
○
○
○
○
○
○
○
○
O
Antipole output
V
COM
Antipole output power supply (7V)
B output
CC
BOUT
FBB
O
I
Time constant pin for B-output DC return
Output system ground
GND2
GOUT
FBG
O
I
G output
Time constant pin for G-output DC return
R output
ROUT
FBR
O
I
Time constant pin for R-output DC return
Output system power supply
Output DC level setting pin
Analog 3V power supply
V
2
CC
SIGCENT
I
V
1
CC
NC
NC
NC
-
-
-
BYIN
I
B-Y input
R-Y input
○
○
RYIN
I
NC
-
VREG
NC
O
Reference voltage
○
RESET
YIN
I
I
I
I
System reset
○
○
○
○
Brightness signal input
Power-ON blanking time constant pin
Sync input
START-UP
SYNCIN
VSEPTC
Time constant and external VD input for vertical sync
○
separation
63
64
F0ADJ
GND1
O
Filter F0 adjustment
○
○
3V ground
No.8928-11/26
LV4147W
Analog pin function description
Pin No.
Pin Name
Pin Voltage
Pin Description
Equivqlent Circuit
1
2
3
EXTR
EXTG
EXTB
-
The external digital signal is entered. All of
RGB outputs become the black level when the
threshold value is about 0.7V for Vth1 and
about 1.8V for Vth2 and any one of RGB
exceeds Vth1 and become the white level only
for the output in which the input exceeds Vth2.
Connect to the ground when not using.
V
1
CC
25μA
300Ω
1
2
3
0.7V
GND1
4
TRAP
1.0V
External trap pin.
V
1
CC
Trap can be inserted into Y-signal by
connecting L and C in series to GND when
TRAP ON is set.
75μA
1kΩ
300Ω
4
200μA
GND1
13
TEST1
-
Test pin.
V
2
DD
Connect this pin normally to GND for use.
100kΩ
20k
Ω
Ω
13
20k
100kΩ
GND1
35
SCAN
-
Scan select control output pin. Output from
the open collector
V
2
CC
35
GND2
36
FBCOM
1.5V
Feedback circuit smoothing capacitor pin for
precharge output DC level control. Because of
high impedance, a capacitor with small
leakage is used.
V
1
CC
1kΩ
1kΩ
1kΩ
1kΩ
36
GND1
37
38
GNDCOM
COMOUT
0V
Gland of antipole output
Antipole output
V
2/2
CC
V
COM
CC
150Ω
38
20Ω
GNDCOM
39
V
COM
7V
Power supply for antipole output
CC
Continued on next page.
No.8928-12/26
LV4147W
Continued from preceding page.
Pin No.
Pin Name
Pin Voltage
C2/2
Pin Description
Equivqlent Circuit
40
43
45
BOUT
GOUT
ROUT
V
RGB primary color signal output.
CC
V
2
CC
40
43
45
20Ω
20Ω
1kΩ
GND2
41
44
46
FBB
FBG
FBR
1.5V
Feedback circuit smoothing capacitor pin for
RGB output DC level control.Because of high
impedance, a capacitor with small leakage is
used.
V
1
CC
1kΩ
1kΩ
1kΩ
1kΩ
41
44
46
100kΩ
GND1
42
47
48
GND2
0V
7V
V
2 ground.
CC
V
2
Power supply of output system
CC
SIGCENT
V
2/2
Apply external voltage when the signal output
DC voltage is to be used for those other than
1/2 VCC2.
CC
V
2
CC
300Ω
48
150kΩ
GND2
49
V
1
3.0V
1.7V
Analog 3V power supply.
CC
53
54
BYIN
RYIN
Enter the color difference of R-Y/B-Y.
V
1
CC
The clamp level in this case is about 1.7V.
4kΩ
10kΩ
1kΩ
53
54
5kΩ
30μA
40μA
4kΩ
GND1
56
VREG
2.0V
Regulator output pin. Connect an external
V
1
CC
capacitor of 1μF or more.
56
18.5kΩ
30kΩ
GND1
Continued on next page.
No.8928-13/26
LV4147W
Continued from preceding page.
Pin No.
58
Pin Name
RESET
Pin Voltage
-
Pin Description
Equivqlent Circuit
C-MOS circuit reset pin. Normally, connect a
capacitor between this pin and GND during
use.
V
2
DD
2μA
(Threshold value = 2.0V)
300Ω
58
1kΩ
GND1
59
60
61
62
63
64
YIN
START-UP
SYNCIN
VSEPTC
f0ADJ
1.6V
Y signal input pin. The standard input signal
level is 0.5Vp-p (from sync chip to 100%
white).
V
1
CC
1kΩ
59
20μA
GND1
-
Time constant connection pin to set the RGB
output to the black level at power ON.
V
2
DD
1μA
Connect the pin to V 2 when not using.
DD
(Threshold value = 2.0V)
300
Ω
60
1kΩ
GND1
1.6V
1.7V
1.5V
0V
Input pin for sync separation.
V
2
DD
1kΩ
1kΩ
61
500Ω
0.6μA
12μA
GND1
Time constant connection pin for vertical sync
separation. (The pin is used also for external
VD input.)
V
2
DD
500Ω
1kΩ
62
1kΩ
20μA
20μA
GND1
Reference current generation pin for filter.
15kΩ is connected between this pin and GND
to generate the reference current. (Keep the
pin open for trap OFF mode.)
V
1
CC
200Ω
5pF
500Ω
500Ω
63
5pF
GND1
GND1
3V ground.
No.8928-14/26
LV4147W
Digital pin function description
Pin No.
Pin Name
Pin Voltage
Equivalent Circuit
Power supply dedicated for VCO.
Phase comparator output.
Pin Description
6
5
6
V
1
-
-
DD
RPD
V
VCO
DD
5kΩ 10kΩ
1kΩ
1kΩ
100kΩ
GND1
1.5V
7
V
1
0
-
Digital ground for VCO.
SS
8
9
TEST2
TEST3
Test pin.Normally, connect the input side
(TEST2) to GND during use.
V
1
DD
8
9
600Ω
V
1
SS
10
11
12
LOAD
DATA
SCLK
-
Serial bus input pin.
V
2
DD
2kΩ
V
2
SS
14
V
2
-
-
Digital output pin.
Digital output pin.
DD
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
34
32
XSTH2
STH2
XSTH1
STH1
CKH4
CKH3
V
2
DD
CKH2
CKH1
XDSG
DSG
BLHD
HD
V
2
XSTV/STV2
STV
SS
CKV2/CKV4
CKV1/CKV2
VD
XENB
ENB
V
2
O
Digital ground.
SS
No.8928-15/26
LV4147W
No.8928-16/26
LV4147W
No.8928-17/26
LV4147W
No.8928-18/26
LV4147W
Input sine wave (1)
SG No.
Sine wave
SIG1
With/without sine wave video signal
(Amplitude, Frequency variable)
150mV
← Value shown in the left 0dB
143mV
SIG2
357mV
150mV
143mV
SIG3
SIG4
5-step staircase wave
143mV
V
amplitude variable
L
VS variable : 143mV, unless otherwise specified.
V
L
WS variable : 4.7μs, unless otherwise specified.
f
variable : NTSC 15.734kHz
PAL 15.625kHz,
H
VS
WS
unless otherwise specified.
f
H
Input sine wave (2)
SG No.
Sine wave
SIG5
30μs
5μs
GND
V
L
V
amplitude variable
L
SYNC
timing
SIG6
SIG7
75mV
Frequency variable
175mV
143mV
10-step staircase wave
357mV
143mV
SIG8
sin2
357mV
2T pulse
143mV
No.8928-19/26
LV4147W
Serial bus communication specifications
(1) Conditions for serial transfer
DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
ts1
th1
50%
SCLK
tw1H
tw1L
LOAD
50%
ts0
th0
tw2
Parameter
Symbol
Conditions
min
typ
max
unit
Serial transfer
Data setup time
ts0
LOAD setup time to start SCLK.
DATA setup time to start SCLK.
LOAD hold time to start SCLK
Data hold time to start SCLK.
SCLK pulse width.
150
ns
ns
ns
ns
ns
ns
μs
ts1
150
150
150
160
160
1.0
Data holdup time
Pulse width
th0
th1
tw1L
tw1H
tw2
SCLK pulse width.
LOAD pulse width.
No.8928-20/26
LV4147W
(2) 3-wave serial format
DATA
SCLK
LOAD
Data length : 16bit
Clock frequency : 3MHz or less
Only when SCLK is input in 16-bit clock while LOAD is in the L period, DATA is accepted at rise of
LOAD.
Note : When SCLK is in 15-bit or 17-bit clock while LOAD is in the L period, DATA is not accepted.
(3) Data output timing
1. Various mode settings
DATA accepted at rise of LOAD is set at fall of the vertical sync signal.
When the data is transmitted several times for the same item, the data immediately before the vertical sync signal
becomes valid.
2. Setting of the electric volume
Concurrently with acceptance of DATA at rise of LOAD, the D/A output data is changed.
No.8928-21/26
LV4147W
(4) Data specifications 1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Description
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Not used
Not used
TRAP ON
TRAP OFF
Not used
Not used
○
○
○
○
○
○
○
System changeover NTSC
System changeover PAL
External VSYNC input OFF
External VSYNC input ON
Y/color difference clamp position, pedestal
Y/color difference clamp position, SYNC
Sample hold phase SHS1
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Sample hold phase SHS2
Sample hold phase SHS3
Sample hold phase ALL through
HD output polarity, positive
○
○
○
HD output polarity, negative
VD output polarity, positive
VD output polarity, negative
Panel selection 521 × 218 : 110,000 mode
Panel selection 557 × 234 : 130,000 mode
Panel selection 800 × 225: 180,000 mode
For test. Do not set this bit to "1".
Field overlap method, odd number on even number
Field overlap method, even number on odd number
○
○
○
○
Normal mode
(Note 6)
521×218 (EVF) + 557×234 (monitor) driving (Note 6-3)
BLHD output ON
BLHD output Stop
Sync generator function, OFF
Sync generator functionON (output other than HD, VD, BLHD, and SPCLK is turned OFF).
Normal mode
○
×
×
×
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
Skipping OFF mode for PAL (Indication of no skipping)
For test. Do not set this bit to "1".
Not used
×
Not used
Not used
Normal mode
○
×
×
×
×
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
Not used
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
For test. Do not set this bit to "1".
×
×
×
No.8928-22/26
LV4147W
(4) Data specifications 2
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
HC5 HC4 HC3 HC2 HC1 H-position setting, 2/fh x 31 steps
VP2 VP1 VP0 V-position setting, 1H x 4 steps
Description
Default
10000
010
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
×
×
×
×
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
×
×
×
×
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
×
×
×
×
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
(Note 2)
(Note 3)
(Note 4)
(Note 5)
×
×
HD6 HD5 HD4 HD3 HD2 HD phase setting, 4/fh x 31 steps
HW5 HW4 HW3 HW2 HW1 BLHD pulse setting, 2/fh x 31 steps
00000
10000
○
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Monitor horizontal inversion, normal scan mode
Monitor horizontal inversion, reverse scan mode
Monitor vertical inversion, normal scan mode
Monitor vertical inversion, reverse scan mode
EVF horizontal inversion, normal scan mode
EVF horizontal inversion, reverse scan mode
EVF vertical inversion, normal scan mode
EVF vertical inversion, reverse scan mode
Scan changeover pin, normalSCAN pin : OPEN
Scan changeover pin, reverse scanSCAN pin : OPEN
Not used
○
○
○
○
○
Not used
VCO sensitivity changeover 1
VCO sensitivity changeover 2
○
VCO sensitivity changeover 3
VCO sensitivity changeover 4
Monitor scan stop mode
Monitor display mode
EVF scan stop mode
EVF display mode
(Note 6-4)
(Note 6-4)
○
○
○
blanking period CHK/STH stop OFF (NORMAL)
blanking period CKH/STH stop ON (power save mode)
H blanking period CKH stop OFF (NORMAL)
○
○
H blanking period CKH stop ON (power save mode)
Panel connection form MODE 1
Panel connection form MODE 2
Normal mode
(Note 6-1)
(Note 6-2)
○
For test. Do not set this bit to “1”.
×
(4) Data specifications 3 (DAC set)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Description
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 TINT adjustment
10000000
10000000
10010101
10001100
10000000
10000000
01100100
00000000
01010000
10000000
10000000
10101100
00000000
10000000
10000000
10000000
0000
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 COLOR adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 BRIGHT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CONTRAST adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 R-BRIGHT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 B-BRIGHT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 γ-1 adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 γ-2 adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Antipole output amplitude adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 R-CONT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 B-CONT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 BLKLIMT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Not used
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 PICTURE adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 USER-BRIGHT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 VCO adjustment
×
×
×
×
DA3 DA2 DA1 DA0 WHTLIMT adjustment
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Test mode. Do not set this address.
No.8928-23/26
LV4147W
(Note 1) Sample hold phase
S/H pulse timing
CKH1
S/H1
S/H4
S/H4
S/H4
R
G
B
A
B
S/H2
S/H3
SH3
C
SH1 SH2
SH4
Horizontal inversion
Normal scan
Horizontal inversion
Reverse scan
SHS1
SHS2
SHS3
SHS1
SHS2
SHS3
SH1
SH2
SH3
SH4
B
A
C
SH1
SH2
SH3
SH4
B
A
A
C
through
through
through
C
through
B
B
Through
A
A
C
C
B
B
A
through
C
SH1 : SH pulse for R signal
SH3 : SH pulse for B signal
SH2 : SH pulse for G signal
SH4 : Common SH pulse for RGB signal
(Note 2) H-Position set
(step 1 = 2×1/fvco)
: 1/fvco ≈ 90ns <521×218, 557×234 mode>
: 1/fvco ≈ 60ns <881×228 mode>
CLK (fh)
STH
10001(+1)
10000 (Default)
01111 (-1)
Step 1 Step 1
Step 15
Step 16
Center
No.8928-24/26
LV4147W
(Note 3) V-Position set
000
001
010
011
100
-2H
-1H
2H
STV
(DEFAULT)
+1H
+2H
(Note 4) HD phase set
(step 1 = 4×1/fvco)
HSYNC
HD
00000
(Default)
11111
HD
Step 31
(Note 5) BLHD phase set
(step 1 = 2×1/fvco)
00000
Step 16
Approx.6μs
BLHD
10000
(Default)
Step 15
11111
ON/OFF (output L fixed) possible with the serial bus
No.8928-25/26
LV4147W
(Note 6) Output signal by mode
MODE1 (Note 6-1)
MODE2 (Note 6-2)
(521×218)
Scan OFF
(Note 6-4)
Normal
Normal
+
(557×234) (Note 6-3)
For
Pin No.
Pin symbol
For
For
monitor
○
Motor
EVF
OFF
Common For EVF
Common For EVF
Common For EVF
monitor
monitor
OFF
“L”
○
18
17
22
21
28
STH1
XSTH1
CKH1
CKH2
STV
○
○
○
○
←
←
←
←
←
○
○
○
○
○
○
○
“H”
“L”
“H”
←
○
○
○
○
*
○
27
30
29
XSTV/STV2
CKV1/CKV2
CKV2/CKV4
*
←
←
←
←
←
←
(STV2)
○
○
○
○
*
*
(CKV2)
(CKV2)
○
(CKV4)
○
○
(CKV4)
○
*
*
34
33
24
23
16
15
20
19
ENB
XENB
PCG
○
○
○
○
○
○
○
○
←
←
←
←
←
←
←
←
←
←
○
○
○
○
○
○
○
○
○
○
○
○
○
○
←
XPCG
STH2
XSTH2
CKH3
CKH4
←
“L”
“H”
“L”
“H”
* : Generated with an external inverte
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of May, 2007. Specifications and information herein are subject
to change without notice.
PS No.8928-26/26
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