LV5254LG [SANYO]
Bi-CMOS LSI Inverting Charge Pump Regulator IC; BI -CMOS LSI反相电荷泵稳压器IC
| 型号： | LV5254LG |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Bi-CMOS LSI Inverting Charge Pump Regulator IC |
| 文件： | 总14页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0584
Bi-CMOS LSI
LV5254LG
Inverting Charge Pump Regulator IC
Overview
The LV5254LG is an inverting charge pump regulator IC.
Functions
• Inverting charge pump regulator
Specifications
Absolute Maximum Ratings at Ta = 25°C, SGND and PGND = 0V
Parameter
Symbol
Conditions
Ratings
Unit
V
Input supply voltage
V
max
SV
DD
= PV
DD
6.5
6.5
DD
VS pin input voltage
VS max
V
STBY pin input voltage
S1 and S2 pin input voltage
Maximum output current
Operating temperature
Storage temperature
STBY max
S1, S2 max
6.5
V
6.5
V
I
110
mA
°C
°C
OUT
Topr
Tstg
-20 to +85
-40 to +125
Recommended Operating Conditions at Ta = 25°C, SGND and PGND = 0V
Parameter
Symbol
Conditions
Ratings
Unit
V
Input supply voltage
V
SV
DD
= PV
DD
3.5 to 6
1 to 4.5
100
DD
VS pin input voltage
Output current
VS
V
I
mA
OUT
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
31407 MS PC 20060915-S00004 No.A0584-1/14
LV5254LG
Electrical Characteristics
(a) Electrical Characteristics
Ta = 25°C, SV
DD
and PV
DD
= 4.6V, SGND and PGND = 0V, CLK = 2MHz, unless otherwise specified.
Ratings
Parameter
Symbol
Conditions
C2, C5 = 1μF, I = 60mA
Unit
min
typ
max
Output ripple
Standby mode V
Vrp
20
mVp-p
μA
O
current
I
stby
dd
1
DD
Operating V
Operating V
current 1
current 2
I
ope1
ope2
I
I
= 0mA
2.2
3.2
mA
mA
%
DD
DD
dd
O
O
I
= 60mA
dd
Power efficiency
Peff
V
= 4.6V, V
OUT
= -2.8V, I
= 60mA
OUT
57.5
DD
Reference voltage
V
I
1.262
115
1.300
1.339
V
REF
Overcurrent protection threshold
current
mA
OCP
Overcurrent protection latch off wait
time
t
Fclk = 2MHz
Fclk = 2MHz
6
ms
OCP
Regulator output on time
tregon
fclk
3.5
2
ms
MHz
°C
Internal clock frequency*
Thermal shutdown circuit operating
temperature
TSD
Design guarantee
170
V
discharge resistance
RDIS
RVS
650
280
170
Ω
kΩ
kΩ
V
OUT
VS pin input resistance
180
100
1.6
0
480
300
STBY pin pull-down resistance
STBY pin control voltage
RSHD
V
H
L
V
th
DD
V
V
0.3
V
th
S1 and S2 pin control voltage
H
0.7V
V
V
th
DD
0
DD
V
L
0.3
V
th
* : The charge pump operating frequency, Fcp, is the internal clock frequency divided by two, i.e. Fclk/2.
(b) Output Characteristics
Ta = 25°C, SV
DD
and PV = 4.6V, SGND and PGND = 0V, CLK = 2MHz, unless otherwise specified.
DD
Fixed Output Voltage (Vout = -2.8V) Mode
Outputs a fixed voltage of -2.8V determined by an internal resistor.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
4.37
max
4.83
Input supply voltage
V
SV
= PV
DD DD
V
V
DD
Output voltage precision
Maximum output current
V
V
= +4.37 to +4.83V
= 60mA
-2.884
-2.8
-2.716
OUT
DD
I
OUT
I
V
V
= +4.37 to +4.83V
= -2.8V
70
mA
OUT
DD
OUT
VS Mode
Outputs a voltage that is -1 times the voltage VS input to the VS pin.
Ratings
typ
Parameter
Symbol
VS
Conditions
Unit
min
1
max
4.5
-1
VS pin input voltage
V
V
V
V
VS pin output voltage range
Output voltage precision
Output voltage precision
V
*1
-4.5
OUT
VS = 1 to 2V, I
= 0 to 60mA
-1.05VS
-1.03VS
-VS
-VS
-0.95VS
-0.97VS
OUT
VS = 2 to 4.5V, I
= 0 to 60mA
OUT
No.A0584-2/14
LV5254LG
External Setting Mode
Outputs a voltage determined by external resistors and the external reference voltage.
See page 8, External Setting Mode Applications and the Output Voltage Setting Method for the method for setting the
V
voltage.
OUT
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
-4.5
-5
max
Output voltage range
FB pin voltage
V
*1
V
-1
V
OUT
VFB
IFB
= 5V, I
= 5V, I
= 0 to 100mA
= 0 to 100mA
20
mV
nA
DD
OUT
OUT
FB pin current
V
70
200
DD
*1 : The V
OUT
range that can be set and the current drive capacity of the charge pump regulator are, in principle, determined by the relationship between the
voltage and the set voltage. (See the "Relationship Between the Input and Output Voltages" ) Contact your SANYO Semiconductors
values of the V
DD
representative for more detailed information.
Logic Function Tables
The pins S1 and S2 must be connected to V
Mode
(high) or ground (low) according to the mode to be used.
DD
Description
S1
S2
Mode 1
Mode 2
Mode 3
Outputs a fixed voltage of -2.8V determined by an internal resistor.
High
Low
High
Low
High
High
Outputs a voltage that is -1 times the voltage VS input to the VS pin.
Outputs a voltage determined by an external resistor and the external reference voltage.
Package Dimensions
unit : mm (typ)
3330
Pd max – Ta
Specified board : 50×40×0.8mm3
0.8
0.7
0.6
glass epoxy
4-layer (2S2P)
printed circuit board
Top View
3.0
Bottom View
0.5
0.4
0.2
E
D
C
B
A
0.3
0.5
0
–
Side View
20
0
20
40
60
80
100
Ambient temperature, Ta – °C
SANYO : FLGA24(3.0X3.0)
No.A0584-3/14
LV5254LG
Pin Assignment
FLGA24 (3mm×3mm)
E
D
C
B
A
S2
SGND VREF
1
2
3
4
5
6
7
9
5
4
8
3
2
1
24
STBY
S1
FB
VS
22
20
16
23
SV
TEST
V
OUT
DD
DD
21
19
18
PV
11
12
10
13
14
+
-
C1
PGND C1
C2
15
17
TOP VIEW
Pin Descriptions
Pin No.
Pin
Functions
9
SV
Small signal system V
DD
DD
11
1
PV
Power system V
DD
DD
SGND
PGND
Small signal system ground
Power system ground
15
13
17
18
21
24
22
23
2
+
C1
Inversion capacitor connection (driver side)
-
C1
Inversion capacitor connection (charge transfer side)
Charge pump output
C2
V
Regulator output
OUT
VREF
FB
Band gap voltage output
Feedback pin
VS
VS mode output setting
STBY
S1
Standby mode control
4
Sensing mode selection 1
Sensing mode selection 2
Test mode enable (normally not used)
3
S2
8
TEST
* : The test mode enable pin must be left open. (There is a built-in pull-down resistor, and this pin should always be low.)
No.A0584-4/14
LV5254LG
Block Diagram and Application Circuit Example 1 (Internal fixed-voltage mode)
C4 = 10μF
SV
V
PV
DD
DD
DD
Charge
Pump
Thermal
Shutdown
OSC
+
-
C1
C1
C1 = 1μF
Clock
Driver
SGND
PGND
Discharge
V
V
OUT
OUT
Overcurrent
Protection
C5 = 1μF
C2
Output Tr
TEST
C6
Error Amplifier
C2 = 1μF
STBY
+
VREF
FB
−
OFF ON
VREF
C3 = 0.1μF
S1
S2
VS
V
DD
• Use ceramic capacitors for the external capacitors and connect them as close as possible to the IC. We recommend
using class B devices with excellent temperature characteristics.)
• Use capacitors with the same values for the charge pump capacitors C1 and C2.
We recommend a capacitance of 1μF for C1 and C2. (See figure 4 on page 10)
• SV
and PV
must be at the same potential. Short them together with the shortest possible line and use a ceramic
DD
DD
capacitor with a value of 1μF or greater for C4 (which is inserted between this point and PGND). C4 must be mounted
as close as possible to the IC.
• C6 is a phase compensation capacitor. It is required for stable regulator operation.
No.A0584-5/14
LV5254LG
Application Circuit Example 2 (VS mode)
C4 = 10μF
SV
V
PV
DD
DD
DD
Charge
Pump
Thermal
Shutdown
OSC
+
-
C1
C1
C1 = 1μF
Clock
Driver
SGND
PGND
Discharge
V
V
OUT
OUT
Overcurrent
Protection
C5 = 1μF
C2
Output Tr
TEST
C6
Error Amplifier
C2 = 1μF
STBY
+
VREF
FB
−
OFF ON
VREF
C3 = 0.1μF
S1
S2
VS
VS
V
DD
Application Circuit Example 3 (External setting mode)
C4 = 10μF
SV
DD
V
PV
DD
DD
Charge
Pump
Thermal
Shutdown
OSC
+
C1
C1
C1 = 1μF
-
Clock
Driver
SGND
PGND
Discharge
V
V
OUT
OUT
Overcurrent
Protection
C5 = 1μF
C2
Output Tr
TEST
C6
R2
R1
Error Amplifier
C2 = 1μF
STBY
+
−
VREF
FB
OFF ON
VREF
C3 = 0.1μF
S1
S2
Vref_ext
VS
V
DD
No.A0584-6/14
LV5254LG
Recommended Power On and Off Sequences
V
DD
SV
(pin 9)
DD
(pin 11)
PV
DD
VS (pin 23) : VS mode
or
VREF_ext
(external reference voltage)
External setting mode
STBY (pin 2)
CP CLK (1MHz)
(1) (2) (3) (4)
(5) (6)
(7)
(8) (9)
CP output
C2 (pin 18)
-V
DD
tpre :
0.5ms
tsoft :
2ms
ton :
1ms
tregon :
3.5ms
Regulator output
V
(pin 21)
OUT
V
OUT
(1) Apply the V
voltage to the SV
DD
and PV pins.
DD
DD
(2) If VS mode is used, apply the VS voltage. If external setting mode is used, apply the external reference voltage.
(3) Start pre-charging the flying capacitor with a high-level input to the STBY pin.
(4) Start charging the pump-up capacitor with the charge pump sub-driver (soft start).
(5) Switch to the charge pump driver. This starts charging of the pump-up capacitor by the main driver.
(6) Regulator output starts.
(7) Stop IC drive by applying a low-level input to the STBY pin to start V
discharge transistor. (This operates when the STBY pin is low.)
output discharge operation by the internal
OUT
(8) If VS mode is used, shut down the VS voltage, and if external setting mode is used, shut down the external reference
voltage.
(9) Shut down the V
DD
voltage.
No.A0584-7/14
LV5254LG
Overcurrent Protection Operation
This IC includes a function that protects against overcurrent in V
current flows, the IC will latch and stop the output. To recover from this stopped state, set the STBY pin low and then
. If the V
output is shorted and a large
OUT
OUT
set it high again.
External Setting Mode Applications and the Output Voltage Setting Method
In the LV5254's external setting mode, the output voltage is set by the external resistors R1 and R2 and by the external
reference voltage, Vref_ext. In this mode, the output voltage is expressed by equation (1). The second term in equation
(1) is the error amplifier's offset component and the third term is the offset component due to the feedback current. The
voltage precision achieved by an application can be determined by considering the tolerances of the parameters in
equation (1).
Vref_ext
FB
VFB
IFB
C6
V
OUT
C5
V
OUT
R2
= - ⋅Vref_ext+
R1+R2
R1
…
⋅VFB-R2⋅IFB (1)
V
OUT
R1
No.A0584-8/14
LV5254LG
Relationship Between the Input and Output Voltages
Equation (2) gives the relationship between the input voltage and output voltage. In the LV5254, a charge pump circuit
generates VC2, which is the V level inverted, and generates the output voltage V by regulating that inverted
IN OUT
voltage. In this case, due to the charge pump block impedance Ron, the voltage drop I × Ron (where I is the load
O
O
current) is generated. (* Here we are ignoring the capacitor loss components in the charge pump capacitors C1 and C2.)
The LV5254's current capacity is expressed by equation (3). At this time, the impedance Ron increases with
temperature. Thus the current capacity decreases with increasing temperature.
Input voltage
CP output voltage
VC2
Regulator output
V
V
IN
OUT
CP
Regulator
I
OUT
Load current Iout
Ron × I
OUT
ΔVreg
Voltage drop due to the
charge pump block impedance
Voltage drop in the
regulator block
…
V
= VC2+ΔVreg = (-V +Ron×I
)+ΔVreg (2)
OUT
: Output voltage, V : Input voltage, I : Load current, Ron : Charge pump block impedance,
OUT
IN OUT
V
OUT
IN
ΔVreg : Regulator voltage drop
…
[max] = (V +V -ΔVreg [min]) / Ron (3)
IN OUT
I
O
I
[max] : Maximum load current, ΔVreg [min] : Minimum regulator voltage drop
O
Ron – Ta
19
V
= 5V
DD
18
17
16
15
14
13
12
–
20
0
20
40
60
80
90
Ambient temperature, Ta – °C
Figure 1 : Charge Pump Block Impedance Temperature Characteristics : Assumed Worst Case (C1, C2 = 1μF)
No.A0584-9/14
LV5254LG
Next, consider figure 2, which shows the relationship between the input voltage V and the charge pump block
IN
impedance Ron at Ta = 85°C, which is the maximum temperature for which operation is guaranteed. At Ta = 85°C, if
ΔVreg [min] = 0.3V (inferred worst case value), the LV5254's maximum output current can be expressed as equation
(4).
…
[max] = (V +V -0.3) / Ron (4)
IN OUT
I
O
The current capacity shown in figure 3 can be determined from the characteristics in figure 2 when V
-3V.
is set to be
OUT
Ron – V
I
max – V
IN
Figure 2
Figure 3
IN
O
25
23
21
19
120
100
80
Ta = 85°C
Ta = 85°C
60
40
17
15
20
0
3.5
4
4.5
5
5.5
6
3.5
4
4.5
5
5.2
Input voltage, V
IN
– V
Input voltage, V – V
IN
Figure 2 : Charge Pump Block Impedance -
Input Voltage Characteristics
Figure 3 : Maximum Output Current - Input
Voltage Characteristics when
(Ta = 85°C) : Assumed Worst Case
(C1, C2 = 1μF)
V
= -3V (Ta = 85°C) :
OUT
Assumed Worst Case
(C1, C2 = 1μF)
Caution : The characteristics values presented in this reference documentation are nothing other than inferred worst-case
values. No guarantee or warranty is made with respect to these values.
Loss in the Charge Pump Capacitors
Voltage loss occurs in the pump capacitors C1 and C2 in the charge pump circuit. Figure 4 shows the charge pump
output vs. load current characteristics (with the C1 and C2 value as a parameter) at room temperature when V
= 5V.
DD
Note that the load regulation becomes worse as the value of the capacitors C1 and C2 is reduced. To minimize the loss
in these capacitor, we recommend using a value of 1μF for C1 and C2.
Charge Pump Output
– Load Current Characteristics
–
–
3.6
3.8
–
4
–
–
–
–
4.2
4.4
4.6
4.8
–
5
0
20
40
60
80
100
Load current, I – mA
O
Figure 4 : Charge Pump Output - Load Current Characteristics when V
purposes.
= 5V, data provided for reference
DD
No.A0584-10/14
LV5254LG
IC start and stop
1. Startup waveform (External setting mode)
Ta = 27°C V
= 5V I
OUT
= 0mA
Ta = 27°C V
= 5V I
DD OUT
= 60mA
DD
1
1
STBY
VREF
STBY
VREF
1.6V
1.6V
STBY
2.00V/S
STBY
2.00V/S
1
2
1
2
2
2
VREF
VREF
1.00V/S
1.00V/S
3,4
V
3,4
3
3
V
V
OUT
2.00V/S
OUT
2.00V/S
-2.9V
-4.4V
-2.9V
-5V
V
OUT
OUT
C2
CP
output
C2
CP
output
4
4
C2
2.00V/S
C2
2.00V/S
4msec
4msec
1ms/s
1ms/s
(a) No load - Startup waveform
2. Falling waveform (External setting mode)
(b) 50Ω - Startup waveform
Ta = 27°C V
= 5V I
OUT
= 0mA
Ta = 27°C V = 5V I
DD OUT
= 60mA
DD
1
1
STBY
2.00V/S
STBY
2.00V/S
STBY
VREF
STBY
VREF
1
2
1
2
2
2
VREF
VREF
1.00V/S
1.00V/S
0V
0V
V
3,4
V
3,4
OUT
OUT
3
3
-2.9V
V
V
-2.9V
OUT
2.00V/S
OUT
2.00V/S
-4.4V
-5V
C2
CP
output
C2
CP
output
4
4
C2
C2
2.00V/S
2.00V/S
3msec
3msec
1ms/s
1ms/s
(a) No load - Falling waveform
(b) 50Ω - Falling waveform
Internal fixed mode - Regulator
Load regulation - Internal fixed mode V
= 4.6V
Efficiency - Internal fixed mode V
70
= 4.6V
DD
DD
DD
–
2.7
V
= 4.6V
Room temperature
–
–
–
–
2.725
60
50
40
30
20
Ta = 90°C
Ta = -20°C
–
2.75
Room temperature
Ta = -20°C
Ta = 90°C
2.775
–
2.8
2.825
–
2.85
10
0
2.875
–
2.9
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
Load current, I
– mA
Load current, I
– mA
OUT
OUT
No.A0584-11/14
LV5254LG
VS mode - Regulator
VS mode (VS = 1V) Load regulation V
= 5V
VS mode (VS = 2.5V) Load regulation V
–
2.4
= 5V
DD
DD
–
0.9
–
–
2.45
0.95
Ta = 30°C
Ta = 60°C
Ta = 0°C
Ta = 30°C
Ta = 60°C
–
–
2.5
1
Ta = 90°C
Ta = 0°C
Ta = -30°C
Ta = 90°C
Ta = -30°C
–
–
2.55
1.05
–
–
2.6
1.1
0
20
40
60
80
100
0
20
40
60
80
100
Load current, I
OUT
– mA
Load current, I – mA
OUT
VS mode (VS = 3.3V) Load regulation V
= 5V
VS mode (VS = 4.5V) Load regulation V
–
4.4
= 6V
DD
DD
–
3.2
Ta = 60°C
Ta = 30°C
Ta = 0°C
Ta = 60°C
Ta = 30°C
Ta = 0°C
–
–
4.45
3.25
Ta = 90°C
Ta = -30°C
Ta = 90°C
Ta = -30°C
–
–
4.5
3.3
–
–
4.55
3.35
–
–
4.6
3.4
0
20
40
60
80
0
20
40
60
80
Load current, I
OUT
– mA
Load current, I – mA
OUT
VS mode (VS = 2.5V) Line regulation characteristics I
= 60mA
VS mode (VS = 1V) Line regulation characteristics I
0.95
= 60mA
OUT
OUT
–
–
2.45
–
–
0.975
2.475
Ta = -30°C
Ta = 90°C
Ta = Room temperature
Ta = -30°C
Ta = 90°C
–
–
1
2.5
Ta = Room temperature
–
–
1.025
2.525
–
–
2.55
4.5
1.05
3.5
5
5.5
6
4
4.5
5
5.5
6
Intput voltage, V
– V
Intput voltage, V
– V
DD
DD
No.A0584-12/14
LV5254LG
External Setting Mode Applications and the Output Voltage Setting Method
Load regulation characteristics
Line regulation characteristics
–
–
–
–
2.88
2.89
2.88
2.89
V
= 5V
I
= 60mA
DD
OUT
R1 = 82kΩ
V
= 5V
DD
R2 = 240kΩ
Vref_ext = 1V
R1 = 82kΩ
R2 = 240kΩ
Vref_ext = 1V
–
–
2.9
2.91
2.92
2.93
2.9
2.91
2.92
2.93
Ta = 0°C
Ta = 60°C
Ta = 30°C
Ta = 30°C
Ta = 60°C
–
–
–
–
–
–
Ta = -30°C
Ta = -30°C
Ta = 90°C
Ta = 90°C
Ta = 0°C
–
–
–
–
2.94
2.95
2.94
2.95
0
10
20
30
40
50
60
70
80
90
100
4.5
5
5.5
6
Load current, I
OUT
– mA
Intput voltage, V – V
DD
Overcurrent protection function detection current value
Overcurrent protection - Ambient temperature dependence characteristics
180
V
= 6V
DD
V
= 5.5V
170
160
150
140
130
120
110
DD
100
–
–
20
40
0
20
40
60
80
100
Ambient temperature, Ta – °C
No.A0584-13/14
LV5254LG
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of March, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0584-14/14
相关型号：
©2020 ICPDF网 联系我们和版权申明